From 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Sat, 23 Dec 2017 18:18:56 +1100 Subject: Remove make preinstall A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254. --- bsps/arm/altera-cyclone-v/headers.am | 45 + bsps/arm/altera-cyclone-v/include/bsp.h | 50 + .../altera-cyclone-v/include/bsp/alt_16550_uart.h | 1555 ++ .../include/bsp/alt_address_space.h | 825 + bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h | 964 + .../altera-cyclone-v/include/bsp/alt_clock_group.h | 114 + .../include/bsp/alt_clock_manager.h | 1434 ++ bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h | 1007 + .../altera-cyclone-v/include/bsp/alt_dma_common.h | 162 + .../altera-cyclone-v/include/bsp/alt_dma_program.h | 951 + .../include/bsp/alt_generalpurpose_io.h | 1254 + .../altera-cyclone-v/include/bsp/alt_hwlibs_ver.h | 56 + bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h | 2024 ++ .../include/bsp/alt_interrupt_common.h | 533 + .../include/bsp/alt_mpu_registers.h | 156 + .../include/bsp/alt_qspi_private.h | 167 + .../include/bsp/alt_reset_manager.h | 291 + bsps/arm/altera-cyclone-v/include/bsp/hwlib.h | 189 + bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h | 76 + bsps/arm/altera-cyclone-v/include/bsp/irq.h | 41 + .../include/bsp/socal/alt_acpidmap.h | 3569 +++ .../include/bsp/socal/alt_clkmgr.h | 6464 +++++ .../include/bsp/socal/alt_dmanonsecure.h | 144 + .../include/bsp/socal/alt_dmasecure.h | 144 + .../altera-cyclone-v/include/bsp/socal/alt_gpio.h | 1991 ++ .../altera-cyclone-v/include/bsp/socal/alt_i2c.h | 5940 +++++ .../altera-cyclone-v/include/bsp/socal/alt_l3.h | 6299 +++++ .../altera-cyclone-v/include/bsp/socal/alt_qspi.h | 5951 +++++ .../include/bsp/socal/alt_qspidata.h | 52 + .../include/bsp/socal/alt_rstmgr.h | 3382 +++ .../altera-cyclone-v/include/bsp/socal/alt_sdr.h | 4149 ++++ .../include/bsp/socal/alt_sysmgr.h | 24810 +++++++++++++++++++ .../altera-cyclone-v/include/bsp/socal/alt_uart.h | 5158 ++++ bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h | 8026 ++++++ .../arm/altera-cyclone-v/include/bsp/socal/socal.h | 259 + bsps/arm/altera-cyclone-v/include/tm27.h | 24 + bsps/arm/atsam/headers.am | 269 + bsps/arm/atsam/include/bsp.h | 102 + bsps/arm/atsam/include/bsp/atsam-clock-config.h | 62 + bsps/arm/atsam/include/bsp/atsam-i2c.h | 74 + bsps/arm/atsam/include/bsp/atsam-spi.h | 36 + bsps/arm/atsam/include/bsp/i2c.h | 36 + bsps/arm/atsam/include/bsp/irq.h | 30 + bsps/arm/atsam/include/bsp/pin-config.h | 36 + bsps/arm/atsam/include/bsp/power.h | 245 + bsps/arm/atsam/include/bsp/sc16is752.h | 68 + bsps/arm/atsam/include/bsp/spi.h | 36 + bsps/arm/atsam/include/libchip/chip.h | 124 + bsps/arm/atsam/include/libchip/compiler.h | 476 + bsps/arm/atsam/include/libchip/include/acc.h | 152 + bsps/arm/atsam/include/libchip/include/adc.h | 179 + bsps/arm/atsam/include/libchip/include/aes.h | 68 + bsps/arm/atsam/include/libchip/include/afe_dma.h | 116 + bsps/arm/atsam/include/libchip/include/afec.h | 190 + bsps/arm/atsam/include/libchip/include/chip.h | 1 + bsps/arm/atsam/include/libchip/include/dac_dma.h | 150 + bsps/arm/atsam/include/libchip/include/efc.h | 128 + .../arm/atsam/include/libchip/include/exceptions.h | 52 + bsps/arm/atsam/include/libchip/include/flashd.h | 91 + bsps/arm/atsam/include/libchip/include/gmac.h | 349 + bsps/arm/atsam/include/libchip/include/gmacd.h | 283 + bsps/arm/atsam/include/libchip/include/hsmci.h | 155 + bsps/arm/atsam/include/libchip/include/icm.h | 112 + bsps/arm/atsam/include/libchip/include/isi.h | 200 + bsps/arm/atsam/include/libchip/include/iso7816_4.h | 110 + bsps/arm/atsam/include/libchip/include/mcan.h | 329 + bsps/arm/atsam/include/libchip/include/mcid.h | 170 + bsps/arm/atsam/include/libchip/include/mediaLB.h | 45 + bsps/arm/atsam/include/libchip/include/mpu.h | 222 + bsps/arm/atsam/include/libchip/include/pio.h | 217 + .../atsam/include/libchip/include/pio_capture.h | 79 + bsps/arm/atsam/include/libchip/include/pio_it.h | 117 + bsps/arm/atsam/include/libchip/include/pmc.h | 101 + bsps/arm/atsam/include/libchip/include/pwmc.h | 137 + bsps/arm/atsam/include/libchip/include/qspi.h | 236 + bsps/arm/atsam/include/libchip/include/qspi_dma.h | 115 + bsps/arm/atsam/include/libchip/include/rstc.h | 64 + bsps/arm/atsam/include/libchip/include/rtc.h | 102 + bsps/arm/atsam/include/libchip/include/rtt.h | 82 + .../include/same70/component/component_acc.h | 128 + .../include/same70/component/component_aes.h | 191 + .../include/same70/component/component_afec.h | 483 + .../include/same70/component/component_chipid.h | 123 + .../include/same70/component/component_dacc.h | 184 + .../include/same70/component/component_efc.h | 111 + .../include/same70/component/component_gmac.h | 1240 + .../include/same70/component/component_gpbr.h | 53 + .../include/same70/component/component_hsmci.h | 335 + .../include/same70/component/component_icm.h | 192 + .../include/same70/component/component_isi.h | 280 + .../include/same70/component/component_matrix.h | 301 + .../include/same70/component/component_mcan.h | 845 + .../include/same70/component/component_pio.h | 1711 ++ .../include/same70/component/component_pmc.h | 723 + .../include/same70/component/component_pwm.h | 644 + .../include/same70/component/component_qspi.h | 216 + .../include/same70/component/component_rstc.h | 79 + .../include/same70/component/component_rswdt.h | 72 + .../include/same70/component/component_rtc.h | 234 + .../include/same70/component/component_rtt.h | 71 + .../include/same70/component/component_sdramc.h | 173 + .../include/same70/component/component_smc.h | 144 + .../include/same70/component/component_spi.h | 161 + .../include/same70/component/component_ssc.h | 280 + .../include/same70/component/component_supc.h | 295 + .../include/same70/component/component_tc.h | 346 + .../include/same70/component/component_trng.h | 73 + .../include/same70/component/component_twihs.h | 250 + .../include/same70/component/component_uart.h | 151 + .../include/same70/component/component_usart.h | 478 + .../include/same70/component/component_usbhs.h | 909 + .../include/same70/component/component_utmi.h | 63 + .../include/same70/component/component_wdt.h | 72 + .../include/same70/component/component_xdmac.h | 616 + .../libchip/include/same70/pio/pio_same70j19.h | 431 + .../libchip/include/same70/pio/pio_same70j20.h | 437 + .../libchip/include/same70/pio/pio_same70j21.h | 437 + .../libchip/include/same70/pio/pio_same70n19.h | 495 + .../libchip/include/same70/pio/pio_same70n20.h | 495 + .../libchip/include/same70/pio/pio_same70n21.h | 495 + .../libchip/include/same70/pio/pio_same70q19.h | 668 + .../libchip/include/same70/pio/pio_same70q20.h | 668 + .../libchip/include/same70/pio/pio_same70q21.h | 668 + .../atsam/include/libchip/include/same70/same70.h | 55 + .../include/libchip/include/same70/same70j19.h | 623 + .../include/libchip/include/same70/same70j20.h | 630 + .../include/libchip/include/same70/same70j21.h | 630 + .../include/libchip/include/same70/same70n19.h | 636 + .../include/libchip/include/same70/same70n20.h | 636 + .../include/libchip/include/same70/same70n21.h | 636 + .../include/libchip/include/same70/same70q19.h | 684 + .../include/libchip/include/same70/same70q20.h | 684 + .../include/libchip/include/same70/same70q21.h | 689 + .../include/libchip/include/same70/system_same70.h | 80 + .../include/sams70/component/component_acc.h | 128 + .../include/sams70/component/component_aes.h | 191 + .../include/sams70/component/component_afec.h | 483 + .../include/sams70/component/component_chipid.h | 123 + .../include/sams70/component/component_dacc.h | 184 + .../include/sams70/component/component_efc.h | 111 + .../include/sams70/component/component_gpbr.h | 53 + .../include/sams70/component/component_hsmci.h | 335 + .../include/sams70/component/component_icm.h | 192 + .../include/sams70/component/component_isi.h | 280 + .../include/sams70/component/component_matrix.h | 461 + .../include/sams70/component/component_pio.h | 1711 ++ .../include/sams70/component/component_pmc.h | 786 + .../include/sams70/component/component_pwm.h | 667 + .../include/sams70/component/component_qspi.h | 216 + .../include/sams70/component/component_rstc.h | 79 + .../include/sams70/component/component_rswdt.h | 72 + .../include/sams70/component/component_rtc.h | 234 + .../include/sams70/component/component_rtt.h | 71 + .../include/sams70/component/component_sdramc.h | 173 + .../include/sams70/component/component_smc.h | 144 + .../include/sams70/component/component_spi.h | 161 + .../include/sams70/component/component_ssc.h | 280 + .../include/sams70/component/component_supc.h | 295 + .../include/sams70/component/component_tc.h | 346 + .../include/sams70/component/component_trng.h | 73 + .../include/sams70/component/component_twihs.h | 250 + .../include/sams70/component/component_uart.h | 151 + .../include/sams70/component/component_usart.h | 478 + .../include/sams70/component/component_usbhs.h | 905 + .../include/sams70/component/component_utmi.h | 63 + .../include/sams70/component/component_wdt.h | 72 + .../include/sams70/component/component_xdmac.h | 616 + .../libchip/include/sams70/pio/pio_sams70j19.h | 406 + .../libchip/include/sams70/pio/pio_sams70j20.h | 407 + .../libchip/include/sams70/pio/pio_sams70j21.h | 407 + .../libchip/include/sams70/pio/pio_sams70n19.h | 464 + .../libchip/include/sams70/pio/pio_sams70n20.h | 463 + .../libchip/include/sams70/pio/pio_sams70n21.h | 463 + .../libchip/include/sams70/pio/pio_sams70q19.h | 637 + .../libchip/include/sams70/pio/pio_sams70q20.h | 637 + .../libchip/include/sams70/pio/pio_sams70q21.h | 637 + .../atsam/include/libchip/include/sams70/sams70.h | 55 + .../include/libchip/include/sams70/sams70j19.h | 610 + .../include/libchip/include/sams70/sams70j20.h | 610 + .../include/libchip/include/sams70/sams70j21.h | 610 + .../include/libchip/include/sams70/sams70n19.h | 616 + .../include/libchip/include/sams70/sams70n20.h | 616 + .../include/libchip/include/sams70/sams70n21.h | 616 + .../include/libchip/include/sams70/sams70q19.h | 664 + .../include/libchip/include/sams70/sams70q20.h | 664 + .../include/libchip/include/sams70/sams70q21.h | 664 + .../include/libchip/include/sams70/system_sams70.h | 77 + .../include/samv71/component/component_acc.h | 135 + .../include/samv71/component/component_aes.h | 198 + .../include/samv71/component/component_afec.h | 490 + .../include/samv71/component/component_chipid.h | 123 + .../include/samv71/component/component_dacc.h | 191 + .../include/samv71/component/component_efc.h | 118 + .../include/samv71/component/component_gmac.h | 1246 + .../include/samv71/component/component_gpbr.h | 53 + .../include/samv71/component/component_hsmci.h | 342 + .../include/samv71/component/component_icm.h | 224 + .../include/samv71/component/component_isi.h | 287 + .../include/samv71/component/component_matrix.h | 181 + .../include/samv71/component/component_mcan.h | 868 + .../include/samv71/component/component_mlb.h | 192 + .../include/samv71/component/component_pio.h | 1717 ++ .../include/samv71/component/component_pmc.h | 729 + .../include/samv71/component/component_pwm.h | 651 + .../include/samv71/component/component_qspi.h | 223 + .../include/samv71/component/component_rstc.h | 79 + .../include/samv71/component/component_rswdt.h | 72 + .../include/samv71/component/component_rtc.h | 241 + .../include/samv71/component/component_rtt.h | 71 + .../include/samv71/component/component_sdramc.h | 180 + .../include/samv71/component/component_smc.h | 151 + .../include/samv71/component/component_spi.h | 168 + .../include/samv71/component/component_ssc.h | 287 + .../include/samv71/component/component_supc.h | 302 + .../include/samv71/component/component_tc.h | 353 + .../include/samv71/component/component_trng.h | 80 + .../include/samv71/component/component_twihs.h | 264 + .../include/samv71/component/component_uart.h | 162 + .../include/samv71/component/component_usart.h | 485 + .../include/samv71/component/component_usbhs.h | 961 + .../include/samv71/component/component_utmi.h | 63 + .../include/samv71/component/component_wdt.h | 72 + .../include/samv71/component/component_xdmac.h | 625 + .../libchip/include/samv71/pio/pio_samv71j19.h | 441 + .../libchip/include/samv71/pio/pio_samv71j20.h | 442 + .../libchip/include/samv71/pio/pio_samv71j21.h | 442 + .../libchip/include/samv71/pio/pio_samv71n19.h | 499 + .../libchip/include/samv71/pio/pio_samv71n20.h | 498 + .../libchip/include/samv71/pio/pio_samv71n21.h | 498 + .../libchip/include/samv71/pio/pio_samv71q19.h | 672 + .../libchip/include/samv71/pio/pio_samv71q20.h | 672 + .../libchip/include/samv71/pio/pio_samv71q21.h | 672 + .../atsam/include/libchip/include/samv71/samv71.h | 58 + .../include/libchip/include/samv71/samv71j19.h | 637 + .../include/libchip/include/samv71/samv71j20.h | 637 + .../include/libchip/include/samv71/samv71j21.h | 637 + .../include/libchip/include/samv71/samv71n19.h | 643 + .../include/libchip/include/samv71/samv71n20.h | 643 + .../include/libchip/include/samv71/samv71n21.h | 643 + .../include/libchip/include/samv71/samv71q19.h | 691 + .../include/libchip/include/samv71/samv71q20.h | 691 + .../include/libchip/include/samv71/samv71q21.h | 696 + .../include/libchip/include/samv71/system_samv71.h | 80 + bsps/arm/atsam/include/libchip/include/sdramc.h | 68 + bsps/arm/atsam/include/libchip/include/smc.h | 174 + bsps/arm/atsam/include/libchip/include/spi.h | 116 + bsps/arm/atsam/include/libchip/include/spi_dma.h | 146 + bsps/arm/atsam/include/libchip/include/ssc.h | 72 + bsps/arm/atsam/include/libchip/include/supc.h | 75 + bsps/arm/atsam/include/libchip/include/tc.h | 77 + bsps/arm/atsam/include/libchip/include/timetick.h | 101 + bsps/arm/atsam/include/libchip/include/trace.h | 231 + bsps/arm/atsam/include/libchip/include/trng.h | 50 + bsps/arm/atsam/include/libchip/include/twi.h | 114 + bsps/arm/atsam/include/libchip/include/twid.h | 140 + bsps/arm/atsam/include/libchip/include/uart.h | 68 + bsps/arm/atsam/include/libchip/include/uart_dma.h | 137 + bsps/arm/atsam/include/libchip/include/usart.h | 164 + bsps/arm/atsam/include/libchip/include/usart_dma.h | 137 + bsps/arm/atsam/include/libchip/include/usbhs.h | 1699 ++ bsps/arm/atsam/include/libchip/include/video.h | 79 + bsps/arm/atsam/include/libchip/include/wdt.h | 74 + .../libchip/include/xdma_hardware_interface.h | 58 + bsps/arm/atsam/include/libchip/include/xdmac.h | 640 + bsps/arm/atsam/include/libchip/include/xdmad.h | 253 + bsps/arm/atsam/include/tm27.h | 1 + bsps/arm/beagle/headers.am | 14 + bsps/arm/beagle/include/bsp.h | 364 + bsps/arm/beagle/include/bsp/bbb-gpio.h | 45 + bsps/arm/beagle/include/bsp/bbb-pwm.h | 178 + bsps/arm/beagle/include/bsp/beagleboneblack.h | 72 + bsps/arm/beagle/include/bsp/i2c.h | 211 + bsps/arm/beagle/include/bsp/irq.h | 23 + bsps/arm/beagle/include/tm27.h | 1 + bsps/arm/csb336/headers.am | 11 + bsps/arm/csb336/include/bsp.h | 68 + bsps/arm/csb336/include/bsp/irq.h | 95 + bsps/arm/csb336/include/mc9328mxl.h | 486 + bsps/arm/csb336/include/tm27.h | 1 + bsps/arm/csb337/headers.am | 21 + bsps/arm/csb337/include/at91rm9200.h | 344 + bsps/arm/csb337/include/at91rm9200_dbgu.h | 89 + bsps/arm/csb337/include/at91rm9200_emac.h | 160 + bsps/arm/csb337/include/at91rm9200_gpio.h | 401 + bsps/arm/csb337/include/at91rm9200_mem.h | 115 + bsps/arm/csb337/include/at91rm9200_pmc.h | 169 + bsps/arm/csb337/include/at91rm9200_usart.h | 146 + bsps/arm/csb337/include/bits.h | 48 + bsps/arm/csb337/include/bsp.h | 78 + bsps/arm/csb337/include/bsp/irq.h | 63 + bsps/arm/csb337/include/font8x16.h | 3615 +++ bsps/arm/csb337/include/sed1356.h | 52 + bsps/arm/csb337/include/sed1356_16bit.h | 566 + bsps/arm/csb337/include/tm27.h | 1 + bsps/arm/edb7312/headers.am | 11 + bsps/arm/edb7312/include/bsp.h | 72 + bsps/arm/edb7312/include/bsp/irq.h | 92 + bsps/arm/edb7312/include/ep7312.h | 218 + bsps/arm/edb7312/include/tm27.h | 1 + bsps/arm/gdbarmsim/headers.am | 11 + bsps/arm/gdbarmsim/include/bsp.h | 82 + bsps/arm/gdbarmsim/include/bsp/irq.h | 95 + bsps/arm/gdbarmsim/include/bsp/swi.h | 110 + bsps/arm/gdbarmsim/include/tm27.h | 1 + bsps/arm/gumstix/headers.am | 12 + bsps/arm/gumstix/include/bsp.h | 84 + bsps/arm/gumstix/include/bsp/irq.h | 29 + bsps/arm/gumstix/include/ffuart.h | 48 + bsps/arm/gumstix/include/pxa255.h | 128 + bsps/arm/gumstix/include/tm27.h | 1 + bsps/arm/headers.am | 45 + bsps/arm/imx/headers.am | 22 + .../arm/imx/include/arm/freescale/imx/imx_ccmvar.h | 64 + .../imx/include/arm/freescale/imx/imx_ecspireg.h | 111 + .../arm/imx/include/arm/freescale/imx/imx_gpcreg.h | 162 + .../arm/imx/include/arm/freescale/imx/imx_i2creg.h | 54 + .../imx/include/arm/freescale/imx/imx_iomuxreg.h | 61 + .../imx/include/arm/freescale/imx/imx_iomuxvar.h | 49 + .../arm/imx/include/arm/freescale/imx/imx_srcreg.h | 104 + .../imx/include/arm/freescale/imx/imx_uartreg.h | 174 + .../imx/include/arm/freescale/imx/imx_wdogreg.h | 62 + bsps/arm/imx/include/bsp.h | 84 + bsps/arm/imx/include/bsp/irq.h | 38 + bsps/arm/imx/include/tm27.h | 24 + bsps/arm/include/bsp/arm-a8core-start.h | 55 + bsps/arm/include/bsp/arm-a9mpcore-clock.h | 38 + bsps/arm/include/bsp/arm-a9mpcore-irq.h | 40 + bsps/arm/include/bsp/arm-a9mpcore-regs.h | 133 + bsps/arm/include/bsp/arm-a9mpcore-start.h | 172 + bsps/arm/include/bsp/arm-cp15-start.h | 187 + bsps/arm/include/bsp/arm-errata.h | 121 + bsps/arm/include/bsp/arm-gic-irq.h | 112 + bsps/arm/include/bsp/arm-gic-regs.h | 138 + bsps/arm/include/bsp/arm-gic-tm27.h | 103 + bsps/arm/include/bsp/arm-gic.h | 207 + bsps/arm/include/bsp/arm-pl011-regs.h | 130 + bsps/arm/include/bsp/arm-pl011.h | 51 + bsps/arm/include/bsp/arm-pl050-regs.h | 57 + bsps/arm/include/bsp/arm-pl050.h | 47 + bsps/arm/include/bsp/arm-pl111-fb.h | 44 + bsps/arm/include/bsp/arm-pl111-regs.h | 184 + bsps/arm/include/bsp/arm-release-id.h | 152 + bsps/arm/include/bsp/armv7m-irq.h | 36 + bsps/arm/include/bsp/linker-symbols.h | 167 + bsps/arm/include/bsp/lpc-dma.h | 221 + bsps/arm/include/bsp/lpc-emc.h | 170 + bsps/arm/include/bsp/lpc-i2s.h | 132 + bsps/arm/include/bsp/lpc-lcd.h | 213 + bsps/arm/include/bsp/lpc-timer.h | 159 + bsps/arm/include/bsp/start.h | 183 + bsps/arm/include/cmsis_gcc.h | 1373 + bsps/arm/include/core_cm7.h | 2512 ++ bsps/arm/include/core_cmFunc.h | 87 + bsps/arm/include/core_cmInstr.h | 87 + bsps/arm/include/core_cmSimd.h | 96 + bsps/arm/include/libcpu/am335x.h | 704 + bsps/arm/include/libcpu/mmu.h | 32 + bsps/arm/include/libcpu/omap3.h | 384 + bsps/arm/include/libcpu/omap_timer.h | 39 + bsps/arm/include/uart.h | 163 + bsps/arm/lm3s69xx/headers.am | 15 + bsps/arm/lm3s69xx/include/bsp.h | 52 + bsps/arm/lm3s69xx/include/bsp/io.h | 191 + bsps/arm/lm3s69xx/include/bsp/irq.h | 107 + bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h | 407 + bsps/arm/lm3s69xx/include/bsp/ssi.h | 43 + bsps/arm/lm3s69xx/include/bsp/syscon.h | 43 + bsps/arm/lm3s69xx/include/bsp/uart.h | 46 + bsps/arm/lm3s69xx/include/tm27.h | 1 + bsps/arm/lpc176x/headers.am | 30 + bsps/arm/lpc176x/include/bsp.h | 98 + bsps/arm/lpc176x/include/bsp/adc-defs.h | 96 + bsps/arm/lpc176x/include/bsp/adc.h | 60 + bsps/arm/lpc176x/include/bsp/can-defs.h | 183 + bsps/arm/lpc176x/include/bsp/can.h | 179 + bsps/arm/lpc176x/include/bsp/common-types.h | 118 + bsps/arm/lpc176x/include/bsp/dma.h | 98 + bsps/arm/lpc176x/include/bsp/gpio-defs.h | 218 + bsps/arm/lpc176x/include/bsp/io-defs.h | 142 + bsps/arm/lpc176x/include/bsp/io.h | 88 + bsps/arm/lpc176x/include/bsp/irq.h | 108 + bsps/arm/lpc176x/include/bsp/lpc-clock-config.h | 45 + bsps/arm/lpc176x/include/bsp/lpc-gpio.h | 100 + bsps/arm/lpc176x/include/bsp/lpc176x.h | 1585 ++ bsps/arm/lpc176x/include/bsp/mbed-pinmap.h | 50 + bsps/arm/lpc176x/include/bsp/pwmout-defs.h | 105 + bsps/arm/lpc176x/include/bsp/pwmout.h | 73 + bsps/arm/lpc176x/include/bsp/system-clocks.h | 91 + bsps/arm/lpc176x/include/bsp/timer-defs.h | 449 + bsps/arm/lpc176x/include/bsp/timer.h | 195 + bsps/arm/lpc176x/include/bsp/watchdog-defs.h | 65 + bsps/arm/lpc176x/include/bsp/watchdog.h | 70 + bsps/arm/lpc176x/include/tm27.h | 1 + bsps/arm/lpc24xx/headers.am | 21 + bsps/arm/lpc24xx/include/bsp.h | 128 + bsps/arm/lpc24xx/include/bsp/dma.h | 95 + bsps/arm/lpc24xx/include/bsp/i2c.h | 71 + bsps/arm/lpc24xx/include/bsp/io.h | 1154 + bsps/arm/lpc24xx/include/bsp/irq.h | 140 + bsps/arm/lpc24xx/include/bsp/lcd.h | 91 + bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h | 49 + bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h | 130 + bsps/arm/lpc24xx/include/bsp/lpc17xx.h | 207 + bsps/arm/lpc24xx/include/bsp/lpc24xx.h | 2206 ++ bsps/arm/lpc24xx/include/bsp/ssp.h | 47 + bsps/arm/lpc24xx/include/bsp/start-config.h | 121 + bsps/arm/lpc24xx/include/bsp/system-clocks.h | 89 + bsps/arm/lpc24xx/include/tm27.h | 1 + bsps/arm/lpc32xx/headers.am | 19 + bsps/arm/lpc32xx/include/bsp.h | 259 + bsps/arm/lpc32xx/include/bsp/boot.h | 114 + bsps/arm/lpc32xx/include/bsp/emc.h | 161 + bsps/arm/lpc32xx/include/bsp/hsu.h | 68 + bsps/arm/lpc32xx/include/bsp/i2c.h | 269 + bsps/arm/lpc32xx/include/bsp/irq.h | 179 + bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h | 59 + bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h | 98 + bsps/arm/lpc32xx/include/bsp/lpc32xx.h | 641 + bsps/arm/lpc32xx/include/bsp/mmu.h | 79 + bsps/arm/lpc32xx/include/bsp/nand-mlc.h | 422 + bsps/arm/lpc32xx/include/tm27.h | 72 + bsps/arm/raspberrypi/headers.am | 20 + bsps/arm/raspberrypi/include/bsp.h | 69 + bsps/arm/raspberrypi/include/bsp/fbcons.h | 47 + bsps/arm/raspberrypi/include/bsp/i2c.h | 95 + bsps/arm/raspberrypi/include/bsp/irq.h | 76 + bsps/arm/raspberrypi/include/bsp/mailbox.h | 32 + bsps/arm/raspberrypi/include/bsp/mmu.h | 68 + bsps/arm/raspberrypi/include/bsp/raspberrypi.h | 572 + bsps/arm/raspberrypi/include/bsp/rpi-fb.h | 55 + bsps/arm/raspberrypi/include/bsp/rpi-gpio.h | 70 + bsps/arm/raspberrypi/include/bsp/spi.h | 77 + bsps/arm/raspberrypi/include/bsp/usart.h | 43 + bsps/arm/raspberrypi/include/bsp/vc.h | 157 + bsps/arm/raspberrypi/include/tm27.h | 1 + bsps/arm/realview-pbx-a9/headers.am | 10 + bsps/arm/realview-pbx-a9/include/bsp.h | 67 + bsps/arm/realview-pbx-a9/include/bsp/irq.h | 102 + bsps/arm/realview-pbx-a9/include/tm27.h | 41 + bsps/arm/rtl22xx/headers.am | 11 + bsps/arm/rtl22xx/include/bsp.h | 226 + bsps/arm/rtl22xx/include/bsp/irq.h | 71 + bsps/arm/rtl22xx/include/lpc22xx.h | 475 + bsps/arm/rtl22xx/include/tm27.h | 1 + bsps/arm/smdk2410/headers.am | 14 + bsps/arm/smdk2410/include/bsp.h | 80 + bsps/arm/smdk2410/include/bsp/irq.h | 96 + bsps/arm/smdk2410/include/s3c2400.h | 676 + bsps/arm/smdk2410/include/s3c2410.h | 825 + bsps/arm/smdk2410/include/s3c24xx.h | 17 + bsps/arm/smdk2410/include/smc.h | 44 + bsps/arm/smdk2410/include/tm27.h | 1 + bsps/arm/stm32f4/headers.am | 29 + bsps/arm/stm32f4/include/bsp.h | 54 + bsps/arm/stm32f4/include/bsp/i2c.h | 96 + bsps/arm/stm32f4/include/bsp/io.h | 416 + bsps/arm/stm32f4/include/bsp/irq.h | 141 + bsps/arm/stm32f4/include/bsp/rcc.h | 196 + bsps/arm/stm32f4/include/bsp/stm32_i2c.h | 113 + bsps/arm/stm32f4/include/bsp/stm32_usart.h | 110 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h | 50 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h | 51 + bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h | 48 + bsps/arm/stm32f4/include/bsp/stm32f4.h | 258 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h | 320 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h | 64 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h | 83 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h | 39 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h | 445 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h | 47 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h | 289 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h | 108 + bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h | 206 + bsps/arm/stm32f4/include/bsp/usart.h | 45 + bsps/arm/stm32f4/include/tm27.h | 1 + bsps/arm/tms570/headers.am | 63 + bsps/arm/tms570/include/bsp.h | 42 + bsps/arm/tms570/include/bsp/irq.h | 160 + bsps/arm/tms570/include/bsp/system-clocks.h | 62 + bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h | 626 + bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h | 72 + bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h | 379 + bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h | 941 + bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h | 183 + bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h | 711 + bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h | 557 + bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h | 126 + bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h | 285 + bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h | 898 + bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h | 468 + bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h | 675 + bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h | 618 + bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h | 324 + bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h | 333 + bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h | 363 + bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h | 235 + bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h | 594 + bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h | 230 + bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h | 332 + bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h | 195 + bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h | 120 + bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h | 298 + bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h | 258 + bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h | 309 + bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h | 359 + bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h | 227 + bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h | 450 + bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h | 918 + bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h | 158 + bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h | 695 + bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h | 84 + bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h | 170 + bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h | 190 + bsps/arm/tms570/include/bsp/tms570-pinmux.h | 137 + bsps/arm/tms570/include/bsp/tms570-pins.h | 10 + bsps/arm/tms570/include/bsp/tms570-pom.h | 60 + bsps/arm/tms570/include/bsp/tms570-rti.h | 46 + bsps/arm/tms570/include/bsp/tms570-sci-driver.h | 65 + bsps/arm/tms570/include/bsp/tms570-sci.h | 45 + bsps/arm/tms570/include/bsp/tms570-vim.h | 48 + bsps/arm/tms570/include/bsp/tms570.h | 137 + bsps/arm/tms570/include/bsp/tms570_hwinit.h | 31 + bsps/arm/tms570/include/bsp/tms570_selftest.h | 214 + .../tms570/include/bsp/tms570_selftest_parity.h | 110 + bsps/arm/tms570/include/bsp/tms570lc4357-pins.h | 1114 + bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h | 690 + bsps/arm/tms570/include/tm27.h | 1 + bsps/arm/xilinx-zynq/headers.am | 15 + bsps/arm/xilinx-zynq/include/bsp.h | 80 + .../arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h | 73 + bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h | 35 + bsps/arm/xilinx-zynq/include/bsp/i2c.h | 50 + bsps/arm/xilinx-zynq/include/bsp/irq.h | 115 + bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h | 150 + bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h | 67 + bsps/arm/xilinx-zynq/include/tm27.h | 36 + 538 files changed, 221145 insertions(+) create mode 100644 bsps/arm/altera-cyclone-v/headers.am create mode 100644 bsps/arm/altera-cyclone-v/include/bsp.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/hwlib.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/irq.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h create mode 100644 bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h create mode 100644 bsps/arm/altera-cyclone-v/include/tm27.h create mode 100644 bsps/arm/atsam/headers.am create mode 100644 bsps/arm/atsam/include/bsp.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-clock-config.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-i2c.h create mode 100644 bsps/arm/atsam/include/bsp/atsam-spi.h create mode 100644 bsps/arm/atsam/include/bsp/i2c.h create mode 100644 bsps/arm/atsam/include/bsp/irq.h create mode 100644 bsps/arm/atsam/include/bsp/pin-config.h create mode 100644 bsps/arm/atsam/include/bsp/power.h create mode 100644 bsps/arm/atsam/include/bsp/sc16is752.h create mode 100644 bsps/arm/atsam/include/bsp/spi.h create mode 100644 bsps/arm/atsam/include/libchip/chip.h create mode 100644 bsps/arm/atsam/include/libchip/compiler.h create mode 100644 bsps/arm/atsam/include/libchip/include/acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/adc.h create mode 100644 bsps/arm/atsam/include/libchip/include/aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/afe_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/chip.h create mode 100644 bsps/arm/atsam/include/libchip/include/dac_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/exceptions.h create mode 100644 bsps/arm/atsam/include/libchip/include/flashd.h create mode 100644 bsps/arm/atsam/include/libchip/include/gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/gmacd.h create mode 100644 bsps/arm/atsam/include/libchip/include/hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/iso7816_4.h create mode 100644 bsps/arm/atsam/include/libchip/include/mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/mcid.h create mode 100644 bsps/arm/atsam/include/libchip/include/mediaLB.h create mode 100644 bsps/arm/atsam/include/libchip/include/mpu.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio_capture.h create mode 100644 bsps/arm/atsam/include/libchip/include/pio_it.h create mode 100644 bsps/arm/atsam/include/libchip/include/pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/pwmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/qspi_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/same70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/same70/system_same70.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h create mode 100644 bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h create mode 100644 bsps/arm/atsam/include/libchip/include/sdramc.h create mode 100644 bsps/arm/atsam/include/libchip/include/smc.h create mode 100644 bsps/arm/atsam/include/libchip/include/spi.h create mode 100644 bsps/arm/atsam/include/libchip/include/spi_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/ssc.h create mode 100644 bsps/arm/atsam/include/libchip/include/supc.h create mode 100644 bsps/arm/atsam/include/libchip/include/tc.h create mode 100644 bsps/arm/atsam/include/libchip/include/timetick.h create mode 100644 bsps/arm/atsam/include/libchip/include/trace.h create mode 100644 bsps/arm/atsam/include/libchip/include/trng.h create mode 100644 bsps/arm/atsam/include/libchip/include/twi.h create mode 100644 bsps/arm/atsam/include/libchip/include/twid.h create mode 100644 bsps/arm/atsam/include/libchip/include/uart.h create mode 100644 bsps/arm/atsam/include/libchip/include/uart_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/usart.h create mode 100644 bsps/arm/atsam/include/libchip/include/usart_dma.h create mode 100644 bsps/arm/atsam/include/libchip/include/usbhs.h create mode 100644 bsps/arm/atsam/include/libchip/include/video.h create mode 100644 bsps/arm/atsam/include/libchip/include/wdt.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdmac.h create mode 100644 bsps/arm/atsam/include/libchip/include/xdmad.h create mode 100644 bsps/arm/atsam/include/tm27.h create mode 100644 bsps/arm/beagle/headers.am create mode 100644 bsps/arm/beagle/include/bsp.h create mode 100644 bsps/arm/beagle/include/bsp/bbb-gpio.h create mode 100644 bsps/arm/beagle/include/bsp/bbb-pwm.h create mode 100644 bsps/arm/beagle/include/bsp/beagleboneblack.h create mode 100644 bsps/arm/beagle/include/bsp/i2c.h create mode 100644 bsps/arm/beagle/include/bsp/irq.h create mode 100644 bsps/arm/beagle/include/tm27.h create mode 100644 bsps/arm/csb336/headers.am create mode 100644 bsps/arm/csb336/include/bsp.h create mode 100644 bsps/arm/csb336/include/bsp/irq.h create mode 100644 bsps/arm/csb336/include/mc9328mxl.h create mode 100644 bsps/arm/csb336/include/tm27.h create mode 100644 bsps/arm/csb337/headers.am create mode 100644 bsps/arm/csb337/include/at91rm9200.h create mode 100644 bsps/arm/csb337/include/at91rm9200_dbgu.h create mode 100644 bsps/arm/csb337/include/at91rm9200_emac.h create mode 100644 bsps/arm/csb337/include/at91rm9200_gpio.h create mode 100644 bsps/arm/csb337/include/at91rm9200_mem.h create mode 100644 bsps/arm/csb337/include/at91rm9200_pmc.h create mode 100644 bsps/arm/csb337/include/at91rm9200_usart.h create mode 100644 bsps/arm/csb337/include/bits.h create mode 100644 bsps/arm/csb337/include/bsp.h create mode 100644 bsps/arm/csb337/include/bsp/irq.h create mode 100644 bsps/arm/csb337/include/font8x16.h create mode 100644 bsps/arm/csb337/include/sed1356.h create mode 100644 bsps/arm/csb337/include/sed1356_16bit.h create mode 100644 bsps/arm/csb337/include/tm27.h create mode 100644 bsps/arm/edb7312/headers.am create mode 100644 bsps/arm/edb7312/include/bsp.h create mode 100644 bsps/arm/edb7312/include/bsp/irq.h create mode 100644 bsps/arm/edb7312/include/ep7312.h create mode 100644 bsps/arm/edb7312/include/tm27.h create mode 100644 bsps/arm/gdbarmsim/headers.am create mode 100644 bsps/arm/gdbarmsim/include/bsp.h create mode 100644 bsps/arm/gdbarmsim/include/bsp/irq.h create mode 100644 bsps/arm/gdbarmsim/include/bsp/swi.h create mode 100644 bsps/arm/gdbarmsim/include/tm27.h create mode 100644 bsps/arm/gumstix/headers.am create mode 100644 bsps/arm/gumstix/include/bsp.h create mode 100644 bsps/arm/gumstix/include/bsp/irq.h create mode 100644 bsps/arm/gumstix/include/ffuart.h create mode 100644 bsps/arm/gumstix/include/pxa255.h create mode 100644 bsps/arm/gumstix/include/tm27.h create mode 100644 bsps/arm/headers.am create mode 100644 bsps/arm/imx/headers.am create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h create mode 100644 bsps/arm/imx/include/bsp.h create mode 100644 bsps/arm/imx/include/bsp/irq.h create mode 100644 bsps/arm/imx/include/tm27.h create mode 100644 bsps/arm/include/bsp/arm-a8core-start.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-clock.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-irq.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-regs.h create mode 100644 bsps/arm/include/bsp/arm-a9mpcore-start.h create mode 100644 bsps/arm/include/bsp/arm-cp15-start.h create mode 100644 bsps/arm/include/bsp/arm-errata.h create mode 100644 bsps/arm/include/bsp/arm-gic-irq.h create mode 100644 bsps/arm/include/bsp/arm-gic-regs.h create mode 100644 bsps/arm/include/bsp/arm-gic-tm27.h create mode 100644 bsps/arm/include/bsp/arm-gic.h create mode 100644 bsps/arm/include/bsp/arm-pl011-regs.h create mode 100644 bsps/arm/include/bsp/arm-pl011.h create mode 100644 bsps/arm/include/bsp/arm-pl050-regs.h create mode 100644 bsps/arm/include/bsp/arm-pl050.h create mode 100644 bsps/arm/include/bsp/arm-pl111-fb.h create mode 100644 bsps/arm/include/bsp/arm-pl111-regs.h create mode 100644 bsps/arm/include/bsp/arm-release-id.h create mode 100644 bsps/arm/include/bsp/armv7m-irq.h create mode 100644 bsps/arm/include/bsp/linker-symbols.h create mode 100644 bsps/arm/include/bsp/lpc-dma.h create mode 100644 bsps/arm/include/bsp/lpc-emc.h create mode 100644 bsps/arm/include/bsp/lpc-i2s.h create mode 100644 bsps/arm/include/bsp/lpc-lcd.h create mode 100644 bsps/arm/include/bsp/lpc-timer.h create mode 100644 bsps/arm/include/bsp/start.h create mode 100644 bsps/arm/include/cmsis_gcc.h create mode 100644 bsps/arm/include/core_cm7.h create mode 100644 bsps/arm/include/core_cmFunc.h create mode 100644 bsps/arm/include/core_cmInstr.h create mode 100644 bsps/arm/include/core_cmSimd.h create mode 100644 bsps/arm/include/libcpu/am335x.h create mode 100644 bsps/arm/include/libcpu/mmu.h create mode 100644 bsps/arm/include/libcpu/omap3.h create mode 100644 bsps/arm/include/libcpu/omap_timer.h create mode 100644 bsps/arm/include/uart.h create mode 100644 bsps/arm/lm3s69xx/headers.am create mode 100644 bsps/arm/lm3s69xx/include/bsp.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/io.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/irq.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/ssi.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/syscon.h create mode 100644 bsps/arm/lm3s69xx/include/bsp/uart.h create mode 100644 bsps/arm/lm3s69xx/include/tm27.h create mode 100644 bsps/arm/lpc176x/headers.am create mode 100644 bsps/arm/lpc176x/include/bsp.h create mode 100755 bsps/arm/lpc176x/include/bsp/adc-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/adc.h create mode 100755 bsps/arm/lpc176x/include/bsp/can-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/can.h create mode 100644 bsps/arm/lpc176x/include/bsp/common-types.h create mode 100644 bsps/arm/lpc176x/include/bsp/dma.h create mode 100644 bsps/arm/lpc176x/include/bsp/gpio-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/io-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/io.h create mode 100644 bsps/arm/lpc176x/include/bsp/irq.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc-gpio.h create mode 100644 bsps/arm/lpc176x/include/bsp/lpc176x.h create mode 100755 bsps/arm/lpc176x/include/bsp/mbed-pinmap.h create mode 100755 bsps/arm/lpc176x/include/bsp/pwmout-defs.h create mode 100755 bsps/arm/lpc176x/include/bsp/pwmout.h create mode 100644 bsps/arm/lpc176x/include/bsp/system-clocks.h create mode 100644 bsps/arm/lpc176x/include/bsp/timer-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/timer.h create mode 100644 bsps/arm/lpc176x/include/bsp/watchdog-defs.h create mode 100644 bsps/arm/lpc176x/include/bsp/watchdog.h create mode 100644 bsps/arm/lpc176x/include/tm27.h create mode 100644 bsps/arm/lpc24xx/headers.am create mode 100644 bsps/arm/lpc24xx/include/bsp.h create mode 100644 bsps/arm/lpc24xx/include/bsp/dma.h create mode 100644 bsps/arm/lpc24xx/include/bsp/i2c.h create mode 100644 bsps/arm/lpc24xx/include/bsp/io.h create mode 100644 bsps/arm/lpc24xx/include/bsp/irq.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lcd.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc17xx.h create mode 100644 bsps/arm/lpc24xx/include/bsp/lpc24xx.h create mode 100644 bsps/arm/lpc24xx/include/bsp/ssp.h create mode 100644 bsps/arm/lpc24xx/include/bsp/start-config.h create mode 100644 bsps/arm/lpc24xx/include/bsp/system-clocks.h create mode 100644 bsps/arm/lpc24xx/include/tm27.h create mode 100644 bsps/arm/lpc32xx/headers.am create mode 100644 bsps/arm/lpc32xx/include/bsp.h create mode 100644 bsps/arm/lpc32xx/include/bsp/boot.h create mode 100644 bsps/arm/lpc32xx/include/bsp/emc.h create mode 100644 bsps/arm/lpc32xx/include/bsp/hsu.h create mode 100644 bsps/arm/lpc32xx/include/bsp/i2c.h create mode 100644 bsps/arm/lpc32xx/include/bsp/irq.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h create mode 100644 bsps/arm/lpc32xx/include/bsp/lpc32xx.h create mode 100644 bsps/arm/lpc32xx/include/bsp/mmu.h create mode 100644 bsps/arm/lpc32xx/include/bsp/nand-mlc.h create mode 100644 bsps/arm/lpc32xx/include/tm27.h create mode 100644 bsps/arm/raspberrypi/headers.am create mode 100644 bsps/arm/raspberrypi/include/bsp.h create mode 100644 bsps/arm/raspberrypi/include/bsp/fbcons.h create mode 100644 bsps/arm/raspberrypi/include/bsp/i2c.h create mode 100644 bsps/arm/raspberrypi/include/bsp/irq.h create mode 100644 bsps/arm/raspberrypi/include/bsp/mailbox.h create mode 100644 bsps/arm/raspberrypi/include/bsp/mmu.h create mode 100644 bsps/arm/raspberrypi/include/bsp/raspberrypi.h create mode 100644 bsps/arm/raspberrypi/include/bsp/rpi-fb.h create mode 100644 bsps/arm/raspberrypi/include/bsp/rpi-gpio.h create mode 100644 bsps/arm/raspberrypi/include/bsp/spi.h create mode 100644 bsps/arm/raspberrypi/include/bsp/usart.h create mode 100644 bsps/arm/raspberrypi/include/bsp/vc.h create mode 100644 bsps/arm/raspberrypi/include/tm27.h create mode 100644 bsps/arm/realview-pbx-a9/headers.am create mode 100644 bsps/arm/realview-pbx-a9/include/bsp.h create mode 100644 bsps/arm/realview-pbx-a9/include/bsp/irq.h create mode 100644 bsps/arm/realview-pbx-a9/include/tm27.h create mode 100644 bsps/arm/rtl22xx/headers.am create mode 100644 bsps/arm/rtl22xx/include/bsp.h create mode 100644 bsps/arm/rtl22xx/include/bsp/irq.h create mode 100644 bsps/arm/rtl22xx/include/lpc22xx.h create mode 100644 bsps/arm/rtl22xx/include/tm27.h create mode 100644 bsps/arm/smdk2410/headers.am create mode 100644 bsps/arm/smdk2410/include/bsp.h create mode 100644 bsps/arm/smdk2410/include/bsp/irq.h create mode 100644 bsps/arm/smdk2410/include/s3c2400.h create mode 100644 bsps/arm/smdk2410/include/s3c2410.h create mode 100644 bsps/arm/smdk2410/include/s3c24xx.h create mode 100644 bsps/arm/smdk2410/include/smc.h create mode 100644 bsps/arm/smdk2410/include/tm27.h create mode 100644 bsps/arm/stm32f4/headers.am create mode 100644 bsps/arm/stm32f4/include/bsp.h create mode 100644 bsps/arm/stm32f4/include/bsp/i2c.h create mode 100644 bsps/arm/stm32f4/include/bsp/io.h create mode 100644 bsps/arm/stm32f4/include/bsp/irq.h create mode 100644 bsps/arm/stm32f4/include/bsp/rcc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32_i2c.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32_usart.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h create mode 100755 bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h create mode 100644 bsps/arm/stm32f4/include/bsp/usart.h create mode 100644 bsps/arm/stm32f4/include/tm27.h create mode 100644 bsps/arm/tms570/headers.am create mode 100644 bsps/arm/tms570/include/bsp.h create mode 100644 bsps/arm/tms570/include/bsp/irq.h create mode 100644 bsps/arm/tms570/include/bsp/system-clocks.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h create mode 100644 bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pinmux.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pins.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-pom.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-rti.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-sci-driver.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-sci.h create mode 100644 bsps/arm/tms570/include/bsp/tms570-vim.h create mode 100644 bsps/arm/tms570/include/bsp/tms570.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_hwinit.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_selftest.h create mode 100644 bsps/arm/tms570/include/bsp/tms570_selftest_parity.h create mode 100644 bsps/arm/tms570/include/bsp/tms570lc4357-pins.h create mode 100644 bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h create mode 100644 bsps/arm/tms570/include/tm27.h create mode 100644 bsps/arm/xilinx-zynq/headers.am create mode 100644 bsps/arm/xilinx-zynq/include/bsp.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/i2c.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/irq.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h create mode 100644 bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h create mode 100644 bsps/arm/xilinx-zynq/include/tm27.h (limited to 'bsps/arm') diff --git a/bsps/arm/altera-cyclone-v/headers.am b/bsps/arm/altera-cyclone-v/headers.am new file mode 100644 index 0000000000..f63ee38854 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/hwlib.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h +include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/irq.h + +include_bsp_socaldir = $(includedir)/bsp/socal +include_bsp_socal_HEADERS = +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h +include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h diff --git a/bsps/arm/altera-cyclone-v/include/bsp.h b/bsps/arm/altera-cyclone-v/include/bsp.h new file mode 100644 index 0000000000..4118823958 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H +#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 + +#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) + +#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) + +#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) + +#define BSP_ARM_L2C_310_BASE 0xfffef000 + +#define BSP_ARM_L2C_310_ID 0x410000c9 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h new file mode 100644 index 0000000000..bca6f63e00 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h @@ -0,0 +1,1555 @@ +/* + * Altera - SoC UART Manager + */ + +/***************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ALT_16550_UART_H__ +#define __ALT_16550_UART_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup UART UART Driver API + * + * This module defines the Universal Asynchronous Receiver/Transmitter (UART) + * API for accessing and using the UART resources. The API allows for general + * control of a 16550 compatible UART controller. + * + * This implementation can control the following UARTs: + * * SoCFPGA On-board UARTs + * * Altera 16550 Compatible Soft IP UART + * + * The following reference materials were used in the design of this API: + * * Synopsys® DesignWare DW_apb_uart Databook v3.10a + * + * @{ + */ + +/*! + * \addtogroup UART_BASIC UART Basic + * + * This group of APIs provides basic access to the UART to initialize, + * uninitialize, read, write, and reset the UART. + * + * @{ + */ + +/*! + * This type definition enumerates the list of UARTs available on the system. + */ +typedef enum ALT_16550_DEVICE_e +{ + /*! + * This option selects UART0 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART0 = 0, + + /*! + * This option selects UART1 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART1 = 1, + + /*! + * This option selects an Altera 16550 Compatible soft IP UART. The memory + * location of the device must be provided as part of the initialization. + */ + ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 +} +ALT_16550_DEVICE_t; + +/*! + * This structure is used to represent a handle to a specific UART on the + * system. The internal members are undocumented and should be not altered + * outside of this API. + */ +typedef struct ALT_16550_HANDLE_s +{ + ALT_16550_DEVICE_t device; + void * location; + alt_freq_t clock_freq; + uint32_t data; + uint32_t fcr; +} +ALT_16550_HANDLE_t; + +/*! + * Performs the initialization steps needed by the UART. This should be the + * first API call made when accessing a particular UART + * + * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 + * baud. + * + * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before + * initialization. + * + * \param device + * The UART device identifier. + * + * \param location + * The memory of the location for the given UART. For SoCFPGA + * UARTs, this parameter is ignored. + * + * \param clock_freq + * The clock frequency of the serial clock for the given UART. + * For SoCFPGA UARTs, this paramter is ignored. + * + * \param handle + * [out] A pointer to a handle that will represent the UART. This + * handle should subsequently be used when calling other UART + * APIs. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. + * \retval ALT_E_BAD_CLK The required clock is not yet setup. + */ +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle); + +/*! + * Performs the uninitialization steps for the UART. This should be the last + * API call made to cleanup the UART. + * + * After calling this function, the handle will need to be initialized again + * before being used by calling alt_16550_init(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); + +/*! + * Resets the UART to the default configuration. The UART will be reset and + * reinitialized. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); + +/*! + * Starts the UART after all configuration has been completed. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops the UART. While UART configuration can be done while enabled, it is + * not recommended. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads a single character from the UART receiver buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * [out] Pointer to an output parameter that contains the in + * receiver buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item); + +/*! + * Writes a single character to the UART transmitter buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * The character to write to the transmitter buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item); + +/*! + * @} + */ + +/*! + * \addtogroup UART_FIFO UART FIFO Interface + * + * This group of APIs provides access, configuration, and control of the UART + * FIFO. The FIFO allows the UART to buffer received data and data to be + * transmitted. + * + * @{ + */ + +/*! + * This type definition enumerates the receiver FIFO level conditions that + * will trigger the receiver FIFO to issue a receiver FIFO full event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_RX_e +{ + /*! + * 1 or more character(s) in the receiver FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_RX_ANY = 0, + + /*! + * 25% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, + + /*! + * 50% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, + + /*! + * 2 characters less than the receiver FIFO capacity will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_RX_t; + +/*! + * This type definition enumerates the transmitter FIFO level conditions that + * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_TX_e +{ + /*! + * Transmitter FIFO being completely empty will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, + + /*! + * 2 or less character(s) in the transmitter FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, + + /*! + * 25% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, + + /*! + * 50% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_TX_t; + +/*! + * Enables FIFO on the UART. This will enable both the receiver FIFO and + * transmitter FIFO. Both FIFOs will be cleared. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables FIFOs on the UART. This will disable both the receiver FIFO and + * transmitter FIFO. Any data left in the FIFOs will be lost. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the given buffer from the receiver FIFO in the UART. + * + * The available characters in the FIFO can be determined by a few ways. Users + * can determine the number of items by calling alt_16550_fifo_level_get_rx(). + * + * Another way is by using the RX trigger and RX interrupt. First determine the + * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired + * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the + * triggering point by applying trigger description on the FIFO size. Enable RX + * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires + * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering + * point value can be used to determine the RX FIFO level. If the interrupt + * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be + * completely emptied by repeatedly polling the Line Status + * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). + * These steps are necessary if the UART does not implement FIFO level query + * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible + * Soft UART. + * + * Reading more data than that which is available can result in invalid data + * appearing like valid data. + * + * The FIFO must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * [out] Pointer to a buffer where the specified count of + * characters from the receiver FIFO will be copied to. + * + * \param count + * The count of characters from the receiver FIFO to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count); + +/*! + * Writes the given buffer to the transmitter FIFO in the UART. + * + * The available space in the FIFO can be determined by a few ways. Users can + * determine the number of items by calculating the FIFO capacity minus the + * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and + * alt_16550_fifo_level_get_tx() respectively. + * + * Another way is by using the TX trigger and TX interrupt. First determine the + * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired + * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the + * triggering point by applying the trigger description on the FIFO size. + * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX + * interrupt fires, calculate the empty entries in the FIFO by subtracting the + * TX FIFO size and the calculated value. These steps are necessary if the UART + * does not implement FIFO level query functionality. As of 13.0sp1, this + * applies to the Altera 16550 Compatible Soft UART. + * + * Writing more data that there is space can result in data lost due to + * overflowing. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * Pointer to a buffer from where the specified count of + * characters will be copied to the transmitter FIFO. + * + * \param count + * The count of characters from the given buffer to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count); + +/*! + * Clears the contents of the receiver FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the transmitter FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the receiver and transmitter FIFO. Any characters + * which were previously contained on those FIFOs will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the size of the receiver FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the size of the transmitter FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the current level of the receiver FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_read(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Queries the current level of the transmitter FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_write(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Sets the receiver FIFO level which will trigger the receiver FIFO to issue + * receiver FIFO full event. For the list of available receiver FIFO trigger + * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the receiver FIFO which is needed to trigger a + * receiver FIFO full event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger); + +/*! + * Sets the transmitter FIFO level which will trigger the transmitter FIFO to + * transmitter FIFO empty event. For the list of available transmitter FIFO + * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the transmitter FIFO which is needed to trigger a + * transmitter FIFO empty event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger); + +/*! + * @} + */ + +/*! + * \addtogroup UART_BAUD UART Baudrate Interface + * + * This group of APIs allows for the configuration of the UART's baudrate + * generation related functions. + * + * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with + * the configured divisor. + * + * @{ + */ + +/*! + * This enumeration lists out the common baudrates used with modem and serial + * ports. Not every baudrate is available for the UART due to the limits of + * the serial clock frequency and divisor value. + */ +typedef enum ALT_16550_BAUDRATE_e +{ + ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ + ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ + ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ + ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ + ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ + ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ + ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ + ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ + ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ + ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ + ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ + ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ + ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ + ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ + ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ + ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ + ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ + ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ + ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ +} +ALT_16550_BAUDRATE_t; + +/*! + * Gets the baudrate for the UART. + * + * This is done by calculating the baudrate from the divisor and the serial + * clock. The reported baudrate may not correspond exactly to the request + * baudrate. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * [out] Pointer to an output paramter that contains the current + * baudrate of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate); + +/*! + * Sets the baudrate for the UART. This change will take effect when the UART + * moves from disabled to enabled. + * + * This is done by calculating the correct divisor using the request baudrate + * and the known serial clock. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * The requested baudrate for the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to + * limitations of the baudrate divisor and/or + * serial clock. + */ +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate); + +/*! + * Gets the baudrate divisor for the UART. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * [out] Pointer to an output parameter that contains the current + * divisor used for baudrate generation. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor); + +/*! + * Sets the baudrate divisor for the UART. This change will take effect when + * the UART moves from disabled to enabled. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * The specified divisor value to use for baudrate generation. + * Valid values are 1 - 65535. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the + * specified divisor is not supported by the + * UART. + */ +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor); + +/*! + * @} + */ + +/*! + * \addtogroup UART_INT UART Interrupt Interface + * + * This group of APIs provides access, configuration, and control of the + * UART interrupts. + * + * @{ + */ + +/*! + * This type definition enumerates the different interrupt conditions that can + * be generated by the UART controller. + * + * Interrupts are listed in highest to lowest priority order. + */ +typedef enum ALT_16550_INT_STATUS_e +{ + /*! + * This interrupt signals that a overrun, parity, or framing error + * occurred, or a break event occured. The interrupt is cleared by reading + * the line status by calling alt_16550_line_status_get() or by disabling + * line status interrupts by calling alt_16550_int_disable_line(). + */ + ALT_16550_INT_STATUS_LINE = 0x6, + + /*! + * This interrupt signals that some data is available to be read from the + * UART. The definition of some depends on whether FIFOs are enabled or + * not. + * + * If FIFOs are disabled, this interrupt signals that the receiver + * contains data. In this case, the interrupt is cleared by reading the + * data from the UART by calling alt_16550_read(). + * + * If FIFOs are enabled, this interrupt signals that the receiver FIFO + * level is above the receiver trigger level specified. In this case, the + * interrupt is cleared by reading a sufficiently large buffer from the + * receiver FIFO such that the FIFO is filled below the receiver trigger + * level specified by calling alt_16550_fifo_read() or by adjusting the + * receiver trigger level appropriately by calling + * alt_16550_fifo_trigger_set_rx(). + * + * In either case, this interrupt can also be cleared by disabling + * receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_DATA = 0x4, + + /*! + * This interrupt signals that data is available in the receiver FIFO and + * that there has been no activity with the receiver FIFO for the last 4 + * character frames. In essence, the receiver FIFO has temporarily settled + * thus it may be a good time to empty the receiver FIFO. This interrupt + * is only available if FIFOs are enabled. The interrupt is cleared by + * reading from the receiver FIFO by calling alt_16550_fifo_read() or by + * disabling receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, + + /*! + * This interrupt signals that the transmitter is idling. The definition + * of idling depends on whether FIFOs are enabled or not. + * + * If FIFOs are disabled, this interrupt signals that the transmitter + * shift register is empty. In this case, the interrupt is cleared by + * writing data to the UART by calling alt_16550_write(). + * + * If FIFO are enabled, this interrupt signals that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * the interrupt is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * In either case, this interrupt can also be cleared by disabling + * transmitter interrupts by calling alt_16550_int_disable_tx(). + */ + ALT_16550_INT_STATUS_TX_IDLE = 0x2, + + /*! + * Modem status interrupt pending. The interrupt is cleared by reading the + * modem status by calling alt_16550_modem_status_get() or by disabling + * modem status interrupts by calling alt_16550_int_disable_modem(). + */ + ALT_16550_INT_STATUS_MODEM = 0x0, + + /*! + * No interrupts pending. + */ + ALT_16550_INT_STATUS_NONE = 0x1 +} +ALT_16550_INT_STATUS_t; + +/*! + * Enables the receiver FIFO to generate interrupts. Enabling this interrupt + * allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_RX_DATA + * * ALT_16550_INT_STATUS_RX_TIMEOUT + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the transmitter FIFO to generate interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_TX_IDLE + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the transmitter FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the receiver to generate line status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_LINE + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver from generating line status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the UART to generate modem status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_MODEM + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the UART from generate modem status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables all interrupts on the UART. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the interrupt status of the UART. This returns the highest priority + * interrupt pending. The appropriate interrupts must be enabled for them be + * generated in the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * interrupt status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_MODEM UART Modem Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Modem interface. + * + * @{ + */ + +/*! + * This type definition enumerates the set of UART modem status conditions as + * register mask values. + */ +typedef enum ALT_16550_MODEM_STATUS_e +{ + /*! + * Data Carrier Detect. This status indicates that the carrier has been + * detected by the modem. It corresponds to an inverted dcd_n input. DCD + * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DCD = 1 << 7, + + /*! + * Ring Indicator. This status indicates that the telephone ringing signal + * has been redeived by the modem. It corresponds to an inverted ri_n + * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is + * logic 0. + */ + ALT_16550_MODEM_STATUS_RI = 1 << 6, + + /*! + * Data Set Ready. This status indicates that the modem is ready to + * establish communications with the UART. It corresponds to an inverted + * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when + * dsr_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DSR = 1 << 5, + + /*! + * Clear To Send. This status indicates the current state of the modem + * cts_n line. It corresponds to an inverted cts_n input. CTS is + * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. + */ + ALT_16550_MODEM_STATUS_CTS = 1 << 4, + + /*! + * Delta Data Carrier Detect. This status condition indicates that the + * Data Carrier Detect has changed since the last time the modem status + * was read. Reading the modem status clears this status. For more + * information about the Data Carrier Detect status, see + * ALT_16550_MODEM_STATUS_DCD. + */ + ALT_16550_MODEM_STATUS_DDCD = 1 << 3, + + /*! + * Trailing Edge of Ring Indicator. This status indicates that the Ring + * Indicator has changed from asserted to unasserted. Reading the modem + * status will clear this status. For more information about the Ring + * Indicator status, reference ALT_16550_MODEM_STATUS_RI. + */ + ALT_16550_MODEM_STATUS_TERI = 1 << 2, + + /*! + * Delta Data Set Ready. This status condition indicates that the Data Set + * Ready has changed since the last time the modem status was read. + * Reading the modem status will clear this status. For more information + * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. + */ + ALT_16550_MODEM_STATUS_DDSR = 1 << 1, + + /*! + * Delta Clear To Send. This status condition indicates that the Clear To + * Send has changed since the last time the modem status was read. Reading + * the modem status will clear this status. For more information about the + * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. + */ + ALT_16550_MODEM_STATUS_DCTS = 1 << 0 +} +ALT_16550_MODEM_STATUS_t; + +/*! + * Enables automatic flow control in the UART modem. When in this mode, the + * rts_n is gated with the threshold trigger condition of the receiver FIFO. + * + * The Altera 16550 Compatible Soft IP UART may not have this option enabled. + * + * The FIFOs must be enabled for flow control to be used. + * + * The recommended bring up for flow control is as follows: + * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). + * This will allow both the receiver FIFO and user RTS to control the rts_n + * output. Because the user RTS is not enabled, the rts_n will be inactive + * high. + * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the + * receiver FIFO to have full control of the rts_n output. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables automatic flow control in the UART modem. + * + * The recommended bring down for flow control is as follows: + * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable + * generation of the rts_n ouput. + * * Disable automatic flow control by calling + * alt_16550_flowcontrol_disable(). + * + * The receiver FIFO will still be active after these steps. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Puts the UART in loopback mode. This is used for diagnostic and test + * purposes. + * + * The SoCFPGA UARTs does not support automatic flow control when in loopback + * mode. + * + * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and + * later. Setting this has no effect with 13.0. + * + * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are + * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) + * are held inactive high externally and internally looped back to the inputs. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Takes the UART out of loopback mode. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. RTS is used to inform the modem that the UART is ready to receive + * data. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. DTR is used to inform the modem that UART is ready to + * establish communications. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the modem status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * modem status of the UART as a register mask. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_LINE UART Line Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Line interface. + * + * @{ + */ + +/*! + * This type definition enumerates the supported databits per frame. + */ +typedef enum ALT_16550_DATABITS_e +{ + /*! + * This option selects 5 databits per frame. + */ + ALT_16550_DATABITS_5 = 0, + + /*! + * This option selects 6 databits per frame. + */ + ALT_16550_DATABITS_6 = 1, + + /*! + * This option selects 7 databits per frame. + */ + ALT_16550_DATABITS_7 = 2, + + /*! + * This option selects 8 databits per frame. + */ + ALT_16550_DATABITS_8 = 3 +} +ALT_16550_DATABITS_t; + +/*! + * This type definition enumerates the supported stopbits per frame. + */ +typedef enum ALT_16550_STOPBITS_e +{ + /*! + * This options specifies 1 stopbit per frame. + */ + ALT_16550_STOPBITS_1 = 0, + + /*! + * This options specifies 2 stopbits per frame. If the frame is + * configured with 5 databits, 1.5 stopbits is used instead. + */ + ALT_16550_STOPBITS_2 = 1 +} +ALT_16550_STOPBITS_t; + +/*! + * This type definition enumerates the possible parity to use per frame. + */ +typedef enum ALT_16550_PARITY_e +{ + /*! + * This option disables the parity error detection bit in the data frame. + */ + ALT_16550_PARITY_DISABLE = 0, + + /*! + * This option enables the odd parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_ODD = 1, + + /*! + * This option enables the even parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_EVEN = 2 +} +ALT_16550_PARITY_t; + +/*! + * This type definition enumerates the set of UART line status conditions as + * register mask values. + */ +typedef enum ALT_16550_LINE_STATUS_e +{ + /*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ + ALT_16550_LINE_STATUS_RFE = 1 << 7, + + /*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ + ALT_16550_LINE_STATUS_TEMT = 1 << 6, + + /*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ + ALT_16550_LINE_STATUS_THRE = 1 << 5, + + /*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). + * + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ + ALT_16550_LINE_STATUS_BI = 1 << 4, + + /*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). + * + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ + ALT_16550_LINE_STATUS_FE = 1 << 3, + + /*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. + * + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ + ALT_16550_LINE_STATUS_PE = 1 << 2, + + /*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. + * + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. + * + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. + */ + ALT_16550_LINE_STATUS_OE = 1 << 1, + + /*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ + ALT_16550_LINE_STATUS_DR = 1 << 0 +} +ALT_16550_LINE_STATUS_t; + +/*! + * Sets the configuration for a given character frame. + * + * \param handle + * The UART device handle. + * + * \param databits + * The number of databits for each character frame. + * + * \param parity + * The parity to use for each character frame. + * + * \param stopbits + * The number of stopbits for each character frame. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits); + +/*! + * Starts transmitting a break condition by transmitting a logic 0 state + * longer than a frame would normally be transmitted. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops transmitting a break condition. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the line status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * line status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_16550_UART_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h new file mode 100644 index 0000000000..781cc49aa3 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h @@ -0,0 +1,825 @@ +/*! \file + * Altera - SoC FPGA Address Space Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ + +#include +#include "hwlib.h" +#include "socal/hps.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +// ARM Level 2 Cache Controller L2C-310 Register Interface + +// Address Filtering Start Register +// The Address Filtering Start Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_start | Address filtering start address for +// | | bits [31:20] of the filtering address. +// [19:1] | Reserved | SBZ/RAZ +// [0] | address_filtering_enable | 0 - address filtering disabled +// | | 1 - address filtering enabled. + +// Address Filtering Start Register Address +#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00 +#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST) +// Address Filtering Start Register - Start Value Mask +#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000 +// Address Filtering Start Register - Reset Start Address Value (1 MB) +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +// Address Filtering Start Register - Enable Flag Mask +#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001 +// Address Filtering Start Register - Reset Enable Flag Value (Enabled) +#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1 + +// Address Filtering End Register +// The Address Filtering End Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_end | Address filtering end address for bits +// | | [31:20] of the filtering address. +// [19:0] | Reserved | SBZ/RAZ + +// Address Filtering End Register Address +#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04 +#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) +// Address Filtering End Register - End Value Mask +#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 +// Address Filtering End Register - Reset End Address Value (3 GiB) +#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager + * + * This module contains group APIs for managing the HPS address space. This + * module contains group APIs to manage: + * * Memory Map Control + * * Memory Coherence + * * Cache Managment + * * MMU Managment + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control + * + * This group API provides functions to map and remap selected address ranges + * into the accessible (visible) views of the MPU and non MPU address spaces. + * + * \b Caveats + * + * \b NOTE: Caution should be observed when remapping address 0 to different + * memory. The code performing the remapping operation should not be executing + * in the address range being remapped to different memory. + * + * For example, if address 0 is presently mapped to OCRAM and the code is + * preparing to remap address 0 to SDRAM, then the code must not be executing in + * the range 0 to 64 KB as this address space is about to be remapped to + * different memory. If the code performing the remap operation is executing + * from OCRAM then it needs to be executing from its permanently mapped OCRAM + * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR). + * + * \b NOTE: The MPU address space view is controlled by two disparate hardware + * control interfaces: the L3 remap register and the L2 cache address filtering + * registers. To complicate matters, the L3 remap register is write-only which + * means not only that current remap register state cannot be read but also that + * a read-modify-write operation cannot be performed on the register. + * + * This should not present a problem in most use case scenarios except for the + * case where a current MPU address space mapping of 0 to SDRAM is being changed + * to to a mapping of 0 to Boot ROM or OCRAM. + * + * In this case, a two step process whereby the L3 remap register is first set + * to the new desired MPU address 0 mapping and then the L2 cache address + * filtering registers have their address ranges adjusted accordingly must be + * followed. An example follows: +\verbatim +// 1 MB reset default value for address filtering start +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +uint32_t addr_filt_start; +uint32_t addr_filt_end; + +// Perform L3 remap register programming first by setting the desired new MPU +// address space 0 mapping. Assume OCRAM for the example. +alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...); + +// Next, adjust the L2 cache address filtering range. Set the start address to +// the default reset value and retain the existing end address configuration. +alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end); +if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET) +{ + alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end); +} +\endverbatim + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the MPU address space attributes. + * + * The MPU address space consists of the ARM Cortex A9 processors and associated + * processor peripherals (cache, MMU). + */ +typedef enum ALT_ADDR_SPACE_MPU_ATTR_e +{ + ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address + * 0x0 for the MPU L3 master. Note + * that the Boot ROM is also + * always mapped to address + * 0xfffd_0000 for the MPU L3 + * master independent of + * attribute. + */ + + ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the MPU L3 master. Note + * that the On-chip RAM is also + * always mapped to address + * 0xffff_0000 for the MPU L3 + * master independent of this + * attribute. + */ +} ALT_ADDR_SPACE_MPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the non-MPU address space attributes. + * + * The non-MPU address space consists of the non-MPU L3 masters including the + * DMA controllers (standalone and those built into peripherals), the F2H AXI + * Bridge, and the DAP. + */ +typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e +{ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 + * for the non-MPU L3 masters. + */ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the non-MPU L3 + * masters. Note that the On-chip + * RAM is also always mapped to + * address 0xffff_0000 for the + * non-MPU L3 masters independent + * of this attribute. + */ +} ALT_ADDR_SPACE_NONMPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the HPS to FPGA bridge accessiblity + * attributes. + */ +typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the Lightweight HPS to FPGA bridge + * accessiblity attributes. + */ +typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * Configures the mapped and accessible (visible) address ranges for the HPS + * MPU, non-MPU, and Bridge address spaces. + * + * \param mpu_attr + * The MPU address space configuration attributes. + * + * \param nonmpu_attr + * The non-MPU address space configuration attributes. + * + * \param h2f_attr + * The H2F Bridge attribute mapping and accessibility attributes. + * + * \param lwh2f_attr + * The Lightweight H2F Bridge attribute mapping and accessibility + * attributes. + * + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_INV_OPTION One or more invalid attribute options were + * specified. + */ +ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, + ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, + ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, + ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr); + +/******************************************************************************/ +/*! + * Maps SDRAM to address 0x0 for the MPU address space view. + * + * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest + * 64KB of the boot region are accessible because the size of the Boot ROM and + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not + * accessible to the MPU unless address 0 is remapped to SDRAM after reset. + * + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access + * SDRAM. + * + * \internal + * The remap to address 0x0 is achieved by configuring the L2 cache Address + * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM + * AXI (M1) master port by calling: + * + * alt_l2_addr_filter_cfg_set(0x0, ); + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering . + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter + * + * The L2 cache address filter controls where physical addresses within certain + * ranges of the MPU address space are directed. + * + * The L2 cache has master port connections to the L3 interconnect and the SDRAM + * controller. A programmable address filter controls which portions of the + * 32-bit physical address space use each master. + * + * When l2 address filtering is configured and enabled, a physical address will + * be redirected to one master or the other based upon the address filter + * configuration. + * + * If \b address_filter_start <= \e physical_address < \b address_filter_end: + * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller) + * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect) + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering for more information. + * @{ + */ + +/******************************************************************************/ +/*! + * Get the L2 cache address filtering configuration settings. + * + * \param addr_filt_start + * [out] An output parameter variable for the address filtering + * start address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \param addr_filt_end + * [out] An output parameter variable for the address filtering + * end address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start + * or \e addr_filt_end or both are invalid addresses. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, + uint32_t* addr_filt_end); + +/******************************************************************************/ +/*! + * Set the L2 cache address filtering configuration settings. + * + * Address filtering start and end values must be 1 MiB aligned. + * + * \param addr_filt_start + * The address filtering start address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \param addr_filt_end + * The address filtering end address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more address arguments do not satisfy the argument + * constraints. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, + uint32_t addr_filt_end); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where Output ID is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: Chapter 6: Cortex-A9 Microprocessor Unit Subsystem in + * Volume 3: Hard Processor System Technical Reference Manual of the + * Arria V or Cyclone V Device Handbook for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a (var)\ + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + +/*! @} */ + +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h new file mode 100644 index 0000000000..8d088ab744 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup CACHE_MGR Cache Management API + * + * This module defines the cache management API for enabling and disabling L1 + * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 + * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform + * cache maintenance operations on these caches. This includes the following + * operations: + * * Invalidate: Marks the cache line as being invalid, freeing up the space + * to cache other data. All APIs which enable caches invalidates the memory + * before being enabling the cache. + * * Clean: If the cache line is dirty, it synchronizes the cache line data + * with the upper level memory system and marks that line as clean. All APIs + * which disable caches cleans the memory before disabling the cache. + * * Purge: A term used in this API as a short form for clean and invalidate. + * This operation cleans and invalidates a cache line in that order, as a + * single command to the cache controller. + * + * The following reference materials were used in the design of this API: + * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore Technical Reference Manual + * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference + * Manual + * + * @{ + */ + +/*! + * \addtogroup CACHE_SYS System Level Cache Management API + * + * This API group provides cache maintenance operations which affects multiple + * cache levels. + * + * The enable and disable functions enables and disables all caches in the + * system respectively. For caches shared by the CPU core(s), particularly the + * L2 cache, once that cache is enabled or disabled it will not be invalidated + * or cleaned again respectively. This allows the safe system-wide enable and + * disable to be used in single-core and multi-core scenarios. + * + * For cache maintenance operations, this API implements the procedures + * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, + * subsection "System cache maintenance considerations". This allows for a + * convenient way to invalidate, clean, or clean and invalidate cache data from + * the L1 to L2 to L3 while avoiding any potential race conditions in + * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is + * set in "non-exclusive" mode. This means a segment of data can reside in both + * the L1 and L2 simultaneously. This is the default mode for caches in the + * system. + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * @{ + */ + +/*! + * Enables support for a non-flat virtual memory. A flat virtual memory is + * where every virtual address matches exactly to the physical address, making + * the virtual to physical translation trivial. Adding support for non-flat + * adds some overhead for the VA to PA translation and error detection. + * + * To enable non-flat virtual memory support, defined + * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling + * HWLibs. + */ +#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY +#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) +#endif + +/*! + * This is the system wide cache line size, given in bytes. + */ +#define ALT_CACHE_LINE_SIZE 32 + +/*! + * Enables all caches and features which improve reliability and speed on all + * cache controllers visible to the current CPU core. This includes parity + * error detection. Cache controllers visible to multiple CPU cores, for + * example the L2, will first be checked to be disabled before being enabled. + * All necessary cache maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_enable(void); + +/*! + * Disables all cache controllers visible to the current CPU core. Cache + * controllers visible to multiple CPU cores, for example the L2, will first + * be checked to be enabled before being disabled. All necessary cache + * maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_disable(void); + +/*! + * Invalidates the specified contents of all cache levels visible to the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L2 invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); + +/*! + * Cleans the specified contents of all cache levels visible to the current + * CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean address(es) + * -# L2 cache sync + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the specified contents of all cache levels visible + * to the current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean and invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L1 L1 Cache Management API + * + * This API group provides functions to interact with various components of the + * L1 cache on the SoCFPGA. This includes the following cache components: + * * Instruction Cache + * * Data Cache + * * Parity error detection + * * Dynamic branch prediction + * * Data prefetching + * + * The API within this group only affects the L1 cache on the current CPU. To + * interact the L1 cache on another CPU, the API must be called from that other + * CPU. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Enables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_enable_all(void); + +/*! + * Disables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_disable_all(void); + +/*! + * Enables the L1 instruction cache on the current CPU core. If the cache is + * already enabled, nothing is done. Otherwise the instruction cache is first + * invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); + +/*! + * Disables the L1 instruction cache on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); + +/*! + * Returns \b true when the L1 instruction cache is enabled and \b false when + * it is disabled on the current CPU core. + * + * \retval true The L1 instruction cache is enabled. + * \retval false The L1 instruction cache is disabled. + */ +bool alt_cache_l1_instruction_is_enabled(void); + +/*! + * Invalidates the contents of the L1 instruction cache on the current CPU + * core. + * + * Normally this is done automatically as part of + * alt_cache_l1_instruction_enable(), but in certain circumstances it may be + * necessary to invalidate it manually. An example of this situation is when + * the address space is remapped and the processor executes instructions from + * the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); + +/*! + * Enables the L1 data cache on the current CPU core. + * + * If the cache is already enabled nothing is done. Otherwise the data cache is + * first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_enable(void); + +/*! + * Disables the L1 data cache on the current CPU core. + * + * If the cache is already disabled nothing is done. Otherwise the data cache + * is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_disable(void); + +/*! + * Returns \b true when the L1 data cache is enabled and \b false when it is + * disabled on the current CPU core. + * + * \retval true The L1 data cache is enabled. + * \retval false The L1 data cache is disabled. + */ +bool alt_cache_l1_data_is_enabled(void); + +/*! + * Invalidates the specified contents of the L1 data cache on the current CPU + * core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); + +/*! + * Invalidates the entire contents of the L1 data cache on the current CPU + * core. + * + * Normally this is done automatically as part of alt_cache_l1_data_enable(), + * but in certain circumstances it may be necessary to invalidate it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); + +/*! + * Cleans the specified contents of the L1 data cache on the current CPU core + * for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); + +/*! + * Cleans the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L1 data cache on the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * Normally this is done automatically as part of alt_cache_l1_data_disable(), + * but in certain circumstances it may be necessary to purged it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); + +/*! + * Enables the parity error detection feature in the L1 caches on the current + * CPU core. + * + * Ideally parity should be enabled before any L1 caches are enabled. If the + * instruction, data, and / or dynamic branch predictor caches are already + * enabled, they will first be cleaned (if needed) and disabled before parity + * is enabled in hardware. Afterwards, the affected caches will be invalidated + * and enabled. + * + * Parity and TLB interaction deserves special attention. The TLB is considered + * to be a L1 cache but is enabled when the MMU, which is grouped in another + * API, is enabled. Due to the system-wide influence of the MMU, it cannot be + * disabled and enabled with impunity as the other L1 caches, which are + * designed to operate as transparently as possible. Thus parity error + * detection must be enabled before the L1 TLB cache, and by extension the MMU, + * is enabled. + * + * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt + * for the current CPU core must be enabled using the interrupt controller API. + * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error + * is detected while the other PARITYFAIL interrupts are for parity errors in a + * specific memory. Refer to the interrupt controller API for more details + * about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate CPU parity + * interrupt will be raised. CPU parity interrupts are all edge triggered and + * are cleared by acknowledging them in the interrupt controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_enable(void); + +/*! + * Disables parity error detection in the L1 caches. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled on the current CPU core. + * + * \retval true Parity error detection for L1 caches is + * enabled. + * \retval false Parity error detection for L1 caches is + * disabled. + */ +bool alt_cache_l1_parity_is_enabled(void); + +/*! + * Enables the dynamic branch predictor features on the current CPU core. + * + * This operation enables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). Affected caches are automatically + * invalidated before use. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_enable(void); + +/*! + * Disables the dynamic branch predictor features on the current CPU core. + * + * This operation disables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_disable(void); + +/*! + * Returns \b true when both the dynamic predictor features are enabled and + * \b false when they are disabled on the current CPU core. + * + * \retval true The L1 branch predictor caches are all enabled. + * \retval false Some or all L1 branch predictor caches are + * disabled. + */ +bool alt_cache_l1_branch_is_enabled(void); + +/*! + * Invalidates the dynamic branch predictor feature caches on the current CPU + * core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); + +/*! + * Enables the L1 cache data prefetch feature on the current CPU core. + * + * This allows data to be prefetched into the data cache before it is to be + * used. For example in a loop the current iteration may want to preload the + * data which will be used in the next teration. This is done by using the PLD + * instructions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); + +/*! + * Disables the L1 cache data prefetch feature on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); + +/*! + * Returns \b true if the L1 cache data prefetch feature is enabled and + * \b false if it is disabled on the current CPU core. + * + * \retval true The L1 data cache prefetch feature is enabled. + * \retval false The L1 data cache prefetch feature is disabled. + */ +bool alt_cache_l1_prefetch_is_enabled(void); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L2 L2 Cache Management API + * + * This API group provides functions to interact with various features of the + * L2 cache on the SoCFPGA. This includes the following features: + * * L2 cache + * * Parity error detection + * * Data prefetching + * * Interrupt Management + * + * \internal + * Additional features that may be implemented in the future: + * * Lockdown + * * Event counter + * \endinternal + * + * The API within this group affects the L2 cache which is visible to all CPUs + * on the system. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Initializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_init(void); + +/*! + * Uninitializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_uninit(void); + +/*! + * Enables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); + +/*! + * Disables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); + +/*! + * Returns \b true if either L2 cache data or instruction prefetch features are + * enabled and \b false if no prefetching features are enabled. + * + * \retval true The L2 data and instruction prefetch features + * are enabled. + * \retval false Some L2 data and instruction prefetch features + * are disabled. + */ +bool alt_cache_l2_prefetch_is_enabled(void); + +/*! + * Enables parity error detection in the L2 cache. + * + * Ideally parity should be enabled before the L2 cache is enabled. If the + * cache is already enabled, it will first be cleaned and disabled before + * parity is enabled in hardware. Afterwards, the cache will be invalidated and + * enabled. + * + * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or + * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is + * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt + * must be enabled using the interrupt controller API. Refer to the interrupt + * controller API for more details about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate L2 cache parity + * interrupt will be raised. To clear the parity interrupt(s), the appropriate + * L2 cache parity interrupt must be cleared by calling + * alt_cache_l2_int_status_clear(). + * + * For ECC support, refer to the ECC related API documentation for more + * information. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_enable(void); + +/*! + * Disables parity error detection in the L2 cache. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled. + * + * \retval true The L2 cache parity error detection feature is + * enabled. + * \retval false The L2 cache parity error detection feature is + * disabled. + */ +bool alt_cache_l2_parity_is_enabled(void); + +/*! + * Enables the L2 cache. + * + * If the L2 cache is already enabled, nothing is done. Otherwise the entire + * contents of the cache is first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_enable(void); + +/*! + * Disables the L2 cache. + * + * If the L2 cache is already disabled, nothing is done. Otherwise the entire + * contents of the cache is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_disable(void); + +/*! + * Returns \b true when the L2 cache is enabled and \b false when it is + * disabled. + * + * \retval true The L2 cache is enabled. + * \retval false The L2 cache is disabled. + */ +bool alt_cache_l2_is_enabled(void); + +/*! + * Flushes the L2 cache controller hardware buffers. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_sync(void); + +/*! + * Invalidates the specified contents of the L2 cache for the given memory + * segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); + +/*! + * Invalidates th entire contents of the L2 cache. + * + * Normally this is done automatically as part of alt_cache_l2_enable(), but + * in certain circumstances it may be necessary to invalidate it manually. An + * example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); + +/*! + * Cleans the specified contents of the L2 cache for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); + +/*! + * Cleans the entire L2 cache. All L2 cache controller interrupts will be + * temporarily disabled while the clean operation is in progress and restored + * once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L2 cache for the + * given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); + +/*! + * Cleans and invalidates the entire L2 cache. All L2 cache controller + * interrupts will be temporarily disabled while the clean and invalidate + * operation is in progress and restored once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_purge_all(void); + +/*! + * This type definition enumerates all the interrupt conditions that can be + * generated by the L2 cache controller as register mask values. + */ +enum ALT_CACHE_L2_INTERRUPT_e +{ + /*! Decode error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, + + /*! Slave error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, + + /*! Error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, + + /*! Error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, + + /*! Error on the L2 data RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, + + /*! Error on the L2 tag RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, + + /*! Parity error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, + + /*! Parity error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, + + /*! Event counter overflow or increment. */ + ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 +}; +typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; + +/*! + * Enables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); + +/*! + * Disables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); + +/*! + * Gets the condition(s) causing the L2 cache controller to interrupt as a + * register mask. + * + * \returns A register mask of the currently asserted and enabled + * conditions resulting in an interrupt being generated. + */ +uint32_t alt_cache_l2_int_status_get(void); + +/*! + * Clears the specified conditon(s) causing the L2 cache controller to + * interrupt as a mask. Condition(s) specified which are not causing an + * interrupt or condition(s) specified which are not enabled are ignored. + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h new file mode 100644 index 0000000000..a43608e9f3 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ + +#ifndef __ALT_CLK_GRP_H__ +#define __ALT_CLK_GRP_H__ + +#include "hwlib.h" +#include "socal/alt_clkmgr.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * This type definition enumerates the clock groups + */ +typedef enum ALT_CLK_GRP_e +{ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + +} ALT_CLK_GRP_t; + +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. + */ +typedef struct ALT_CLK_GROUP_RAW_CFG_s +{ + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. + */ + union ALT_CLK_GROUP_RAW_CFG_u + { + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + + } clkgrp; +} ALT_CLK_GROUP_RAW_CFG_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_CLK_GRP_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h new file mode 100644 index 0000000000..d6d96544f7 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h @@ -0,0 +1,1434 @@ +/*! \file + * Contains definitions for the Altera Hardware Libraries Clock Manager + * Application Programming Interface + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_CLK_MGR_H__ +#define __ALT_CLK_MGR_H__ + +#include "hwlib.h" +#include "alt_clock_group.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup CLK_MGR The Clock Manager API + * + * This module defines the Clock Manager API for accessing, configuring, and + * controlling the HPS clock resources. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition is an opaque type definition for clock frequency values + * in Hz. + */ +typedef uint32_t alt_freq_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the names of the clock and PLL resources + * managed by the Clock Manager. + */ +typedef enum ALT_CLK_e +{ + /* Clock Input Pins */ + ALT_CLK_IN_PIN_OSC1, + /*!< \b OSC_CLK_1_HPS + * External oscillator input: + * * Input Pin + * * Clock source to Main PLL + * * Clock source to SDRAM PLL + * and Peripheral PLL if selected via + * register write + * * Clock source for clock in safe mode + */ + + ALT_CLK_IN_PIN_OSC2, + /*!< \b OSC_CLK_2_HPS + * External Oscillator input: + * * Input Pin + * * Optional clock source to SDRAM PLL + * and Peripheral PLL if selected + * * Typically used for Ethernet + * reference clock + */ + + + /* FPGA Clock Sources External to HPS */ + ALT_CLK_F2H_PERIPH_REF, + /*2C 0 TX */ + ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ + ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ + ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ + ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ + ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ + ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ + ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ + ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ + ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ + ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ + ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ + ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ + ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ + ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ + ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ + ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ + ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ + ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ + ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ + ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ + ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ + ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ + ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ +} +ALT_DMA_PERIPH_t; + +/*! + * This type enumerates the DMA security state options available. + */ +typedef enum ALT_DMA_SECURITY_e +{ + ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ + ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ + ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ +} +ALT_DMA_SECURITY_t; + +/*! + * This type definition enumerates the DMA event-interrupt resources. + */ +typedef enum ALT_DMA_EVENT_e +{ + ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ + ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ + ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ + ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ + ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ + ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ + ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ + ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ + ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ +} +ALT_DMA_EVENT_t; + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h new file mode 100644 index 0000000000..5fa876f237 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h @@ -0,0 +1,951 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_PROGRAM_H__ +#define __ALT_DMA_PROGRAM_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_PRG DMA Controller Programming API + * + * This API provides functions for dynamically defining and assembling microcode + * programs for execution on the DMA controller. + * + * The microcode program assembly API provides users with the ability to develop + * highly optimized and tailored algorithms for data transfer between SoC FPGA + * IP blocks and/or system memory. + * + * The same microcode program assembly facilities are also used to implement the + * functions found in the HWLIB Common DMA Operations functional API. + * + * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA + * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated + * from used specified system memory. Once a microcode program has been + * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA + * channel thread. The microcode program may be rerun on any DMA channel thread + * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t + * containing the program is maintained. + * + * @{ + */ + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line width in bytes. It is recommended that the program buffers be + * sized to a multiple of the cache line size. This will allow for the most + * efficient microcode speed and space utilization. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line count. Thus the total size of the cache is the cache line size + * multipled by the cache line count. Programs larger than the cache size risk + * having a cache miss while executing. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) + +/*! + * This preprocessor definition determines the size of the program buffer + * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate + * size for most DMA microcode programs. If calls within this API are + * reporting out of memory response codes, consider increasing the provisioned + * program buffersize. + * + * To specify another DMA microcode program buffer size, redefine the macro + * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in + * your Makefile. It is recommended that the size be a multiple of the + * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for + * more information. The largest supported buffer size is 65536 bytes. + */ +#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) +#endif + +/*! + * This type defines the structure used to assemble and contain a microcode + * program which can be executed by the DMA controller. The internal members + * are undocumented and should not be altered outside of this API. + */ +typedef struct ALT_DMA_PROGRAM_s +{ + uint32_t flag; + + uint16_t buffer_start; + uint16_t code_size; + + uint16_t loop0; + uint16_t loop1; + + uint16_t sar; + uint16_t dar; + + /* + * Add a little extra space so that regardless of where this structure + * sits in memory, a suitable start address can be aligned to the cache + * line stride while providing the requested buffer space. + */ + uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + + ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; +} +ALT_DMA_PROGRAM_t; + +/*! + * This type definition enumerates the DMA controller register names for use in + * microcode program definition. + */ +typedef enum ALT_DMA_PROGRAM_REG_e +{ + /*! Source Address Register */ + ALT_DMA_PROGRAM_REG_SAR = 0x0, + + /*! Destination Address Register */ + ALT_DMA_PROGRAM_REG_DAR = 0x2, + + /*! Channel Control Register */ + ALT_DMA_PROGRAM_REG_CCR = 0x1 +} +ALT_DMA_PROGRAM_REG_t; + +/*! + * This type definition enumerates the instruction modifier options available + * for use with selected DMA microcode instructions. + * + * The enumerations values are context dependent upon the instruction being + * modified. + * + * For the DMALD[S|B], DMALDP\, DMAST[S|B], and + * DMASTP\ microcode instructions, the enumeration + * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the S option modifier + * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the B + * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies + * that no modifier is present for instructions where use of [S|B] is + * optional. + * + * For the DMAWFP microcode instruction, the enumerations + * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding + * options \. + */ +typedef enum ALT_DMA_PROGRAM_INST_MOD_e +{ + /*! + * This DMA instruction modifier specifies that no special modifier is + * added to the instruction. + */ + ALT_DMA_PROGRAM_INST_MOD_NONE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies S case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_SINGLE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies B case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_BURST, + + /*! + * This DMA instruction modifier specifies a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_PERIPH +} +ALT_DMA_PROGRAM_INST_MOD_t; + +/*! + * This function initializes a system memory buffer for use as a DMA microcode + * program buffer. This should be the first API call made on the program + * buffer type. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function verifies that the DMA microcode program buffer is no longer + * in use and performs any needed uninitialization steps. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function clears the existing DMA microcode program in the given + * program buffer. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function validate that the given DMA microcode program buffer contains + * a well formed program. If caches are enabled, the program buffer contents + * will be cleaned to RAM. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The given program is well formed. + * \retval ALT_E_ERROR The given program is not well formed. + * \retval ALT_E_TMO The cache operation timed out. + */ +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function reports the number bytes incremented for the register + * specified. The purpose is to determine the progress of an ongoing DMA + * transfer. + * + * It is implemented by calculating the difference of the programmed SAR or DAR + * with the current channel SAR or DAR register value. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param channel + * The channel that the program is running on. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param current + * The current snapshot value of the register read from the DMA + * channel. + * + * \param progress + * [out] A pointer to a memory location that will be used to store + * the number of bytes transfered. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified + * register is invalid, or the DMAMOV for the + * specified register has not yet been assembled + * in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress); + +/*! + * This function updates a pre-existing DMAMOV value affecting the SAR or DAR + * registers. This allows for pre-assembled programs that can be used on + * different source and destination addresses. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param val + * The value to update to. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV + * for the specified register has not yet been + * assembled in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val); + +/*! + */ + +/*! + * Assembles a DMAADDH (Add Halfword) instruction into the microcode program + * buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA program buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADDH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode + * program buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADNH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAEND (End) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAEND +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to flush. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral specified. + */ +// Assembler Syntax: DMAFLUSHP +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMAGO (Go) instruction into the microcode program buffer. This + * instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param channel + * The stopped channel to act upon. + * + * \param val + * The value to write to the channel program counter register. + * + * \param sec + * The security state for the operation. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel or security specified. + */ +// Assembler Syntax: DMAGO , <32-bit_immediate> [, ns] +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec); + +/*! + * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAKILL +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMALD (Load) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + */ +// Assembler Syntax: DMALD[S|B] +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALDP (Load and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMALDP +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMALP (Loop) instruction into the microcode program buffer. + * This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param iterations + * The number of iterations to run for. Valid values are 1 - 256. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid iterations specified. + * \retval ALT_E_BAD_OPERATION All loop registers are in use. + */ +// Assembler Syntax: DMALP [|] +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations); + +/*! + * Assembles a DMALPEND (Loop End) instruction into the microcode program + * buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the loop terminator. Only + * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE + * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. + * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to + * the program buffer before adding this + * DMALPEND instruction. + */ +// Assembler Syntax: DMALPEND[S|B] +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALPFE (Loop Forever) instruction into the microcode program + * buffer. No instruction is added to the buffer but a previous DMALPEND to + * create an infinite loop. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMALPFE +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAMOV (Move) instruction into the microcode program buffer. + * This instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param chan_reg + * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, + * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy + * the value to. + * + * \param val + * The value to write to the specified register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAMOV , <32-bit_immediate> +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); + +/*! + * Assembles a DMANOP (No Operation) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMANOP +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMARMB +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMASEV (Send Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to send. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMASEV +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt); + +/*! + * Assembles a DMAST (Store) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAST[S|B] +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMASTP (Store and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMASTP +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMASTZ (Store Zero) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMASTZ +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAWFE (Wait For Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to wait for. + * + * \param invalid + * If invalid is set to true, the instruction will be configured + * to invalidate the instruction cache for the current DMA + * thread. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMAWFE [, invalid] +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid); + +/*! + * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to wait on. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, + * ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier + * specified. + */ +// Assembler Syntax: DMAWFP , +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAWMB +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * \addtogroup DMA_CCR Support for DMAMOV CCR + * + * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the + * dynamic microcode programming of the assembler directive: +\verbatim + +DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA] + [SP] [SC] + [DB<1-16>] [DS<8|16|32|64|128>] [DA] + [DP] [DC] + [ES<8|16|32|64|128>] + +\endverbatim +* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). +* +* For example the assembler directive: +\verbatim +DMAMOV CCR SB1 SS32 DB1 DS32 +\endverbatim +* would be dynamically programmed with the following API call: +\verbatim +alt_dma_program_DMAMOV( pgm, + ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES8 + ) + ); +\endverbatim +* +* Each CCR option category should be specified regardless of whether it +* specifies a custom value or the normal default value (i.e. an +* ALT_DMA_CCR_OPT_*_DEFAULT. +* +* @{ +*/ + +/* + * Source Address {Fixed,Incrementing} + */ +/*! Source Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_SAF (0 << 0) +/*! Source Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_SAI (1 << 0) +/*! Source Address Default value. */ +#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI + +/* + * Source burst Size (in bits) + */ +/*! Source burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_SS8 (0 << 1) +/*! Source burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_SS16 (1 << 1) +/*! Source burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_SS32 (2 << 1) +/*! Source burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_SS64 (3 << 1) +/*! Source burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_SS128 (4 << 1) +/*! Source burst Size default bits. */ +#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 + +/* + * Source burst Length (in transfer(s)) + */ +/*! Source Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) +/*! Source Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) +/*! Source Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) +/*! Source Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) +/*! Source Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) +/*! Source Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) +/*! Source Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) +/*! Source Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) +/*! Source Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) +/*! Source Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) +/*! Source Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) +/*! Source Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) +/*! Source Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) +/*! Source Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) +/*! Source Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) +/*! Source Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) +/*! Source Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 + +/* + * Source Protection + */ +/*! Source Protection bits for AXI bus ARPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) +/*! Source Protection bits default value. */ +#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) + +/* + * Source cache + */ +/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ +#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) +/*! Source Cache bits default value. */ +#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) + +/* + * Destination Address {Fixed,Incrementing} + */ +/*! Destination Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_DAF (0 << 14) +/*! Destination Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_DAI (1 << 14) +/*! Destination Address Default value. */ +#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI + +/* + * Destination burst Size (in bits) + */ +/*! Destination burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_DS8 (0 << 15) +/*! Destination burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_DS16 (1 << 15) +/*! Destination burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_DS32 (2 << 15) +/*! Destination burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_DS64 (3 << 15) +/*! Destination burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_DS128 (4 << 15) +/*! Destination burst Size default bits. */ +#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 + +/* + * Destination Burst length (in transfer(s)) + */ +/*! Destination Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) +/*! Destination Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) +/*! Destination Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) +/*! Destination Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) +/*! Destination Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) +/*! Destination Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) +/*! Destination Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) +/*! Destination Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) +/*! Destination Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) +/*! Destination Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) +/*! Destination Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) +/*! Destination Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) +/*! Destination Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) +/*! Destination Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) +/*! Destination Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) +/*! Destination Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) +/*! Destination Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 + +/* + * Destination Protection + */ +/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) +/*! Destination Protection bits default value. */ +#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) + +/* + * Destination Cache + */ +/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ +#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) +/*! Destination Cache bits default value. */ +#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) + +/* + * Endian Swap size (in bits) + */ +/*! Endian Swap: No swap, 8-bit data. */ +#define ALT_DMA_CCR_OPT_ES8 (0 << 28) +/*! Endian Swap: Swap bytes within 16-bit data. */ +#define ALT_DMA_CCR_OPT_ES16 (1 << 28) +/*! Endian Swap: Swap bytes within 32-bit data. */ +#define ALT_DMA_CCR_OPT_ES32 (2 << 28) +/*! Endian Swap: Swap bytes within 64-bit data. */ +#define ALT_DMA_CCR_OPT_ES64 (3 << 28) +/*! Endian Swap: Swap bytes within 128-bit data. */ +#define ALT_DMA_CCR_OPT_ES128 (4 << 28) +/*! Endian Swap: Default byte swap. */ +#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 + +/*! Default CCR register options for a DMAMOV CCR assembler directive. */ +#define ALT_DMA_CCR_OPT_DEFAULT \ + (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ + ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ + ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ + ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ + ALT_DMA_CCR_OPT_ES8) + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h new file mode 100644 index 0000000000..0a7abaef8e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h @@ -0,0 +1,1254 @@ +/*! \file + * Altera - GPIO Module + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_GPIO_H__ +#define __ALT_GPIO_H__ + +#include +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ALT_GPIO_BITMASK 0x1FFFFFFF + +/* If the GPIO special test mode flag was not defined in the makefile, */ + /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that */ + /* the production code version of alt_gpio_port_data_read() is included. */ + /* If the flag is defined as true in the makefile, then the test version */ + /* located in the test code file is substituted instead of the version */ + /* in this file. */ +#ifndef ALT_GPIO_DATAREAD_TEST_MODE +#define ALT_GPIO_DATAREAD_TEST_MODE false +#endif + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API + * + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output + * Manager resources. These include both the general-purpose GPIO signals and + * the input-only GPI signals that are shared with the DDR interface.\n \n + * The GPIO API presents two views or perspectives of the GPIO signals. The first + * is to view the GPIO signals in a traditional way, as separate GPIO ports + * each comprised of a number of GPIO bits. The second perspective is of a + * unified flat view that presents the GPIO and GPI signals as a set of indexed + * bits, a view that allows the programmer to mostly ignore the port and pin + * hardware configuration and read/write/configure the GPIO and GPI signals + * independently of the underlying hardware implementation. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * This functional group contains functions to control, configure and manage + * the general-purpose IO signals as individual signals or as groups of signals. + * This group of functions can operate on multiple bits within the same GPIO + * port and accepts a bit mask to specify which bits an operation will operate on. + * Other bits within the same GPIO port are not changed. + * + * This example shows how multiple drivers or applications can use this feature + * to easily prevent conflict while accessing the same GPIO port: + * \verbatim + #define DRIVER_0_GPIO_MSK 0x0010FF03; + #define DRIVER_1_GPIO_MSK 0x002000F8; + #define DRIVER_2_GPIO_MSK 0x03C00004; + #define DRIVER_3_GPIO_MSK 0x000F0000; + + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3); + alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1); + \endverbatim + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the data direction (input or output) of + * the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_DIR_e +{ + /*! # */ + ALT_GPIO_PIN_INPUT, + /*! # */ + ALT_GPIO_PIN_OUTPUT +} ALT_GPIO_PIN_DIR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the type of interrupt source + * (level-triggered or edge-triggered) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_TYPE_e +{ + /*! # */ + ALT_GPIO_PIN_LEVEL_TRIG_INT, + /*! # */ + ALT_GPIO_PIN_EDGE_TRIG_INT +} ALT_GPIO_PIN_TYPE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the polarity of the interrupt sources + * (falling-edge or rising-edge for edge-triggered interrupts, active-low or + * active-high for level-triggered interrupts) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_POL_e +{ + /*! Indicates active-low for level-triggered interrupts and + * falling-edge for edge-triggered interrupts */ + ALT_GPIO_PIN_ACTIVE_LOW, + + /*! Indicates active-high for level-triggered interrupts and + * rising-edge for edge-triggered interrupt */ + ALT_GPIO_PIN_ACTIVE_HIGH +} ALT_GPIO_PIN_POL_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not the debounce metastability + * flip-flops are inserted or not. These are used to debounce signals presented + * to the GPIO inputs. A signal must be steady for two periods of the + * gpio_db_clk clock before it is considered valid. The frequency of the + * gpio_db_clk clock may be set using the Clock Manager API. + */ + +typedef enum ALT_GPIO_PIN_DEBOUNCE_e +{ + /*! # */ + ALT_GPIO_PIN_NODEBOUNCE, + /*! # */ + ALT_GPIO_PIN_DEBOUNCE +} ALT_GPIO_PIN_DEBOUNCE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not level-sensitive interrupts + * are synchronized to the internal pclk_intr clock. It has no effect for GPIO + * signals that are selected as outputs, or if the interrupt is not enabled, + * or if the interrupt is set to be edge-triggered. This is a port-wide option. + */ + +typedef enum ALT_GPIO_PIN_SYNC_e +{ + /*! # */ + ALT_GPIO_PIN_NOSYNC, + /*! # */ + ALT_GPIO_PIN_SYNC +} ALT_GPIO_PIN_SYNC_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the possible data states of the GPIO bits. + */ + +typedef enum ALT_GPIO_PIN_DATA_e +{ + /*! # */ + ALT_GPIO_PIN_DATAZERO, + /*! # */ + ALT_GPIO_PIN_DATAONE +} ALT_GPIO_PIN_DATA_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the GPIO ports that the GPIO manager + * handles. + */ + +typedef enum ALT_GPIO_PORT_e +{ + /*! + * \b Port \b A - 29-bit GPIO port A. + */ + ALT_GPIO_PORTA, + + /*! + * \b Port \b B - 29-bit GPIO port B. + */ + ALT_GPIO_PORTB, + + /*! + * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, + * 14 bits are used for GPI-only signals that are shared + * with the DDR interface, 2 bits are not used. Some signals + * may not be connected on some versions. See the relevant + * pin mux data. + */ + ALT_GPIO_PORTC, + + /*! + * \b Unknown \b Port - Used to indicate an error. + */ + ALT_GPIO_PORT_UNKNOWN +} ALT_GPIO_PORT_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits within the GPIO ports + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not + * standardized in C/C++, the following are defined as masks. \n + * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits + * had previously been set to outputs), the user could use the syntax: \par + * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b + * ALT_GPIO_BIT4); + */ + +typedef enum ALT_GPIO_PORTBIT_e +{ + /*! # */ + ALT_GPIO_BIT0 = ALT_TWO_TO_POW0, + /*! # */ + ALT_GPIO_BIT1 = ALT_TWO_TO_POW1, + /*! # */ + ALT_GPIO_BIT2 = ALT_TWO_TO_POW2, + /*! # */ + ALT_GPIO_BIT3 = ALT_TWO_TO_POW3, + /*! # */ + ALT_GPIO_BIT4 = ALT_TWO_TO_POW4, + /*! # */ + ALT_GPIO_BIT5 = ALT_TWO_TO_POW5, + /*! # */ + ALT_GPIO_BIT6 = ALT_TWO_TO_POW6, + /*! # */ + ALT_GPIO_BIT7 = ALT_TWO_TO_POW7, + /*! # */ + ALT_GPIO_BIT8 = ALT_TWO_TO_POW8, + /*! # */ + ALT_GPIO_BIT9 = ALT_TWO_TO_POW9, + /*! # */ + ALT_GPIO_BIT10 = ALT_TWO_TO_POW10, + /*! # */ + ALT_GPIO_BIT11 = ALT_TWO_TO_POW11, + /*! # */ + ALT_GPIO_BIT12 = ALT_TWO_TO_POW12, + /*! # */ + ALT_GPIO_BIT13 = ALT_TWO_TO_POW13, + /*! # */ + ALT_GPIO_BIT14 = ALT_TWO_TO_POW14, + /*! # */ + ALT_GPIO_BIT15 = ALT_TWO_TO_POW15, + /*! # */ + ALT_GPIO_BIT16 = ALT_TWO_TO_POW16, + /*! # */ + ALT_GPIO_BIT17 = ALT_TWO_TO_POW17, + /*! # */ + ALT_GPIO_BIT18 = ALT_TWO_TO_POW18, + /*! # */ + ALT_GPIO_BIT19 = ALT_TWO_TO_POW19, + /*! # */ + ALT_GPIO_BIT20 = ALT_TWO_TO_POW20, + /*! # */ + ALT_GPIO_BIT21 = ALT_TWO_TO_POW21, + /*! # */ + ALT_GPIO_BIT22 = ALT_TWO_TO_POW22, + /*! # */ + ALT_GPIO_BIT23 = ALT_TWO_TO_POW23, + /*! # */ + ALT_GPIO_BIT24 = ALT_TWO_TO_POW24, + /*! # */ + ALT_GPIO_BIT25 = ALT_TWO_TO_POW25, + /*! # */ + ALT_GPIO_BIT26 = ALT_TWO_TO_POW26, + /*! # */ + ALT_GPIO_BIT27 = ALT_TWO_TO_POW27, + /*! # */ + ALT_GPIO_BIT28 = ALT_TWO_TO_POW28, + ALT_GPIO_BIT29 = ALT_TWO_TO_POW29, /* Not currently used */ + ALT_GPIO_BIT30 = ALT_TWO_TO_POW30, /* Not currently used */ + ALT_GPIO_BIT31 = (int32_t) (1UL<<31), /* Not currently used */ + + ALT_GPIO_BITNUM_MAX = (28), + ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX), + ALT_END_OF_GPIO_PORT_SIGNALS = (32) +} ALT_GPIO_PORTBIT_t; + + + +/******************************************************************************/ +/*! + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) + * specified. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all data direction bits of the port. + * \param config + * The data-directions of the bits to be set in this operation. + * Individual bits are: \n \b 0 - Use as an input (default). \n + * \b 1 - Use as an output. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the data direction configuration of selected bits of the + * specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to read and + * return. Other bits (where mask bits equal zero) are returned + * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * return all data direction bits of the port. + * + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * configured as an input. + * \n \b 1 - The signal is configured as an output. + * + */ +uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the GPIO data outputs of the specified GPIO module to a logic one or + * zero. Outputs are only set if the data direction for those bits is also + * set to configure them as outputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (mask bits equal one) to apply this + * operation to. Other bits (mask bits equal zero) are + * not changed. + * \param val + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * are used. Setting the three MSBs causes an error. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the value of the data inputs of the specified GPIO module. This is + * the current logic value of the pin, whether set to be an input or an output. + * \n If a given signal is set to be an output, this input value can be read to + * determine if the pin is grounded, pulled high, or is floating. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of + * the port. + * + * \retval uint32_t The current value of the GPIO module input signals. + */ +uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * This functional group contains functions to control and manage the + * interrupts of the General-Purpose IO modules. + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets edge-triggered or level-triggered interrupt configuration for the + * specified signals of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all interrupt type bits of the port. + * \param config + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b + * 1 - Set the interrupt for this bit to be edge-sensitive. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration + * bits of the port. + * \retval uint32_t + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - + * The interrupt for this bit is set to be edge-sensitive. + * + */ +uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the interrupt polarity of the signals of the specified GPIO register + * (when used as inputs) to active-high or active-low (for level-sensitive + * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts). + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. + * \param config + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to + * active-low or falling-edge mode (default). \n \b 1 - Set the + * interrupt polarity for this bit to active-high or rising-edge mode. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the active-high or active-low polarity configuration for the + * possible interrupt sources of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the + * configuration bits of the port. + * + * \retval uint32_t + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to + * active-low or falling-edge mode. \n \b 1 = The interrupt + * polarity for this bit is set to active-high or rising-edge mode. + * + */ +uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets the debounce configuration for input signals of the specified GPIO + * module. If debounce is selected, metastability flip-flops are inserted to + * debounce signals presented to the GPIO inputs. A signal must be steady for + * two periods of the gpio_db_clk clock before it is considered valid. The + * frequency of the gpio_db_clk clock may be set using the Clock Manager API. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure the debounce setting for all bits of the port. + * \param config + * The debounce configuration to set. Individual bits are: \n + * \b 0 - Debounce is not selected for this signal (default). \n + * \b 1 - Debounce is selected for this signal. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the debounce configuration for the input signals of the specified + * GPIO register. If debounce is selected, metastability flip-flops are + * inserted to debounce signals presented to the GPIO inputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce + * configuration bits of the port. + * + * \retval uint32_t + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * Debounce is selected for this signal. + * + */ +uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to + * an internal clock signal. This is a port-wide option that controls all + * level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. + * \n \b Zero - Do not synchronize to internal clock signal. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t config); + +/******************************************************************************/ +/*! + * + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive + * interrupts to the internal clock signal. This is a port-wide option that + * controls all level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + + + * \retval ALT_E_TRUE Synchronization to clock is enabled for + * level-sensitive interrupts. + * \retval ALT_E_FALSE Synchronization to clock is disabled for + * level-sensitive interrupts. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Configures a group of GPIO signals with identical setup parameters. Allows + * for configuring all parameters of a given port at one time. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits to apply this operation to. Other bits (mask + * set to zero) are not changed. + * \param dir + * Data direction. + * \param type + * Edge-triggered or level-triggered interrupts. + * \param pol + * Active-high or active-low polarity. + * \param debounc + * Debounce signals or not. + * \param data + * Set the data output to this value. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc, + uint32_t data); + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Enables the specified GPIO data input interrupts. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Disables the specified GPIO data module interrupt. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the current state of the specified GPIO port interrupts enables. + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt enable configuration that was read. Individual bits + * are: \n \b 0 = The interrupt for this bit is not enabled. \n \b + * 1 = The interrupt for this bit is enabled. + */ +uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Masks or unmasks selected interrupt source bits of the data register of + * the specified GPIO module. Uses a second bit mask to determine which + * signals may be changed by this call. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * Which bits to change among the port \n \b 0 = + * Do not change this bit. \n \b 1 = Allow this bit to change. + * \param val + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = + * Mask the interrupt for this bit. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the interrupt mask of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * interrupt for this bit is masked. + * + */ +uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the interrupt pending status of all signals of the specified GPIO + * register. + * + * + * \param gpio_pid + * The GPIO port identifier. + + * \retval uint32_t + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The interrupt for this bit is pending. + * + */ +uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Clear the interrupt pending status of selected signals of the + * specified GPIO register. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param clrmask + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt for this bit will be cleared. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid, + uint32_t clrmask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * This functional group presents a perspective of the General-Purpose IO + * signals as individual GPIO and GPI bits spread across a number of signals + * across several GPIO ports. This allows the programmer the freedom to generally + * ignore the underlying port and signal structure of the GPIO hardware if + * desired. + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits as one flat array spread + * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering + * must match the hardware bit-ordering. + * + */ +typedef enum ALT_GPIO_1BIT_e +{ + /*! # */ + ALT_GPIO_1BIT_0, + /*! # */ + ALT_GPIO_1BIT_1, + /*! # */ + ALT_GPIO_1BIT_2, + /*! # */ + ALT_GPIO_1BIT_3, + /*! # */ + ALT_GPIO_1BIT_4, + /*! # */ + ALT_GPIO_1BIT_5, + /*! # */ + ALT_GPIO_1BIT_6, + /*! # */ + ALT_GPIO_1BIT_7, + /*! # */ + ALT_GPIO_1BIT_8, + /*! # */ + ALT_GPIO_1BIT_9, + /*! # */ + ALT_GPIO_1BIT_10, + /*! # */ + ALT_GPIO_1BIT_11, + /*! # */ + ALT_GPIO_1BIT_12, + /*! # */ + ALT_GPIO_1BIT_13, + /*! # */ + ALT_GPIO_1BIT_14, + /*! # */ + ALT_GPIO_1BIT_15, + /*! # */ + ALT_GPIO_1BIT_16, + /*! # */ + ALT_GPIO_1BIT_17, + /*! # */ + ALT_GPIO_1BIT_18, + /*! # */ + ALT_GPIO_1BIT_19, + /*! # */ + ALT_GPIO_1BIT_20, + /*! # */ + ALT_GPIO_1BIT_21, + /*! # */ + ALT_GPIO_1BIT_22, + /*! # */ + ALT_GPIO_1BIT_23, + /*! # */ + ALT_GPIO_1BIT_24, + /*! # */ + ALT_GPIO_1BIT_25, + /*! # */ + ALT_GPIO_1BIT_26, + /*! # */ + ALT_GPIO_1BIT_27, + /*! # */ + ALT_GPIO_1BIT_28, + /*! # */ + ALT_GPIO_1BIT_29, + /*! # */ + ALT_GPIO_1BIT_30, + /*! # */ + ALT_GPIO_1BIT_31, + /*! # */ + ALT_GPIO_1BIT_32, + /*! # */ + ALT_GPIO_1BIT_33, + /*! # */ + ALT_GPIO_1BIT_34, + /*! # */ + ALT_GPIO_1BIT_35, + /*! # */ + ALT_GPIO_1BIT_36, + /*! # */ + ALT_GPIO_1BIT_37, + /*! # */ + ALT_GPIO_1BIT_38, + /*! # */ + ALT_GPIO_1BIT_39, + /*! # */ + ALT_GPIO_1BIT_40, + /*! # */ + ALT_GPIO_1BIT_41, + /*! # */ + ALT_GPIO_1BIT_42, + /*! # */ + ALT_GPIO_1BIT_43, + /*! # */ + ALT_GPIO_1BIT_44, + /*! # */ + ALT_GPIO_1BIT_45, + /*! # */ + ALT_GPIO_1BIT_46, + /*! # */ + ALT_GPIO_1BIT_47, + /*! # */ + ALT_GPIO_1BIT_48, + /*! # */ + ALT_GPIO_1BIT_49, + /*! # */ + ALT_GPIO_1BIT_50, + /*! # */ + ALT_GPIO_1BIT_51, + /*! # */ + ALT_GPIO_1BIT_52, + /*! # */ + ALT_GPIO_1BIT_53, + /*! # */ + ALT_GPIO_1BIT_54, + /*! # */ + ALT_GPIO_1BIT_55, + /*! # */ + ALT_GPIO_1BIT_56, + /*! # */ + ALT_GPIO_1BIT_57, + /*! # */ + ALT_GPIO_1BIT_58, + /*! # */ + ALT_GPIO_1BIT_59, + /*! # */ + ALT_GPIO_1BIT_60, + /*! # */ + ALT_GPIO_1BIT_61, + /*! # */ + ALT_GPIO_1BIT_62, + /*! # */ + ALT_GPIO_1BIT_63, + /*! # */ + ALT_GPIO_1BIT_64, + /*! # */ + ALT_GPIO_1BIT_65, + /*! # */ + ALT_GPIO_1BIT_66, + /*! # */ + ALT_GPIO_1BIT_67, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_68, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_69, /* Not bonded out on some versions */ + + /*! The last of the input/output bits */ + ALT_GPIO_1BIT_70, /* Not bonded out on some versions */ + + + /*! This and the following signals are not present on all SoCs. \n + * If present, the selection between their use as 14 General-purpose inputs or + * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift + * Register) and software to make this selection is in the IO Manager API. If + * they are present, they are restricted to using the same power supply voltage + * as the SDRAM module.*/ + ALT_HLGPI_0, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_1, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_2, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_3, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_4, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_5, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_6, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_7, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_8, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_9, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_10, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_11, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_12, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_13, /* Not bonded out on some versions */ + + ALT_HLGPI_14, /* Not bonded out */ + + ALT_HLGPI_15, /* Not bonded out */ + + ALT_GPIO_INVALID, + ALT_END_OF_GPIO_SIGNALS = -1, + ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15 +} ALT_GPIO_1BIT_t; + + +/******************************************************************************/ +/*! + * This configuration record definition is used for configuring bits and + * groups of bits of the GPIO interface. + */ +typedef struct ALT_GPIO_CONFIG_RECORD_s +{ + /*! + * The index number of the signal to configure. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * The data direction of the signal. */ + ALT_GPIO_PIN_DIR_t direction; + /*! + * Edge-triggered or level triggered interrupts. */ + ALT_GPIO_PIN_TYPE_t type; + /*! + * Active-high or active-low trigger for the interrupt. */ + ALT_GPIO_PIN_POL_t polarity; + /*! + * Enable or disable GPIO debounce capability. */ + ALT_GPIO_PIN_DEBOUNCE_t debounce; + /*! + * If the signal is an output, the data value to be output. */ + ALT_GPIO_PIN_DATA_t data; +} ALT_GPIO_CONFIG_RECORD_t; + +/******************************************************************************/ +/*! + * This pin record type definition is comprised of the signal index and + * associated input or output data. + */ +typedef struct ALT_GPIO_PIN_RECORD_s +{ + /*! + * The index number of the signal. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * Data - zero or one. */ + ALT_GPIO_PIN_DATA_t val; +} ALT_GPIO_PIN_RECORD_t; + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * @{ + */ +/******************************************************************************/ +/*! + * Configures all parameters for one bit (signal) of the GPIO ports. + * + * \param signal_num + * The GPIO port signal index. + * \param dir + * The data direction for this signal. + * \param type + * Edge-triggered or Level-triggered interrupt for this signal. + * \param pol + * Active-high or active-low interrupt polarity for this signal. + * \param debounce + * Enable the debounce flip-flops for this signal or not. + * \param data + * If the GPIO signal is set to be an output, set it to + * this value + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce, + ALT_GPIO_PIN_DATA_t data); + +/******************************************************************************/ +/*! + * Returns the configuration parameters of a given GPIO bit. + * + * \param signal_num + * The GPIO port signal index. + * \param config + * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. + * The fields of this configuration record are filled in + * by the function. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_CONFIG_RECORD_t *config); + +/******************************************************************************/ +/*! + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, + * alt_gpio_port_config(). Each bit may be configured differently and bits may + * be listed in any order. + * + * \param config_array + * Pointer to an array of GPIO_CONFIG_RECORD_s configuration + * records. These definitions contain all the parameters + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration + * listed is used. \n Configuration terminates either when \b len + * signals have been configured or if the next signal number index + * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). + * + * \param len + * Length of array to configure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. + * + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. Only the signal indices in the first field of each + * configuration record need be filled in. This function will + * fill in all the other fields of the configuration record, + * returning all configuration parameters in the array. + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the + * configuration record will contain multiple entries for + * that signal. \n Configuration reading terminates either when + * \b len signal configurations have been read or if the next + * signal number index in the array is equal to + * \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read and return. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. The difference between this version and + * alt_gpio_group_config_get() is this version follows a separate list of + * signal indices instead of having the signal list provided in the first + * field of the configuration records in the array. + * + * \param pinid_array + * Pointer to a list of signal index numbers. These indices + * are copied to the first field of each configuration record + * in the returned array. + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple + * identical entries for that signal. \n Configuration reading + * terminates either when \b len signal configurations have been + * read or if the next signal number index in the array is equal + * to \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + * + */ +ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, + ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions + * + * These are useful utility functions for the general-purpose input & output + * module. + * + * @{ */ +/******************************************************************************/ +/*! + * Returns the ID code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The component code of the module, GPIO_MODULE_IDCODE. + */ +uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the version code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The encoded revision number of the module. + */ +uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Extracts the GPIO port ID from the supplied GPIO Signal Index Number. + */ +ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num); + + +/******************************************************************************/ +/*! + * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index + * Number. + * */ +ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); + +/******************************************************************************/ +/*! + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the + * signal number of the lowest bit in the bitmask presented is returned. + * + */ +ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, + uint32_t bitmask); + + +/*! @} */ +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_GPIO_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h new file mode 100644 index 0000000000..7596d50d66 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_HWLIBS_VER_H__ + +/*********************************************************************** + * + * Set of macros to provide version information + * + ***********************************************************************/ + +/* This is the major revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MAJOR_REV 13 + +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 + +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ +#define ALTERA_HWLIBS_REV 0 + +/* This is a text string containing the current release and service pack IDs */ +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + + +#endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h new file mode 100644 index 0000000000..7af55cf4ac --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h @@ -0,0 +1,2024 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - I2C Controller API + */ + +#ifndef __ALT_I2C_H__ +#define __ALT_I2C_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_i2c.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C I2C Controller API + * + * This module defines an API for configuring and managing the HPS I2C controllers. + * + * The I2C controller provides support for a communication link between integrated + * circuits on a board. It is a simple two-wire bus which consists of a serial + * data line (SDA) and a serial clock (SCL) for use in applications such as + * temperature sensors and voltage level translators to EEPROMs, A/D and D/A + * converters, CODECs, and many types of microprocessors. + * + * The Hard Processor System (HPS) provides four I2C controllers to enable system + * software to communicate serially with I2C buses. Each I2C controller can + * operate in master or slave mode, and support standard mode of up to 100 + * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C + * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) + * controller. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + * + * Features of the I2C Controller: + * * Support both 100 KBps and 400 KBps modes + * * One of the following I2C operations: master or slave + * * Support both 7-bit and 10-bit addressing modes + * * Mixed read and write combined-format transactions + * * Bulk transmit mode + * * DMA handshaking interface + * + * For a complete details on the configuration and operation of I2C controller, + * consult the following references: + * * Cyclone V Device Handbook Volume 3: Hard Processor System Technical + * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2) + * * Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a + * * The I2C-Bus Specification Version 2.1 + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the operational state of I2C by + * transfer operation. + */ +typedef enum ALT_I2C_TRANSFER_TYPE_e +{ + ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ + ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ + ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ + ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ + ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ +} +ALT_I2C_TRANSFER_TYPE_t; + + +/* + * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is + * initialized by a call to alt_i2c_init() and subsequently used by the other I2C + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_I2C_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_I2C_DEV_s +{ + void * location; /*!< HPS address of I2C instance. */ + alt_freq_t clock_freq; /*!< Input clock frequency. */ + uint32_t last_target; /*!< Last issued target address. */ +} +ALT_I2C_DEV_t; + +/*! + * This type enumerates the HPS I2C controller instances. + */ +typedef enum ALT_I2C_CTLR_e +{ + ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ + ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ + ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ + ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ +} ALT_I2C_CTLR_t; + +/*! + * This type enumerates the modes that the I2C controller may operate in. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + */ +typedef enum ALT_I2C_MODE_e +{ + ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ + ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ +} ALT_I2C_MODE_t; + +/*! + * This type enumerates the I2C controller operational speed modes. + * + * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) + * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, + * fast mode devices are downward compatible. For instance, fast mode devices can + * communicate with standard mode devices in 0 to 100 Kbps I2C bus + * system. However, standard mode devices are not upward compatible and should not + * be incorporated in a fast-mode I2C bus system as they cannot follow the higher + * transfer rate and therefore unpredictable states would occur. + * + * This setting is relevant only if one is operating the I2C in master mode. + */ +typedef enum ALT_I2C_SPEED_e +{ + ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, + /*!< Standard mode (0 to 100 Kbps) */ + ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST + /*!< Fast mode (<= 400 Kbps) */ +} ALT_I2C_SPEED_t; + +/*! + * This type enumerates the two addressing modes formats supported by the I2C + * controller. + * + * The I2C controller does not support mixed address format - that is, a 7-bit + * address transaction followed by a 10-bit address transaction or vice versa - + * combined format transactions. + */ +typedef enum ALT_I2C_ADDR_MODE_e +{ + ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, + /*!< 7-Bit Address Format */ + ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 + /*!< 10-Bit Address Format */ +} ALT_I2C_ADDR_MODE_t; + +/*! + * This type enumerates interrupt status conditions for the I2C controller. + */ +typedef enum ALT_I2C_STATUS_e +{ + ALT_I2C_STATUS_RX_UNDER = 1UL << 0, + /*!< Set if the processor attempts to read the + * receive buffer when it is empty. If the I2C + * controller is disabled, this status keeps + * maintains its state until the master or slave + * state machines go into idle, then this + * interrupt is cleared. + */ + ALT_I2C_STATUS_RX_OVER = 1UL << 1, + /*!< Set if the receive buffer is completely + * filled to capacity and an additional byte is + * received from an external I2C device. The I2C + * controller acknowledges this, but any data + * bytes received after the FIFO is full are + * discarded. If the I2C controller is disabled, + * this status maintains its statue until the + * master or slave state machines go into idle, + * then this interrupt is cleared. + */ + ALT_I2C_STATUS_RX_FULL = 1UL << 2, + /*!< Set when the receive buffer reaches or goes + * above the RX_TL threshold. It is + * automatically cleared by hardware when buffer + * level goes below the threshold. If the I2C + * controller is disabled, the RX FIFO is + * flushed and held in reset; therefore the RX + * FIFO is not full. So this bit is cleared once + * the I2C controller is disabled, regardless of + * the activity that continues. + */ + ALT_I2C_STATUS_TX_OVER = 1UL << 3, + /*!< Set during transmit if the transmit buffer is + * filled to capacity and the processor attempts + * to issue another I2C command. When the I2C + * controller is disabled, this bit maintains + * its state until the master or slave state + * machines go into idle, then this interrupt is + * cleared. + */ + ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, + /*!< This bit is set to 1 when the transmit buffer + * is at or below the configured threshold + * value. It is automatically cleared by + * hardware when the buffer level goes above the + * threshold. When the I2C controller is + * disabled, the TX FIFO is flushed and held in + * reset. The TX FIFO appears as if it has no + * data in it, so this bit is set to 1, provided + * there is activity in the master or slave + * state machines. When there is no longer + * activity, then this bit is set to 0. + * + */ + ALT_I2C_STATUS_RD_REQ = 1UL << 5, + /*!< This bit is set to 1 when I2C is acting as a + * slave and another I2C master is attempting to + * read data from the I2C. The I2C holds the bus + * in a wait state until this interrupt is + * serviced, which means that the slave has been + * addressed by a remote master that is asking + * for data to be transferred. The processor + * must respond to this interrupt and then write + * the requested data. This bit is set to 0 just + * after the processor by calling + * alt_i2c_int_clear() with + * ALT_I2C_STATUS_RD_REQ in the mask.. + */ + ALT_I2C_STATUS_TX_ABORT = 1UL << 6, + /*!< This bit indicates if I2C, as an I2C + * transmitter, is unable to complete the + * intended actions on the contents of the + * transmit FIFO. This situation can occur both + * as an I2C master or an I2C slave, and is + * referred to as a 'transmit abort'. When this + * bit is set to 1, the IC_TX_ABRT_SOURCE + * register indicates the reason why the + * transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX + * FIFO whenever this bit is set. The TX FIFO + * remains in this flushed state until the + * register alt_i2c_int_clear() with + * ALT_I2C_STATUS_TX_ABORT in the mask is + * called. Once this happens, the TX FIFO is + * then ready to accept more data bytes from the + * APB interface. + */ + ALT_I2C_STATUS_RX_DONE = 1UL << 7, + /*!< When the I2C is acting as a + * slave-transmitter, this bit is set to 1 if + * the master does not acknowledge a transmitted + * byte. This occurs on the last byte of the + * transmission, indicating that the + * transmission is done. + */ + ALT_I2C_STATUS_ACTIVITY = 1UL << 8, + /*!< This bit captures I2C activity and stays set + * until it is cleared. There are four ways to + * clear it: + * * Disabling the I2C controller + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ACTIVITY in the mask. + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ALL in the mask. + * * System reset + * + * Once this bit is set, it stays set unless one + * of the four methods is used to clear it. Even + * if the I2C module is idle, this bit remains + * set until cleared, indicating that there was + * activity on the bus. + */ + ALT_I2C_STATUS_STOP_DET = 1UL << 9, + /*!< Indicates whether a STOP condition has + * occurred on the I2C interface regardless of + * whether I2C is operating in slave or master + * mode. + */ + ALT_I2C_STATUS_START_DET = 1UL << 10, + /*!< Indicates whether a START or RESTART + * condition has occurred on the I2C interface + * regardless of whether I2C is operating in + * slave or master mode. + */ + ALT_I2C_STATUS_INT_CALL = 1UL << 11, + /*!< Set only when a General Call address is + * received and it is acknowledged. It stays set + * until it is cleared either by disabling I2C + * or when alt_i2c_int_clear() with + * ALT_I2C_STATUS_CALL in the mask is + * called. I2C stores the received data in the + * Rx buffer. + */ + ALT_I2C_STATUS_INT_ALL = 0xFFF, + /*!< All Combined and Individual Interrupts. This + * enumeration value can be used to clear, + * disable, and enable the combined interrupt + * and all individual interrupt status + * conditions. As a side effect, when passed to + * alt_i2c_int_clear(), clears the source causes + * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the + * ALT_I2C_STATUS_TX_ABORT condition. + */ +} ALT_I2C_STATUS_t; + +/*! + * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. + * + * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when + * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or + * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. + * + * \internal + * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. + * \endinternal + */ +typedef enum ALT_I2C_TX_ABORT_CAUSE_e +{ + ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, + /*!< Master Abort 7 Bit Address - If set (1), + * Master is in 7-bit addressing mode and the + * address sent was not acknowledged by any + * slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, + /*!< Master Abort 10 Bit Address Byte 1 - If set + * (1), Master is in 10-bit address mode and the + * first 10-bit address byte was not + * acknowledged by any slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, + /*!< Master Abort 10 Bit Address Byte 2 - If set + * (1), Master is in 10-bit address mode and the + * second address byte of the 10-bit address was + * not acknowledged by any slave + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, + /*!< Master Abort TX NOACK Bit - If set (1), + * Master has received an acknowledgement for + * the address, but when it sent data byte(s) + * following the address, it did not receive an + * acknowledge from the remote slave(s). This is + * a master-mode only bit. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, + /*!< Master Abort GC Noack Bit - If set (1), I2C + * controller in master mode sent a General Call + * and no slave on the bus acknowledged the + * General Call. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, + /*!< Master Abort GC Read Bit - If set (1), I2C + * controller in master mode sent a General Call + * but the user programmed the byte following + * the General Call to be a read from the bus + * (IC_DATA_CMD[9] is set to 1). + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, + /*!< Master HS MC Ack - If set (1), Master is in + * High Speed mode and the High Speed Master + * code was acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, + /*!< Master Abort START Byte - If set (1), Master + * has sent a START Byte and the START Byte was + * acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, + /*!< Master HS Restart Disabled - If set (1), the + * restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the user is trying to + * use the master to transfer data in High Speed + * mode. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, + /*!< Master Abort START No Restart - To clear, the + * source of the ABRT_SBYTE_NORSTRT must be + * fixed first; restart must be enabled + * (IC_CON[5]=1), the SPECIAL bit must be + * cleared (IC_TAR[11]), or the GC_OR_START bit + * must be cleared (IC_TAR[10]). Once the source + * of the ABRT_SBYTE_NORSTRT is fixed, then this + * bit can be cleared in the same manner as + * other bits in this register. If the source of + * the ABRT_SBYTE_NORSTRT is not fixed before + * attempting to clear this bit, bit 9 clears + * for one cycle and then gets re-asserted. + * + * If set (1), the restart is disabled + * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + * user is trying to send a START Byte. + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, + /*!< Master Abort 10 Bit No Restart - If set (1), + * the restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the master sends a read + * command in 10-bit addressing mode. + * + * Role of I2C: Master Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, + /*!< Master Operation with Master Disabled - If set + * (1), user tries to initiate a Master + * operation with the Master mode disabled. + * + * Role of I2C: Master or Slave-Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, + /*!< Master Abort Arbitration Lost - If set (1), + * master has lost arbitration, or if + * IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same + * time. + * + * Role of I2C: Master or Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, + /*!< Slave Abort Flush TXFIFO - If set (1), Slave + * has received a read command and some data + * exists in the TX FIFO so the slave issues a + * TX_ABRT interrupt to flush old data in TX + * FIFO. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, + /*!< Slave Abort Arbitration Lost - If set (1), + * Slave lost the bus while transmitting data to + * a remote master. IC_TX_ABRT_SOURCE[12] is set + * at the same time. + * + * Note: Even though the slave never owns the + * bus, something could go wrong on the + * bus. This is a fail safe check. For instance, + * during a data transmission at the low-to-high + * transition of SCL, if what is on the data bus + * is not what is supposed to be transmitted, + * then DW_apb_i2c no longer own the bus. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 + /*!< Slave Abort Read TX - If set (1), + * when the processor side responds to a + * slave mode request for data to be transmitted + * to a remote master and user writes a 1 in CMD + * (bit 8) of IC_DATA_CMD register. + * + * Role of I2C: Slave-Transmitter. + */ +} ALT_I2C_TX_ABORT_CAUSE_t; + +/*! + * This type defines a structure for configuration of the SCL high and low counts + * to ensure proper I/O timing with the device interface. + * + * The SCL count values are only relevant if the I2C controller is enabled to as + * an I2C master. The SCL count values are ignored when the I2C controller is + * enabled as an I2C slave. + * + * See: Clock Frequency Configuration section of Chapter 20. I2C + * Controller in the Cyclone V Device Handbook Volume 3: Hard + * Processor System Technical Reference Manual for a complete discussion + * of calculation of the proper SCL clock high and low times. + */ +typedef struct ALT_I2C_MASTER_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; + /*!< The address mode (7 or 10 bit) when + * acting as a master. + */ + bool restart_enable; + /*!< This setting determines whether RESTART + * conditions may be sent when acting as a + * master. When the \e restart_enable is + * false, the I2C controller master is + * incapable of performing the following + * functions: + * * Sending a START BYTE + * * Performing any high-speed mode + * operation + * * Performing direction changes in + * combined format mode + * * Performing a read operation with a + * 10-bit address + */ + ALT_I2C_SPEED_t speed_mode; + /*!< The speed mode of the I2C operation. + */ + uint16_t ss_scl_hcnt; + /*!< The SCL clock high-period count for + * standard speed. + */ + uint16_t ss_scl_lcnt; + /*!< The SCL clock low-period count for + * standard speed. + */ + uint16_t fs_scl_hcnt; + /*!< The SCL clock high-period count for fast + * speed. + */ + uint16_t fs_scl_lcnt; + /*!< The SCL clock low-period count for fast + * speed. + */ + uint8_t fs_spklen; + /*!< The duration, measured in ic_clk cycles, + * of the longest spike that is filtered out + * by the spike suppression logic when the + * component is operating in SS or FS modes. + */ +} ALT_I2C_MASTER_CONFIG_t; + +/*! + * This type defines a structure for configuration of the I2C controller when it + * is operating in slave mode. + */ +typedef struct ALT_I2C_SLAVE_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when + * acting as a slave. + */ + uint32_t addr; /*!< The slave address to which the I2C + * controller responds when acting as a + * slave. + */ + bool nack_enable; /*!< Enable generation of a NACK. when the + * I2C controller is a + * slave-receiver. If \b true, it can + * only generate a NACK after a data + * byte is received; hence, the data + * transfer is aborted and the data + * received is not pushed onto the + * receive buffer. When \b false, it + * generates NACK/ACK, depending on + * normal criteria. + * * \b true = generate NACK after data + * byte received + * * \b false = generate NACK/ACK normally + */ +} ALT_I2C_SLAVE_CONFIG_t; + +/*! + * Initialize the specified I2C controller instance for use and return a device + * handle referencing it. + * + * \param i2c + * The HPS I2C controller instance to initialize. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); + +/*! + * Reset the specified I2C controller instance for use. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); + +/*! + * Uninitialize the I2C controller referenced by the \e i2c_dev handle. + * + * This function attempts to gracefully shutdown the I2C controller by waiting for + * any inpcomplete transactions to finish and then putting the I2C controller into + * reset. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Disables the I2C controller. + * + * When the I2C controller is disabled, the following occurs: + * * The TX FIFO and RX FIFO get flushed. + * * The I2C interrupt status conditions remain active until the I2C controller + * goes into IDLE state. + * + * If the controller is transmitting, it stops as well as deletes the contents of + * the transmit buffer after the current transfer is complete. If the module is + * receiving, the controller stops the current transfer at the end of the current + * byte and does not acknowledge the transfer. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 0 + * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Gets the current configuration of the I2C controller when operating in master + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding + * the returned I2C master mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in master mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired + * I2C master mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * This is a utility function that returns the speed based on parameters of the + * I2C master configuration. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * [out] Speed (Hz) of the I2C bus currently configured at. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg, + uint32_t * speed_in_hz); + +/*! + * This is a utility function that computes parameters for the I2C master + * configuration that best matches the speed requested. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * Speed (Hz) of the I2C bus to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz); + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Gets the current configuration of the I2C controller when operating in slave + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding + * the returned I2C slave mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in slave mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired + * I2C slave mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration + * + * The I2C protocol specification requires 300ns of hold time on the SDA signal in + * standard and fast speed modes. Board delays on the SCL and SDA signals can mean + * that the hold-time requirement is met at the I2C master, but not at the I2C + * slave (or vice-versa). Because each system may encounter differing board signal + * delays, the I2C controller provides the capability to adjust of the SDA + * hold-time. + * + * The functions in this section provide software configuration of SDA hold time + * for the I2C controller. + * + * @{ + */ + +/*! + * Gets the currently configured value for the SDA hold time in I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock + * ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time); + +/*! + * Sets the configured value for the SDA hold time in terms of I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time); + +/*! @} */ + +/*! + * Gets the current operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * [out] The current operational mode enabled for the I2C + * controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode); + +/*! + * Sets the operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * The operational mode to enable for the I2C controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode); + +/*! + * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if + * either the Slave Finite State Machine (FSM) is not in the IDLE state or the + * Master Finite State Machine (FSM) is not in the IDLE state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.ACTIVITY == 1 + * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); + +/*! + * This function reads a single data byte from the receive FIFO. + * + * This function is used to perform low level access to the data bytes + * received by the I2C controller and buffered in the receive FIFO. It + * may be used by master-receivers or slave receivers. + * + * This function does not check for valid data in the receive FIFO + * beforehand and may cause an underflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_receive() or alt_i2c_master_receive() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * [out] The single data byte read from the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); + +/*! + * This function writes a single data byte to the transmit FIFO. + * + * This function is used to perform low level writes of data to the + * transmit FIFO for transmission by the I2C controller. It may be + * used by slave receivers. + * + * This function does not check whether the transmit FIFO is full or + * not beforehand and may cause an overflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_transmit() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * The data byte to write to the transmission FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); + +/*! + * This function acts in the role of a slave-receiver by receiving a single data + * byte from the I2C bus in response to a write command from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is data in the RX FIFO to + * accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] A pointer to a buffer to contain the received data byte. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, + uint8_t *data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting a single + * data byte to the I2C bus in response to a read request from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * The data byte to transmit. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting data in + * bulk to the I2C bus in response to a series of read requests from a master. + * + * In the standard I2C protocol, all transactions are single byte transactions and + * the slave responds to a remote master read request by writing one byte into the + * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request + * from the remote master (master-receiver), at a minimum there should be at least + * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is + * capable of handling more data in the TX FIFO so that subsequent read requests + * can receive that data without raising an interrupt or software having to poll + * to request more data. This eliminates overhead latencies from being incurred by + * servicing the interrupt or polling for data requests each time had there been a + * restriction of having only one entry placed in the TX FIFO. + * + * If the remote master acknowledges the data sent by the slave-transmitter and + * there is no data in the slave's TX FIFO, the I2C controller raises the read + * request interrupt and waits for data to be written into the TX FIFO before it + * can be sent to the remote master. + * + * If the programmer knows in advance that the master is requesting a packet of \e + * n bytes, then when another master request for data is received, the TX FIFO + * could be written with \e n number bytes and the master receives it as a + * continuous stream of data. For example, the slave continues to send data to the + * master as long as the master is acknowledging the data sent and there is data + * available in the TX FIFO. There is no need to hold the SCL line low or to issue + * READ request again. + * + * If the remote master is to receive \e n bytes from the slave but the programmer + * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave + * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores + * any excess bytes. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to the data buffer to transmit. + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: Section Slave-Transfer Operation for Bulk Transfers of the DW + * Databook for details of implementation and error conditions that may occur. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size); + +/*! + * This function returns the current target address. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * [out] The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); + +/*! + * This function updates the target slave address for any upcoming I2C bus IO. + * + * This API is not suitlabe for being called in an interrupt context as it + * will wait for the TX FIFO to flush before applying the changes. If the TX + * FIFO is known to be empty and the controller idle, then it can be safely + * called. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); + +/*! + * This function acts in the role of a master-transmitter by issuing a write + * command and transmitting data to the I2C bus. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to a data buffer to transmit + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function acts in the role of a master-receiver by receiving one or more + * data bytes transmitted from a slave in response to read requests issued from + * this master. + * + * This function causes the master to issue the required number of read requests + * to the slave and read the received data bytes from the Rx FIFO. + * + * The \e issue_restart and \e issue_stop parameters apply to the final read + * request transaction in the \e num_data_entries sequence required to fulfill the + * aggregate receive request. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] The data buffer to receive the requested \e size bytes. + * + * \param size + * The size of the data buffer to read from the RX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a READ request on the + * bus. This function is typically used during master-receiver transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is + * written with "don't care" values as these bits are ignored by the + * I2C controller . + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a send byte on the + * bus. This function is typically used during master-transmitter/slave-transmitter + * transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param value + * The data item to be transmitted. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 0 (write request). + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop); + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_GEN_CALL General Call + * + * The functions in this group support General Call addresses. + * + * The general call address is for addressing every device connected to the I2C + * bus at the same time. However, if a device does not need any of the data + * supplied within the general call structure, it can ignore this address by not + * issuing an acknowledgment. If a device does require data from a general call + * address, it acknowledges this address and behaves as a slave-receiver. The + * master does not actually know how many devices acknowledged if one or more + * devices respond. The second and following bytes are acknowledged by every + * slave-receiver capable of handling this data. A slave who cannot process one of + * these bytes must ignore it by not-acknowledging. If one or more slaves + * acknowledge, the not-acknowledge will not be seen by the master. + * + * The functions in this group do not provide any general call functional command + * interpretation or implementation (e.g. software reset). + * + * @{ + */ + +/*! + * This function acts in the role of a master-transmitter by issuing a general + * call command to all devices connected to the I2C bus. + * + * The \e issue_restart and \e issue_stop parameters apply to the final write + * transaction in the \e num_data_entries byte transmission sequence. + * + * The I2C controller must be in master mode before calling this function. + * + * The target slave address will be modified by this function. Call + * alt_i2c_master_target_set() to reset the slave target address for + * subsequent IO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * An array of data byte(s) to transmit. + * + * \param num_data_entries + * The number of entries (bytes) in \e data to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * Disables the I2C controller from responding to a General Call address. The + * controller will respond with a NACK and no General Call status conditions or + * interrupts are generated. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller to respond with an ACK when it receives a General + * Call address. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call + * addresses. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions + * + * The functions in this group provide management for the I2C controller status + * conditions and interrupts. + * + * Each I2C controller has a single combined interrupt output (\b + * ALT_INT_INTERRUPT_I2Cn_IRQ). The following events can generate an + * interrupt: + * * General Call Address Received + * * Start or Restart Condition Occurred + * * Stop Condition Occurred + * * I2C Controller Activity + * * Receive Done + * * Transmit Abort + * * Read Request + * * Transmit Buffer Empty + * * Transmit Overflow + * * Receive Buffer Full + * * Receive Overflow + * * Receive Underflow + * + * These interrupt status conditions may be monitored either by polling their + * status or by configuring interrupt handlers using the HWLIB Interrupt + * Controller API. + * + * Functions to get the current status, enable or disable (i.e. mass or unmask), + * and clear interrupt status conditions for the I2C controller are defined in + * this section. + * + * @{ + */ + +/*! + * Returns the current I2C controller interrupt status conditions. + * + * This function returns the current value of the I2C controller interrupt status + * register value which reflects the current I2C controller status conditions that + * are not disabled (i.e. masked). + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Returns the I2C controller raw interrupt status conditions irrespective of + * the interrupt status condition enablement state. + * + * This function returns the current value of the I2C controller raw interrupt + * status register value which reflects the current I2C controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Clears the specified I2C controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Disable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_enable() is used to enable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Enable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_disable() is used to disable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Gets the cause of I2C transmission abort. A I2C transmission abort indicates + * that the I2C transmitter is unable to complete the intended actions on the + * contents of the transmit FIFO. This situation can occur both as an I2C master + * or an I2C slave, and is referred to as a "transmit abort". + * + * The returned value of this function is the value of the IC_TX_ABRT_SOURCE + * register which indicates the cause why the transmit abort occurred. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cause + * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t + * causes of the transmission abort. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_ABRT_SOURCE + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) + * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller receive FIFO. + */ +#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) + * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller transmit FIFO. + */ +#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_DMA DMA Interface + * + * The DMA interface has a configurable threshold value that controls the + * level of entries that triggers the burst handshaking request used for DMA + * integration. + * + * For the TX threshold, if the number of entries in the TX FIFO is at or + * below the set threshold, a DMA handshaking request will be made. The valid + * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * For the RX threshold, if the number of entries in the RX FIFO is above the + * set threshold, a DMA handshaking request will be made. The valid range for + * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * Having a higher threshold can improve the AXI bus utilization at the + * expense of the likelyhoold of overflow / underflow conditions. + * @{ + */ + +/*! + * Gets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! + * Gets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_I2C_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h new file mode 100644 index 0000000000..004fd3188c --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h @@ -0,0 +1,533 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_INT_COMMON_H__ +#define __ALT_INT_COMMON_H__ + +#include "hwlib.h" +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup INT_COMMON Interrupt Controller Common Definitions + * + * This module contains the definitions common to the Interrupt Controller + * Low-Level API and Interrupt Controller Manager Interface. + * + * @{ + */ + +/*! + * This type definition enumerates all the interrupt identification types. + */ +typedef enum ALT_INT_INTERRUPT_e +{ + ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */ + ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */ + ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */ + ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */ + ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */ + ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */ + ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */ + ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */ + ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */ + ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */ + ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */ + ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */ + ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */ + ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */ + ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */ + ALT_INT_INTERRUPT_SGI15 = 15, + /*!< + * Software Generated Interrupts (SGI), 0 - 15. + * * All interrupts in this group are software triggered. + */ + + ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */ + /*!< + * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU + * private timer, and watchdog timer. + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, + /*!< + * Interrupts sourced from CPU0. + * + * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU0. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, + /*!< + * Interrupts sourced from CPU1. + * + * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU1. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */ + ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */ + ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, + /*!< + * Interrupts sourced from the Snoop Control Unit (SCU). + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */ + ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, + /*!< + * Interrupts sourced from the L2 Cache Controller. + * + * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache + * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, + * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts. + * Consult the L2C documentation for information on these interrupts. + * + * * ECC interrupts in this group are edge triggered. + * * Other interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, + /*!< + * Interrupts sourced from the SDRAM Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, + /*!< + * Interrupt request from the FPGA logic, 0 - 63. + * * Trigger type depends on the implementation in the FPGA. + */ + + ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, + /*!< + * Interrupts sourced from the DMA Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, + /*!< + * Interrupts sourced from the Ethernet MAC 0 (EMAC0). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156, + /*!< + * Interrupts sourced from the Ethernet MAC 1 (EMAC1). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, + /*!< + * Interrupts sourced from the USB OTG 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, + /*!< + * Interrupts sourced from the USB OTG 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */ + ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, + /*!< + * Interrupts sourced from the CAN Controller 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */ + ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, + /*!< + * Interrupts sourced from the CAN Controller 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, + /*!< + * Interrupts sourced from the SDMMC Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, + /*!< + * Interrupts sourced from the NAND Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, + /*!< + * Interrupts sourced from the QSPI Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */ + ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */ + ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */ + ALT_INT_INTERRUPT_SPI3_IRQ = 189, + /*!< + * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */ + ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */ + ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */ + ALT_INT_INTERRUPT_I2C3_IRQ = 193, + /*!< + * Interrupts sourced from the I2C Controllers 0 - 3. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_UART0 = 194, /*!< # */ + ALT_INT_INTERRUPT_UART1 = 195, + /*!< + * Interrupts sourced from the UARTs 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */ + ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */ + ALT_INT_INTERRUPT_GPIO2 = 198, + /*!< + * Interrupts sourced from the GPIO 0 - 2. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */ + ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, + /*!< + * Interrupts sourced from the Timer controllers. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */ + ALT_INT_INTERRUPT_WDOG1_IRQ = 204, + /*!< + * Interrupts sourced from the Watchdog Timers 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, + /*!< + * Interrupts sourced from the Clock Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, + /*!< + * Interrupts sourced from the Clock Manager MPU Wakeup. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, + /*!< + * Interrupts sourced from the FPGA Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */ + ALT_INT_INTERRUPT_NCTIIRQ1 = 209, + /*!< + * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */ + ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 + /*!< + * Interrupts sourced from the On-chip RAM. + * * All interrupts in this group are level triggered. + */ + +} ALT_INT_INTERRUPT_t; + +/*! + * This is the CPU target type. It is used to specify a set of CPUs on the + * system. If only bit 0 is set then it specifies a set of CPUs containing + * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit + * up to the number of CPUs on the system. + */ +typedef uint32_t alt_int_cpu_target_t; + +/*! + * This type definition enumerates all the interrupt trigger types. + */ +typedef enum ALT_INT_TRIGGER_e +{ + /*! + * Edge triggered interrupt. This applies to Private Peripheral Interrupts + * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs + * 16 - 1019. + */ + ALT_INT_TRIGGER_EDGE, + + /*! + * Level triggered interrupt. This applies to Private Peripheral + * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with + * interrupt IDs 16 - 1019. + */ + ALT_INT_TRIGGER_LEVEL, + + /*! + * Software triggered interrupt. This applies to Software Generated + * Interrupts (SGI) only, with interrupt IDs 0 - 15. + */ + ALT_INT_TRIGGER_SOFTWARE, + + /*! + * All triggering types except for those in the Shared Peripheral Interrupts + * (SPI) F2S FPGA family interrupts can be determined by the system + * automatically. In all functions which ask for the triggering type, the + * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger + * type for all non F2S interrupt types. + */ + ALT_INT_TRIGGER_AUTODETECT, + + /*! + * The interrupt triggering information is not applicable. This is possibly + * due to querying an invalid interrupt identifier. + */ + ALT_INT_TRIGGER_NA +} +ALT_INT_TRIGGER_t; + +/*! + * This type definition enumerates all the target list filter options. This is + * used by the trigger Software Generated Interrupt (SGI) feature to issue a + * SGI to the specified processor(s) in the system. Depending on the target + * list filter and the target list, interrupts can be routed to any + * combinations of CPUs. + */ +typedef enum ALT_INT_SGI_TARGET_e +{ + /*! + * This filter list uses the target list parameter to specify which CPUs + * to send the interrupt to. If target list is 0, no interrupts are sent. + */ + ALT_INT_SGI_TARGET_LIST, + + /*! + * This filter list sends the interrupt all CPUs except the current CPU. + * The target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, + + /*! + * This filter list sends the interrupt to the current CPU only. The + * target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_SENDER_ONLY +} +ALT_INT_SGI_TARGET_t; + +/*! + * Extracts the CPUID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7) + +/*! + * Extracts the ACKINTID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF) + +/*! + * The callback to use when an interrupt needs to be serviced. + * + * \param icciar The Interrupt Controller CPU Interrupt + * Acknowledgement Register value (ICCIAR) value + * corresponding to the current interrupt. + * + * \param context The user provided context. + */ +typedef void (*alt_int_callback_t)(uint32_t icciar, void * context); + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_INT_COMMON_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h new file mode 100644 index 0000000000..2ead15df86 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h @@ -0,0 +1,156 @@ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_MPUSCU_H__ +#define __ALT_MPUSCU_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/************************************************************************************************************/ +/* alt_mpuscu.h */ +/* */ +/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */ +/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */ +/* */ +/************************************************************************************************************/ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0x00 +#endif + + +/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */ +/* and is the address of the base of the Snoop Control Unit (SCU) */ +#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET) +#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET) +#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET) +#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET) +#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET) + + + /* offsets */ + /* Global Timer offsets */ +#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200 +#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000 +#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004 +#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008 +#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C +#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010 +#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014 +#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018 + +/* Global Timer bitmasks */ +#define GLOBALTMR_ENABLE_BIT 0x00000001 +#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002 +#define GLOBALTMR_INT_ENABLE_BIT 0x00000004 +#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008 +#define GLOBALTMR_PS_MASK 0x0000FF00 +#define GLOBALTMR_PS_SHIFT 8 +#define GLOBALTMR_INT_STATUS_BIT 0x00000001 + +/* Global timer constants */ +#define GLOBALTMR_MAX 0xFFFFFFFF +#define GLOBALTMR_PS_MAX 0x000000FF + + +/* Private timer offsets */ +#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600 +#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000 +#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004 +#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008 +#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C + +/* Private timer bitmasks */ +#define CPU_PRIV_TMR_ENABLE 0x00000001 +#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002 +#define CPU_PRIV_TMR_INT_EN 0x00000004 +#define CPU_PRIV_TMR_PS_MASK 0x0000FF00 +#define CPU_PRIV_TMR_PS_SHIFT 8 +#define CPU_PRIV_TMR_INT_STATUS 0x00000001 + +/* Private timer constants */ +#define CPU_PRIV_TMR_MAX 0xFFFFFFFF +#define CPU_PRIV_TMR_PS_MAX 0x000000FF + + + + /* Watchdog timer offsets */ +#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620 +#define WDOG_LOAD_REG_OFFSET 0x00000000 +#define WDOG_CNTR_REG_OFFSET 0x00000004 +#define WDOG_CTRL_REG_OFFSET 0x00000008 +#define WDOG_INTSTAT_REG_OFFSET 0x0000000C +#define WDOG_RSTSTAT_REG_OFFSET 0x00000010 +#define WDOG_DISABLE_REG_OFFSET 0x00000014 + + /* Watchdog timer bitmasks : */ + /* Control Register bitmasks */ +#define WDOG_TMR_ENABLE 0x00000001 +#define WDOG_AUTO_RELOAD 0x00000002 +#define WDOG_INT_EN 0x00000004 +#define WDOG_WDT_MODE 0x00000008 +#define WDOG_PS_MASK 0x0000FF00 +#define WDOG_PS_SHIFT 8 + /* Interrupt Status Register bitmasks */ +#define WDOG_INT_STAT_BIT 0x00000001 + /* Reset Status Register bitmasks */ +#define WDOG_RST_STAT_BIT 0x00000001 + + /* Watchdog timer constants */ +#define WDOG_TMR_MAX UINT32_MAX +#define WDOG_PS_MAX UINT8_MAX +#define WDOG_DISABLE_VAL0 0x12345678 +#define WDOG_DISABLE_VAL1 0x87654321 + + + + /* Interrupt Manager offsets */ +/* */ +#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100 +#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000 +#define INT_DIST_TYPE_REG 0x00000004 + + +/* Upper bound of the MPUSCU address space */ +#define MPUSCU_MAX 0x00001FFF + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_MPUSCU_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h new file mode 100644 index 0000000000..21fd3a957d --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_PRIVATE_H__ +#define __ALT_QSPI_PRIVATE_H__ + +#include "socal/socal.h" + +// +// This section provisions support for various flash devices. +// + +#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 + +///// + +#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 +#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B +#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 +#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B +#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 +#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB +#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 +#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 +#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB +#endif + +///// + +// Default delay timing (in ns) for N25Q. +// These values are from the N25Q handbook. The timing correctness is difficult +// to test because the test setup does not feature mutliple chips. +#define ALT_QSPI_TSHSL_NS_DEF (50) +#define ALT_QSPI_TSD2D_NS_DEF (0) +#define ALT_QSPI_TCHSH_NS_DEF (4) +#define ALT_QSPI_TSLCH_NS_DEF (4) + +/* +// Default delay timing (in ns) +#define ALT_QSPI_TSHSL_NS_DEF (200) +#define ALT_QSPI_TSD2D_NS_DEF (255) +#define ALT_QSPI_TCHSH_NS_DEF (20) +#define ALT_QSPI_TSLCH_NS_DEF (20) +*/ + +// Flash commands +#define ALT_QSPI_STIG_OPCODE_READ (0x03) +#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) +#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) +#define ALT_QSPI_STIG_OPCODE_PP (0x02) +#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) +#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) +#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) +#define ALT_QSPI_STIG_OPCODE_WREN (0x06) +#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) +#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) +#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) +#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) +#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) +#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) +#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) +#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) +#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) +#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) +#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) +#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) +#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) +#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) + +// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) +#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) +#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) +#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) +#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) +#endif + +// Spansion commands +// #define OPCODE_ECRM (0xFF) // Exit continuous read mode + +#define QSPI_READ_CLK_MHZ (50) +#define QSPI_FASTREAD_CLK_MHZ (100) + +// Manufacturer ID +#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) +#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron +#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) +#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion +#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) +#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) + +#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) +#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) + +#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) + +#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) + +///// + +#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, uint32_t * output, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, const uint32_t * input, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t address, + uint32_t timeout); + +ALT_STATUS_CODE alt_qspi_device_wren(void); +ALT_STATUS_CODE alt_qspi_device_wrdis(void); +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); + +#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h new file mode 100644 index 0000000000..d719e3f05e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h @@ -0,0 +1,291 @@ +/*! \file + * Altera - SoC Reset Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_RESET_MGR_H__ +#define __ALT_RESET_MGR_H__ + +#include "hwlib.h" +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup RST_MGR The Reset Manager + * + * The Reset Manager API defines functions for accessing, configuring, and + * controlling the HPS reset behavior. + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_STATUS Reset Status + * + * This functional group provides information on various aspects of SoC reset + * status and timeout events. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the set of reset causes and timeout events as + * register mask values. + */ +typedef enum ALT_RESET_EVENT_e +{ + /*! Power-On Voltage Detector Cold Reset */ + ALT_RESET_EVENT_PORVOLTRST = 0x00000001, + + /*! nPOR Pin Cold Reset */ + ALT_RESET_EVENT_NPORPINRST = 0x00000002, + + /*! FPGA Core Cold Reset */ + ALT_RESET_EVENT_FPGACOLDRST = 0x00000004, + + /*! CONFIG_IO Cold Reset */ + ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008, + + /*! Software Cold Reset */ + ALT_RESET_EVENT_SWCOLDRST = 0x00000010, + + /*! nRST Pin Warm Reset */ + ALT_RESET_EVENT_NRSTPINRST = 0x00000100, + + /*! FPGA Core Warm Reset */ + ALT_RESET_EVENT_FPGAWARMRST = 0x00000200, + + /*! Software Warm Reset */ + ALT_RESET_EVENT_SWWARMRST = 0x00000400, + + /*! MPU Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_MPUWD0RST = 0x00001000, + + /*! MPU Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_MPUWD1RST = 0x00002000, + + /*! L4 Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_L4WD0RST = 0x00004000, + + /*! L4 Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_L4WD1RST = 0x00008000, + + /*! FPGA Core Debug Reset */ + ALT_RESET_EVENT_FPGADBGRST = 0x00040000, + + /*! DAP Debug Reset */ + ALT_RESET_EVENT_CDBGREQRST = 0x00080000, + + /*! SDRAM Self-Refresh Timeout */ + ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000, + + /*! FPGA manager handshake Timeout */ + ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000, + + /*! SCAN manager handshake Timeout */ + ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000, + + /*! FPGA handshake Timeout */ + ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000, + + /*! ETR Stall Timeout */ + ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000 +} ALT_RESET_EVENT_t; + +/******************************************************************************/ +/*! + * Gets the reset and timeout events that caused the last reset. + * + * The ALT_RESET_EVENT_t enumeration values should be used to selectively + * examine the returned reset cause(s). + * + * \returns A mask of the reset and/or timeout events that caused the last + * reset. + */ +uint32_t alt_reset_event_get(void); + +/******************************************************************************/ +/*! + * Clears the reset and timeout events that caused the last reset. + * + * \param event_mask + * A mask of the selected reset and timeout events to clear in the + * Reset Manager \e stat register. The mask selection can be formed + * using the ALT_RESET_EVENT_t enumeration values. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_CTRL Reset Control + * + * This functional group provides global and selective reset control for the SoC + * and its constituent modules. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initiate a cold reset of the SoC. + * + * If this function is successful, then it should never return. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_cold_reset(void); + +/******************************************************************************/ +/*! + * Initiate a warm reset of the SoC. + * + * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced + * reset handshake with certain modules can optionally be requested in an + * attempt to ensure an orderly reset transition. + * + * \param warm_reset_delay + * Specifies the number of cycles after the Reset Manager releases + * the Clock Manager reset before releasing any other hardware + * controlled resets. Value must be greater than 16 and less than + * 256. + * + * \param nRST_pin_clk_assertion + * Specifies that number of clock cycles (osc1_clk?) to externally + * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <= + * (2**20 - 1). A value of 0 prevents any assertion of nRST. + * + * \param sdram_refresh + * Controls whether the contents of SDRAM survive a hardware + * sequenced warm reset. The reset manager requests the SDRAM + * controller to put SDRAM devices into self-refresh mode before + * asserting warm reset signals. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param fpga_mgr_handshake + * Controls whether a handshake between the reset manager and FPGA + * manager occurs before a warm reset. The handshake is used to + * warn the FPGA manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param scan_mgr_handshake + * Controls whether a handshake between the reset manager and scan + * manager occurs before a warm reset. The handshake is used to + * warn the scan manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param fpga_handshake + * Controls whether a handshake between the reset manager and the + * FPGA occurs before a warm reset. The handshake is used to warn + * the FPGA that a warm reset is imminent so that the FPGA prepare + * for the reset event in soft IP. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param etr_stall + * Controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate + * any more) to the L3 Interconnect before a warm reset. An + * argument value of \b true enables the option, \b false disables + * the option. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, + uint32_t nRST_pin_clk_assertion, + bool sdram_refresh, + bool fpga_mgr_handshake, + bool scan_mgr_handshake, + bool fpga_handshake, + bool etr_stall); + +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_RESET_MGR_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h new file mode 100644 index 0000000000..aba7e877c4 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h @@ -0,0 +1,189 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HWLIB_H__ +#define __HWLIB_H__ + +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ + +#include "alt_hwlibs_ver.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * The type definition for status codes returned by the HWLIB. + */ +typedef int32_t ALT_STATUS_CODE; + +/*! Definitions of status codes returned by the HWLIB. */ + +/*! The operation was successful. */ +#define ALT_E_SUCCESS 0 + +/*! The operation failed. */ +#define ALT_E_ERROR (-1) +/*! FPGA configuration error detected.*/ +#define ALT_E_FPGA_CFG (-2) +/*! FPGA CRC error detected. */ +#define ALT_E_FPGA_CRC (-3) +/*! An error occurred on the FPGA configuration bitstream input source. */ +#define ALT_E_FPGA_CFG_STM (-4) +/*! The FPGA is powered off. */ +#define ALT_E_FPGA_PWR_OFF (-5) +/*! The SoC does not currently control the FPGA. */ +#define ALT_E_FPGA_NO_SOC_CTRL (-6) +/*! The FPGA is not in USER mode. */ +#define ALT_E_FPGA_NOT_USER_MODE (-7) +/*! An argument violates a range constraint. */ +#define ALT_E_ARG_RANGE (-8) +/*! A bad argument value was passed. */ +#define ALT_E_BAD_ARG (-9) +/*! The operation is invalid or illegal. */ +#define ALT_E_BAD_OPERATION (-10) +/*! An invalid option was selected. */ +#define ALT_E_INV_OPTION (-11) +/*! An operation or response timeout period expired. */ +#define ALT_E_TMO (-12) +/*! The argument value is reserved or unavailable. */ +#define ALT_E_RESERVED (-13) +/*! A clock is not enabled or violates an operational constraint. */ +#define ALT_E_BAD_CLK (-14) +/*! The version ID is invalid. */ +#define ALT_E_BAD_VERSION (-15) +/*! The buffer does not contain enough free space for the operation. */ +#define ALT_E_BUF_OVF (-20) + +/*! + * Indicates a FALSE condition. + */ +#define ALT_E_FALSE (0) +/*! + * Indicates a TRUE condition. + */ +#define ALT_E_TRUE (1) + +/* Note, additional positive status codes may be defined to return + * a TRUE condition with additional information */ + + +/* Some other useful definitions */ + +/*! + * Specifies the current major and minor revision of the HWLibs. The + * MS four decimal digits specify the Altera ACDS release number, the + * LS two decimal digits specify minor revisions of the HWLibs, if any. + * + * A typical use is: + * \code + * #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0) + * \endcode + * for a dependency on the major or minor ACDS revision + * or + * \code + * #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12) + * \endcode + * for a dependency on the hwlibs revision + * + */ +#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c)) + +#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \ + ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV) + +/*! + * Allow some parts of the documentation to be hidden by setting to zero + */ +#define ALTERA_INTERNAL_ONLY_DOCS 1 + + +/*! + * Provide base address of MPU address space + */ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0 +#endif + +/*! + * These constants are sometimes useful: + */ +#define ALT_MILLISECS_IN_A_SEC 1000 +#define ALT_MICROSECS_IN_A_SEC 1000000 +#define ALT_NANOSECS_IN_A_SEC 1000000000 + +#define ALT_TWO_TO_POW0 (1) +#define ALT_TWO_TO_POW1 (1<<1) +#define ALT_TWO_TO_POW2 (1<<2) +#define ALT_TWO_TO_POW3 (1<<3) +#define ALT_TWO_TO_POW4 (1<<4) +#define ALT_TWO_TO_POW5 (1<<5) +#define ALT_TWO_TO_POW6 (1<<6) +#define ALT_TWO_TO_POW7 (1<<7) +#define ALT_TWO_TO_POW8 (1<<8) +#define ALT_TWO_TO_POW9 (1<<9) +#define ALT_TWO_TO_POW10 (1<<10) +#define ALT_TWO_TO_POW11 (1<<11) +#define ALT_TWO_TO_POW12 (1<<12) +#define ALT_TWO_TO_POW13 (1<<13) +#define ALT_TWO_TO_POW14 (1<<14) +#define ALT_TWO_TO_POW15 (1<<15) +#define ALT_TWO_TO_POW16 (1<<16) +#define ALT_TWO_TO_POW17 (1<<17) +#define ALT_TWO_TO_POW18 (1<<18) +#define ALT_TWO_TO_POW19 (1<<19) +#define ALT_TWO_TO_POW20 (1<<20) +#define ALT_TWO_TO_POW21 (1<<21) +#define ALT_TWO_TO_POW22 (1<<22) +#define ALT_TWO_TO_POW23 (1<<23) +#define ALT_TWO_TO_POW24 (1<<24) +#define ALT_TWO_TO_POW25 (1<<25) +#define ALT_TWO_TO_POW26 (1<<26) +#define ALT_TWO_TO_POW27 (1<<27) +#define ALT_TWO_TO_POW28 (1<<28) +#define ALT_TWO_TO_POW29 (1<<29) +#define ALT_TWO_TO_POW30 (1<<30) +#define ALT_TWO_TO_POW31 (1<<31) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HWLIB_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h new file mode 100644 index 0000000000..9a4411d637 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2CDRV_H +#define I2CDRV_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +rtems_device_driver i2cdrv_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +rtems_device_driver i2cdrv_ioctl( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +#define I2C_DRIVER_TABLE_ENTRY \ + { \ + i2cdrv_initialize, \ + i2cdrv_open, \ + i2cdrv_close, \ + i2cdrv_read, \ + i2cdrv_write, \ + i2cdrv_ioctl \ + } + +#define I2C_IOC_SET_SLAVE_ADDRESS 1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2CDRV_H */ diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h new file mode 100644 index 0000000000..c136500415 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H +#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Use interrupt IDs as defined in alt_interrupt_common.h */ +#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0 +#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */ \ No newline at end of file diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h new file mode 100644 index 0000000000..3a6bf0fffa --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h new file mode 100644 index 0000000000..1875a84f10 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h @@ -0,0 +1,6464 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_CLKMGR */ + +#ifndef __ALTERA_ALT_CLKMGR_H__ +#define __ALTERA_ALT_CLKMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Clock Manager Module - ALT_CLKMGR + * Clock Manager Module + * + * Registers in the Clock Manager module + * + */ +/* + * Register : Control Register - ctrl + * + * Contains fields that control the entire Clock Manager. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Safe Mode + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x1 | Enable SafeMode on Warm Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Safe Mode - safemode + * + * When set the Clock Manager is in Safe Mode. + * + * In Safe Mode Clock Manager register settings defining clock behavior are ignored + * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the + * optional exception of debug clocks, are directly generated from the EOSC1 clock + * input, all PLLs are bypassed, all programmable dividers are set to 1 and all + * clocks are enabled. + * + * This bit should only be cleared when clocks have been correctly configured + * + * This field is set on a cold reset and optionally on a warm reset and may not be + * set by SW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_MSB 0 +/* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable SafeMode on Warm Reset - ensfmdwr + * + * When set the Clock Manager will respond to a Safe Mode request from the Reset + * Manager on a warm reset by setting the Safe Mode bit. When clear the clock + * manager will not set the the Safe Mode bit on a warm reset This bit is cleared + * on a cold reset. Warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2 +/* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_CTL. + */ +struct ALT_CLKMGR_CTL_s +{ + uint32_t safemode : 1; /* Safe Mode */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_CTL. */ +typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_CTL_OFST 0x0 + +/* + * Register : PLL Bypass Register - bypass + * + * Contains fields that control bypassing each PLL. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x1 | Main PLL Bypass + * [1] | RW | 0x1 | SDRAM PLL Bypass + * [2] | RW | 0x0 | SDRAM PLL Bypass Source + * [3] | RW | 0x1 | Peripheral PLL Bypass + * [4] | RW | 0x0 | Peripheral PLL Bypass Source + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Bypass - mainpll + * + * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks + * generated by the Main PLL are directly driven from the Main PLL input clock. The + * bypass source for Main PLL is the external eosc1_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0 +/* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDRAM PLL Bypass - sdrpll + * + * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all + * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or + * the SDRAM PLL input clock. + * + * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass + * Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Bypass Source - sdrpllsrc + * + * This bit defines the bypass source forSDRAM PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Peripheral PLL Bypass - perpll + * + * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all + * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk + * or the Peripheral PLL input clock. + * + * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL + * Bypass Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_MSB 3 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Bypass Source - perpllsrc + * + * This bit defines the bypass source forPeripheral PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_BYPASS. + */ +struct ALT_CLKMGR_BYPASS_s +{ + uint32_t mainpll : 1; /* Main PLL Bypass */ + uint32_t sdrpll : 1; /* SDRAM PLL Bypass */ + uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */ + uint32_t perpll : 1; /* Peripheral PLL Bypass */ + uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_BYPASS. */ +typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */ +#define ALT_CLKMGR_BYPASS_OFST 0x4 + +/* + * Register : Interrupt Status Register - inter + * + * Contains fields that indicate the PLL lock status. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock + * [3] | RW | 0x0 | Main PLL Lost Lock + * [4] | RW | 0x0 | Peripheral PLL Lost Lock + * [5] | RW | 0x0 | SDRAM PLL Lost Lock + * [6] | R | Unknown | Main PLL Current Lock Status + * [7] | R | Unknown | Peripheral PLL Current Lock Status + * [8] | R | Unknown | SDRAM PLL Current Lock Status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock - mainpllachieved + * + * If 1, the Main PLL has achieved lock at least once since this bit was cleared. + * If 0, the Main PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock - perpllachieved + * + * If 1, the Peripheral PLL has achieved lock at least once since this bit was + * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was + * cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock - sdrpllachieved + * + * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared. + * If 0, the SDRAM PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Lost Lock - mainplllost + * + * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, + * the Main PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Lost Lock - perplllost + * + * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. + * If 0, the Peripheral PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Lost Lock - sdrplllost + * + * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If + * 0, the SDRAM PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Main PLL Current Lock Status - mainplllocked + * + * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Peripheral PLL Current Lock Status - perplllocked + * + * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is + * currently not locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDRAM PLL Current Lock Status - sdrplllocked + * + * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTER. + */ +struct ALT_CLKMGR_INTER_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */ + uint32_t mainplllost : 1; /* Main PLL Lost Lock */ + uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */ + uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */ + const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */ + const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */ + const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTER. */ +typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */ +#define ALT_CLKMGR_INTER_OFST 0x8 + +/* + * Register : Interrupt Enable Register - intren + * + * Contain fields that enable the interrupt. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved + * + * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved + * + * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock + * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is + * not ORed into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved + * + * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost + * + * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the + * Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost + * + * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost + * + * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTREN. + */ +struct ALT_CLKMGR_INTREN_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTREN. */ +typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */ +#define ALT_CLKMGR_INTREN_OFST 0xc + +/* + * Register : Debug clock Control Register - dbctrl + * + * Contains fields that control the debug clocks. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK + * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1 + * + * When this bit is set the debug root clock (Main PLL C2 output) will always be + * bypassed to the EOSC1_clk independent of any other clock manager settings. + * When clear the debug source will be a function of register settings in the clock + * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, + * and dbg_timer_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0 +/* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Debug Clocks Enable Safe Mode - ensfmdwr + * + * When this bit is set the debug clocks will be affected by the assertion of Safe + * Mode on a warm reset if Stay OSC1 is not set. + * + * When this bit is clear the debug clocks will not be affected by the assertion of + * Safe Mode on a warm reset. + * + * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe + * Mode bit is cleared independent of this bit.The reset value of this bit is + * applied on a cold reset; warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1 +/* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_DBCTL. + */ +struct ALT_CLKMGR_DBCTL_s +{ + uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */ + uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_DBCTL. */ +typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */ +#define ALT_CLKMGR_DBCTL_OFST 0x10 + +/* + * Register : Status Register - stat + * + * Provides status of Hardware Managed Clock transition State Machine. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | HW Managed Clocks BUSY + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HW Managed Clocks BUSY - busy + * + * This read only bit indicates that the Hardware Managed clock's state machine is + * active. If the state machine is active, then the clocks are in transition. + * Software should poll this bit after changing the source of internal clocks when + * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes + * to any of these registers, SW should wait until this bit is IDLE before + * proceeding with any other register writes in the Clock Manager. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------- + * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable + * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks stable + */ +#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks in transition + */ +#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_MSB 0 +/* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_RESET 0x0 +/* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */ +#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */ +#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_STAT. + */ +struct ALT_CLKMGR_STAT_s +{ + const uint32_t busy : 1; /* HW Managed Clocks BUSY */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_STAT. */ +typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_STAT_OFST 0x14 + +/* + * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL + * Main PLL Group + * + * Contains registers with settings for the Main PLL. + * + */ +/* + * Register : Main PLL VCO Control Register - vco + * + * Contains settings that control the Main PLL VCO. The VCO output frequency is the + * input frequency multiplied by the numerator (M+1) and divided by the denominator + * (N+1). The VCO input clock source is always eosc1_clk. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO. + */ +struct ALT_CLKMGR_MAINPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0 + +/* + * Register : Main PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC. + */ +struct ALT_CLKMGR_MAINPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4 + +/* + * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk + * + * Contains settings that control clock mpu_clk generated from the C0 output of the + * Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/2 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. + */ +struct ALT_CLKMGR_MAINPLL_MPUCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8 + +/* + * Register : Main PLL C1 Control Register for Clock main_clk - mainclk + * + * Contains settings that control clock main_clk generated from the C1 output of + * the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc + +/* + * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk + * + * Contains settings that control clock dbg_base_clk generated from the C2 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. + */ +struct ALT_CLKMGR_MAINPLL_DBGATCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10 + +/* + * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk + * + * Contains settings that control clock main_qspi_clk generated from the C3 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14 + +/* + * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk + * + * Contains settings that control clock main_nand_sdmmc_clk generated from the C4 + * output of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18 + +/* + * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk + * + * Contains settings that control clock cfg_s2f_user0_clk generated from the C5 + * output of the Main PLL. + * + * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0xf | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf +/* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. + */ +struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the Main PLL. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | l4_main_clk Enable + * [1] | RW | 0x1 | l3_mp_clk Enable + * [2] | RW | 0x1 | l4_mp_clk Enable + * [3] | RW | 0x1 | l4_sp_clk Enable + * [4] | RW | 0x1 | dbg_at_clk Enable + * [5] | RW | 0x1 | dbg_clk Enable + * [6] | RW | 0x1 | dbg_trace_clk Enable + * [7] | RW | 0x1 | dbg_timer_clk Enable + * [8] | RW | 0x1 | cfg_clk Enable + * [9] | RW | 0x1 | s2f_user0_clk Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_main_clk Enable - l4mainclk + * + * Enables clock l4_main_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l3_mp_clk Enable - l3mpclk + * + * Enables clock l3_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : l4_mp_clk Enable - l4mpclk + * + * Enables clock l4_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : l4_sp_clk Enable - l4spclk + * + * Enables clock l4_sp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : dbg_at_clk Enable - dbgatclk + * + * Enables clock dbg_at_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : dbg_clk Enable - dbgclk + * + * Enables clock dbg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : dbg_trace_clk Enable - dbgtraceclk + * + * Enables clock dbg_trace_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : dbg_timer_clk Enable - dbgtimerclk + * + * Enables clock dbg_timer_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : cfg_clk Enable - cfgclk + * + * Enables clock cfg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : s2f_user0_clk Enable - s2fuser0clk + * + * Enables clock s2f_user0_clk output. + * + * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_EN. + */ +struct ALT_CLKMGR_MAINPLL_EN_s +{ + uint32_t l4mainclk : 1; /* l4_main_clk Enable */ + uint32_t l3mpclk : 1; /* l3_mp_clk Enable */ + uint32_t l4mpclk : 1; /* l4_mp_clk Enable */ + uint32_t l4spclk : 1; /* l4_sp_clk Enable */ + uint32_t dbgatclk : 1; /* dbg_at_clk Enable */ + uint32_t dbgclk : 1; /* dbg_clk Enable */ + uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */ + uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */ + uint32_t cfgclk : 1; /* cfg_clk Enable */ + uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 + +/* + * Register : Main Divide Register - maindiv + * + * Contains fields that control clock dividers for main clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [1:0] | RW | 0x0 | L3 MP Clock Divider + * [3:2] | RW | 0x0 | L3 SP Clock Divider + * [6:4] | RW | 0x0 | L4 MP Clock Divider + * [9:7] | RW | 0x0 | L4 SP Clock Divider + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L3 MP Clock Divider - l3mpclk + * + * The l3_mp_clk is divided down from the l3_main_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : L3 SP Clock Divider - l3spclk + * + * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : L4 MP Clock Divider - l4mpclk + * + * The l4_mp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070) + +/* + * Field : L4 SP Clock Divider - l4spclk + * + * The l4_sp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. + */ +struct ALT_CLKMGR_MAINPLL_MAINDIV_s +{ + uint32_t l3mpclk : 2; /* L3 MP Clock Divider */ + uint32_t l3spclk : 2; /* L3 SP Clock Divider */ + uint32_t l4mpclk : 3; /* L4 MP Clock Divider */ + uint32_t l4spclk : 3; /* L4 SP Clock Divider */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 + +/* + * Register : Debug Divide Register - dbgdiv + * + * Contains fields that control clock dividers for debug clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [1:0] | RW | 0x0 | Debug AT Clock Divider + * [3:2] | RW | 0x1 | Debug Clock Divider + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug AT Clock Divider - dbgatclk + * + * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value + * specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Clock Divider - dbgclk + * + * The dbg_clk is divided down from the dbg_at_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. + */ +struct ALT_CLKMGR_MAINPLL_DBGDIV_s +{ + uint32_t dbgatclk : 2; /* Debug AT Clock Divider */ + uint32_t dbgclk : 2; /* Debug Clock Divider */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 + +/* + * Register : Debug Trace Divide Register - tracediv + * + * Contains a field that controls the clock divider for the debug trace clock + * derived from the Main PLL + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [2:0] | RW | 0x0 | Debug Trace Clock Divider + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Trace Clock Divider - traceclk + * + * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the + * value specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. + */ +struct ALT_CLKMGR_MAINPLL_TRACEDIV_s +{ + uint32_t traceclk : 3; /* Debug Trace Clock Divider */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c + +/* + * Register : L4 MP SP APB Clock Source - l4src + * + * Contains fields that select the clock source for L4 MP and SP APB interconnect + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | l4_mp_clk Source + * [1] | RW | 0x0 | l4_sp_clk Source + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_mp_clk Source - l4mp + * + * Selects the source for l4_mp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l4_sp_clk Source - l4sp + * + * Selects the source for l4_sp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC. + */ +struct ALT_CLKMGR_MAINPLL_L4SRC_s +{ + uint32_t l4mp : 1; /* l4_mp_clk Source */ + uint32_t l4sp : 1; /* l4_sp_clk Source */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30 + +/* + * Register : Main PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT. + */ +struct ALT_CLKMGR_MAINPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_MAINPLL. + */ +struct ALT_CLKMGR_MAINPLL_s +{ + volatile ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +struct ALT_CLKMGR_MAINPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL + * Peripheral PLL Group + * + * Contains registers with settings for the Peripheral PLL. + * + */ +/* + * Register : Peripheral PLL VCO Control Register - vco + * + * Contains settings that control the Peripheral PLL VCO. The VCO output frequency + * is the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - psrc + * + * Controls the VCO input clock source. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_VCO. + */ +struct ALT_CLKMGR_PERPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t psrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_VCO_OFST 0x0 + +/* + * Register : Peripheral PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_MISC. + */ +struct ALT_CLKMGR_PERPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_MISC_OFST 0x4 + +/* + * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk + * + * Contains settings that control clock emac0_clk generated from the C0 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8 + +/* + * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk + * + * Contains settings that control clock emac1_clk generated from the C1 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc + +/* + * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk + * + * Contains settings that control clock periph_qspi_clk generated from the C2 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. + */ +struct ALT_CLKMGR_PERPLL_PERQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10 + +/* + * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk + * + * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. + */ +struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14 + +/* + * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk + * + * Contains settings that control clock periph_base_clk generated from the C4 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. + */ +struct ALT_CLKMGR_PERPLL_PERBASECLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18 + +/* + * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk + * + * Contains settings that control clock s2f_user1_clk generated from the C5 output + * of the Peripheral PLL. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. + */ +struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the + * Peripheral PLL + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | emac0_clk Enable + * [1] | RW | 0x1 | emac1_clk Enable + * [2] | RW | 0x1 | usb_mp_clk Enable + * [3] | RW | 0x1 | spi_m_clk Enable + * [4] | RW | 0x1 | can0_clk Enable + * [5] | RW | 0x1 | can1_clk Enable + * [6] | RW | 0x1 | gpio_clk Enable + * [7] | RW | 0x1 | s2f_user1_clk Enable + * [8] | RW | 0x1 | sdmmc_clk Enable + * [9] | RW | 0x1 | nand_x_clk Enable + * [10] | RW | 0x1 | nand_clk Enable + * [11] | RW | 0x1 | qspi_clk Enable + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_clk Enable - emac0clk + * + * Enables clock emac0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : emac1_clk Enable - emac1clk + * + * Enables clock emac1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : usb_mp_clk Enable - usbclk + * + * Enables clock usb_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : spi_m_clk Enable - spimclk + * + * Enables clock spi_m_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : can0_clk Enable - can0clk + * + * Enables clock can0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : can1_clk Enable - can1clk + * + * Enables clock can1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : gpio_clk Enable - gpioclk + * + * Enables clock gpio_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : s2f_user1_clk Enable - s2fuser1clk + * + * Enables clock s2f_user1_clk output. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : sdmmc_clk Enable - sdmmcclk + * + * Enables clock sdmmc_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : nand_x_clk Enable - nandxclk + * + * Enables clock nand_x_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : nand_clk Enable - nandclk + * + * Enables clock nand_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : qspi_clk Enable - qspiclk + * + * Enables clock qspi_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EN. + */ +struct ALT_CLKMGR_PERPLL_EN_s +{ + uint32_t emac0clk : 1; /* emac0_clk Enable */ + uint32_t emac1clk : 1; /* emac1_clk Enable */ + uint32_t usbclk : 1; /* usb_mp_clk Enable */ + uint32_t spimclk : 1; /* spi_m_clk Enable */ + uint32_t can0clk : 1; /* can0_clk Enable */ + uint32_t can1clk : 1; /* can1_clk Enable */ + uint32_t gpioclk : 1; /* gpio_clk Enable */ + uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */ + uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */ + uint32_t nandxclk : 1; /* nand_x_clk Enable */ + uint32_t nandclk : 1; /* nand_clk Enable */ + uint32_t qspiclk : 1; /* qspi_clk Enable */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EN_OFST 0x20 + +/* + * Register : Divide Register - div + * + * Contains fields that control clock dividers for clocks derived from the + * Peripheral PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [2:0] | RW | 0x0 | USB Clock Divider + * [5:3] | RW | 0x0 | SPI Master Clock Divider + * [8:6] | RW | 0x0 | CAN0 Clock Divider + * [11:9] | RW | 0x0 | CAN1 Clock Divider + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB Clock Divider - usbclk + * + * The usb_mp_clk is divided down from the periph_base_clk by the value specified + * in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : SPI Master Clock Divider - spimclk + * + * The spi_m_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : CAN0 Clock Divider - can0clk + * + * The can0_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) + +/* + * Field : CAN1 Clock Divider - can1clk + * + * The can1_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_DIV. + */ +struct ALT_CLKMGR_PERPLL_DIV_s +{ + uint32_t usbclk : 3; /* USB Clock Divider */ + uint32_t spimclk : 3; /* SPI Master Clock Divider */ + uint32_t can0clk : 3; /* CAN0 Clock Divider */ + uint32_t can1clk : 3; /* CAN1 Clock Divider */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 + +/* + * Register : GPIO Divide Register - gpiodiv + * + * Contains a field that controls the clock divider for the GPIO De-bounce clock. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO De-bounce Clock Divider - gpiodbclk + * + * The gpio_db_clk is divided down from the periph_base_clk by the value plus one + * specified in this field. The value 0 (divide by 1) is illegal. A value of 1 + * indicates divide by 2, 2 divide by 3, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24 +/* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff +/* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000 +/* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV. + */ +struct ALT_CLKMGR_PERPLL_GPIODIV_s +{ + uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28 + +/* + * Register : Flash Clock Source Register - src + * + * Contains fields that select the source clocks for the flash controllers. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [1:0] | RW | 0x1 | SDMMC Clock Source + * [3:2] | RW | 0x1 | NAND Clock Source + * [5:4] | RW | 0x1 | QSPI Clock Source + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC Clock Source - sdmmc + * + * Selects the source clock for the SDMMC. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NAND Clock Source - nand + * + * Selects the source clock for the NAND. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : QSPI Clock Source - qspi + * + * Selects the source clock for the QSPI. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * main_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * periph_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_SRC. + */ +struct ALT_CLKMGR_PERPLL_SRC_s +{ + uint32_t sdmmc : 2; /* SDMMC Clock Source */ + uint32_t nand : 2; /* NAND Clock Source */ + uint32_t qspi : 2; /* QSPI Clock Source */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c + +/* + * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_STAT. + */ +struct ALT_CLKMGR_PERPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_STAT_OFST 0x30 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_PERPLL. + */ +struct ALT_CLKMGR_PERPLL_s +{ + volatile ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +struct ALT_CLKMGR_PERPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL + * SDRAM PLL Group + * + * Contains registers with settings for the SDRAM PLL. + * + */ +/* + * Register : SDRAM PLL VCO Control Register - vco + * + * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is + * the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | SDRAM All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - ssrc + * + * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk + * before changing this field. + * + * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------ + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * f2s_sdram_ref_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : SDRAM All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO. + */ +struct ALT_CLKMGR_SDRPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t ssrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 + +/* + * Register : SDRAM PLL VCO Advanced Control Register - ctrl + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL. + */ +struct ALT_CLKMGR_SDRPLL_CTL_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4 + +/* + * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk + * + * Contains settings that control clock ddr_dqs_clk generated from the C0 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8 + +/* + * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk + * + * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output + * of the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc + +/* + * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk + * + * Contains settings that control clock ddr_dq_clk generated from the C2 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 + +/* + * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk + * + * Contains settings that control clock s2f_user2_clk generated from the C5 output + * of the SDRAM PLL. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. + */ +struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14 + +/* + * Register : Enable Register - en + * + * Contains fields that control the SDRAM Clock Group enables generated from the + * SDRAM PLL clock outputs. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | ddr_dqs_clk Enable + * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable + * [2] | RW | 0x1 | ddr_dq_clk Enable + * [3] | RW | 0x1 | s2f_user2_clk Enable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ddr_dqs_clk Enable - ddrdqsclk + * + * Enables clock ddr_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk + * + * Enables clock ddr_2x_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ddr_dq_clk Enable - ddrdqclk + * + * Enables clock ddr_dq_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : s2f_user2_clk Enable - s2fuser2clk + * + * Enables clock s2f_user2_clk output. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_EN. + */ +struct ALT_CLKMGR_SDRPLL_EN_s +{ + uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */ + uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */ + uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */ + uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_EN_OFST 0x18 + +/* + * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT. + */ +struct ALT_CLKMGR_SDRPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_SDRPLL. + */ +struct ALT_CLKMGR_SDRPLL_s +{ + volatile ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +struct ALT_CLKMGR_SDRPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR. + */ +struct ALT_CLKMGR_s +{ + volatile ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */ + volatile ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */ + volatile ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */ + volatile ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR. */ +struct ALT_CLKMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */ + volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile uint32_t inter; /* ALT_CLKMGR_INTER */ + volatile uint32_t intren; /* ALT_CLKMGR_INTREN */ + volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile uint32_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_CLKMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h new file mode 100644 index 0000000000..1425708983 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMANONSECURE */ + +#ifndef __ALTERA_ALT_DMANONSECURE_H__ +#define __ALTERA_ALT_DMANONSECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE + * nonsecure DMA Module Address Space + * + * Address space allocated to the nonsecure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ +#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMANONSECURE_REG. + */ +struct ALT_DMANONSECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMANONSECURE_REG. */ +typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ +#define ALT_DMANONSECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMANONSECURE. + */ +struct ALT_DMANONSECURE_s +{ + volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ +struct ALT_DMANONSECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h new file mode 100644 index 0000000000..5941433268 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMASECURE */ + +#ifndef __ALTERA_ALT_DMASECURE_H__ +#define __ALTERA_ALT_DMASECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : secure DMA Module Address Space - ALT_DMASECURE + * secure DMA Module Address Space + * + * Address space allocated to the secure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMASECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ +#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMASECURE_REG. + */ +struct ALT_DMASECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMASECURE_REG. */ +typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ +#define ALT_DMASECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMASECURE. + */ +struct ALT_DMASECURE_s +{ + volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ +struct ALT_DMASECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMASECURE_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h new file mode 100644 index 0000000000..8bc4640161 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h @@ -0,0 +1,1991 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_GPIO */ + +#ifndef __ALTERA_ALT_GPIO_H__ +#define __ALTERA_ALT_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : GPIO Module - ALT_GPIO + * GPIO Module + * + * Registers in the GPIO module + * + */ +/* + * Register : Port A Data Register - gpio_swporta_dr + * + * This GPIO Data register is used to input or output data + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [28:0] | RW | 0x0 | Port A Data + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data - gpio_swporta_dr + * + * Values written to this register are output on the I/O signals of the GPIO Data + * Register, if the corresponding data direction bits for GPIO Data Direction Field + * are set to Output mode. The value read back is equal to the last value written + * to this register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DR. + */ +struct ALT_GPIO_SWPORTA_DR_s +{ + uint32_t gpio_swporta_dr : 29; /* Port A Data */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DR_OFST 0x0 +/* The address of the ALT_GPIO_SWPORTA_DR register. */ +#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST)) + +/* + * Register : Port A Data Direction Register - gpio_swporta_ddr + * + * This register establishes the direction of each corresponding GPIO Data Field + * Bit. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [28:0] | RW | 0x0 | Port A Data Direction Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data Direction Field - gpio_swporta_ddr + * + * Values written to this register independently control the direction of the + * corresponding data bit in the Port A Data Register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:----------------- + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Input Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0 +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Output Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DDR. + */ +struct ALT_GPIO_SWPORTA_DDR_s +{ + uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DDR_OFST 0x4 +/* The address of the ALT_GPIO_SWPORTA_DDR register. */ +#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST)) + +/* + * Register : Interrupt Enable Register - gpio_inten + * + * The Interrupt enable register allows interrupts for each bit of the Port A data + * register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Enable Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable Field - gpio_inten + * + * Allows each bit of Port A Data Register to be configured for interrupt + * capability. Interrupts are disabled on the corresponding bits of Port A Data + * Register if the corresponding data direction register is set to Output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A + * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Disable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Enable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28 +/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0 +/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTEN. + */ +struct ALT_GPIO_INTEN_s +{ + uint32_t gpio_inten : 29; /* Interrupt Enable Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTEN. */ +typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */ +#define ALT_GPIO_INTEN_OFST 0x30 +/* The address of the ALT_GPIO_INTEN register. */ +#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST)) + +/* + * Register : Interrupt Mask Register - gpio_intmask + * + * Controls which pins cause interrupts on Port A Data Register inputs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [28:0] | RW | 0x0 | Interrupt Mask Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Mask Field - gpio_intmask + * + * Controls whether an interrupt on Port A Data Register can generate an interrupt + * to the interrupt controller by not masking it. The unmasked status can be read + * as well as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Interrupt bits are unmasked + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Mask Interrupt + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28 +/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0 +/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTMSK. + */ +struct ALT_GPIO_INTMSK_s +{ + uint32_t gpio_intmask : 29; /* Interrupt Mask Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTMSK. */ +typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */ +#define ALT_GPIO_INTMSK_OFST 0x34 +/* The address of the ALT_GPIO_INTMSK register. */ +#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST)) + +/* + * Register : Interrupt Level Register - gpio_inttype_level + * + * The interrupt level register defines the type of interrupt (edge or level). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [28:0] | RW | 0x0 | Interrupt Level Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Level Field - gpio_inttype_level + * + * This field controls the type of interrupt that can occur on the Port A Data + * Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------- + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Level-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Edge-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28 +/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0 +/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL. + */ +struct ALT_GPIO_INTTYPE_LEVEL_s +{ + uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */ +typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */ +#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38 +/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */ +#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST)) + +/* + * Register : Interrupt Polarity Register - gpio_int_polarity + * + * Controls the Polarity of Interrupts that can occur on inputs of Port A Data + * Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Polarity Control Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Polarity Control Field - gpio_int_polarity + * + * Controls the polarity of edge or level sensitivity that can occur on input of + * Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active low + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active high + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28 +/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0 +/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INT_POL. + */ +struct ALT_GPIO_INT_POL_s +{ + uint32_t gpio_int_polarity : 29; /* Polarity Control Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INT_POL. */ +typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */ +#define ALT_GPIO_INT_POL_OFST 0x3c +/* The address of the ALT_GPIO_INT_POL register. */ +#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST)) + +/* + * Register : Interrupt Status Register - gpio_intstatus + * + * The Interrupt status is reported for all Port A Data Register Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Status Field - gpio_intstatus + * + * Interrupt status of Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Active + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTSTAT. + */ +struct ALT_GPIO_INTSTAT_s +{ + uint32_t gpio_intstatus : 29; /* Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTSTAT. */ +typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_INTSTAT_OFST 0x40 +/* The address of the ALT_GPIO_INTSTAT register. */ +#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST)) + +/* + * Register : Raw Interrupt Status Register - gpio_raw_intstatus + * + * This is the Raw Interrupt Status Register for Port A Data Register. It is used + * with the Interrupt Mask Register to allow interrupts from the Port A Data + * Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [28:0] | RW | 0x0 | Raw Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Raw Interrupt Status Field - gpio_raw_intstatus + * + * Raw interrupt of status of Port A Data Register (premasking bits) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------ + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Active + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_RAW_INTSTAT. + */ +struct ALT_GPIO_RAW_INTSTAT_s +{ + uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */ +typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_RAW_INTSTAT_OFST 0x44 +/* The address of the ALT_GPIO_RAW_INTSTAT register. */ +#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST)) + +/* + * Register : Debounce Enable Register - gpio_debounce + * + * Debounces each IO Pin + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : gpio_debounce + * + * Controls whether an external signal that is the source of an interrupt needs to + * be debounced to remove any spurious glitches. A signal must be valid for two + * periods of an external clock (gpio_db_clk) before it is internally processed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * No debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * Enable debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28 +/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29 +/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0 +/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_DEBOUNCE. + */ +struct ALT_GPIO_DEBOUNCE_s +{ + uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */ +typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */ +#define ALT_GPIO_DEBOUNCE_OFST 0x48 +/* The address of the ALT_GPIO_DEBOUNCE register. */ +#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST)) + +/* + * Register : Clear Interrupt Register - gpio_porta_eoi + * + * Port A Data Register interrupt handling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [28:0] | W | 0x0 | Clears Edge Interrupts Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clears Edge Interrupts Field - gpio_porta_eoi + * + * Controls the clearing of edge type interrupts from the Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * No interrupt clear + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * Clear interrupt + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28 +/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29 +/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0 +/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_PORTA_EOI. + */ +struct ALT_GPIO_PORTA_EOI_s +{ + uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */ +typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */ +#define ALT_GPIO_PORTA_EOI_OFST 0x4c +/* The address of the ALT_GPIO_PORTA_EOI register. */ +#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST)) + +/* + * Register : External Port A Register - gpio_ext_porta + * + * The external port register is used to input data to the metastability flops. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [28:0] | R | 0x0 | External Port Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : External Port Field - gpio_ext_porta + * + * When Port A Data Register is configured as Input, then reading this location + * reads the values on the signals. When the data direction of Port A Data Register + * is set as Output, reading this location reads Port A Data Register + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28 +/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29 +/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_EXT_PORTA. + */ +struct ALT_GPIO_EXT_PORTA_s +{ + const uint32_t gpio_ext_porta : 29; /* External Port Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */ +typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */ +#define ALT_GPIO_EXT_PORTA_OFST 0x50 +/* The address of the ALT_GPIO_EXT_PORTA register. */ +#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST)) + +/* + * Register : Synchronization Level Register - gpio_ls_sync + * + * The Synchronization level register is used to synchronize input with l4_mp_clk + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Synchronization Level Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Synchronization Level Field - gpio_ls_sync + * + * The level-sensitive interrupts is synchronized to l4_mp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * No synchronization to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0 +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * Synchronize to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0 +/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1 +/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001 +/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe +/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0 +/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_LS_SYNC. + */ +struct ALT_GPIO_LS_SYNC_s +{ + uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_LS_SYNC. */ +typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */ +#define ALT_GPIO_LS_SYNC_OFST 0x60 +/* The address of the ALT_GPIO_LS_SYNC register. */ +#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST)) + +/* + * Register : ID Code Register - gpio_id_code + * + * GPIO ID code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | ID Code Field + * + */ +/* + * Field : ID Code Field - gpio_id_code + * + * Chip identification + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0 +/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_ID_CODE. + */ +struct ALT_GPIO_ID_CODE_s +{ + const uint32_t gpio_id_code : 32; /* ID Code Field */ +}; + +/* The typedef declaration for register ALT_GPIO_ID_CODE. */ +typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_ID_CODE_OFST 0x64 +/* The address of the ALT_GPIO_ID_CODE register. */ +#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST)) + +/* + * Register : GPIO Version Register - gpio_ver_id_code + * + * GPIO Component Version + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------------ + * [31:0] | R | 0x3230382a | ASCII Component Version Field + * + */ +/* + * Field : ASCII Component Version Field - gpio_ver_id_code + * + * ASCII value for each number in the version, followed by *. For example. + * 32_30_31_2A represents the version 2.01 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a +/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_VER_ID_CODE. + */ +struct ALT_GPIO_VER_ID_CODE_s +{ + const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */ +}; + +/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */ +typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_VER_ID_CODE_OFST 0x6c +/* The address of the ALT_GPIO_VER_ID_CODE register. */ +#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST)) + +/* + * Register : Configuration Register 2 - gpio_config_reg2 + * + * Specifies the bit width of port A. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [4:0] | R | 0x1c | Port A Width (less 1) + * [9:5] | R | 0x7 | Port B Width (less 1) + * [14:10] | R | 0x7 | Port C Width (less 1) + * [19:15] | R | 0x7 | Port D Width (less 1) + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Width (less 1) - encoded_id_pwidth_a + * + * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width + * less one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Port B Width (less 1) - encoded_id_pwidth_b + * + * Specifies the width of GPIO Port B. Ignored because there is no Port B in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : Port C Width (less 1) - encoded_id_pwidth_c + * + * Specifies the width of GPIO Port C. Ignored because there is no Port C in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00) + +/* + * Field : Port D Width (less 1) - encoded_id_pwidth_d + * + * Specifies the width of GPIO Port D. Ignored because there is no Port D in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG2. + */ +struct ALT_GPIO_CFG_REG2_s +{ + const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */ + const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */ + const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */ + const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG2. */ +typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG2_OFST 0x70 +/* The address of the ALT_GPIO_CFG_REG2 register. */ +#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST)) + +/* + * Register : Configuration Register 1 - gpio_config_reg1 + * + * Reports settings of various GPIO configuration parameters + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | R | 0x0 | NUM PORTS + * [4] | R | 0x1 | PORT A SINGLE CTL + * [5] | R | 0x1 | PORT B SINGLE CTL + * [6] | R | 0x1 | PORT C SINGLE CTL + * [7] | R | 0x1 | PORT D SINGLE CTL + * [8] | R | 0x0 | HW PORTA + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [12] | R | 0x1 | Port A Interrupt Field + * [13] | R | 0x1 | Debounce Field + * [14] | R | 0x1 | Encoded GPIO Parameters Available + * [15] | R | 0x1 | ID Field + * [20:16] | R | 0x1f | Encoded ID Width Field + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apb_data_width + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NUM PORTS - num_ports + * + * The value of this register is fixed at one port (Port A). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS + * + * Number of GPIO Ports = 1 + */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 +/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c +/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PORT A SINGLE CTL - porta_single_ctl + * + * Indicates the mode of operation of Port A to be software controlled only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PORT B SINGLE CTL - portb_single_ctl + * + * Indicates the mode of operation of Port B to be software controlled only. + * Ignored because there is no Port B in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : PORT C SINGLE CTL - portc_single_ctl + * + * Indicates the mode of operation of Port C to be software controlled only. + * Ignored because there is no Port C in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : PORT D SINGLE CTL - portd_single_ctl + * + * Indicates the mode of operation of Port D to be software controlled only. + * Ignored because there is no Port D in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : HW PORTA - hw_porta + * + * The value is fixed to enable Port A configuration to be controlled by software + * only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------- + * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA + * + * Software Configuration Control Enabled + */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 +/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 +/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff +/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Port A Interrupt Field - porta_intr + * + * The value of this field is fixed to allow interrupts on Port A. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR + * + * Port A Interrupts Enabled + */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Debounce Field - debounce + * + * The value of this field is fixed to allow debouncing of the Port A signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE + * + * Debounce is Enabled + */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 +/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Encoded GPIO Parameters Available - add_encoded_params + * + * Fixed to allow the indentification of the Designware IP component. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS + * + * Enable IP indentification + */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : ID Field - gpio_id + * + * Provides an ID code value + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID + * + * GPIO ID Code + */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 +/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff +/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Encoded ID Width Field - encoded_id_width + * + * This value is fixed at 32 bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH + * + * Width of ID Field + */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 +/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f +/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG1. + */ +struct ALT_GPIO_CFG_REG1_s +{ + const uint32_t apb_data_width : 2; /* APB DATA WIDTH */ + const uint32_t num_ports : 2; /* NUM PORTS */ + const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */ + const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */ + const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */ + const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */ + const uint32_t hw_porta : 1; /* HW PORTA */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t porta_intr : 1; /* Port A Interrupt Field */ + const uint32_t debounce : 1; /* Debounce Field */ + const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */ + const uint32_t gpio_id : 1; /* ID Field */ + const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG1. */ +typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG1_OFST 0x74 +/* The address of the ALT_GPIO_CFG_REG1 register. */ +#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_GPIO. + */ +struct ALT_GPIO_s +{ + volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_s ALT_GPIO_t; +/* The struct declaration for the raw register contents of register group ALT_GPIO. */ +struct ALT_GPIO_raw_s +{ + volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_GPIO_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h new file mode 100644 index 0000000000..b50543a884 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h @@ -0,0 +1,5940 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_I2C */ + +#ifndef __ALTERA_ALT_I2C_H__ +#define __ALTERA_ALT_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : I2C Module - ALT_I2C + * I2C Module + * + * Registers in the I2C module + * + */ +/* + * Register : Control Register - ic_con + * + * This register can be written only when the I2C is disabled, which corresponds to + * the Bit [0] of the Enable Register being set to 0. Writes at other times have no + * effect. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | Master Enable + * [2:1] | RW | 0x2 | Master Speed Control + * [3] | RW | 0x1 | Slave Address Size + * [4] | RW | 0x1 | Master Address Size + * [5] | RW | 0x1 | Restart Enable + * [6] | RW | 0x1 | Slave Disable + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Enable - master_mode + * + * This bit controls whether the i2c master is enabled. + * + * NOTE: Software should ensure that if this bit is written with '1', then bit 6 + * should also be written with a '1'. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------- + * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled + * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master disabled + */ +#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master enabled + */ +#define ALT_I2C_CON_MST_MOD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_MSB 0 +/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_RESET 0x1 +/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ +#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ +#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Speed Control - speed + * + * These bits control at which speed the I2C operates, its setting is relevant only + * if one is operating the I2C in master mode. Hardware protects against illegal + * values being programmed by software. This field should be programmed only with + * standard or fast speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) + * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * standard mode (100 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * fast mode (400 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_MSB 2 +/* The width in bits of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_WIDTH 2 +/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_RESET 0x2 +/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ +#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ +#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Slave Address Size - ic_10bitaddr_slave + * + * When acting as a slave, this bit controls whether the I2C responds to 7- or + * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave + * Address Register are compared. The I2C responds will only respond to 10-bit + * addressing transfers that match the full 10 bits of the Slave Address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Address Size - ic_10bitaddr_master + * + * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing + * mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Restart Enable - ic_restart_en + * + * Determines whether RESTART conditions may be sent when acting as a master. Some + * older slaves do not support handling RESTART conditions; however, RESTART + * conditions are used in several I2C operations. When RESTART is disabled, the + * master is prohibited from performing the following functions + * + * * Changing direction within a transfer (split), + * + * * Sending a START BYTE, + * + * * High-speed mode operation, + * + * * Combined format transfers in 7-bit addressing modes, + * + * * Read operation with a 10-bit address, + * + * * Sending multiple bytes per transfer, + * + * By replacing RESTART condition followed by a STOP and a subsequent START + * condition, split operations are broken down into multiple I2C transfers. If the + * above operations are performed, it will result in setting bit [6](tx_abort) of + * the Raw Interrupt Status Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable + * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master disable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master enable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 +/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ +#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave Disable - ic_slave_disable + * + * This bit controls whether I2C has its slave disabled. The slave will be + * disabled, after reset. + * + * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of + * this register should also be written with a 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------- + * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable + * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave disable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave enable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 +/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ +#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CON. + */ +struct ALT_I2C_CON_s +{ + uint32_t master_mode : 1; /* Master Enable */ + uint32_t speed : 2; /* Master Speed Control */ + uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ + uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ + uint32_t ic_restart_en : 1; /* Restart Enable */ + uint32_t ic_slave_disable : 1; /* Slave Disable */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CON. */ +typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ +#define ALT_I2C_CON_OFST 0x0 +/* The address of the ALT_I2C_CON register. */ +#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) + +/* + * Register : Target Address Register - ic_tar + * + * This register can be written to only when the ic_enable register is set to 0. + * This register is 13 bits wide. All bits can be dynamically updated as long as + * any set of the following conditions are true, + * + * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND + * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register + * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master + * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO + * Register [IC_STATUS bit [2] is set to 1]) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [9:0] | RW | 0x55 | Master Target Address + * [10] | RW | 0x0 | General Call OR Start + * [11] | RW | 0x0 | Special + * [12] | RW | 0x1 | Master Addressing Bit Control + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Target Address - ic_tar + * + * This is the target address for any master transaction. When transmitting a + * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + * write only once into these bits. If the ic_tar and ic_sar are the same, loopback + * exists but the FIFOs are shared between master and slave, so full loopback is + * not feasible. Only one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit to only a slave. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_MSB 9 +/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_WIDTH 10 +/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_RESET 0x55 +/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ +#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : General Call OR Start - gc_or_start + * + * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates + * whether a General Call or START byte command is to be performed by the I2C or + * General Call Address after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw + * Interrupt_Status register. The I2C remains in General Call mode until the + * special bit value (bit 11) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------- + * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call + * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * General Call + */ +#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * START Byte + */ +#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_MSB 10 +/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 +/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ +#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ +#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Special - special + * + * This bit indicates whether software performs a General Call or START BYTE + * command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------------------------- + * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar + * : | | normally + * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in + * : | | gc_or_start + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Ignore bit 10 gc_or_start and use ic_tar normally + */ +#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Perform special I2C command as specified in gc_or_start + */ +#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_MSB 11 +/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_RESET 0x0 +/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ +#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ +#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Addressing Bit Control - ic_10bitaddr_master + * + * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit + * addressing mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 7bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 10bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 +/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TAR. + */ +struct ALT_I2C_TAR_s +{ + uint32_t ic_tar : 10; /* Master Target Address */ + uint32_t gc_or_start : 1; /* General Call OR Start */ + uint32_t special : 1; /* Special */ + uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TAR. */ +typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ +#define ALT_I2C_TAR_OFST 0x4 +/* The address of the ALT_I2C_TAR register. */ +#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) + +/* + * Register : Slave Address Register - ic_sar + * + * Holds Address of Slave + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [9:0] | RW | 0x55 | Slave Address + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Address - ic_sar + * + * The Slave Address register holds the slave address when the I2C is operating as + * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address + * Register are used. This register can be written only when the I2C interface is + * disabled, which corresponds to field bit 0 of the Enable Register being set to + * 0. Writes at other times have no effect. + * + * Note, the default values cannot be any of the reserved address locations: that + * is, + * + * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not + * guaranteed if you program the Slave Address Register or Target Address Register + * to a reserved value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_MSB 9 +/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_WIDTH 10 +/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_RESET 0x55 +/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ +#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ +#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SAR. + */ +struct ALT_I2C_SAR_s +{ + uint32_t ic_sar : 10; /* Slave Address */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SAR. */ +typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ +#define ALT_I2C_SAR_OFST 0x8 +/* The address of the ALT_I2C_SAR register. */ +#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) + +/* + * Register : Tx Rx Data and Command Register - ic_data_cmd + * + * This is the register the CPU writes to when filling the TX FIFO. Reading from + * this register returns bytes from RX FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | RW | 0x0 | Tx Rx Data + * [8] | W | 0x0 | Master Read Write Control + * [9] | W | 0x0 | Generate Stop + * [10] | W | 0x0 | Generate Restart + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Rx Data - dat + * + * This Field contains the data to be transmitted or received on the I2C bus. If + * you are writing to these bits and want to perform a read, bits 7:0 (dat) are + * ignored by the I2C. However, when you read from this register, these bits return + * the value of data received on the I2C interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_MSB 7 +/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 +/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ +#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Master Read Write Control - cmd + * + * This bit controls whether a read or a write is performed. This bit does not + * control the direction when the I2C acts as a slave. It controls only the + * direction when it acts as a master. When a command is entered in the TX FIFO, + * this bit distinguishes the write and read commands. In slave-receiver mode, this + * bit is a 'don't care' because writes to this register are not required. In + * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. + * When programming this bit, you should remember the following: attempting to + * perform a read operation after a General Call command has been sent results in a + * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special + * in the Target Address Register has been cleared. If a '1' is written to this bit + * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. + * + * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a + * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master + * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, + * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------- + * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read + * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Read + */ +#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Write + */ +#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_MSB 8 +/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ +#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Generate Stop - stop + * + * This bit controls whether a STOP is issued after the byte is sent or received. + * + * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is + * empty. If the Tx FIFO is not empty, the master immediately tries to start a new + * transfer by issuing a START and arbitrating for the bus. + * + * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO + * is empty. If the Tx FIFO is not empty, the master continues the current transfer + * by sending/receiving data bytes according to the value of the CMD bit. If the Tx + * FIFO is empty, the master holds the SCL line low and stalls the bus until a new + * command is available in the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop + * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Do Not Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_MSB 9 +/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ +#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Generate Restart - restart + * + * This bit controls whether a RESTART is issued before the byte is sent or + * received. + * + * 1 = A RESTART is issued before the data is sent/received (according to the value + * of CMD), regardless of whether or not the transfer direction is changing from + * the previous command. + * + * 0 = A RESTART is issued only if the transfer direction is changing from the + * previous command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------------------- + * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart + * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart On Direction Change + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_MSB 10 +/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ +#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DATA_CMD. + */ +struct ALT_I2C_DATA_CMD_s +{ + uint32_t dat : 8; /* Tx Rx Data */ + uint32_t cmd : 1; /* Master Read Write Control */ + uint32_t stop : 1; /* Generate Stop */ + uint32_t restart : 1; /* Generate Restart */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DATA_CMD. */ +typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ +#define ALT_I2C_DATA_CMD_OFST 0x10 +/* The address of the ALT_I2C_DATA_CMD register. */ +#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) + +/* + * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt + * + * This register sets the SCL clock high-period count for standard speed. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x190 | Std Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL High Period - ic_ss_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock high-period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this being written, and if attempted results in 6 being set. It + * is readable and writeable. + * + * NOTE: This register must not be programmed to a value higher than 65525, because + * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter + * reaches a value of IC_SS_SCL_HCNT + 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 +/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_HCNT. + */ +struct ALT_I2C_SS_SCL_HCNT_s +{ + uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 +/* The address of the ALT_I2C_SS_SCL_HCNT register. */ +#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) + +/* + * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt + * + * This register sets the SCL clock low-period count for standard speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register register being set to 0. + * Writes at other times have no effect. The minimum valid value is 8; hardware + * prevents values less than this from being written, and if attempted, results in + * 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 +/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_LCNT. + */ +struct ALT_I2C_SS_SCL_LCNT_s +{ + uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 +/* The address of the ALT_I2C_SS_SCL_LCNT register. */ +#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt + * + * This register sets the SCL clock high-period count for fast speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [15:0] | RW | 0x3c | Fast Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This register sets the SCL clock high-period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register goes away and becomes read-only returning 0s if + * in Standard Speed Mode. This register can be written only when the I2C interface + * is disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this from being written, and if attempted results in 6 being + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c +/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_HCNT. + */ +struct ALT_I2C_FS_SCL_HCNT_s +{ + uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c +/* The address of the ALT_I2C_FS_SCL_HCNT register. */ +#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt + * + * This register sets the SCL clock low period count + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x82 | Fast Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register can be written only when the I2C interface is + * disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect.The minimum valid value is 8; hardware prevents + * values less than this being written, and if attempted results in 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 +/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_LCNT. + */ +struct ALT_I2C_FS_SCL_LCNT_s +{ + uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 +/* The address of the ALT_I2C_FS_SCL_LCNT register. */ +#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) + +/* + * Register : Interrupt Status Register - ic_intr_stat + * + * Each bit in this register has a corresponding mask bit in the Interrupt Mask + * Register. These bits are cleared by reading the matching Interrupt Clear + * Register. The unmasked raw versions of these bits are available in the Raw + * Interrupt Status Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Receiver Under + * [1] | R | 0x0 | Receiver Over + * [2] | R | 0x0 | Receive Full + * [3] | R | 0x0 | Interrupt Transmit Over + * [4] | R | 0x0 | Interrupt Transmit Empty + * [5] | R | 0x0 | Interrupt Read Request + * [6] | R | 0x0 | Interrupt TX Abort + * [7] | R | 0x0 | Interrupt RX Done + * [8] | R | 0x0 | Interrupt R_activity + * [9] | R | 0x0 | Interrupt Stop Detect + * [10] | R | 0x0 | Interrupt Start Detect + * [11] | R | 0x0 | Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receiver Under - r_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the Tx Rx Data and Command Register. If the module is disabled, + * Enable Register is set to 0, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receiver Over - r_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled, + * Enable Register bit[0] is set to 0 this bit keeps its level until the master or + * slave state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Full - r_rx_full + * + * Set when the receive buffer reaches or goes above the Receive FIFO Threshold + * Value(rx_tl). It is automatically cleared by hardware when buffer level goes + * below the threshold. If the module is disabled, Bit [0] of the Enable Register + * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not + * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a + * 0, regardless of the activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Transmit Over - r_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the Data and Command + * Register. When the module is disabled, this bit keeps its level until the master + * or slave state machines goes into idle, then interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Transmit Empty - r_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, this bit is set to 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Read Request - r_rd_req + * + * This bit is set to 1 when i2c is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt TX Abort - r_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit + * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the + * reason why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt RX Done - r_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt R_activity - r_activity + * + * This bit captures I2C activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * I2C reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Stop Detect - r_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Start Detect - r_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt General Call - r_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_STAT. + */ +struct ALT_I2C_INTR_STAT_s +{ + const uint32_t r_rx_under : 1; /* Receiver Under */ + const uint32_t r_rx_over : 1; /* Receiver Over */ + const uint32_t r_rx_full : 1; /* Receive Full */ + const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ + const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ + const uint32_t r_rd_req : 1; /* Interrupt Read Request */ + const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ + const uint32_t r_rx_done : 1; /* Interrupt RX Done */ + const uint32_t r_activity : 1; /* Interrupt R_activity */ + const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ + const uint32_t r_start_det : 1; /* Interrupt Start Detect */ + const uint32_t r_gen_call : 1; /* Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_STAT. */ +typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_INTR_STAT_OFST 0x2c +/* The address of the ALT_I2C_INTR_STAT register. */ +#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) + +/* + * Register : Interrupt Mask Register - ic_intr_mask + * + * These bits mask their corresponding interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [0] | RW | 0x1 | Mask RX Under + * [1] | RW | 0x1 | RX Buffer Over + * [2] | RW | 0x1 | RX Buffer Full + * [3] | RW | 0x1 | TX Buffer Over + * [4] | RW | 0x1 | TX Buffer Empty + * [5] | RW | 0x1 | Read Request + * [6] | RW | 0x1 | TX Abort + * [7] | RW | 0x1 | RX Done + * [8] | RW | 0x0 | Activity Bit + * [9] | RW | 0x0 | Stop Detect + * [10] | RW | 0x0 | Start Detect + * [11] | RW | 0x1 | General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mask RX Under - m_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * and then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : RX Buffer Over - m_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0, this bit keeps its level until the master or slave state + * machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : RX Buffer Full - m_rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TX Buffer Over - m_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TX Buffer Empty - m_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Request - m_rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TX Abort - m_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : RX Done - m_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Activity Bit - m_activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the i2c + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Stop Detect - m_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether i2c is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Start Detect - m_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : General Call - m_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_MSK. + */ +struct ALT_I2C_INTR_MSK_s +{ + uint32_t m_rx_under : 1; /* Mask RX Under */ + uint32_t m_rx_over : 1; /* RX Buffer Over */ + uint32_t m_rx_full : 1; /* RX Buffer Full */ + uint32_t m_tx_over : 1; /* TX Buffer Over */ + uint32_t m_tx_empty : 1; /* TX Buffer Empty */ + uint32_t m_rd_req : 1; /* Read Request */ + uint32_t m_tx_abrt : 1; /* TX Abort */ + uint32_t m_rx_done : 1; /* RX Done */ + uint32_t m_activity : 1; /* Activity Bit */ + uint32_t m_stop_det : 1; /* Stop Detect */ + uint32_t m_start_det : 1; /* Start Detect */ + uint32_t m_gen_call : 1; /* General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_MSK. */ +typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ +#define ALT_I2C_INTR_MSK_OFST 0x30 +/* The address of the ALT_I2C_INTR_MSK register. */ +#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) + +/* + * Register : Raw Interrupt Status Register - ic_raw_intr_stat + * + * Unlike the ic_intr_stat register, these bits are not masked so they always show + * the true status of the I2C. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | I2C Raw Interrupt RX Under + * [1] | R | 0x0 | Raw Interrupt RX Over + * [2] | R | 0x0 | Raw Interrupt RX Full + * [3] | R | 0x0 | Raw Interrupt TX Over + * [4] | R | 0x0 | Raw Interrupt TX Empty + * [5] | R | 0x0 | Raw Interrupt Read Request + * [6] | R | 0x0 | Raw Interrupt TX Abort + * [7] | R | 0x0 | Raw Interrupt RX Done + * [8] | R | 0x0 | Raw Interrupt Activity + * [9] | R | 0x0 | Raw Interrupt Stop Detect + * [10] | R | 0x0 | Raw Interrupt Start Detect + * [11] | R | 0x0 | Raw Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I2C Raw Interrupt RX Under - rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt RX Over - rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0), this bit keeps its level until the master or slave state + * machines go into then, this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt RX Full - rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt TX Over - tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt TX Empty - tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Read Request - rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The i2c holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt TX Abort - tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt RX Done - rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Activity - activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the i2c module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Stop Detect - stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Start Detect - start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt General Call - gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RAW_INTR_STAT. + */ +struct ALT_I2C_RAW_INTR_STAT_s +{ + const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ + const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ + const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ + const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ + const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ + const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ + const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ + const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ + const uint32_t activity : 1; /* Raw Interrupt Activity */ + const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ + const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ + const uint32_t gen_call : 1; /* Raw Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ +typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 +/* The address of the ALT_I2C_RAW_INTR_STAT register. */ +#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) + +/* + * Register : Receive FIFO Threshold Register - ic_rx_tl + * + * I2C Receive FIFO Threshold Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rx_tl + * + * Controls the level of entries (or above) that triggers the RX_FULL interrupt + * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + * additional restriction that hardware does not allow this value to be set to a + * value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_MSB 7 +/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 +/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ +#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ +#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RX_TL. + */ +struct ALT_I2C_RX_TL_s +{ + uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RX_TL. */ +typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ +#define ALT_I2C_RX_TL_OFST 0x38 +/* The address of the ALT_I2C_RX_TL register. */ +#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - ic_tx_tl + * + * Sets FIFO depth for Interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tx_tl + * + * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the + * additional restriction that it may not be set to value larger than the depth of + * the buffer. If an attempt is made to do that, the actual value set will be the + * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + * a value of 255 sets the threshold for 255 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_MSB 7 +/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 +/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ +#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ +#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_TL. + */ +struct ALT_I2C_TX_TL_s +{ + uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_TL. */ +typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ +#define ALT_I2C_TX_TL_OFST 0x3c +/* The address of the ALT_I2C_TX_TL register. */ +#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) + +/* + * Register : Combined and Individual Interrupt Register - ic_clr_intr + * + * Controls Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Combined and Individual Interrupt Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Combined and Individual Interrupt Bits - clr_intr + * + * Read this register to clear the combined interrupt, all individual interrupts, + * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + * interrupts but software clearable interrupts. Refer to Bit 9 of the + * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 +/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 +/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_INTR. + */ +struct ALT_I2C_CLR_INTR_s +{ + const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_INTR. */ +typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ +#define ALT_I2C_CLR_INTR_OFST 0x40 +/* The address of the ALT_I2C_CLR_INTR register. */ +#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) + +/* + * Register : Rx Under Interrupt Register - ic_clr_rx_under + * + * Rx Under Interrupt Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Clear Rx Under Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Rx Under Interrupt Bit - clr_rx_under + * + * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_UNDER. + */ +struct ALT_I2C_CLR_RX_UNDER_s +{ + const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ +typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 +/* The address of the ALT_I2C_CLR_RX_UNDER register. */ +#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) + +/* + * Register : RX Over Interrupt Register - ic_clr_rx_over + * + * Clears Rx over Interrupt Bit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX Over Interrupt Bit - clr_rx_over + * + * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_OVER. + */ +struct ALT_I2C_CLR_RX_OVER_s +{ + const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ +typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_OVER_OFST 0x48 +/* The address of the ALT_I2C_CLR_RX_OVER register. */ +#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) + +/* + * Register : TX Over Interrupt Register - ic_clr_tx_over + * + * Clears Over Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | TX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TX Over Interrupt Bit - clr_tx_over + * + * Read this register to clear the TX_OVER interrupt (bit 3) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_OVER. + */ +struct ALT_I2C_CLR_TX_OVER_s +{ + const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ +typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_OVER_OFST 0x4c +/* The address of the ALT_I2C_CLR_TX_OVER register. */ +#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) + +/* + * Register : Interrupt Read Request Register - ic_clr_rd_req + * + * Clear RD_REQ Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Interrupt Register Read Request Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Register Read Request Bit - clr_rd_req + * + * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RD_REQ. + */ +struct ALT_I2C_CLR_RD_REQ_s +{ + const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ +typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ +#define ALT_I2C_CLR_RD_REQ_OFST 0x50 +/* The address of the ALT_I2C_CLR_RD_REQ register. */ +#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) + +/* + * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt + * + * Clear TX_ABRT Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Tx Abort Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Abort Interrupt Bit - clr_tx_abort + * + * Read this register to clear the TX_ABRT interrupt (bit 6) of the + * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also + * releases the TX FIFO from the flushed/reset state, allowing more writes to the + * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to + * clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_ABRT. + */ +struct ALT_I2C_CLR_TX_ABRT_s +{ + const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ +typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 +/* The address of the ALT_I2C_CLR_TX_ABRT register. */ +#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) + +/* + * Register : Rx Done Interrupt Register - ic_clr_rx_done + * + * Clear RX_DONE Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX_DONE Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX_DONE Interrupt Bit - clr_rx_done + * + * Read this register to clear the RX_DONE interrupt (bit 7) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_DONE. + */ +struct ALT_I2C_CLR_RX_DONE_s +{ + const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ +typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_DONE_OFST 0x58 +/* The address of the ALT_I2C_CLR_RX_DONE register. */ +#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) + +/* + * Register : Activity Interrupt Register - ic_clr_activity + * + * Clears ACTIVITY Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Activity Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Interrupt Bit - clr_activity + * + * Reading this register clears the ACTIVITY interrupt if the I2C is not active + * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + * bit continues to be set. It is automatically cleared by hardware if the module + * is disabled and if there is no further activity on the bus. The value read from + * this register to get status of the ACTIVITY interrupt (bit 8) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_ACTIVITY. + */ +struct ALT_I2C_CLR_ACTIVITY_s +{ + const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ +typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ +#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c +/* The address of the ALT_I2C_CLR_ACTIVITY register. */ +#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) + +/* + * Register : Stop Detect Interrupt Register - ic_clr_stop_det + * + * Clear Interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | R | 0x0 | Stop Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Detect Interrupt Bit - clr_stop_det + * + * Read this register to clear the clr_stop_det interrupt (bit 9) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_STOP_DET. + */ +struct ALT_I2C_CLR_STOP_DET_s +{ + const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ +typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_STOP_DET_OFST 0x60 +/* The address of the ALT_I2C_CLR_STOP_DET register. */ +#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) + +/* + * Register : Start Detect Interrupt Register - ic_clr_start_det + * + * Clears START_DET Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Start Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Detect Interrupt Bit - clr_start_det + * + * Read this register to clear the start_det interrupt (bit 10) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_START_DET. + */ +struct ALT_I2C_CLR_START_DET_s +{ + const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ +typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_START_DET_OFST 0x64 +/* The address of the ALT_I2C_CLR_START_DET register. */ +#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) + +/* + * Register : GEN CALL Interrupt Register - ic_clr_gen_call + * + * Clear GEN_CALL Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | GEN CALL Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GEN CALL Interrupt Bit - clr_gen_call + * + * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_GEN_CALL. + */ +struct ALT_I2C_CLR_GEN_CALL_s +{ + const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ +typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ +#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 +/* The address of the ALT_I2C_CLR_GEN_CALL register. */ +#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) + +/* + * Register : Enable Register - ic_enable + * + * Enable and disable i2c operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Enable Bit + * [1] | RW | 0x0 | TX abort Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Bit - enable + * + * Controls whether the I2C is enabled. Software can disable I2C while it is + * active. However, it is important that care be taken to ensure that I2C is + * disabled properly. When the I2C is disabled, the following occurs: + * + * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register + * are still active until I2C goes into IDLE state. If the module is transmitting, + * it stops as well as deletes the contents of the transmit buffer after the + * current transfer is complete. If the module is receiving, the I2C stops the + * current transfer at the end of the current byte and does not acknowledge the + * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register + * ic_enable_status is added to allow software to determine when the hardware has + * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. + * Only one register is required to be monitored. Procedure for Disabling I2C + * + * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling + * period for the highest I2C transfer speed used in the system and supported by + * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this + * ti2c_poll is 25us. + * + * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any + * repeated polling operation exceeds this maximum value, an error is reported. 3. + * Execute a blocking thread/process/function that prevents any further I2C master + * transactions to be started by software, but allows any pending transfers to be + * completed. + * + * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. + * + * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment + * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant + * error code. + * + * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the + * previous step. Otherwise, exit with a relevant success code. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------|:------|:----------------------------------------------- + * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an + * : | | erased state + * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it + * : | | is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Disables i2c. TX and RX FIFOs are held in an erased state + */ +#define ALT_I2C_EN_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Enables i2c. Software can disable i2c while it is active + */ +#define ALT_I2C_EN_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_EN field value from a register. */ +#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX abort Bit - txabort + * + * Write 1 does a TX abort. Self cleared on abort completion + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_MSB 1 +/* The width in bits of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_RESET 0x0 +/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ +#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ +#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN. + */ +struct ALT_I2C_EN_s +{ + uint32_t enable : 1; /* Enable Bit */ + uint32_t txabort : 1; /* TX abort Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN. */ +typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ +#define ALT_I2C_EN_OFST 0x6c +/* The address of the ALT_I2C_EN register. */ +#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) + +/* + * Register : Status Register - ic_status + * + * This is a read-only register used to indicate the current transfer status and + * FIFO status. The status register may be read at any time. None of the bits in + * this register request an interrupt.When the I2C is disabled by writing 0 in bit + * 0 of the ic_enable register: + * + * * Bits 1 and 2 are set to 1 + * + * * Bits 3 and 4 are set to 0 + * + * When the master or slave state machines goes to idle + * + * * Bits 5 and 6 are set to 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | R | 0x0 | Activity Status Bit + * [1] | R | 0x1 | TX FIFO Not Full Bit + * [2] | R | 0x1 | TX FIFO Empty Bit + * [3] | R | 0x0 | RX FIFO Empty Bit + * [4] | R | 0x0 | RX FIFO Full Bit + * [5] | R | 0x0 | Master FSM Activity Status Bit + * [6] | R | 0x0 | Slave FSM Activity Status Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Status Bit - activity + * + * I2C Activity. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX FIFO Not Full Bit - tfnf + * + * Transmit Fifo Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is full + */ +#define ALT_I2C_STAT_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_MSB 1 +/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ +#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TX FIFO Empty Bit - tfe + * + * Transmit FIFO Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is empty + */ +#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_MSB 2 +/* The width in bits of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ +#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RX FIFO Empty Bit - rfne + * + * Receive FIFO Not Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is empty + */ +#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_MSB 3 +/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ +#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RX FIFO Full Bit - rff + * + * Receive FIFO Completely Full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------- + * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is not full + */ +#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is full + */ +#define ALT_I2C_STAT_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_MSB 4 +/* The width in bits of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ +#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master FSM Activity Status Bit - mst_activity + * + * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is + * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c + * : | | is not Active + * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of + * : | | i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is in IDLE state. Master part of i2c is not Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is not in IDLE state. Master part of i2c is Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 +/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave FSM Activity Status Bit - slv_activity + * + * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + * the IDLE state, this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of + * : | | i2c is not Active + * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part + * : | | of i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is in IDLE state so the Slave part of i2c is not Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is not in IDLE state so the Slave part of i2c is Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 +/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_STAT. + */ +struct ALT_I2C_STAT_s +{ + const uint32_t activity : 1; /* Activity Status Bit */ + const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ + const uint32_t tfe : 1; /* TX FIFO Empty Bit */ + const uint32_t rfne : 1; /* RX FIFO Empty Bit */ + const uint32_t rff : 1; /* RX FIFO Full Bit */ + const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ + const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_STAT. */ +typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ +#define ALT_I2C_STAT_OFST 0x70 +/* The address of the ALT_I2C_STAT register. */ +#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) + +/* + * Register : Transmit FIFO Level Register - ic_txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat + * register. The slave bulk transmit mode is aborted The register increments + * whenever data is placed into the transmit FIFO and decrements when data is + * taken from the transmit FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [6:0] | R | 0x0 | Transmit FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level Bit - txflr + * + * Transmit FIFO Level.Contains the number of valid data entries in the transmit + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_MSB 6 +/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 +/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ +#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ +#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TXFLR. + */ +struct ALT_I2C_TXFLR_s +{ + const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TXFLR. */ +typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ +#define ALT_I2C_TXFLR_OFST 0x74 +/* The address of the ALT_I2C_TXFLR register. */ +#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - ic_rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * Whenever there is a transmit abort caused by any of the events tracked in + * ic_tx_abrt_source The register increments whenever data is placed into the + * receive FIFO and decrements when data is taken from the receive FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [6:0] | R | 0x0 | Receive FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Bit - rxflr + * + * Receive FIFO Level. Contains the number of valid data entries in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_MSB 6 +/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 +/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ +#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ +#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RXFLR. + */ +struct ALT_I2C_RXFLR_s +{ + const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RXFLR. */ +typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ +#define ALT_I2C_RXFLR_OFST 0x78 +/* The address of the ALT_I2C_RXFLR register. */ +#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) + +/* + * Register : SDA Hold Register - ic_sda_hold + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the falling edge of SCL, relative to SDA changing, + * when I2C services a read request in a slave-transmitter operation. The relevant + * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x1 | SDA Hold Bit + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Hold Bit - ic_sda_hold + * + * Program to a minimum 0f 300ns. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 +/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 +/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 +/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_HOLD. + */ +struct ALT_I2C_SDA_HOLD_s +{ + uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ +typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ +#define ALT_I2C_SDA_HOLD_OFST 0x7c +/* The address of the ALT_I2C_SDA_HOLD register. */ +#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) + +/* + * Register : Transmit Abort Source Register - ic_tx_abrt_source + * + * This register has 16 bits that indicate the source of the TX_ABRT bit. Except + * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the + * ic_clr_intr register is read. To clear Bit 9, the source of the + * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), + * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be + * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then + * this bit can be cleared in the same manner as other bits in this register. If + * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear + * this bit, Bit 9 clears for one cycle and is then re-asserted. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Master Abort 7 Bit Address + * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 + * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 + * [3] | RW | 0x0 | Master Abort TX Noack Bit + * [4] | RW | 0x0 | Master Abort GC Noack Bit + * [5] | RW | 0x0 | Master Abort GC Read Bit + * [6] | RW | 0x0 | Master HS MC Ack + * [7] | RW | 0x0 | Master Abort START Byte + * [8] | RW | 0x0 | Master HS Restart Disabled + * [9] | RW | 0x0 | Master Abort START No Restart + * [10] | RW | 0x0 | Master Abort 10 Bit No Restart + * [11] | RW | 0x0 | Master Oper Master Dis + * [12] | RW | 0x0 | Master Abort Arbitration Lost + * [13] | RW | 0x0 | Slave Abort Flush TXFIFO + * [14] | RW | 0x0 | Slave Abort Arbitration Lost + * [15] | RW | 0x0 | Slave Abort Read TX + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack + * + * Master is in 7-bit addressing mode and the address sent was not acknowledged by + * any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack + * + * Master is in 10-bit address mode and the first 10-bit address byte was not + * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack + * + * Master is in 10-bit address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or + * Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Master Abort TX Noack Bit - abrt_txdata_noack + * + * This is a master-mode only bit. Master has received an acknowledgement for the + * address, but when it sent data byte(s) following the address, it did not receive + * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Abort GC Noack Bit - abrt_gcall_noack + * + * i2c in master mode sent a General Call and no slave on the bus acknowledged the + * General Call. Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master Abort GC Read Bit - abrt_gcall_read + * + * i2c in master mode sent a General Call but the user programmed the byte + * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to + * 1). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Master HS MC Ack - abrt_hs_ackdet + * + * Master is in High Speed mode and the High Speed Master code was acknowledged + * (wrong behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Master Abort START Byte - abrt_sbyte_ackdet + * + * Master has sent a START Byte and the START Byte was acknowledged (wrong + * behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Master HS Restart Disabled - abrt_hs_norstrt + * + * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is + * trying to use the master to transfer data in High Speed mode. Role of i2c: + * Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Master Abort START No Restart - abrt_sbyte_norstrt + * + * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; + * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared + * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the + * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the + * same manner as other bits in this register. If the source of the + * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 + * clears for one cycle and then gets reasserted. 1: The restart is disabled + * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. + * Role of I2C: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt + * + * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends + * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Master Oper Master Dis - abrt_master_dis + * + * User tries to initiate a Master operation with the Master mode disabled. Role of + * I2C: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Abort Arbitration Lost - arb_lost + * + * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: I2C can be both master and slave + * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo + * + * Slave has received a read command and some data exists in the TX FIFO so the + * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: + * Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Slave Abort Arbitration Lost - abrt_slv_arblost + * + * Slave lost the bus while transmitting data to a remote master. + * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never + * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. + * For instance, during a data transmission at the low-to-high transition of SCL, + * if what is on the data bus is not what is supposed to be transmitted, then i2c + * no longer own the bus. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Slave Abort Read TX - abrt_slvrd_intx + * + * When the processor side responds to a slave mode request for data to be + * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + * register. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_ABRT_SRC. + */ +struct ALT_I2C_TX_ABRT_SRC_s +{ + uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ + uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ + uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ + uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ + uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ + uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ + uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ + uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ + uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ + uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ + uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ + uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ + uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ + uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ + uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ + uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ +typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ +#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 +/* The address of the ALT_I2C_TX_ABRT_SRC register. */ +#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) + +/* + * Register : Generate Slave Data NACK - ic_slv_data_nack_only + * + * The register is used to generate a NACK for the data part of a transfer when i2c + * is acting as a slave-receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | Generate Nack Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generate Nack Bit - nack + * + * This Bit control Nack generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:-------------------------------------- + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK after data byte receive + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK/ACK normally + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 +/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 +/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. + */ +struct ALT_I2C_SLV_DATA_NACK_ONLY_s +{ + uint32_t nack : 1; /* Generate Nack Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ +typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) + +/* + * Register : DMA Control - ic_dma_cr + * + * The register is used to enable the DMA Controller interface operation. There is + * a separate bit for transmit and receive. This can be programmed regardless of + * the state of IC_ENABLE. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Receive DMA Enable Bit + * [1] | RW | 0x0 | Transmit DMA Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable Bit - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------- + * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable + * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA disable + */ +#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_MSB 0 +/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable Bit - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------- + * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable + * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA disable + */ +#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_MSB 1 +/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_CR. + */ +struct ALT_I2C_DMA_CR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable Bit */ + uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_CR. */ +typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ +#define ALT_I2C_DMA_CR_OFST 0x88 +/* The address of the ALT_I2C_DMA_CR register. */ +#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) + +/* + * Register : DMA Transmit Data Level - ic_dma_tdlr + * + * This register supports DMA Transmit Operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Transmit Data Level Bit - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_TDLR. + */ +struct ALT_I2C_DMA_TDLR_s +{ + uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ +typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_TDLR_OFST 0x8c +/* The address of the ALT_I2C_DMA_TDLR register. */ +#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) + +/* + * Register : Receive Data Level - ic_dma_rdlr + * + * DMA Control Signals Interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [5:0] | RW | 0x0 | Receive Data Level Bits + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level Bits - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when + * the number of valid data entries in the receive FIFO is equal to or more than + * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then + * dma_rx_req is asserted when or more data entries are present in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_RDLR. + */ +struct ALT_I2C_DMA_RDLR_s +{ + uint32_t dmardl : 6; /* Receive Data Level Bits */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ +typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_RDLR_OFST 0x90 +/* The address of the ALT_I2C_DMA_RDLR register. */ +#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) + +/* + * Register : SDA Setup Register - ic_sda_setup + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the rising edge of SCL relative to SDA changing by + * holding SCL low when I2C services a read request while operating as a slave- + * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the + * I2C Bus Specification. This register must be programmed with a value equal to or + * greater than 2. + * + * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they + * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C + * when operating as a slave transmitter. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [7:0] | RW | 0x64 | SDA Setup Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Setup Value - sda_setup + * + * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk + * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 +/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 +/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 +/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_SETUP. + */ +struct ALT_I2C_SDA_SETUP_s +{ + uint32_t sda_setup : 8; /* SDA Setup Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ +typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ +#define ALT_I2C_SDA_SETUP_OFST 0x94 +/* The address of the ALT_I2C_SDA_SETUP register. */ +#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) + +/* + * Register : ACK General Call - ic_ack_general_call + * + * The register controls whether i2c responds with a ACK or NACK when it receives + * an I2C General Call address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | ACK General Call Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ACK General Call Bit - ack_gen_call + * + * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General + * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------- + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with a NACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with an ACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. + */ +struct ALT_I2C_ACK_GENERAL_CALL_s +{ + uint32_t ack_gen_call : 1; /* ACK General Call Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ +typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ +#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 +/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) + +/* + * Register : Enable Status Register - ic_enable_status + * + * This register is used to report the i2c hardware status when the IC_ENABLE + * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has + * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE + * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. + * + * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be + * read as '0' because disabling the i2c depends on I2C bus activities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | R | 0x0 | Enable Status Bit + * [1] | R | 0x0 | Slave Disabled While Busy Bit + * [2] | R | 0x0 | Slave Received Data Lost Bit + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Status Bit - ic_en + * + * This bit always reflects the value driven on the output port ic_en. Not used in + * current application. When read as 1, i2c is deemed to be in an enabled state. + * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read + * this bit anytime. When this bit is read as 0, the CPU can safely read + * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ +#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy + * + * This bit indicates if a potential or active Slave operation has been aborted due + * to the setting of the ic_enable register from 1 to 0. This bit is set when the + * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address + * byte of the Slave-Transmitter operation from a remote master; OR, (b) address + * and data bytes of the Slave-Receiver operation from a remote master. When read + * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, + * irrespective of whether the I2C address matches the slave address set in i2c + * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 + * but has not taken effect. NOTE: If the remote I2C master terminates the transfer + * with a STOP condition before the i2c has a chance to NACK a transfer, and + * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as + * 0, i2c is deemed to have been disabled when there is master activity, or when + * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) + * is read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Slave Received Data Lost Bit - slv_rx_data_lost + * + * This bit indicates if a Slave-Receiver operation has been aborted with at least + * one data byte received from an I2C transfer due to the setting of IC ENABLE from + * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an + * aborted I2C transfer (with matching address) and the data phase of the I2C + * transfer has been entered, even though a data byte has been responded with a + * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP + * condition before the i2c has a chance to NACK a transfer, and ic_enable has been + * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have + * been disabled without being actively involved in the data phase of a Slave- + * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is + * read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN_STAT. + */ +struct ALT_I2C_EN_STAT_s +{ + const uint32_t ic_en : 1; /* Enable Status Bit */ + const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ + const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN_STAT. */ +typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ +#define ALT_I2C_EN_STAT_OFST 0x9c +/* The address of the ALT_I2C_EN_STAT register. */ +#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) + +/* + * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen + * + * This register is used to store the duration, measured in ic_clk cycles, of the + * longest spike that is filtered out by the spike suppression logic when the + * component is operating in SS or FS modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [7:0] | RW | 0x2 | Spike Suppression Limit Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Spike Suppression Limit Register - spklen + * + * This register must be set before any I2C bus transaction can take place to + * ensure stable operation. This register sets the duration, measured in ic_clk + * cycles, of the longest spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written only when the I2C + * interface is disabled, which corresponds to the IC_ENABLE register being set to + * 0. Writes at other times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, and if attempted results in 2 + * being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 +/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 +/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 +/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SPKLEN. + */ +struct ALT_I2C_FS_SPKLEN_s +{ + uint32_t spklen : 8; /* Spike Suppression Limit Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ +typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ +#define ALT_I2C_FS_SPKLEN_OFST 0xa0 +/* The address of the ALT_I2C_FS_SPKLEN register. */ +#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) + +/* + * Register : Component Parameter Register 1 - ic_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [1:0] | R | 0x2 | APB Data Width Register + * [3:2] | R | 0x2 | Max Speed Mode + * [4] | R | 0x0 | CNT Registers Access + * [5] | R | 0x1 | Intr IO + * [6] | R | 0x1 | Has DMA + * [7] | R | 0x1 | Add Encoded Params + * [15:8] | R | 0x3f | Rx Buffer Depth + * [23:16] | R | 0x3f | Tx Buffer Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB Data Width Register - apb_data_width + * + * Sets the APB Data Width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Max Speed Mode - max_speed_mode + * + * The value of this field determines the maximum i2c bus interface speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD + * + * Fast Mode (400 kbit/s) + */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : CNT Registers Access - hc_count_values + * + * This makes the *CNT registers readable and writable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES + * + * * CNT registers read/write + */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Intr IO - intr_io + * + * All interrupt sources are combined in to a single output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO + * + * Combined Interrupt Output + */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Has DMA - has_dma + * + * This configures the inclusion of DMA handshaking interface signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA + * + * Has DMA + */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Add Encoded Params - add_encoded_params + * + * By adding in the encoded parameters, this gives firmware an easy and quick way + * of identifying the DesignWare component within an I/O memory map. Some critical + * design-time options determine how a driver should interact with the peripheral. + * There is a minimal area overhead by including these parameters. Allows a single + * driver to be developed for each component which will be self-configurable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------- + * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS + * + * Add Encoded Params + */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Rx Buffer Depth - rx_buffer_depth + * + * Sets Rx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------- + * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH + * + * Rx Fifo Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff +/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Tx Buffer Depth - tx_buffer_depth + * + * Sets Tx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH + * + * Tx Buffer Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff +/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_PARAM_1. + */ +struct ALT_I2C_COMP_PARAM_1_s +{ + const uint32_t apb_data_width : 2; /* APB Data Width Register */ + const uint32_t max_speed_mode : 2; /* Max Speed Mode */ + const uint32_t hc_count_values : 1; /* CNT Registers Access */ + const uint32_t intr_io : 1; /* Intr IO */ + const uint32_t has_dma : 1; /* Has DMA */ + const uint32_t add_encoded_params : 1; /* Add Encoded Params */ + const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ + const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ +typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_I2C_COMP_PARAM_1 register. */ +#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - ic_comp_version + * + * Describes the version of the I2C + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------------- + * [31:0] | R | 0x3132302a | Component Parameter Value + * + */ +/* + * Field : Component Parameter Value - ic_comp_version + * + * Specifies I2C release number (encoded as 4 ASCII characters) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:-----------|:-------------- + * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER + * + * Version 1.20a + */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 +/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a +/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_VER. + */ +struct ALT_I2C_COMP_VER_s +{ + const uint32_t ic_comp_version : 32; /* Component Parameter Value */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_VER. */ +typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ +#define ALT_I2C_COMP_VER_OFST 0xf8 +/* The address of the ALT_I2C_COMP_VER register. */ +#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) + +/* + * Register : Component Type Register - ic_comp_type + * + * Describes a unique ASCII value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x44570140 | Component Type Number + * + */ +/* + * Field : Component Type Number - ic_comp_type + * + * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value + * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit + * unsigned number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_TYPE. + */ +struct ALT_I2C_COMP_TYPE_s +{ + const uint32_t ic_comp_type : 32; /* Component Type Number */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ +typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ +#define ALT_I2C_COMP_TYPE_OFST 0xfc +/* The address of the ALT_I2C_COMP_TYPE register. */ +#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_I2C. + */ +struct ALT_I2C_s +{ + volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ + volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ + volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ + volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ + volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_I2C. */ +typedef volatile struct ALT_I2C_s ALT_I2C_t; +/* The struct declaration for the raw register contents of register group ALT_I2C. */ +struct ALT_I2C_raw_s +{ + volatile uint32_t ic_con; /* ALT_I2C_CON */ + volatile uint32_t ic_tar; /* ALT_I2C_TAR */ + volatile uint32_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile uint32_t ic_enable; /* ALT_I2C_EN */ + volatile uint32_t ic_status; /* ALT_I2C_STAT */ + volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_I2C. */ +typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_I2C_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h new file mode 100644 index 0000000000..12e6f21b89 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h @@ -0,0 +1,6299 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_L3 */ + +#ifndef __ALTERA_ALT_L3_H__ +#define __ALTERA_ALT_L3_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : L3 (NIC-301) GPV Registers - ALT_L3 + * L3 (NIC-301) GPV Registers + * + * Registers to control L3 interconnect settings + * + */ +/* + * Register : Remap - remap + * + * The L3 interconnect has separate address maps for the various L3 Masters. + * Generally, the addresses are the same for most masters. However, the sparse + * interconnect of the L3 switch causes some masters to have holes in their memory + * maps. The remap bits are not mutually exclusive. Each bit can be set + * independently and in combinations. Priority for the bits is determined by the + * bit offset: lower offset bits take precedence over higher offset bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [0] | W | 0x0 | MPU at 0x0 + * [1] | W | 0x0 | Non-MPU at 0x0 + * [2] | ??? | 0x0 | *UNDEFINED* + * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility + * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU at 0x0 - mpuzero + * + * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or + * On-chip RAM. This field only has an effect on the MPU L3 master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3 + * : | | master. Note that the Boot ROM is also always + * : | | mapped to address 0xfffd_0000 for the MPU L3 + * : | | master independent of this field's value. + * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU + * : | | L3 master. Note that the On-chip RAM is also + * : | | always mapped to address 0xffff_0000 for the MPU + * : | | L3 master independent of this field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM + * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent + * of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip + * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master + * independent of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_MSB 0 +/* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */ +#define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Non-MPU at 0x0 - nonmpuzero + * + * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM + * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The + * non-MPU L3 masters are the DMA controllers (standalone and those built-in to + * peripherals), the FPGA2HPS AXI Bridge, and the DAP. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3 + * : | | masters. + * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non- + * : | | MPU L3 masters. Note that the On-chip RAM is + * : | | also always mapped to address 0xffff_0000 for + * : | | the non-MPU L3 masters independent of this + * : | | field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the SDRAM to address 0x0 for the non-MPU L3 masters. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the + * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 + * masters independent of this field's value. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_MSB 1 +/* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */ +#define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga + * + * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated + * address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_H2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_MSB 3 +/* The width in bits of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_H2F field value from a register. */ +#define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga + * + * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or + * not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the + * associated address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_MSB 4 +/* The width in bits of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */ +#define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_REMAP. + */ +struct ALT_L3_REMAP_s +{ + uint32_t mpuzero : 1; /* MPU at 0x0 */ + uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_REMAP. */ +typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */ +#define ALT_L3_REMAP_OFST 0x0 + +/* + * Register Group : Security Register Group - ALT_L3_SECGRP + * Security Register Group + * + * Registers that control slave security. + * + */ +/* + * Register : L4 Main Peripherals Security - l4main + * + * Controls security settings for L4 Main peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | SPI Slave 0 Security + * [1] | W | 0x0 | SPI Slave 1 Security + * [2] | W | 0x0 | DMA Secure Security + * [3] | W | 0x0 | DMA Non-secure Security + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Slave 0 Security - spis0 + * + * Controls whether secure or non-secure masters can access the SPI Slave 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Slave 1 Security - spis1 + * + * Controls whether secure or non-secure masters can access the SPI Slave 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA Secure Security - dmasecure + * + * Controls whether secure or non-secure masters can access the DMA Secure slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Non-secure Security - dmanonsecure + * + * Controls whether secure or non-secure masters can access the DMA Non-secure + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MAIN. + */ +struct ALT_L3_SEC_L4MAIN_s +{ + uint32_t spis0 : 1; /* SPI Slave 0 Security */ + uint32_t spis1 : 1; /* SPI Slave 1 Security */ + uint32_t dmasecure : 1; /* DMA Secure Security */ + uint32_t dmanonsecure : 1; /* DMA Non-secure Security */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MAIN. */ +typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */ +#define ALT_L3_SEC_L4MAIN_OFST 0x0 + +/* + * Register : L4 SP Peripherals Security - l4sp + * + * Controls security settings for L4 SP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | W | 0x0 | SDRAM Registers Security + * [1] | W | 0x0 | SP Timer 0 Security + * [2] | W | 0x0 | I2C0 Security + * [3] | W | 0x0 | I2C1 Security + * [4] | W | 0x0 | I2C2 (EMAC 0) Security + * [5] | W | 0x0 | I2C3 (EMAC 1) Security + * [6] | W | 0x0 | UART 0 Security + * [7] | W | 0x0 | UART 1 Security + * [8] | W | 0x0 | CAN 0 Security + * [9] | W | 0x0 | CAN 1 Security + * [10] | W | 0x0 | SP Timer 1 Security + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Registers Security - sdrregs + * + * Controls whether secure or non-secure masters can access the SDRAM Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SP Timer 0 Security - sptimer0 + * + * Controls whether secure or non-secure masters can access the SP Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : I2C0 Security - i2c0 + * + * Controls whether secure or non-secure masters can access the I2C0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : I2C1 Security - i2c1 + * + * Controls whether secure or non-secure masters can access the I2C1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : I2C2 (EMAC 0) Security - i2c2 + * + * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : I2C3 (EMAC 1) Security - i2c3 + * + * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : UART 0 Security - uart0 + * + * Controls whether secure or non-secure masters can access the UART 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : UART 1 Security - uart1 + * + * Controls whether secure or non-secure masters can access the UART 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : CAN 0 Security - can0 + * + * Controls whether secure or non-secure masters can access the CAN 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : CAN 1 Security - can1 + * + * Controls whether secure or non-secure masters can access the CAN 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 1 Security - sptimer1 + * + * Controls whether secure or non-secure masters can access the SP Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_MSB 10 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SP. + */ +struct ALT_L3_SEC_L4SP_s +{ + uint32_t sdrregs : 1; /* SDRAM Registers Security */ + uint32_t sptimer0 : 1; /* SP Timer 0 Security */ + uint32_t i2c0 : 1; /* I2C0 Security */ + uint32_t i2c1 : 1; /* I2C1 Security */ + uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */ + uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */ + uint32_t uart0 : 1; /* UART 0 Security */ + uint32_t uart1 : 1; /* UART 1 Security */ + uint32_t can0 : 1; /* CAN 0 Security */ + uint32_t can1 : 1; /* CAN 1 Security */ + uint32_t sptimer1 : 1; /* SP Timer 1 Security */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SP. */ +typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */ +#define ALT_L3_SEC_L4SP_OFST 0x4 + +/* + * Register : L4 MP Peripherals Security - l4mp + * + * Controls security settings for L4 MP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [0] | W | 0x0 | FPGA Manager Register Security + * [1] | W | 0x0 | DAP Security + * [2] | W | 0x0 | QSPI Registers Security + * [3] | W | 0x0 | SDMMC Security + * [4] | W | 0x0 | EMAC 0 Security + * [5] | W | 0x0 | EMAC 1 Security + * [6] | W | 0x0 | ACP ID Mapper Security + * [7] | W | 0x0 | GPIO 0 Security + * [8] | W | 0x0 | GPIO 1 Security + * [9] | W | 0x0 | GPIO 2 Security + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Register Security - fpgamgrregs + * + * Controls whether secure or non-secure masters can access the FPGA Manager + * Register slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DAP Security - dap + * + * Controls whether secure or non-secure masters can access the DAP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */ +#define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI Registers Security - qspiregs + * + * Controls whether secure or non-secure masters can access the QSPI Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */ +#define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Security - sdmmc + * + * Controls whether secure or non-secure masters can access the SDMMC slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */ +#define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC 0 Security - emac0 + * + * Controls whether secure or non-secure masters can access the EMAC 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC 1 Security - emac1 + * + * Controls whether secure or non-secure masters can access the EMAC 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : ACP ID Mapper Security - acpidmap + * + * Controls whether secure or non-secure masters can access the ACP ID Mapper + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : GPIO 0 Security - gpio0 + * + * Controls whether secure or non-secure masters can access the GPIO 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : GPIO 1 Security - gpio1 + * + * Controls whether secure or non-secure masters can access the GPIO 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : GPIO 2 Security - gpio2 + * + * Controls whether secure or non-secure masters can access the GPIO 2 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MP. + */ +struct ALT_L3_SEC_L4MP_s +{ + uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */ + uint32_t dap : 1; /* DAP Security */ + uint32_t qspiregs : 1; /* QSPI Registers Security */ + uint32_t sdmmc : 1; /* SDMMC Security */ + uint32_t emac0 : 1; /* EMAC 0 Security */ + uint32_t emac1 : 1; /* EMAC 1 Security */ + uint32_t acpidmap : 1; /* ACP ID Mapper Security */ + uint32_t gpio0 : 1; /* GPIO 0 Security */ + uint32_t gpio1 : 1; /* GPIO 1 Security */ + uint32_t gpio2 : 1; /* GPIO 2 Security */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MP. */ +typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */ +#define ALT_L3_SEC_L4MP_OFST 0x8 + +/* + * Register : L4 OSC1 Peripherals Security - l4osc1 + * + * Controls security settings for L4 OSC1 peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | W | 0x0 | L4 Watchdog Timer 0 Security + * [1] | W | 0x0 | L4 Watchdog Timer 0 Security + * [2] | W | 0x0 | Clock Manager Security + * [3] | W | 0x0 | Reset Manager Security + * [4] | W | 0x0 | System Manager Security + * [5] | W | 0x0 | OSC1 Timer 0 Security + * [6] | W | 0x0 | OSC1 Timer 1 Security + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L4 Watchdog Timer 0 Security - l4wd0 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L4 Watchdog Timer 0 Security - l4wd1 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Clock Manager Security - clkmgr + * + * Controls whether secure or non-secure masters can access the Clock Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reset Manager Security - rstmgr + * + * Controls whether secure or non-secure masters can access the Reset Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : System Manager Security - sysmgr + * + * Controls whether secure or non-secure masters can access the System Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : OSC1 Timer 0 Security - osc1timer0 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OSC1 Timer 1 Security - osc1timer1 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4OSC1. + */ +struct ALT_L3_SEC_L4OSC1_s +{ + uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t clkmgr : 1; /* Clock Manager Security */ + uint32_t rstmgr : 1; /* Reset Manager Security */ + uint32_t sysmgr : 1; /* System Manager Security */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4OSC1. */ +typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */ +#define ALT_L3_SEC_L4OSC1_OFST 0xc + +/* + * Register : L4 SPIM Peripherals Security - l4spim + * + * Controls security settings for L4 SPIM peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | W | 0x0 | SPI Master 0 Security + * [1] | W | 0x0 | SPI Master 1 Security + * [2] | W | 0x0 | Scan Manager Security + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Master 0 Security - spim0 + * + * Controls whether secure or non-secure masters can access the SPI Master 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Master 1 Security - spim1 + * + * Controls whether secure or non-secure masters can access the SPI Master 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Scan Manager Security - scanmgr + * + * Controls whether secure or non-secure masters can access the Scan Manager slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SPIM. + */ +struct ALT_L3_SEC_L4SPIM_s +{ + uint32_t spim0 : 1; /* SPI Master 0 Security */ + uint32_t spim1 : 1; /* SPI Master 1 Security */ + uint32_t scanmgr : 1; /* Scan Manager Security */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SPIM. */ +typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */ +#define ALT_L3_SEC_L4SPIM_OFST 0x10 + +/* + * Register : STM Peripheral Security - stm + * + * Controls security settings for STM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | STM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : STM Security - s + * + * Controls whether secure or non-secure masters can access the STM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_STM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_STM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_STM_S field value from a register. */ +#define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_STM. + */ +struct ALT_L3_SEC_STM_s +{ + uint32_t s : 1; /* STM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_STM. */ +typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */ +#define ALT_L3_SEC_STM_OFST 0x14 + +/* + * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs + * + * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : LWHPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI + * Bridge Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */ +#define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_LWH2F. + */ +struct ALT_L3_SEC_LWH2F_s +{ + uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_LWH2F. */ +typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */ +#define ALT_L3_SEC_LWH2F_OFST 0x18 + +/* + * Register : USB1 Registers Peripheral Security - usb1 + * + * Controls security settings for USB1 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB1 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB1 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB1_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB1_S field value from a register. */ +#define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB1. + */ +struct ALT_L3_SEC_USB1_s +{ + uint32_t s : 1; /* USB1 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB1. */ +typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */ +#define ALT_L3_SEC_USB1_OFST 0x20 + +/* + * Register : NAND Flash Controller Data Peripheral Security - nanddata + * + * Controls security settings for NAND Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | NAND Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */ +#define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NANDDATA. + */ +struct ALT_L3_SEC_NANDDATA_s +{ + uint32_t s : 1; /* NAND Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NANDDATA. */ +typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */ +#define ALT_L3_SEC_NANDDATA_OFST 0x24 + +/* + * Register : USB0 Registers Peripheral Security - usb0 + * + * Controls security settings for USB0 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB0 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB0 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB0_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB0_S field value from a register. */ +#define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB0. + */ +struct ALT_L3_SEC_USB0_s +{ + uint32_t s : 1; /* USB0 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB0. */ +typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */ +#define ALT_L3_SEC_USB0_OFST 0x78 + +/* + * Register : NAND Flash Controller Registers Peripheral Security - nandregs + * + * Controls security settings for NAND Flash Controller Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | NAND Flash Controller Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Registers Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NAND_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NAND_S field value from a register. */ +#define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NAND. + */ +struct ALT_L3_SEC_NAND_s +{ + uint32_t s : 1; /* NAND Flash Controller Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NAND. */ +typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */ +#define ALT_L3_SEC_NAND_OFST 0x7c + +/* + * Register : QSPI Flash Controller Data Peripheral Security - qspidata + * + * Controls security settings for QSPI Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | QSPI Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the QSPI Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */ +#define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_QSPIDATA. + */ +struct ALT_L3_SEC_QSPIDATA_s +{ + uint32_t s : 1; /* QSPI Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */ +typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */ +#define ALT_L3_SEC_QSPIDATA_OFST 0x80 + +/* + * Register : FPGA Manager Data Peripheral Security - fpgamgrdata + * + * Controls security settings for FPGA Manager Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | W | 0x0 | FPGA Manager Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Data Security - s + * + * Controls whether secure or non-secure masters can access the FPGA Manager Data + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA. + */ +struct ALT_L3_SEC_FPGAMGRDATA_s +{ + uint32_t s : 1; /* FPGA Manager Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84 + +/* + * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs + * + * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge + * Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_H2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_H2F_S field value from a register. */ +#define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_H2F. + */ +struct ALT_L3_SEC_H2F_s +{ + uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_H2F. */ +typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */ +#define ALT_L3_SEC_H2F_OFST 0x88 + +/* + * Register : MPU ACP Peripheral Security - acp + * + * Controls security settings for MPU ACP peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | W | 0x0 | MPU ACP Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU ACP Security - s + * + * Controls whether secure or non-secure masters can access the MPU ACP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ACP_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ACP_S field value from a register. */ +#define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ACP. + */ +struct ALT_L3_SEC_ACP_s +{ + uint32_t s : 1; /* MPU ACP Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ACP. */ +typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */ +#define ALT_L3_SEC_ACP_OFST 0x8c + +/* + * Register : ROM Peripheral Security - rom + * + * Controls security settings for ROM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | ROM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ROM Security - s + * + * Controls whether secure or non-secure masters can access the ROM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ROM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ROM_S field value from a register. */ +#define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ROM. + */ +struct ALT_L3_SEC_ROM_s +{ + uint32_t s : 1; /* ROM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ROM. */ +typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */ +#define ALT_L3_SEC_ROM_OFST 0x90 + +/* + * Register : On-chip RAM Peripheral Security - ocram + * + * Controls security settings for On-chip RAM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | W | 0x0 | On-chip RAM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM Security - s + * + * Controls whether secure or non-secure masters can access the On-chip RAM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */ +#define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_OCRAM. + */ +struct ALT_L3_SEC_OCRAM_s +{ + uint32_t s : 1; /* On-chip RAM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_OCRAM. */ +typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */ +#define ALT_L3_SEC_OCRAM_OFST 0x94 + +/* + * Register : SDRAM Data Peripheral Security - sdrdata + * + * Controls security settings for SDRAM Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | W | 0x0 | SDRAM Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Data Security - s + * + * Controls whether secure or non-secure masters can access the SDRAM Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */ +#define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_SDRDATA. + */ +struct ALT_L3_SEC_SDRDATA_s +{ + uint32_t s : 1; /* SDRAM Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_SDRDATA. */ +typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_SDRDATA_OFST 0x98 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SECGRP. + */ +struct ALT_L3_SECGRP_s +{ + volatile ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */ + volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */ + volatile ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */ + volatile ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */ + volatile ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */ + volatile ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */ + volatile ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */ +struct ALT_L3_SECGRP_raw_s +{ + volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile uint32_t stm; /* ALT_L3_SEC_STM */ + volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */ + volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */ + volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */ + volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile uint32_t acp; /* ALT_L3_SEC_ACP */ + volatile uint32_t rom; /* ALT_L3_SEC_ROM */ + volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ID Register Group - ALT_L3_IDGRP + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_4. + */ +struct ALT_L3_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_0. + */ +struct ALT_L3_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_1. + */ +struct ALT_L3_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_2. + */ +struct ALT_L3_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_3. + */ +struct ALT_L3_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_0. + */ +struct ALT_L3_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */ +typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_1. + */ +struct ALT_L3_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */ +typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_2. + */ +struct ALT_L3_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */ +typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_3. + */ +struct ALT_L3_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */ +typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_IDGRP. + */ +struct ALT_L3_IDGRP_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */ +struct ALT_L3_IDGRP_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Master Register Group - ALT_L3_MSTGRP + * Master Register Group + * + * Registers associated with master interfaces in the L3 Interconnect. Note that a + * master in the L3 Interconnect connects to a slave in a module. + * + */ +/* + * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN + * L4 MAIN + * + * Registers associated with the L4 MAIN master. This master is used to access the + * APB slaves on the L4 MAIN bus. + * + */ +/* + * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss + * + * Sets the issuing capability of the preceding switch arbitration scheme to + * multiple or single outstanding transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_BM_ISS. + */ +struct ALT_L3_FN_MOD_BM_ISS_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */ +typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */ +#define ALT_L3_FN_MOD_BM_ISS_OFST 0x8 +/* The address of the ALT_L3_FN_MOD_BM_ISS register. */ +#define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MAIN. + */ +struct ALT_L3_MST_L4MAIN_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +struct ALT_L3_MST_L4MAIN_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SP - ALT_L3_MST_L4SP + * L4 SP + * + * Registers associated with the L4 SP master. This master is used to access the + * APB slaves on the L4 SP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SP. + */ +struct ALT_L3_MST_L4SP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +struct ALT_L3_MST_L4SP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 MP - ALT_L3_MST_L4MP + * L4 MP + * + * Registers associated with the L4 MP master. This master is used to access the + * APB slaves on the L4 MP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MP. + */ +struct ALT_L3_MST_L4MP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +struct ALT_L3_MST_L4MP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1 + * L4 OSC1 + * + * Registers associated with the L4 OSC1 master. This master is used to access the + * APB slaves on the L4 OSC1 bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4OSC1. + */ +struct ALT_L3_MST_L4OSC1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +struct ALT_L3_MST_L4OSC1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM + * L4 SPIM + * + * Registers associated with the L4 SPIM master. This master is used to access the + * APB slaves on the L4 SPIM bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SPIM. + */ +struct ALT_L3_MST_L4SPIM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +struct ALT_L3_MST_L4SPIM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : STM - ALT_L3_MST_STM + * STM + * + * Registers associated with the STM master. This master is used to access the STM + * AXI slave. + * + */ +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_RD field value from a register. */ +#define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_WR field value from a register. */ +#define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD. + */ +struct ALT_L3_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD. */ +typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */ +#define ALT_L3_FN_MOD_OFST 0x108 +/* The address of the ALT_L3_FN_MOD register. */ +#define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_STM. + */ +struct ALT_L3_MST_STM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */ +struct ALT_L3_MST_STM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F + * LWHPS2FPGA + * + * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used + * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the + * registers for all 3 AXI bridges and to access slaves in the FPGA connected to + * the LWHPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_LWH2F. + */ +struct ALT_L3_MST_LWH2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +struct ALT_L3_MST_LWH2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_MST_USB1 + * USB1 + * + * Registers associated with the USB1 master. This master is used to access the + * registers in USB1. + * + */ +/* + * Register : AHB Control Register - ahb_cntl + * + * Sets the block issuing capability to one outstanding transaction. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN + * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : decerr_en + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response. + * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives + * : | | an unaligned address or a write data beat + * : | | without all the byte strobes set, creates a + * : | | DECERR response. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * No DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * If the AHB protocol conversion function receives an unaligned address or a write + * data beat without all the byte strobes set, creates a DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0 +/* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : force_incr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions + * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data + * : | | strobes set, that write data beat is replaced + * : | | with an IDLE beat. Also, causes all transactions + * : | | that are to be output to the AHB domain to be an + * : | | undefined length INCR. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * If a beat is received that has no write data strobes set, that write data beat + * is replaced with an IDLE beat. Also, causes all transactions that are to be + * output to the AHB domain to be an undefined length INCR. + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1 +/* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_AHB_CNTL. + */ +struct ALT_L3_AHB_CNTL_s +{ + uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */ + uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_AHB_CNTL. */ +typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */ +#define ALT_L3_AHB_CNTL_OFST 0x44 +/* The address of the ALT_L3_AHB_CNTL register. */ +#define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB1. + */ +struct ALT_L3_MST_USB1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +struct ALT_L3_MST_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDDATA - ALT_L3_MST_NANDDATA + * NANDDATA + * + * Registers associated with the NANDDATA master. This master is used to access + * data in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NANDDATA. + */ +struct ALT_L3_MST_NANDDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +struct ALT_L3_MST_NANDDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_MST_USB0 + * USB0 + * + * Registers associated with the USB0 master. This master is used to access the + * registers in USB0. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB0. + */ +struct ALT_L3_MST_USB0_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +struct ALT_L3_MST_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDREGS - ALT_L3_MST_NAND + * NANDREGS + * + * Registers associated with the NANDREGS master. This master is used to access the + * registers in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NAND. + */ +struct ALT_L3_MST_NAND_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +struct ALT_L3_MST_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA + * QSPIDATA + * + * Registers associated with the QSPIDATA master. This master is used to access + * data in the QSPI flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_QSPIDATA. + */ +struct ALT_L3_MST_QSPIDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +struct ALT_L3_MST_QSPIDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA + * FPGAMGRDATA + * + * Registers associated with the FPGAMGRDATA master. This master is used to send + * FPGA configuration image data to the FPGA Manager. + * + */ +/* + * Register : Write Tidemark - wr_tidemark + * + * Controls the release of the transaction in the write data FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x4 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Stalls the transaction in the write data FIFO until the number of occupied slots + * in the write data FIFO exceeds the level. Note that the transaction is released + * before this level is achieved if the network receives the WLAST beat or the + * write FIFO becomes full. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3 +/* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4 +/* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4 +/* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_TIDEMARK. + */ +struct ALT_L3_WR_TIDEMARK_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_TIDEMARK. */ +typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */ +#define ALT_L3_WR_TIDEMARK_OFST 0x40 +/* The address of the ALT_L3_WR_TIDEMARK register. */ +#define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA. + */ +struct ALT_L3_MST_FPGAMGRDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +struct ALT_L3_MST_FPGAMGRDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : HPS2FPGA - ALT_L3_MST_H2F + * HPS2FPGA + * + * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to + * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the + * FPGA connected to the HPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_H2F. + */ +struct ALT_L3_MST_H2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +struct ALT_L3_MST_H2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ACP - ALT_L3_MST_ACP + * ACP + * + * Registers associated with the ACP master. This master is used to access the MPU + * ACP slave via the ACP ID Mapper. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ACP. + */ +struct ALT_L3_MST_ACP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +struct ALT_L3_MST_ACP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM - ALT_L3_MST_ROM + * Boot ROM + * + * Registers associated with the Boot ROM master. This master is used to access the + * contents of the Boot ROM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ROM. + */ +struct ALT_L3_MST_ROM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +struct ALT_L3_MST_ROM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : On-chip RAM - ALT_L3_MST_OCRAM + * On-chip RAM + * + * Registers associated with the On-chip RAM master. This master is used to access + * the contents of the On-chip RAM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_OCRAM. + */ +struct ALT_L3_MST_OCRAM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +struct ALT_L3_MST_OCRAM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MSTGRP. + */ +struct ALT_L3_MSTGRP_s +{ + volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +struct ALT_L3_MSTGRP_raw_s +{ + volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Slave Register Group - ALT_L3_SLVGRP + * Slave Register Group + * + * Registers associated with slave interfaces. + * + */ +/* + * Register Group : DAP - ALT_L3_SLV_DAP + * DAP + * + * Registers associated with the DAP slave interface. This slave is used by the DAP + * to access slaves attached to the L3/L4 Interconnect. + * + */ +/* + * Register : Functionality Modification 2 Register - fn_mod2 + * + * Controls bypass merge of upsizing/downsizing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Bypass Merge + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass Merge - bypass_merge + * + * Controls bypass merge of upsizing/downsizing. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that + * : | | could pass through the upsizer legally without + * : | | alteration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network can alter transactions. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network does not alter any transactions that could pass through the upsizer + * legally without alteration. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD2. + */ +struct ALT_L3_FN_MOD2_s +{ + uint32_t bypass_merge : 1; /* Bypass Merge */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD2. */ +typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */ +#define ALT_L3_FN_MOD2_OFST 0x24 +/* The address of the ALT_L3_FN_MOD2 register. */ +#define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST)) + +/* + * Register : Functionality Modification AHB Register - fn_mod_ahb + * + * Controls how AHB-lite burst transactions are converted to AXI tranactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Read Increment Override + * [1] | RW | 0x0 | Write Increment Override + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Increment Override - rd_incr_override + * + * Controls how AHB-lite read burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Increment Override - wr_incr_override + * + * Controls how AHB-lite write burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_AHB. + */ +struct ALT_L3_FN_MOD_AHB_s +{ + uint32_t rd_incr_override : 1; /* Read Increment Override */ + uint32_t wr_incr_override : 1; /* Write Increment Override */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_AHB. */ +typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */ +#define ALT_L3_FN_MOD_AHB_OFST 0x28 +/* The address of the ALT_L3_FN_MOD_AHB register. */ +#define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST)) + +/* + * Register : Read Channel QoS Value - read_qos + * + * QoS (Quality of Service) value for the read channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the read channel. A higher value has a higher + * priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */ +#define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_RD_QOS. + */ +struct ALT_L3_RD_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_RD_QOS. */ +typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */ +#define ALT_L3_RD_QOS_OFST 0x100 +/* The address of the ALT_L3_RD_QOS register. */ +#define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST)) + +/* + * Register : Write Channel QoS Value - write_qos + * + * QoS (Quality of Service) value for the write channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the write channel. A higher value has a + * higher priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */ +#define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_QOS. + */ +struct ALT_L3_WR_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_QOS. */ +typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */ +#define ALT_L3_WR_QOS_OFST 0x104 +/* The address of the ALT_L3_WR_QOS register. */ +#define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DAP. + */ +struct ALT_L3_SLV_DAP_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +struct ALT_L3_SLV_DAP_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : MPU - ALT_L3_SLV_MPU + * MPU + * + * Registers associated with the MPU slave interface. This slave is used by the MPU + * to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_MPU. + */ +struct ALT_L3_SLV_MPU_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +struct ALT_L3_SLV_MPU_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC - ALT_L3_SLV_SDMMC + * SDMMC + * + * Registers associated with the SDMMC slave interface. This slave is used by the + * DMA controller built into the SDMMC to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_SDMMC. + */ +struct ALT_L3_SLV_SDMMC_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +struct ALT_L3_SLV_SDMMC_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA - ALT_L3_SLV_DMA + * DMA + * + * Registers associated with the DMA Controller slave interface. This slave is used + * by the DMA Controller to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DMA. + */ +struct ALT_L3_SLV_DMA_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +struct ALT_L3_SLV_DMA_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGA2HPS - ALT_L3_SLV_F2H + * FPGA2HPS + * + * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is + * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_F2H. + */ +struct ALT_L3_SLV_F2H_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +struct ALT_L3_SLV_F2H_raw_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ETR - ALT_L3_SLV_ETR + * ETR + * + * Registers associated with the ETR (TMC) slave interface. This slave is used by + * the ETR to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_ETR. + */ +struct ALT_L3_SLV_ETR_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +struct ALT_L3_SLV_ETR_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC0 - ALT_L3_SLV_EMAC0 + * EMAC0 + * + * Registers associated with the EMAC0 slave interface. This slave is used by the + * DMA controller built into the EMAC0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC0. + */ +struct ALT_L3_SLV_EMAC0_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +struct ALT_L3_SLV_EMAC0_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC1 - ALT_L3_SLV_EMAC1 + * EMAC1 + * + * Registers associated with the EMAC1 slave interface. This slave is used by the + * DMA controller built into the EMAC1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC1. + */ +struct ALT_L3_SLV_EMAC1_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +struct ALT_L3_SLV_EMAC1_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_SLV_USB0 + * USB0 + * + * Registers associated with the USB0 slave interface. This slave is used by the + * DMA controller built into the USB0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB0. + */ +struct ALT_L3_SLV_USB0_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +struct ALT_L3_SLV_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND - ALT_L3_SLV_NAND + * NAND + * + * Registers associated with the NAND slave interface. This slave is used by the + * DMA controller built into the NAND flash controller to access slaves attached to + * the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_NAND. + */ +struct ALT_L3_SLV_NAND_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +struct ALT_L3_SLV_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_SLV_USB1 + * USB1 + * + * Registers associated with the USB1 slave interface. This slave is used by the + * DMA controller built into the USB1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB1. + */ +struct ALT_L3_SLV_USB1_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +struct ALT_L3_SLV_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLVGRP. + */ +struct ALT_L3_SLVGRP_s +{ + volatile ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +struct ALT_L3_SLVGRP_raw_s +{ + volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3. + */ +struct ALT_L3_s +{ + volatile ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_L3. */ +typedef volatile struct ALT_L3_s ALT_L3_t; +/* The struct declaration for the raw register contents of register group ALT_L3. */ +struct ALT_L3_raw_s +{ + volatile uint32_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3. */ +typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_L3_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h new file mode 100644 index 0000000000..cbec31b76f --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h @@ -0,0 +1,5951 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPI */ + +#ifndef __ALTERA_ALT_QSPI_H__ +#define __ALTERA_ALT_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Controller Module Registers - ALT_QSPI + * QSPI Flash Controller Module Registers + * + * Registers in the QSPI Flash Controller module accessible via its APB slave + * + */ +/* + * Register : QSPI Configuration Register - cfg + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | QSPI Enable + * [1] | RW | 0x0 | Clock Polarity + * [2] | RW | 0x0 | Select Clock Phase + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable Direct Access Controller + * [8] | RW | 0x0 | Legacy IP Mode Enable + * [9] | RW | 0x0 | Peripheral select decode + * [13:10] | RW | 0x0 | Peripheral Chip Select Lines + * [14] | RW | 0x0 | Write Protect Flash Pin + * [15] | RW | 0x0 | Enable DMA Peripheral Interface + * [16] | RW | 0x0 | Enable AHB Address Re-mapping + * [17] | RW | 0x0 | Enter XIP Mode on next READ + * [18] | RW | 0x0 | Enter XIP Mode Immediately + * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor + * [30:23] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE + * + */ +/* + * Field : QSPI Enable - en + * + * If this bit is disabled, the QSPI will finish the current transfer of the data + * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output + * enables are inactive and all pins are set to input mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------|:------|:----------------- + * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI + * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Disable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Enable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_MSB 0 +/* The width in bits of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ +#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Polarity - selclkpol + * + * Controls spiclk modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent high + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Select Clock Phase - selclkphase + * + * Selects whether the clock is in an active or inactive phase outside the SPI + * word. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * Clock Inactive + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable Direct Access Controller - endiracc + * + * If disabled, the Direct Access Controller becomes inactive once the current + * transfer of the data word (FF_W) is complete. When the Direct Access Controller + * and Indirect Access Controller are both disabled, all AHB requests are completed + * with an error response. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl + * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Disable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Enable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_MSB 7 +/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ +#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Legacy IP Mode Enable - enlegacyip + * + * This bit can select the Direct Access Controller/Indirect Access Controller or + * legacy mode.If legacy mode is selected, any write to the controller via the AHB + * interface is serialized and sent to the FLASH device. Any valid AHB read will + * pop the internal RX-FIFO, retrieving data that was forwarded by the external + * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and + * controlled via the HSIZE input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------- + * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode + * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Legacy Mode + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Use Direct/Indirect Access Controller + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 +/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Peripheral select decode - perseldec + * + * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The + * qspi_n_ss_out[3:0] output signals are controlled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode + * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Select external 4-to-16 decode + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Selects 1 of 4 qspi_n_ss_out[3:0] + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_MSB 9 +/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ +#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Peripheral Chip Select Lines - percslines + * + * Peripheral chip select line output decode type. As per perseldec, if perseldec = + * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The + * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] + * require an external 4 to 16 decoder. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_MSB 13 +/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ +#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Write Protect Flash Pin - wp + * + * This bit controls the write protect pin of the flash devices. The signal + * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as + * necessary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect + * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Enable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Disable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_MSB 14 +/* The width in bits of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ +#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable DMA Peripheral Interface - endma + * + * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer + * requests via the DMA peripheral interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode + * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Enable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Disable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_MSB 15 +/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ +#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Enable AHB Address Re-mapping - enahbremap + * + * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted + * and sent to the FLASH device as (address + N), where N is the value stored in + * the remap address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping + * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Enable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Disable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 +/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 +/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff +/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Enter XIP Mode on next READ - enterxipnextrd + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting to + * enabled will inform the controller that the device is ready to enter XIP on the + * next READ instruction. The controller will therefore send the appropriate + * command sequence, including mode bits to cause the device to enter XIP mode. Use + * this register after the controller has ensured the FLASH device has been + * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only AFTER the + * next READ instruction is executed. Software should therefore ensure that at + * least one READ instruction is requested after resetting this bit before it can + * be sure XIP mode in the device is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------- + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Enter XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enter XIP Mode Immediately - enterxipimm + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting enable + * will operate the device in XIP mode immediately. Use this register when the + * external device wakes up in XIP mode (as per the contents of its non- volatile + * configuration register). The controller will assume the next READ instruction + * will be passed to the device as an XIP instruction, and therefore will not + * require the READ opcode to be transferred. Note: To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only after the + * next READ instruction is executed. Software therefore should ensure that at + * least one READ instruction is requested after resetting this bit in order to be + * sure that XIP mode is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately + * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Enter XIP Mode immediately + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Master Mode Baud Rate Divisor - bauddiv + * + * SPI baud rate = ref_clk / (2 * baud_rate_divisor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/2 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/4 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/6 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/8 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/10 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/12 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/14 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/16 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/18 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/20 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/22 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/24 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/26 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/28 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/30 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/32 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_MSB 22 +/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 +/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff +/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf +/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ +#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) + +/* + * Field : Serial interface and QSPI pipeline is IDLE - idle + * + * This is a STATUS read-only bit. Note this is a retimed signal, so there will be + * some inherent delay on the generation of this status signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode + * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_SET 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Non-Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_MSB 31 +/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ +#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_CFG. + */ +struct ALT_QSPI_CFG_s +{ + uint32_t en : 1; /* QSPI Enable */ + uint32_t selclkpol : 1; /* Clock Polarity */ + uint32_t selclkphase : 1; /* Select Clock Phase */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t endiracc : 1; /* Enable Direct Access Controller */ + uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ + uint32_t perseldec : 1; /* Peripheral select decode */ + uint32_t percslines : 4; /* Peripheral Chip Select Lines */ + uint32_t wp : 1; /* Write Protect Flash Pin */ + uint32_t endma : 1; /* Enable DMA Peripheral Interface */ + uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ + uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ + uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ + uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ +}; + +/* The typedef declaration for register ALT_QSPI_CFG. */ +typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ +#define ALT_QSPI_CFG_OFST 0x0 + +/* + * Register : Device Read Instruction Register - devrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode + * [9:8] | RW | 0x0 | Instruction Transfer Width + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [19:18] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Mode Bit Enable + * [23:21] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Read Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Opcode in non-XIP mode - rdopcode + * + * Read Opcode to use when not in XIP mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode + * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Read Opcode in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Fast Read in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 +/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Instruction Transfer Width - instwidth + * + * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions + * sent to SPI flash device (not just read instructions). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all + * : | | SPI flash devices. + * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. + * : | | Supported by all SPI flash devices that support + * : | | the Dual SP (DIO-SPI) Protocol. + * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by all SPI flash devices that + * : | | support the Quad SP (QIO-SPI) Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0. Supported by all SPI flash devices. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that + * support the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash + * devices that support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 +/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets read address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets read data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebits + * + * If this bit is set, the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order + * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * No Order + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * Mode Bits follow address bytes + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 +/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 +/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff +/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Dummy Read Clock Cycles - dummyrdclks + * + * Number of dummy clock cycles required by device for read instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVRD. + */ +struct ALT_QSPI_DEVRD_s +{ + uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ + uint32_t instwidth : 2; /* Instruction Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t enmodebits : 1; /* Mode Bit Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVRD. */ +typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ +#define ALT_QSPI_DEVRD_OFST 0x4 + +/* + * Register : Device Write Instruction Register - devwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | RW | 0x2 | Write Opcode + * [11:8] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [23:18] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Write Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Opcode - wropcode + * + * Write Opcode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 +/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ +#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets write address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Write address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets write data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Write data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Dummy Write Clock Cycles - dummywrclks + * + * Number of dummy clock cycles required by device for write instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVWR. + */ +struct ALT_QSPI_DEVWR_s +{ + uint32_t wropcode : 8; /* Write Opcode */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVWR. */ +typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ +#define ALT_QSPI_DEVWR_OFST 0x8 + +/* + * Register : QSPI Device Delay Register - delay + * + * This register is used to introduce relative delays into the generation of the + * master output signals. All timings are defined in cycles of the qspi_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out + * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit + * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation + * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert + * + */ +/* + * Field : Clock Delay with qspi_n_ss_out - init + * + * Delay in master reference clocks between setting qspi_n_ss_out low and first bit + * transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_MSB 7 +/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ +#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Clock Delay for Last Transaction Bit - after + * + * Delay in master reference clocks between last bit of current transaction and + * deasserting the device chip select (qspi_n_ss_out). By default, the chip select + * will be deasserted on the cycle following the completion of the current + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_MSB 15 +/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ +#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Clock Delay for Chip Select Deactivation - btwn + * + * Delay in master reference clocks between one chip select being de-activated and + * the activation of another. This is used to ensure a quiet period between the + * selection of two different slaves and requires the transmit FIFO to be empty. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_MSB 23 +/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff +/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ +#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Clock Delay for Chip Select Deassert - nss + * + * Delay in master reference clocks for the length that the master mode chip select + * outputs are de-asserted between transactions. The minimum delay is always + * qspi_sck_out period to ensure the chip select is never re-asserted within an + * qspi_sck_out period. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_MSB 31 +/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ +#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DELAY. + */ +struct ALT_QSPI_DELAY_s +{ + uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ + uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ + uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ + uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ +}; + +/* The typedef declaration for register ALT_QSPI_DELAY. */ +typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ +#define ALT_QSPI_DELAY_OFST 0xc + +/* + * Register : Read Data Capture Register - rddatacap + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Bypass + * [4:1] | RW | 0x0 | Read Delay + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass - byp + * + * Controls bypass of the adapted loopback clock circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass + * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * No Bypass + */ +#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * Bypass loopback clock circuit + */ +#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_MSB 0 +/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 +/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 +/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ +#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Read Delay - delay + * + * Delay the read data capturing logic by the programmed number of qspi_clk cycles + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 +/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 +/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e +/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 +/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ +#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RDDATACAP. + */ +struct ALT_QSPI_RDDATACAP_s +{ + uint32_t byp : 1; /* Bypass */ + uint32_t delay : 4; /* Read Delay */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ +typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ +#define ALT_QSPI_RDDATACAP_OFST 0x10 + +/* + * Register : Device Size Register - devsz + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x2 | Number of address Bytes + * [15:4] | RW | 0x100 | Number of Bytes per Device Page + * [20:16] | RW | 0x10 | Number of Bytes per Block + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of address Bytes - numaddrbytes + * + * Number of address bytes. A value of 0 indicates 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 +/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Bytes per Device Page - bytesperdevicepage + * + * Number of bytes per device page. This is required by the controller for + * performing FLASH writes up to and across page boundaries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) + +/* + * Field : Number of Bytes per Block - bytespersubsector + * + * Number of bytes per Block. This is required by the controller for performing the + * write protection logic. The number of bytes per block must be a power of 2 + * number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVSZ. + */ +struct ALT_QSPI_DEVSZ_s +{ + uint32_t numaddrbytes : 4; /* Number of address Bytes */ + uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ + uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVSZ. */ +typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ +#define ALT_QSPI_DEVSZ_OFST 0x14 + +/* + * Register : SRAM Partition Register - srampart + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x40 | Indirect Read Partition Size + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Indirect Read Partition Size - addr + * + * Defines the size of the indirect read partition in the SRAM, in units of SRAM + * locations. By default, half of the SRAM is reserved for indirect read operations + * and half for indirect write operations. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_MSB 6 +/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 +/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 +/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ +#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMPART. + */ +struct ALT_QSPI_SRAMPART_s +{ + uint32_t addr : 7; /* Indirect Read Partition Size */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMPART. */ +typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ +#define ALT_QSPI_SRAMPART_OFST 0x18 + +/* + * Register : Indirect AHB Address Trigger Register - indaddrtrig + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Trigger Address + * + */ +/* + * Field : Trigger Address - addr + * + * This is the base address that will be used by the AHB controller. When the + * incoming AHB read access address matches a range of addresses from this trigger + * address to the trigger address + 15, then the AHB request will be completed by + * fetching data from the Indirect Controllers SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDADDRTRIG. + */ +struct ALT_QSPI_INDADDRTRIG_s +{ + uint32_t addr : 32; /* Trigger Address */ +}; + +/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ +typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ +#define ALT_QSPI_INDADDRTRIG_OFST 0x1c + +/* + * Register : DMA Peripheral Register - dmaper + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [3:0] | RW | 0x0 | Number of Single Bytes + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [11:8] | RW | 0x0 | Number of Burst Bytes + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Single Bytes - numsglreqbytes + * + * Number of bytes in a single type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Burst Bytes - numburstreqbytes + * + * Number of bytes in a burst type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DMAPER. + */ +struct ALT_QSPI_DMAPER_s +{ + uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DMAPER. */ +typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ +#define ALT_QSPI_DMAPER_OFST 0x20 + +/* + * Register : Remap Address Register - remapaddr + * + * This register is used to remap an incoming AHB address to a different address + * used by the FLASH device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Remap Address Offset + * + */ +/* + * Field : Remap Address Offset - value + * + * This offset is added to the incoming AHB address to determine the address used + * by the FLASH device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ +#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_REMAPADDR. + */ +struct ALT_QSPI_REMAPADDR_s +{ + uint32_t value : 32; /* Remap Address Offset */ +}; + +/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ +typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ +#define ALT_QSPI_REMAPADDR_OFST 0x24 + +/* + * Register : Mode Bit Register - modebit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Mode + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * These are the 8 mode bits that are sent to the device following the address + * bytes if mode bit transmission has been enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_MSB 7 +/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_WIDTH 8 +/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_RESET 0x0 +/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ +#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ +#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODBIT. + */ +struct ALT_QSPI_MODBIT_s +{ + uint32_t mode : 8; /* Mode */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODBIT. */ +typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ +#define ALT_QSPI_MODBIT_OFST 0x28 + +/* + * Register : SRAM Fill Register - sramfill + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS + * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS + * + */ +/* + * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 +/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff +/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMFILL. + */ +struct ALT_QSPI_SRAMFILL_s +{ + const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ + const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ +typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ +#define ALT_QSPI_SRAMFILL_OFST 0x2c + +/* + * Register : TX Threshold Register - txthresh + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the transmit FIFO not full interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_TXTHRESH. + */ +struct ALT_QSPI_TXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ +typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_TXTHRESH_OFST 0x30 + +/* + * Register : RX Threshold Register - rxthresh + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the receive FIFO not empty interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RXTHRESH. + */ +struct ALT_QSPI_RXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ +typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_RXTHRESH_OFST 0x34 + +/* + * Register : Interrupt Status Register - irqstat + * + * The status fields in this register are set when the described event occurs and + * the interrupt is enabled in the mask register. When any of these bit fields are + * set, the interrupt output is asserted high. The fields are each cleared by + * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when + * legacy SPI mode is active. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected + * [2] | RW | 0x0 | Indirect Operation Complete + * [3] | RW | 0x0 | Indirect Read Reject + * [4] | RW | 0x0 | Protected Area Write Attempt + * [5] | RW | 0x0 | Illegal AHB Access Detected + * [6] | RW | 0x0 | Transfer Watermark Reached + * [7] | RW | 0x0 | Receive Overflow + * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold + * [9] | RW | 0x0 | Transmit FIFO Full + * [10] | RW | 0x0 | Receive FIFO Compared to Threshold + * [11] | RW | 0x0 | Receive FIFO Full + * [12] | RW | 0x0 | Indirect Read Partition overflow + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected - underflowdet + * + * An underflow is detected when an attempt to transfer data is made when the + * transmit FIFO is empty. This may occur when the AHB write data is being supplied + * too slowly to keep up with the requested write operation. This bit is reset only + * by a system reset and cleared only when the register is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * No Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Operation Complete - indopdone + * + * Controller has completed last triggered indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation + * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * Completed Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject - indrdreject + * + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * Indirect Operation Requested + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt - protwrattempt + * + * Write to protected area was attempted and rejected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * Write Attempt to protected area + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * No Write Attempt + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal AHB Access Detected - illegalacc + * + * Illegal AHB access has been detected. AHB wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this error interrupt to trigger. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * No Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Reached - indxfrlvl + * + * Indirect Transfer Watermark Level Reached + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * Water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * No water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow - rxover + * + * This should only occur in Legacy SPI mode. Set if an attempt is made to push the + * RX FIFO when it is full. This bit is reset only by a system reset and cleared + * only when this register is read. If a new push to the RX FIFO occurs coincident + * with a register read this flag will remain set. 0 : no overflow has been + * detected. 1 : an overflow has occurred. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow + * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * No Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Compared to Threshold - txthreshcmp + * + * Indicates the number of entries in the transmit FIFO with respect to the + * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has > TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has <= TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 +/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full - txfull + * + * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full + * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Compared to Threshold - rxthreshcmp + * + * Indicates the number of entries in the receive FIFO with respect to the + * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has <= RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has > RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO Full - rxfull + * + * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------- + * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full + * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow - indsramfull + * + * Indirect Read Partition of SRAM is full and unable to immediately complete + * indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------- + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is not full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQSTAT. + */ +struct ALT_QSPI_IRQSTAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected */ + uint32_t indopdone : 1; /* Indirect Operation Complete */ + uint32_t indrdreject : 1; /* Indirect Read Reject */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ + uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ + uint32_t rxover : 1; /* Receive Overflow */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ + uint32_t txfull : 1; /* Transmit FIFO Full */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ + uint32_t rxfull : 1; /* Receive FIFO Full */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ +typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ +#define ALT_QSPI_IRQSTAT_OFST 0x40 + +/* + * Register : Interrupt Mask - irqmask + * + * If disabled, the interrupt for the corresponding interrupt status register bit + * is disabled. If enabled, the interrupt for the corresponding interrupt status + * register bit is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected Mask + * [2] | RW | 0x0 | Mask + * [3] | RW | 0x0 | Indirect Read Reject Mask + * [4] | RW | 0x0 | Protected Area Write Attempt Mask + * [5] | RW | 0x0 | Illegal Access Detected Mask + * [6] | RW | 0x0 | Transfer Watermark Breach Mask + * [7] | RW | 0x0 | Receive Overflow Mask + * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask + * [9] | RW | 0x0 | Transmit FIFO Full Mask + * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask + * [11] | RW | 0x0 | Receive FIFO full Mask + * [12] | RW | 0x0 | Indirect Read Partition overflow mask + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected Mask - underflowdet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask - indopdone + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject Mask - indrdreject + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt Mask - protwrattempt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal Access Detected Mask - illegalacc + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Breach Mask - indxfrlvl + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow Mask - rxover + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ +#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full Mask - txfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO full Mask - rxfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow mask - indsramfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQMSK. + */ +struct ALT_QSPI_IRQMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected Mask */ + uint32_t indopdone : 1; /* Mask */ + uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ + uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ + uint32_t rxover : 1; /* Receive Overflow Mask */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ + uint32_t txfull : 1; /* Transmit FIFO Full Mask */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ + uint32_t rxfull : 1; /* Receive FIFO full Mask */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQMSK. */ +typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ +#define ALT_QSPI_IRQMSK_OFST 0x44 + +/* + * Register : Lower Write Protection Register - lowwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the lower block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_LOWWRPROT. + */ +struct ALT_QSPI_LOWWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ +typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ +#define ALT_QSPI_LOWWRPROT_OFST 0x50 + +/* + * Register : Upper Write Protection Register - uppwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the upper block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_UPPWRPROT. + */ +struct ALT_QSPI_UPPWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ +typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ +#define ALT_QSPI_UPPWRPROT_OFST 0x54 + +/* + * Register : Write Protection Register - wrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | Write Protection Inversion Bit + * [1] | RW | 0x0 | Write Protection Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protection Inversion Bit - inv + * + * When enabled, the protection region defined in the lower and upper write + * protection registers is inverted meaning it is the region that the system is + * permitted to write to. When disabled, the protection region defined in the lower + * and upper write protection registers is the region that the system is not + * permitted to write to. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed + * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region allowed + */ +#define ALT_QSPI_WRPROT_INV_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region not allowed + */ +#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_MSB 0 +/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ +#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Protection Enable Bit - en + * + * When enabled, any AHB write access with an address within the protection region + * defined in the lower and upper write protection registers is rejected. An AHB + * error response is generated and an interrupt source triggered. When disabled, + * the protection region is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------------------- + * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected + * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * AHB Write Access rejected + */ +#define ALT_QSPI_WRPROT_EN_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * Protection Region Disabled + */ +#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_MSB 1 +/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ +#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_WRPROT. + */ +struct ALT_QSPI_WRPROT_s +{ + uint32_t inv : 1; /* Write Protection Inversion Bit */ + uint32_t en : 1; /* Write Protection Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_WRPROT. */ +typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ +#define ALT_QSPI_WRPROT_OFST 0x58 + +/* + * Register : Indirect Read Transfer Register - indrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [0] | RW | 0x0 | Start Indirect Read + * [1] | RW | 0x0 | Cancel Indirect Read + * [2] | R | Unknown | Indirect Read Status + * [3] | RW | Unknown | SRAM Full + * [4] | R | Unknown | Queued Indirect Read Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Read - start + * + * When this bit is enabled, it will trigger an indirect read operation. The + * assumption is that the indirect start address and the indirect number of bytes + * register is setup before triggering the indirect read operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read + * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * Trigger Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * No Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ +#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Read - cancel + * + * This bit will cancel all ongoing indirect read operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read + * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Do Not Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ +#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Read Status - rd_status + * + * Indirect read operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress + * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * Read Operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * No read operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ +#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SRAM Full - sram_full + * + * SRAM full and unable to immediately complete an indirect operation. Write a 1 to + * this field to clear it. ; indirect operation (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------- + * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation + * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * Sram Full- Cant complete operation + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * SRram Not Full + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Read Operations - rd_queued + * + * Two indirect read operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read + * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * Queued Indirect Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * No Queued Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - ind_ops_done_status + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Complete operation + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Not Complete + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 +/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - num_ind_ops_done + * + * This field contains the number of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 +/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRD. + */ +struct ALT_QSPI_INDRD_s +{ + uint32_t start : 1; /* Start Indirect Read */ + uint32_t cancel : 1; /* Cancel Indirect Read */ + const uint32_t rd_status : 1; /* Indirect Read Status */ + uint32_t sram_full : 1; /* SRAM Full */ + const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ + uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ + const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRD. */ +typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ +#define ALT_QSPI_INDRD_OFST 0x60 + +/* + * Register : Indirect Read Transfer Watermark Register - indrdwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the minimum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level passes the watermark, an interrupt + * is also generated. This field can be disabled by writing a value of all zeroes. + * The units of this register are BYTES + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDWATER. + */ +struct ALT_QSPI_INDRDWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ +typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ +#define ALT_QSPI_INDRDWATER_OFST 0x64 + +/* + * Register : Indirect Read Transfer Start Address Register - indrdstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [31:0] | RW | 0x0 | Start Address of Indirect Access + * + */ +/* + * Field : Start Address of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its READ + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDSTADDR. + */ +struct ALT_QSPI_INDRDSTADDR_s +{ + uint32_t addr : 32; /* Start Address of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ +typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDRDSTADDR_OFST 0x68 + +/* + * Register : Indirect Read Transfer Number Bytes Register - indrdcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | RW | 0x0 | Indirect Count + * + */ +/* + * Field : Indirect Count - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDCNT. + */ +struct ALT_QSPI_INDRDCNT_s +{ + uint32_t value : 32; /* Indirect Count */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ +typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ +#define ALT_QSPI_INDRDCNT_OFST 0x6c + +/* + * Register : Indirect Write Transfer Register - indwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | 0x0 | Start Indirect Write + * [1] | RW | 0x0 | Cancel Indirect Write + * [2] | R | Unknown | Indirect Write Status + * [3] | R | 0x0 | Reserved + * [4] | R | Unknown | Queued Indirect Write Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Write - start + * + * Writing a 1 to this bit will trigger an indirect write operation. The assumption + * is that the indirect start address and the indirect number of bytes register is + * setup before triggering the indirect write operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------- + * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation + * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * Trigger indirect write operation + */ +#define ALT_QSPI_INDWR_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * No Action + */ +#define ALT_QSPI_INDWR_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ +#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Write - cancel + * + * Writing a 1 to this bit will cancel all ongoing indirect write operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation + * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * Cancel Indirect write operation + */ +#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * No Action + */ +#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ +#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Write Status - rdstat + * + * Indirect write operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation + * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * Indirect write operation + */ +#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * No Action + */ +#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ +#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reserved - sramfull + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ +#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Write Operations - rdqueued + * + * Two indirect write operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation + * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * Two Indirect write operation + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * No Action + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ +#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - inddone + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed + * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * Indirect operation completed + */ +#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * No Action + */ +#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_MSB 5 +/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ +#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - indcnt + * + * This field contains the count of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_MSB 7 +/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ +#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWR. + */ +struct ALT_QSPI_INDWR_s +{ + uint32_t start : 1; /* Start Indirect Write */ + uint32_t cancel : 1; /* Cancel Indirect Write */ + const uint32_t rdstat : 1; /* Indirect Write Status */ + const uint32_t sramfull : 1; /* Reserved */ + const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ + uint32_t inddone : 1; /* Indirect Completion Status */ + const uint32_t indcnt : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWR. */ +typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ +#define ALT_QSPI_INDWR_OFST 0x70 + +/* + * Register : Indirect Write Transfer Watermark Register - indwrwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0xffffffff | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the maximum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level falls below the watermark, an + * interrupt is also generated. This field can be disabled by writing a value of + * all ones. The units of this register are bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff +/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRWATER. + */ +struct ALT_QSPI_INDWRWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ +typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ +#define ALT_QSPI_INDWRWATER_OFST 0x74 + +/* + * Register : Indirect Write Transfer Start Address Register - indwrstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Start of Indirect Access + * + */ +/* + * Field : Start of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its write + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRSTADDR. + */ +struct ALT_QSPI_INDWRSTADDR_s +{ + uint32_t addr : 32; /* Start of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ +typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDWRSTADDR_OFST 0x78 + +/* + * Register : Indirect Write Transfer Count Register - indwrcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Indirect Number of Bytes + * + */ +/* + * Field : Indirect Number of Bytes - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRCNT. + */ +struct ALT_QSPI_INDWRCNT_s +{ + uint32_t value : 32; /* Indirect Number of Bytes */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ +typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ +#define ALT_QSPI_INDWRCNT_OFST 0x7c + +/* + * Register : Flash Command Register - flashcmd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Execute Command + * [1] | R | 0x0 | Command Execution Status + * [6:2] | ??? | 0x0 | *UNDEFINED* + * [11:7] | RW | 0x0 | Number of Dummy Bytes + * [14:12] | RW | 0x0 | Number of Write Data Bytes + * [15] | RW | 0x0 | Write Data Enable + * [17:16] | RW | 0x0 | Number of Address Bytes + * [18] | RW | 0x0 | Mode Bit Enable + * [19] | RW | 0x0 | Command Address Enable + * [22:20] | RW | 0x0 | Number of Read Data Bytes + * [23] | RW | 0x0 | Read Data Enable + * [31:24] | RW | 0x0 | Command Opcode + * + */ +/* + * Field : Execute Command - execcmd + * + * Execute the command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command + * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * Execute Command + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 +/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Command Execution Status - cmdexecstat + * + * Command execution in progress. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * Command Execution Status + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Number of Dummy Bytes - numdummybytes + * + * Set to the number of dummy bytes required This should be setup before triggering + * the command via the execute field of this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f +/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) +/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) + +/* + * Field : Number of Write Data Bytes - numwrdatabytes + * + * Up to 8 Data bytes may be written using this command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Write Data Enable - enwrdata + * + * Set to 1 if the command specified in the command opcode field requires write + * data bytes to be sent to the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes + * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * Command requires write data bytes + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Number of Address Bytes - numaddrbytes + * + * Set to the number of address bytes required (the address itself is programmed in + * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the + * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address + * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 1 Address Byte + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 2 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 3 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 4 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebit + * + * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------- + * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes + * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * Mode Bit follows address bytes + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Command Address Enable - encmdaddr + * + * If enabled, the command specified in bits 31:24 requires an address. This should + * be setup before triggering the command via writing a 1 to the execute field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------- + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * Command in bits 31:24 requires address + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Number of Read Data Bytes - numrddatabytes + * + * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for + * 8 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Read Data Enable - enrddata + * + * If enabled, the command specified in the command opcode field (bits 31:24) + * requires read data bytes to be received from the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data + * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * Command Requires read data + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Command Opcode - cmdopcode + * + * The command opcode field should be setup before triggering the command. For + * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of + * this register launches the command. NOTE : Using this approach to issue commands + * to the device will make use of the instruction type of the device instruction + * configuration register. If this field is set to 2'b00, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * a serial fashion. If this field is set to 2'b01, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command + * opcode, command address, command dummy bytes and command data will all be + * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMD. + */ +struct ALT_QSPI_FLSHCMD_s +{ + uint32_t execcmd : 1; /* Execute Command */ + const uint32_t cmdexecstat : 1; /* Command Execution Status */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ + uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ + uint32_t enwrdata : 1; /* Write Data Enable */ + uint32_t numaddrbytes : 2; /* Number of Address Bytes */ + uint32_t enmodebit : 1; /* Mode Bit Enable */ + uint32_t encmdaddr : 1; /* Command Address Enable */ + uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ + uint32_t enrddata : 1; /* Read Data Enable */ + uint32_t cmdopcode : 8; /* Command Opcode */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ +typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMD_OFST 0x90 + +/* + * Register : Flash Command Address Registers - flashcmdaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Command Address + * + */ +/* + * Field : Command Address - addr + * + * This should be setup before triggering the command with execute field (bit 0) of + * the Flash Command Control register. It is the address used by the command + * specified in the opcode field (bits 31:24) of the Flash Command Control + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDADDR. + */ +struct ALT_QSPI_FLSHCMDADDR_s +{ + uint32_t addr : 32; /* Command Address */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ +typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 + +/* + * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Lower byte) + * + */ +/* + * Field : Command Read Data (Lower byte) - data + * + * This is the data that is returned by the flash device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. + */ +struct ALT_QSPI_FLSHCMDRDDATALO_s +{ + uint32_t data : 32; /* Command Read Data (Lower byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 + +/* + * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Upper byte) + * + */ +/* + * Field : Command Read Data (Upper byte) - data + * + * This is the data that is returned by the FLASH device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. + */ +struct ALT_QSPI_FLSHCMDRDDATAUP_s +{ + uint32_t data : 32; /* Command Read Data (Upper byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 + +/* + * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Command Write Data Lower Byte + * + */ +/* + * Field : Command Write Data Lower Byte - data + * + * This is the command write data lower byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. + */ +struct ALT_QSPI_FLSHCMDWRDATALO_s +{ + uint32_t data : 32; /* Command Write Data Lower Byte */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 + +/* + * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA + * + */ +/* + * Field : data + * + * This is the command write data upper byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. + */ +struct ALT_QSPI_FLSHCMDWRDATAUP_s +{ + uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac + +/* + * Register : Module ID Register - moduleid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------- + * [24:0] | R | 0x1001 | Module ID number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Module ID number - value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_MSB 24 +/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 +/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff +/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 +/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 +/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ +#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) +/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODULEID. + */ +struct ALT_QSPI_MODULEID_s +{ + const uint32_t value : 25; /* Module ID number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODULEID. */ +typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ +#define ALT_QSPI_MODULEID_OFST 0xfc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_QSPI. + */ +struct ALT_QSPI_s +{ + volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ + volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ + volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ + volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ + volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ + volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ + volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ + volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ + volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ + volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ + volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_s ALT_QSPI_t; +/* The struct declaration for the raw register contents of register group ALT_QSPI. */ +struct ALT_QSPI_raw_s +{ + volatile uint32_t cfg; /* ALT_QSPI_CFG */ + volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ + volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ + volatile uint32_t delay; /* ALT_QSPI_DELAY */ + volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ + volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ + volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ + volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ + volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile uint32_t indrd; /* ALT_QSPI_INDRD */ + volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile uint32_t indwr; /* ALT_QSPI_INDWR */ + volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPI_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h new file mode 100644 index 0000000000..19383eefe5 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPIDATA */ + +#ifndef __ALTERA_ALT_QSPIDATA_H__ +#define __ALTERA_ALT_QSPIDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA + * QSPI Flash Module Data (AHB Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPIDATA_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h new file mode 100644 index 0000000000..ab4ac65dcb --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h @@ -0,0 +1,3382 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_RSTMGR */ + +#ifndef __ALTERA_ALT_RSTMGR_H__ +#define __ALTERA_ALT_RSTMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Reset Manager Module - ALT_RSTMGR + * Reset Manager Module + * + * Registers in the Reset Manager module + * + */ +/* + * Register : Status Register - stat + * + * The STAT register contains bits that indicate the reset source or a timeout + * event. For reset sources, a field is 1 if its associated reset requester caused + * the reset. For timeout events, a field is 1 if its associated timeout occured as + * part of a hardware sequenced warm/debug reset. + * + * Software clears bits by writing them with a value of 1. Writes to bits with a + * value of 0 are ignored. + * + * After a cold reset is complete, all bits are reset to their reset value except + * for the bit(s) that indicate the source of the cold reset. If multiple cold + * reset requests overlap with each other, the source de-asserts the request last + * will be logged. The other reset request source(s) de-assert the request in the + * same cycle will also be logged, the rest of the fields are reset to default + * value of 0. + * + * After a warm reset is complete, the bit(s) that indicate the source of the warm + * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT + * register; these bits must be cleared by software writing the STAT register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------- + * [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset + * [1] | RW | 0x0 | nPOR Pin Cold Reset + * [2] | RW | 0x0 | FPGA Core Cold Reset + * [3] | RW | 0x0 | CONFIG_IO Cold Reset + * [4] | RW | 0x0 | Software Cold Reset + * [7:5] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | nRST Pin Warm Reset + * [9] | RW | 0x0 | FPGA Core Warm Reset + * [10] | RW | 0x0 | Software Warm Reset + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset + * [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset + * [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset + * [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset + * [17:16] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | FPGA Core Debug Reset + * [19] | RW | 0x0 | DAP Debug Reset + * [23:20] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | SDRAM Self-Refresh Timeout + * [25] | RW | 0x0 | FPGA manager handshake Timeout + * [26] | RW | 0x0 | SCAN manager handshake Timeout + * [27] | RW | 0x0 | FPGA handshake Timeout + * [28] | RW | 0x0 | ETR Stall Timeout + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Power-On Voltage Detector Cold Reset - porvoltrst + * + * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0 +/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : nPOR Pin Cold Reset - nporpinrst + * + * nPOR pin triggered a cold reset (por_pin_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1 +/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA Core Cold Reset - fpgacoldrst + * + * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2 +/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CONFIG_IO Cold Reset - configiocoldrst + * + * FPGA entered CONFIG_IO mode and a triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3 +/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Software Cold Reset - swcoldrst + * + * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4 +/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : nRST Pin Warm Reset - nrstpinrst + * + * nRST pin triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8 +/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Core Warm Reset - fpgawarmrst + * + * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Software Warm Reset - swwarmrst + * + * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm + * reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10 +/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst + * + * MPU Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst + * + * MPU Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : L4 Watchdog 0 Warm Reset - l4wd0rst + * + * L4 Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : L4 Watchdog 1 Warm Reset - l4wd1rst + * + * L4 Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : FPGA Core Debug Reset - fpgadbgrst + * + * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18 +/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : DAP Debug Reset - cdbgreqrst + * + * DAP triggered debug reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19 +/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout + * + * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to + * put the SDRAM devices into self-refresh mode before starting a hardware + * sequenced warm reset timed-out and the Reset Manager had to proceed with the + * warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24 +/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : FPGA manager handshake Timeout - fpgamgrhstimeout + * + * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving + * configuration clock to FPGA CB before starting a hardware sequenced warm reset + * timed-out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : SCAN manager handshake Timeout - scanhstimeout + * + * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving + * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out + * and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26 +/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : FPGA handshake Timeout - fpgahstimeout + * + * A 1 indicates that Reset Manager's handshake request to FPGA before starting a + * hardware sequenced warm reset timed-out and the Reset Manager had to proceed + * with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : ETR Stall Timeout - etrstalltimeout + * + * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to + * stall its AXI master port before starting a hardware sequenced warm reset timed- + * out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28 +/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_STAT. + */ +struct ALT_RSTMGR_STAT_s +{ + uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */ + uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */ + uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */ + uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */ + uint32_t swcoldrst : 1; /* Software Cold Reset */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */ + uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */ + uint32_t swwarmrst : 1; /* Software Warm Reset */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */ + uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */ + uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */ + uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */ + uint32_t cdbgreqrst : 1; /* DAP Debug Reset */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */ + uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */ + uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */ + uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */ + uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_STAT. */ +typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */ +#define ALT_RSTMGR_STAT_OFST 0x0 + +/* + * Register : Control Register - ctrl + * + * The CTRL register is used by software to control reset behavior.It includes + * fields for software to initiate the cold and warm reset, enable hardware + * handshake with other modules before warm reset, and perform software handshake. + * The software handshake sequence must match the hardware sequence. Software + * mustde-assert the handshake request after asserting warm reset and before de- + * assert the warm reset. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------------------------- + * [0] | RW | 0x0 | Software Cold Reset Request + * [1] | RW | 0x0 | Software Warm Reset Request + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | SDRAM Self-Refresh Enable + * [5] | RW | 0x0 | SDRAM Self-Refresh Request + * [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | FPGA Manager Handshake Enable + * [9] | RW | 0x0 | FPGA Manager Handshake Request + * [10] | R | Unknown | FPGA Manager Handshake Acknowledge + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | SCAN Manager Handshake Enable + * [13] | RW | 0x0 | SCAN Manager Handshake Request + * [14] | R | Unknown | SCAN Manager Handshake Acknowledge + * [15] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | FPGA Handshake Enable + * [17] | RW | 0x0 | FPGA Handshake Request + * [18] | R | Unknown | FPGA Handshake Acknowledge + * [19] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable + * [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request + * [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge + * [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Software Cold Reset Request - swcoldrstreq + * + * This is a one-shot bit written by software to 1 to trigger a cold reset. It + * always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0 +/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Software Warm Reset Request - swwarmrstreq + * + * This is a one-shot bit written by software to 1 to trigger a hardware sequenced + * warm reset. It always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1 +/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM Self-Refresh Enable - sdrselfrefen + * + * This field controls whether the contents of SDRAM devices survive a hardware + * sequenced warm reset. If set to 1, the Reset Manager makes a request to the + * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode + * before asserting warm reset signals. However, if SDRAM is already in warm reset, + * Handshake with SDRAM is not performed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM Self-Refresh Request - sdrselfrefreq + * + * Software writes this field 1 to request to the SDRAM Controller Subsystem that + * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM + * contents across a software warm reset. + * + * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. + * Note that it is possible for the SDRAM Controller Subsystem to never assert + * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack + * + * This is the acknowlege for a SDRAM self-refresh mode request initiated by the + * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put + * the SDRAM devices into self-refresh mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA Manager Handshake Enable - fpgamgrhsen + * + * Enables a handshake between the Reset Manager and FPGA Manager before a warm + * reset. The handshake is used to warn the FPGA Manager that a warm reset it + * coming so it can prepare for it. When the FPGA Manager receives a warm reset + * handshake, the FPGA Manager drives its output clock to a quiescent state to + * avoid glitches. + * + * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting + * warm reset signals. However if the FPGA Manager is already in warm reset, the + * handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Manager Handshake Request - fpgamgrhsreq + * + * Software writes this field 1 to request to the FPGA Manager to idle its output + * clock. + * + * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so + * software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack + * + * This is the acknowlege (high active) that the FPGA manager has successfully + * idled its output clock. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SCAN Manager Handshake Enable - scanmgrhsen + * + * Enables a handshake between the Reset Manager and Scan Manager before a warm + * reset. The handshake is used to warn the Scan Manager that a warm reset it + * coming so it can prepare for it. When the Scan Manager receives a warm reset + * handshake, the Scan Manager drives its output clocks to a quiescent state to + * avoid glitches. + * + * If set to 1, the Reset Manager makes a request to the Scan Managerbefore + * asserting warm reset signals. However if the Scan Manager is already in warm + * reset, the handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : SCAN Manager Handshake Request - scanmgrhsreq + * + * Software writes this field 1 to request to the SCAN manager to idle its output + * clocks. + * + * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. + * its input clock is disabled) so software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack + * + * This is the acknowlege (high active) that the SCAN manager has successfully + * idled its output clocks. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : FPGA Handshake Enable - fpgahsen + * + * This field controls whether to perform handshake with FPGA before asserting warm + * reset. + * + * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm + * reset signals. However if FPGA is already in warm reset state, the handshake is + * not performed. + * + * If set to 0, the handshake is not performed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : FPGA Handshake Request - fpgahsreq + * + * Software writes this field 1 to initiate handshake request to FPGA . + * + * Software waits for the FPGAHSACK to be active and then writes this field to 0. + * Note that it is possible for the FPGA to never assert FPGAHSACK so software + * should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : FPGA Handshake Acknowledge - fpgahsack + * + * This is the acknowlege (high active) that the FPGA handshake acknowledge has + * been received by Reset Manager. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen + * + * This field controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate any more) to + * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager + * makes a request to the ETR to stall its AXI master and waits for it to finish + * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a + * debug reset of the ETR. This stalling is required because the debug logic + * (including the ETR) is reset on a debug reset and the ETR AXI master is + * connected to the L3 Interconnect which is reset on a warm reset and these resets + * can happen independently. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq + * + * Software writes this field 1 to request to the ETR that it stalls its AXI master + * to the L3 Interconnect. + * + * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. + * Note that it is possible for the ETR to never assert ETRSTALLACK so software + * should timeout if ETRSTALLACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack + * + * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ + * field. A 1 indicates that the ETR has stalled its AXI master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst + * + * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to + * indicate that the stall of the ETR AXI master is pending. Hardware leaves the + * ETR stalled until software clears this field by writing it with 1. Software must + * only clear this field when it is ready to have the ETR AXI master start making + * AXI requests to write trace data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_CTL. + */ +struct ALT_RSTMGR_CTL_s +{ + uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */ + uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */ + uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */ + const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */ + uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */ + const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */ + uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */ + const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgahsen : 1; /* FPGA Handshake Enable */ + uint32_t fpgahsreq : 1; /* FPGA Handshake Request */ + const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */ + uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */ + const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */ + uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_CTL. */ +typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */ +#define ALT_RSTMGR_CTL_OFST 0x4 + +/* + * Register : Reset Cycles Count Register - counts + * + * The COUNTS register is used by software to control reset behavior.It includes + * fields for software to control the behavior of the warm reset and nRST pin. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [7:0] | RW | 0x80 | Warm reset release delay count + * [27:8] | RW | 0x800 | nRST Pin Count + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm reset release delay count - warmrstcycles + * + * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and + * then waits for the number of cycles specified in this register before releasing + * the rest of the hardware controlled resets. Value must be greater than 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 +/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 +/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff +/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 +/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 +/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : nRST Pin Count - nrstcnt + * + * The Reset Manager pulls down the nRST pin on a warm reset for the number of + * cycles specified in this register. A value of 0x0 prevents the Reset Manager + * from pulling down the nRST pin. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 +/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 +/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 +/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff +/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 +/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8) +/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_COUNTS. + */ +struct ALT_RSTMGR_COUNTS_s +{ + uint32_t warmrstcycles : 8; /* Warm reset release delay count */ + uint32_t nrstcnt : 20; /* nRST Pin Count */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_COUNTS. */ +typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */ +#define ALT_RSTMGR_COUNTS_OFST 0x8 + +/* + * Register : MPU Module Reset Register - mpumodrst + * + * The MPUMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset + * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by + * the corresponding MPUWARMMASK field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | CPU0 + * [1] | RW | 0x1 | CPU1 + * [2] | RW | 0x0 | Watchdogs + * [3] | RW | 0x0 | SCU/Peripherals + * [4] | RW | 0x0 | L2 + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CPU0 - cpu0 + * + * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1, + * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is + * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted. + * + * When software changes this field from 1 to 0, it triggers the following + * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de- + * asserted. + * + * Software needs to wait for at least 64 osc1_clk cycles between each change of + * this field to keep the proper reset/clkoff sequence. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CPU1 - cpu1 + * + * Resets Cortex-A9 CPU1 in MPU. + * + * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until + * software is ready to release CPU1 from reset by writing 0 to this field. + * + * On single-core devices, writes to this field are ignored.On dual-core devices, + * writes to this field trigger the same sequence as writes to the CPU0 field + * (except the sequence is performed on CPU1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Watchdogs - wds + * + * Resets both per-CPU Watchdog Reset Status registers in MPU. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SCU/Peripherals - scuper + * + * Resets SCU and peripherals. Peripherals consist of the interrupt controller, + * global timer, both per-CPU private timers, and both per-CPU watchdogs (except + * for the Watchdog Reset Status registers). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : L2 - l2 + * + * Resets L2 cache controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_MSB 4 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MPUMODRST. + */ +struct ALT_RSTMGR_MPUMODRST_s +{ + uint32_t cpu0 : 1; /* CPU0 */ + uint32_t cpu1 : 1; /* CPU1 */ + uint32_t wds : 1; /* Watchdogs */ + uint32_t scuper : 1; /* SCU/Peripherals */ + uint32_t l2 : 1; /* L2 */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */ +typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MPUMODRST_OFST 0x10 + +/* + * Register : Peripheral Module Reset Register - permodrst + * + * The PERMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x1 | EMAC0 + * [1] | RW | 0x1 | EMAC1 + * [2] | RW | 0x1 | USB0 + * [3] | RW | 0x1 | USB1 + * [4] | RW | 0x1 | NAND Flash + * [5] | RW | 0x1 | QSPI Flash + * [6] | RW | 0x1 | L4 Watchdog 0 + * [7] | RW | 0x1 | L4 Watchdog 1 + * [8] | RW | 0x1 | OSC1 Timer 0 + * [9] | RW | 0x1 | OSC1 Timer 1 + * [10] | RW | 0x1 | SP Timer 0 + * [11] | RW | 0x1 | SP Timer 1 + * [12] | RW | 0x1 | I2C0 + * [13] | RW | 0x1 | I2C1 + * [14] | RW | 0x1 | I2C2 + * [15] | RW | 0x1 | I2C3 + * [16] | RW | 0x1 | UART0 + * [17] | RW | 0x1 | UART1 + * [18] | RW | 0x1 | SPIM0 + * [19] | RW | 0x1 | SPIM1 + * [20] | RW | 0x1 | SPIS0 + * [21] | RW | 0x1 | SPIS1 + * [22] | RW | 0x1 | SD/MMC + * [23] | RW | 0x1 | CAN0 + * [24] | RW | 0x1 | CAN1 + * [25] | RW | 0x1 | GPIO0 + * [26] | RW | 0x1 | GPIO1 + * [27] | RW | 0x1 | GPIO2 + * [28] | RW | 0x1 | DMA Controller + * [29] | RW | 0x1 | SDRAM Controller Subsystem + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 - emac0 + * + * Resets EMAC0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 - emac1 + * + * Resets EMAC1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 - usb0 + * + * Resets USB0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_MSB 2 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 - usb1 + * + * Resets USB1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_MSB 3 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND Flash - nand + * + * Resets NAND flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_MSB 4 +/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */ +#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : QSPI Flash - qspi + * + * Resets QSPI flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5 +/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : L4 Watchdog 0 - l4wd0 + * + * Resets watchdog 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : L4 Watchdog 1 - l4wd1 + * + * Resets watchdog 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OSC1 Timer 0 - osc1timer0 + * + * Resets OSC1 timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : OSC1 Timer 1 - osc1timer1 + * + * Resets OSC1 timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 0 - sptimer0 + * + * Resets SP timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SP Timer 1 - sptimer1 + * + * Resets SP timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : I2C0 - i2c0 + * + * Resets I2C0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : I2C1 - i2c1 + * + * Resets I2C1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : I2C2 - i2c2 + * + * Resets I2C2 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : I2C3 - i2c3 + * + * Resets I2C3 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : UART0 - uart0 + * + * Resets UART0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_MSB 16 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : UART1 - uart1 + * + * Resets UART1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_MSB 17 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : SPIM0 - spim0 + * + * Resets SPIM0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : SPIM1 - spim1 + * + * Resets SPIM1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SPIS0 - spis0 + * + * Resets SPIS0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : SPIS1 - spis1 + * + * Resets SPIS1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : SD/MMC - sdmmc + * + * Resets SD/MMC controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : CAN0 - can0 + * + * Resets CAN0 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : CAN1 - can1 + * + * Resets CAN1 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : GPIO0 - gpio0 + * + * Resets GPIO0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : GPIO1 - gpio1 + * + * Resets GPIO1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : GPIO2 - gpio2 + * + * Resets GPIO2 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : DMA Controller - dma + * + * Resets DMA controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_MSB 28 +/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */ +#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : SDRAM Controller Subsystem - sdr + * + * Resets SDRAM Controller Subsystem affected by a warm or cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_MSB 29 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PERMODRST. + */ +struct ALT_RSTMGR_PERMODRST_s +{ + uint32_t emac0 : 1; /* EMAC0 */ + uint32_t emac1 : 1; /* EMAC1 */ + uint32_t usb0 : 1; /* USB0 */ + uint32_t usb1 : 1; /* USB1 */ + uint32_t nand : 1; /* NAND Flash */ + uint32_t qspi : 1; /* QSPI Flash */ + uint32_t l4wd0 : 1; /* L4 Watchdog 0 */ + uint32_t l4wd1 : 1; /* L4 Watchdog 1 */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */ + uint32_t sptimer0 : 1; /* SP Timer 0 */ + uint32_t sptimer1 : 1; /* SP Timer 1 */ + uint32_t i2c0 : 1; /* I2C0 */ + uint32_t i2c1 : 1; /* I2C1 */ + uint32_t i2c2 : 1; /* I2C2 */ + uint32_t i2c3 : 1; /* I2C3 */ + uint32_t uart0 : 1; /* UART0 */ + uint32_t uart1 : 1; /* UART1 */ + uint32_t spim0 : 1; /* SPIM0 */ + uint32_t spim1 : 1; /* SPIM1 */ + uint32_t spis0 : 1; /* SPIS0 */ + uint32_t spis1 : 1; /* SPIS1 */ + uint32_t sdmmc : 1; /* SD/MMC */ + uint32_t can0 : 1; /* CAN0 */ + uint32_t can1 : 1; /* CAN1 */ + uint32_t gpio0 : 1; /* GPIO0 */ + uint32_t gpio1 : 1; /* GPIO1 */ + uint32_t gpio2 : 1; /* GPIO2 */ + uint32_t dma : 1; /* DMA Controller */ + uint32_t sdr : 1; /* SDRAM Controller Subsystem */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */ +typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PERMODRST_OFST 0x14 + +/* + * Register : Peripheral 2 Module Reset Register - per2modrst + * + * The PER2MODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | FPGA DMA0 + * [1] | RW | 0x1 | FPGA DMA1 + * [2] | RW | 0x1 | FPGA DMA2 + * [3] | RW | 0x1 | FPGA DMA3 + * [4] | RW | 0x1 | FPGA DMA4 + * [5] | RW | 0x1 | FPGA DMA5 + * [6] | RW | 0x1 | FPGA DMA6 + * [7] | RW | 0x1 | FPGA DMA7 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA DMA0 - dmaif0 + * + * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : FPGA DMA1 - dmaif1 + * + * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA DMA2 - dmaif2 + * + * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : FPGA DMA3 - dmaif3 + * + * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA DMA4 - dmaif4 + * + * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : FPGA DMA5 - dmaif5 + * + * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : FPGA DMA6 - dmaif6 + * + * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA DMA7 - dmaif7 + * + * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PER2MODRST. + */ +struct ALT_RSTMGR_PER2MODRST_s +{ + uint32_t dmaif0 : 1; /* FPGA DMA0 */ + uint32_t dmaif1 : 1; /* FPGA DMA1 */ + uint32_t dmaif2 : 1; /* FPGA DMA2 */ + uint32_t dmaif3 : 1; /* FPGA DMA3 */ + uint32_t dmaif4 : 1; /* FPGA DMA4 */ + uint32_t dmaif5 : 1; /* FPGA DMA5 */ + uint32_t dmaif6 : 1; /* FPGA DMA6 */ + uint32_t dmaif7 : 1; /* FPGA DMA7 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */ +typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PER2MODRST_OFST 0x18 + +/* + * Register : Bridge Module Reset Register - brgmodrst + * + * The BRGMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding BRGWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x1 | HPS2FPGA Bridge + * [1] | RW | 0x1 | LWHPS2FPGA Bridge + * [2] | RW | 0x1 | FPGA2HPS Bridge + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA Bridge - hps2fpga + * + * Resets HPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : LWHPS2FPGA Bridge - lwhps2fpga + * + * Resets LWHPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA2HPS Bridge - fpga2hps + * + * Resets FPGA2HPS Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_BRGMODRST. + */ +struct ALT_RSTMGR_BRGMODRST_s +{ + uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */ + uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */ +typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_BRGMODRST_OFST 0x1c + +/* + * Register : Miscellaneous Module Reset Register - miscmodrst + * + * The MISCMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are only reset by a cold reset + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Boot ROM + * [1] | RW | 0x0 | On-chip RAM + * [2] | RW | 0x0 | System Manager (Cold or Warm) + * [3] | RW | 0x0 | System Manager (Cold-only) + * [4] | RW | 0x0 | FPGA Manager + * [5] | RW | 0x0 | ACP ID Mapper + * [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm) + * [7] | RW | 0x0 | HPS to FPGA Core (Cold-only) + * [8] | RW | 0x0 | nRST Pin + * [9] | RW | 0x0 | Timestamp + * [10] | RW | 0x0 | Clock Manager + * [11] | RW | 0x0 | Scan Manager + * [12] | RW | 0x0 | Freeze Controller + * [13] | RW | 0x0 | System/Debug + * [14] | RW | 0x0 | Debug + * [15] | RW | 0x0 | TAP Controller + * [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Boot ROM - rom + * + * Resets Boot ROM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM - ocram + * + * Resets On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : System Manager (Cold or Warm) - sysmgr + * + * Resets logic in System Manager that doesn't differentiate between cold and warm + * resets + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : System Manager (Cold-only) - sysmgrcold + * + * Resets logic in System Manager that is only reset by a cold reset (ignores warm + * reset) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA Manager - fpgamgr + * + * Resets FPGA Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACP ID Mapper - acpidmap + * + * Resets ACP ID Mapper + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : HPS to FPGA Core (Cold or Warm) - s2f + * + * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm + * resets (h2f_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : HPS to FPGA Core (Cold-only) - s2fcold + * + * Resets logic in FPGA core that is only reset by a cold reset (ignores warm + * reset) (h2f_cold_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : nRST Pin - nrstpin + * + * Pulls nRST pin low + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Timestamp - timestampcold + * + * Resets debug timestamp to 0 (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Clock Manager - clkmgrcold + * + * Resets Clock Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Scan Manager - scanmgr + * + * Resets Scan Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Freeze Controller - frzctrlcold + * + * Resets Freeze Controller in System Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : System/Debug - sysdbg + * + * Resets logic that spans the system and debug domains. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Debug - dbg + * + * Resets logic located only in the debug domain. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TAP Controller - tapcold + * + * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. + * nTRST pin). Cold reset only. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDRAM Controller Subsystem Cold Reset - sdrcold + * + * Resets logic in SDRAM Controller Subsystem affected only by a cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MISCMODRST. + */ +struct ALT_RSTMGR_MISCMODRST_s +{ + uint32_t rom : 1; /* Boot ROM */ + uint32_t ocram : 1; /* On-chip RAM */ + uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */ + uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */ + uint32_t fpgamgr : 1; /* FPGA Manager */ + uint32_t acpidmap : 1; /* ACP ID Mapper */ + uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */ + uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */ + uint32_t nrstpin : 1; /* nRST Pin */ + uint32_t timestampcold : 1; /* Timestamp */ + uint32_t clkmgrcold : 1; /* Clock Manager */ + uint32_t scanmgr : 1; /* Scan Manager */ + uint32_t frzctrlcold : 1; /* Freeze Controller */ + uint32_t sysdbg : 1; /* System/Debug */ + uint32_t dbg : 1; /* Debug */ + uint32_t tapcold : 1; /* TAP Controller */ + uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */ +typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MISCMODRST_OFST 0x20 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_RSTMGR. + */ +struct ALT_RSTMGR_s +{ + volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */ + volatile ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */ + volatile ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t; +/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */ +struct ALT_RSTMGR_raw_s +{ + volatile uint32_t stat; /* ALT_RSTMGR_STAT */ + volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */ + volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_RSTMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h new file mode 100644 index 0000000000..785aa743cb --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h @@ -0,0 +1,4149 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SDR */ + +#ifndef __ALTERA_ALT_SDR_H__ +#define __ALTERA_ALT_SDR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SDRAM Controller - ALT_SDR + * SDRAM Controller + * + * Address map for the SDRAM Interface registers + * + */ +/* + * Register Group : SDRAM Controller Module - ALT_SDR_CTL + * SDRAM Controller Module + * + * Address map for the SDRAM controller and multi-port front-end. + * + * All registers in this group reset to zero. + * + */ +/* + * Register : Controller Configuration Register - ctrlcfg + * + * The Controller Configuration Register determines the behavior of the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [2:0] | RW | Unknown | DRAM Memory Type + * [7:3] | RW | Unknown | DRAM Memory Burst Length + * [9:8] | RW | Unknown | Address Interleaving Order + * [10] | RW | Unknown | ECC Enable + * [11] | RW | Unknown | ECC Auto-Correction Enable + * [12] | RW | Unknown | TBD + * [13] | RW | Unknown | Generate Single Bit Errors + * [14] | RW | Unknown | Generate Double Bit Errors + * [15] | RW | Unknown | Command Reorder Enable + * [21:16] | RW | Unknown | Starvation Limit + * [22] | RW | Unknown | DQS Tracking Enable + * [23] | RW | Unknown | No DM Pins Present + * [24] | RW | Unknown | Burst Interrupt Enable + * [25] | RW | Unknown | Burst Terminate Enable + * [31:26] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : DRAM Memory Type - memtype + * + * Selects memory type. Program this field with one of the following binary values, + * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011" + * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : DRAM Memory Burst Length - membl + * + * Configures burst length as a static decimal value. Legal values are valid for + * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this + * should be programmed with 8 (binary "01000"), for DDR2 it can be + * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with + * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program + * the membl field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8) + +/* + * Field : Address Interleaving Order - addrorder + * + * Selects the order for address interleaving. Programming this field with + * different values gives different mappings between the AXI or Avalon-MM address + * and the SDRAM address. Program this field with the following binary values to + * select the ordering. "00" - chip, row, bank, column, "01" - + * chip, bank, row, column, "10"-row, chip, bank, column + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : ECC Enable - eccen + * + * Enable the generation and checking of ECC. This bit must only be set if the + * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, + * you must clear the useeccasdata field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : ECC Auto-Correction Enable - ecccorren + * + * Enable auto correction of the read data returned when single bit error is + * detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TBD - cfg_enable_ecc_code_overwrites + * + * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable + * ECC error is seen and cause a new read/modify/write to be scheduled for that + * location to clear the ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Generate Single Bit Errors - gensbe + * + * Enable the deliberate insertion of single bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Generate Double Bit Errors - gendbe + * + * Enable the deliberate insertion of double bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Command Reorder Enable - reorderen + * + * This bit controls whether the controller can re-order operations to optimize + * SDRAM bandwidth. It should generally be set to a one. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Starvation Limit - starvelimit + * + * Specifies the number of DRAM burst transactions an individual transaction will + * allow to reorder ahead of it before its priority is raised in the memory + * controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : DQS Tracking Enable - dqstrken + * + * Enables DQS tracking in the PHY. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : No DM Pins Present - nodmpins + * + * Set to a one to enable DRAM operation if no DM pins are connected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Burst Interrupt Enable - burstintren + * + * Set to a one to enable the controller to issue burst interrupt commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Burst Terminate Enable - bursttermen + * + * Set to a one to enable the controller to issue burst terminate commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLCFG. + */ +struct ALT_SDR_CTL_CTLCFG_s +{ + uint32_t memtype : 3; /* DRAM Memory Type */ + uint32_t membl : 5; /* DRAM Memory Burst Length */ + uint32_t addrorder : 2; /* Address Interleaving Order */ + uint32_t eccen : 1; /* ECC Enable */ + uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */ + uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */ + uint32_t gensbe : 1; /* Generate Single Bit Errors */ + uint32_t gendbe : 1; /* Generate Double Bit Errors */ + uint32_t reorderen : 1; /* Command Reorder Enable */ + uint32_t starvelimit : 6; /* Starvation Limit */ + uint32_t dqstrken : 1; /* DQS Tracking Enable */ + uint32_t nodmpins : 1; /* No DM Pins Present */ + uint32_t burstintren : 1; /* Burst Interrupt Enable */ + uint32_t bursttermen : 1; /* Burst Terminate Enable */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */ +typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLCFG_OFST 0x0 + +/* + * Register : DRAM Timings 1 Register - dramtiming1 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [3:0] | RW | Unknown | CAS Write Latency + * [8:4] | RW | Unknown | Additive Latency + * [13:9] | RW | Unknown | CAS Read Latency + * [17:14] | RW | Unknown | Activate to Activate Delay + * [23:18] | RW | Unknown | Four Activate Window Time + * [31:24] | RW | Unknown | Refresh Cycle Time + * + */ +/* + * Field : CAS Write Latency - tcwl + * + * Memory write latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Additive Latency - tal + * + * Memory additive latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : CAS Read Latency - tcl + * + * Memory read latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00) + +/* + * Field : Activate to Activate Delay - trrd + * + * The activate to activate, different banks timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000) + +/* + * Field : Four Activate Window Time - tfaw + * + * The four-activate window timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000) + +/* + * Field : Refresh Cycle Time - trfc + * + * The refresh cycle timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1. + */ +struct ALT_SDR_CTL_DRAMTIMING1_s +{ + uint32_t tcwl : 4; /* CAS Write Latency */ + uint32_t tal : 5; /* Additive Latency */ + uint32_t tcl : 5; /* CAS Read Latency */ + uint32_t trrd : 4; /* Activate to Activate Delay */ + uint32_t tfaw : 6; /* Four Activate Window Time */ + uint32_t trfc : 8; /* Refresh Cycle Time */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 + +/* + * Register : DRAM Timings 2 Register - dramtiming2 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [12:0] | RW | Unknown | Refresh Interval + * [16:13] | RW | Unknown | Activate to Read or Write Delay + * [20:17] | RW | Unknown | Row Precharge Time + * [24:21] | RW | Unknown | Write Recovery Time + * [28:25] | RW | Unknown | Write to Read Time + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Refresh Interval - trefi + * + * The refresh interval timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff) + +/* + * Field : Activate to Read or Write Delay - trcd + * + * The activate to read/write timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000) + +/* + * Field : Row Precharge Time - trp + * + * The precharge to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000) + +/* + * Field : Write Recovery Time - twr + * + * The write recovery timing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000) + +/* + * Field : Write to Read Time - twtr + * + * The write to read timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2. + */ +struct ALT_SDR_CTL_DRAMTIMING2_s +{ + uint32_t trefi : 13; /* Refresh Interval */ + uint32_t trcd : 4; /* Activate to Read or Write Delay */ + uint32_t trp : 4; /* Row Precharge Time */ + uint32_t twr : 4; /* Write Recovery Time */ + uint32_t twtr : 4; /* Write to Read Time */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 + +/* + * Register : DRAM Timings 3 Register - dramtiming3 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [3:0] | RW | Unknown | Read to Precharge Time + * [8:4] | RW | Unknown | Activate to Precharge Time + * [14:9] | RW | Unknown | Row Cycle Time + * [18:15] | RW | Unknown | Mode Register Programming Delay + * [22:19] | RW | Unknown | CAS to CAS Delay + * [31:23] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read to Precharge Time - trtp + * + * The read to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Activate to Precharge Time - tras + * + * The activate to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : Row Cycle Time - trc + * + * The activate to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00) + +/* + * Field : Mode Register Programming Delay - tmrd + * + * Mode register timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000) + +/* + * Field : CAS to CAS Delay - tccd + * + * The CAS to CAS delay time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3. + */ +struct ALT_SDR_CTL_DRAMTIMING3_s +{ + uint32_t trtp : 4; /* Read to Precharge Time */ + uint32_t tras : 5; /* Activate to Precharge Time */ + uint32_t trc : 6; /* Row Cycle Time */ + uint32_t tmrd : 4; /* Mode Register Programming Delay */ + uint32_t tccd : 4; /* CAS to CAS Delay */ + uint32_t : 9; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc + +/* + * Register : DRAM Timings 4 Register - dramtiming4 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------------- + * [9:0] | RW | Unknown | Self-refresh Exit + * [19:10] | RW | Unknown | Power Down Exit + * [23:20] | RW | Unknown | Minimum Low Power State Cycles + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Self-refresh Exit - selfrfshexit + * + * The self refresh exit cycles, tXS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : Power Down Exit - pwrdownexit + * + * The power down exit cycles, tXPDLL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00) + +/* + * Field : Minimum Low Power State Cycles - minpwrsavecycles + * + * The minimum number of cycles to stay in a low power state. This applies to both + * power down and self-refresh and should be set to the greater of tPD and tCKESR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4. + */ +struct ALT_SDR_CTL_DRAMTIMING4_s +{ + uint32_t selfrfshexit : 10; /* Self-refresh Exit */ + uint32_t pwrdownexit : 10; /* Power Down Exit */ + uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10 + +/* + * Register : Lower Power Timing Register - lowpwrtiming + * + * This register controls the behavior of the low power logic in the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [15:0] | RW | Unknown | Auto-power Down Cycles + * [19:16] | RW | Unknown | Clock Disable Delay Cycles + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-power Down Cycles - autopdcycles + * + * The number of idle clock cycles after which the controller should place the + * memory into power-down mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Clock Disable Delay Cycles - clkdisablecycles + * + * Set to a the number of clocks after the execution of an self-refresh to stop the + * clock. This register is generally set based on PHY design latency and should + * generally not be changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING. + */ +struct ALT_SDR_CTL_LOWPWRTIMING_s +{ + uint32_t autopdcycles : 16; /* Auto-power Down Cycles */ + uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14 + +/* + * Register : ODT Control Register - dramodt + * + * This register controls which ODT pin is asserted during reads or writes. Bits + * [1:0] control which ODT pin is asserted during to accesses to chip select 0, + * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For + * example, a value of "1001" will cause ODT[0] to be asserted for + * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this + * to "0001" if there is only one chip select available. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [3:0] | RW | Unknown | Write ODT Control + * [7:4] | RW | Unknown | Read ODT Control + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write ODT Control - cfg_write_odt_chip + * + * This register controls which ODT pin is asserted during writes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Read ODT Control - cfg_read_odt_chip + * + * This register controls which ODT pin is asserted during reads. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMODT. + */ +struct ALT_SDR_CTL_DRAMODT_s +{ + uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */ + uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */ +typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMODT_OFST 0x18 + +/* + * Register : DRAM Address Widths Register - dramaddrw + * + * This register configures the width of the various address fields of the DRAM. + * The values specified in this register must match the memory devices being used. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------- + * [4:0] | RW | Unknown | DRAM Column Address Bits + * [9:5] | RW | Unknown | DRAM Row Address Bits + * [12:10] | RW | Unknown | DRAM Bank Address Bits + * [15:13] | RW | Unknown | DRAM Chip Address Bits + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Column Address Bits - colbits + * + * The number of column address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : DRAM Row Address Bits - rowbits + * + * The number of row address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : DRAM Bank Address Bits - bankbits + * + * The number of bank address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00) + +/* + * Field : DRAM Chip Address Bits - csbits + * + * The number of chip select address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMADDRW. + */ +struct ALT_SDR_CTL_DRAMADDRW_s +{ + uint32_t colbits : 5; /* DRAM Column Address Bits */ + uint32_t rowbits : 5; /* DRAM Row Address Bits */ + uint32_t bankbits : 3; /* DRAM Bank Address Bits */ + uint32_t csbits : 3; /* DRAM Chip Address Bits */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */ +typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c + +/* + * Register : DRAM Interface Data Width Register - dramifwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [7:0] | RW | Unknown | DRAM Interface Data Width + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Interface Data Width - ifwidth + * + * This register controls the interface width of the SDRAM interface, including any + * bits used for ECC. For example, for a 32-bit interface with ECC, program this + * register with 0x28. You must also program the ctrlwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH. + */ +struct ALT_SDR_CTL_DRAMIFWIDTH_s +{ + uint32_t ifwidth : 8; /* DRAM Interface Data Width */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30 + +/* + * Register : DRAM Devices Data Width Register - dramdevwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------ + * [3:0] | RW | Unknown | DRAM Devices Data Width + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Devices Data Width - devwidth + * + * This register specifies the width of the physical DRAM chips, for example 8 or + * 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. + */ +struct ALT_SDR_CTL_DRAMDEVWIDTH_s +{ + uint32_t devwidth : 4; /* DRAM Devices Data Width */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34 + +/* + * Register : DRAM Status Register - dramsts + * + * This register provides the status of the calibration and ECC logic. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | PHY Calibration Successful + * [1] | RW | Unknown | PHY Calibration Failed + * [2] | RW | Unknown | Single Bit Error Seen + * [3] | RW | Unknown | Double Bit Error Seen + * [4] | RW | Unknown | ECC Auto-Correction Dropped + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Calibration Successful - calsuccess + * + * This bit will be set to 1 if the PHY was able to successfully calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : PHY Calibration Failed - calfail + * + * This bit will be set to 1 if the PHY was unable to calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Single Bit Error Seen - sbeerr + * + * This bit will be set to 1 if there have been any ECC single bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Double Bit Error Seen - dbeerr + * + * This bit will be set to 1 if there have been any ECC double bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : ECC Auto-Correction Dropped - corrdrop + * + * This bit will be set to 1 if there any auto-corrections have been dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMSTS. + */ +struct ALT_SDR_CTL_DRAMSTS_s +{ + uint32_t calsuccess : 1; /* PHY Calibration Successful */ + uint32_t calfail : 1; /* PHY Calibration Failed */ + uint32_t sbeerr : 1; /* Single Bit Error Seen */ + uint32_t dbeerr : 1; /* Double Bit Error Seen */ + uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */ +typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMSTS_OFST 0x38 + +/* + * Register : ECC Interrupt Register - dramintr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------------- + * [0] | RW | Unknown | Interrupt Enable + * [1] | RW | Unknown | Mask Single Bit Error Interrupt + * [2] | RW | Unknown | Mask Double Bit Error Interrupt + * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt + * [4] | RW | Unknown | Clear Interrupt Signal + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable - intren + * + * Enable the interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Mask Single Bit Error Interrupt - sbemask + * + * Mask the single bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask Double Bit Error Interrupt - dbemask + * + * Mask the double bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Mask Dropped Auto-correction Interrupt - corrdropmask + * + * Set this bit to a one to mask interrupts for an ECC correction write back + * needing to be dropped. This indicates a burst of memory errors in a short + * period of time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear Interrupt Signal - intrclr + * + * Writing to this self-clearing bit clears the interrupt signal. Writing to this + * bit also clears the error count and error address registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMINTR. + */ +struct ALT_SDR_CTL_DRAMINTR_s +{ + uint32_t intren : 1; /* Interrupt Enable */ + uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */ + uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */ + uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */ + uint32_t intrclr : 1; /* Clear Interrupt Signal */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */ +typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMINTR_OFST 0x3c + +/* + * Register : ECC Single Bit Error Count Register - sbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Single Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Single Bit Error Count - count + * + * Reports the number of single bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_SBECOUNT. + */ +struct ALT_SDR_CTL_SBECOUNT_s +{ + uint32_t count : 8; /* Single Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_SBECOUNT_OFST 0x40 + +/* + * Register : ECC Double Bit Error Count Register - dbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Double Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Double Bit Error Count - count + * + * Reports the number of double bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DBECOUNT. + */ +struct ALT_SDR_CTL_DBECOUNT_s +{ + uint32_t count : 8; /* Double Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DBECOUNT_OFST 0x44 + +/* + * Register : ECC Error Address Register - erraddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [31:0] | RW | Unknown | ECC Error Address + * + */ +/* + * Field : ECC Error Address - addr + * + * The address of the most recent ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_ERRADDR. + */ +struct ALT_SDR_CTL_ERRADDR_s +{ + uint32_t addr : 32; /* ECC Error Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */ +typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_ERRADDR_OFST 0x48 + +/* + * Register : ECC Auto-correction Dropped Count Register - dropcount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------------ + * [7:0] | RW | Unknown | Dropped Auto-correction Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dropped Auto-correction Count - corrdropcount + * + * This gives the count of the number of ECC write back transactions dropped due to + * the internal FIFO overflowing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPCOUNT. + */ +struct ALT_SDR_CTL_DROPCOUNT_s +{ + uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */ +typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c + +/* + * Register : ECC Auto-correction Dropped Address Register - dropaddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [31:0] | RW | Unknown | Dropped Auto-correction Address + * + */ +/* + * Field : Dropped Auto-correction Address - corrdropaddr + * + * This register gives the last address which was dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPADDR. + */ +struct ALT_SDR_CTL_DROPADDR_s +{ + uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */ +typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPADDR_OFST 0x50 + +/* + * Register : Low Power Control Register - lowpwreq + * + * This register instructs the controller to put the DRAM into a power down state. + * Note that some commands are only valid for certain memory types. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | Unknown | Deep Power Down Request + * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask + * [3] | RW | Unknown | Self-refresh Request + * [5:4] | RW | Unknown | Self-refresh Chip Select Mask + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Request - deeppwrdnreq + * + * Write a one to this bit to request a deep power down. This bit should only be + * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Deep Power Down Chip Select Mask - deeppwrdnmask + * + * Write ones to this register to select which DRAM chip selects will be powered + * down. Typical usage is to set both of these bits when deeppwrdnreq is set but + * the controller does support putting a single chip into deep power down and + * keeping the other chip running. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Self-refresh Request - selfrshreq + * + * Write a one to this bit to request the RAM be put into a self refresh state. + * This bit is treated as a static value so the RAM will remain in self-refresh as + * long as this register bit is set to a one. This power down mode can be selected + * for all DRAMs supported by the controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Self-refresh Chip Select Mask - selfrfshmask + * + * Write a one to each bit of this field to have a self refresh request apply to + * both chips. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWREQ. + */ +struct ALT_SDR_CTL_LOWPWREQ_s +{ + uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */ + uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */ + uint32_t selfrshreq : 1; /* Self-refresh Request */ + uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */ +typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWREQ_OFST 0x54 + +/* + * Register : Low Power Acknowledge Register - lowpwrack + * + * This register gives the status of the power down commands requested by the Low + * Power Control register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | Deep Power Down Acknowledge + * [1] | RW | Unknown | Self-refresh Acknowledge + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Acknowledge - deeppwrdnack + * + * This bit is set to a one after a deep power down has been executed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Self-refresh Acknowledge - selfrfshack + * + * This bit is a one to indicate that the controller is in a self-refresh state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRACK. + */ +struct ALT_SDR_CTL_LOWPWRACK_s +{ + uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */ + uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRACK_OFST 0x58 + +/* + * Register : Static Configuration Register - staticcfg + * + * This register controls configuration values which cannot be updated while + * transactions are flowing. + * + * You should write once to this register with the membl and eccen fields set to + * your desired configuration, and then write to the register again with membl and + * eccen and the applycfg bit set. The applycfg bit is write only. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [1:0] | RW | Unknown | Memory Burst Length + * [2] | RW | Unknown | Use ECC Bits As Data + * [3] | RW | Unknown | Apply Configuration Changes + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Memory Burst Length - membl + * + * This field specifies the DRAM burst length. Write the following values to set + * the a burst length appropriate for the specific DRAM being used. "00" + * for burst length 2, "01" for burst length 4, "10" for burst + * length 8. If you set this, you must also set the membl field in the ctrlcfg + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Use ECC Bits As Data - useeccasdata + * + * This field allows the FPGA ports to directly access the extra data bits that are + * normally used to hold the ECC code. The interface width must be set to 24 or 40 + * in the dramifwidth register. If you set this, you must clear the eccen field in + * the ctrlcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Apply Configuration Changes - applycfg + * + * Write with this bit set to apply all the settings loaded in SDR registers to the + * memory interface. This bit is write-only and always returns 0 if read. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_STATICCFG. + */ +struct ALT_SDR_CTL_STATICCFG_s +{ + uint32_t membl : 2; /* Memory Burst Length */ + uint32_t useeccasdata : 1; /* Use ECC Bits As Data */ + uint32_t applycfg : 1; /* Apply Configuration Changes */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */ +typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_STATICCFG_OFST 0x5c + +/* + * Register : Memory Controller Width Register - ctrlwidth + * + * This register controls the width of the physical DRAM interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [1:0] | RW | Unknown | Controller Interface Width + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Controller Interface Width - ctrlwidth + * + * Specifies controller DRAM interface width, with the following encoding. + * "00" for 8-bit, "01" for 16-bit (no ECC) or 24-bit (ECC + * enabled), "10" for 32-bit (no ECC) or 40-bit (ECC enabled). You must + * also program the dramifwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1 +/* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLWIDTH. + */ +struct ALT_SDR_CTL_CTLWIDTH_s +{ + uint32_t ctrlwidth : 2; /* Controller Interface Width */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */ +typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLWIDTH_OFST 0x60 + +/* + * Register : Port Configuration Register - portcfg + * + * This register should be set to a zero in any bit which corresponds to a port + * which does mostly sequential memory accesses. For ports with highly random + * accesses, the bit should be set to a one. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [9:0] | ??? | Unknown | *UNDEFINED* + * [19:10] | RW | Unknown | Auto-precharge Enable + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-precharge Enable - autopchen + * + * One bit per control port. Set bit N to a 1 to have the controller request an + * automatic precharge following bus command completion (close the row + * automatically). Set to a zero to request that the controller attempt to keep a + * row open. For random dominated operations this register should be set to a 1 + * for all active ports. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19 +/* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PORTCFG. + */ +struct ALT_SDR_CTL_PORTCFG_s +{ + uint32_t : 10; /* *UNDEFINED* */ + uint32_t autopchen : 10; /* Auto-precharge Enable */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */ +typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_PORTCFG_OFST 0x7c + +/* + * Register : FPGA Ports Reset Control Register - fpgaportrst + * + * This register implements functionality to allow the CPU to control when the MPFE + * will enable the ports to the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------- + * [13:0] | RW | Unknown | Port Reset Control + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Reset Control - portrstn + * + * This register should be written to with a 1 to enable the selected FPGA port to + * exit reset. Writing a bit to a zero will stretch the port reset until the + * register is written. Read data ports are connected to bits 3:0, with read data + * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped + * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit + * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to + * command port 5 at bit 13. Expected usage would be to set all the bits at the + * same time but setting some bits to a zero and others to a one is supported. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13 +/* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff +/* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000 +/* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0) +/* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST. + */ +struct ALT_SDR_CTL_FPGAPORTRST_s +{ + uint32_t portrstn : 14; /* Port Reset Control */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */ +typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */ +#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 + +/* + * Register : Memory Protection Port Default Register - protportdefault + * + * This register controls the default protection assignment for a port. Ports + * which have explicit rules which define regions which are illegal to access + * should set the bits to pass by default. Ports which have explicit rules which + * define legal areas should set the bit to force all transactions to fail. + * Leaving this register to all zeros should be used for systems which do not + * desire any protection from the memory controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Port Default Action + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Default Action - portdefault + * + * Determines the default action for a transactions from a port. Set a bit to a + * zero to indicate that all accesses from the port should pass by default, set a + * bit to a one if the default protection is to fail the access. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. + */ +struct ALT_SDR_CTL_PROTPORTDEFAULT_s +{ + uint32_t portdefault : 10; /* Port Default Action */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */ +typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c + +/* + * Register : Memory Protection Address Register - protruleaddr + * + * This register is used to control the memory protection for port 0 transactions. + * Address ranges can either be used to allow access to memory regions or disallow + * access to memory regions. If trustzone is being used, access can be enabled for + * protected transactions or disabled for unprotected transactions. The default + * state of this register is to allow all access. Address values used for + * protection are only physical addresses. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------- + * [11:0] | RW | Unknown | Low Address + * [23:12] | RW | Unknown | High Address + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Address - lowaddr + * + * Lower 12 bits of the address for a check. Address is compared to be less than + * or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High Address - highaddr + * + * Upper 12 bits of the address for a check. Address is compared to be greater + * than or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR. + */ +struct ALT_SDR_CTL_PROTRULEADDR_s +{ + uint32_t lowaddr : 12; /* Low Address */ + uint32_t highaddr : 12; /* High Address */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90 + +/* + * Register : Memory Protection ID Register - protruleid + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------ + * [11:0] | RW | Unknown | Low ID + * [23:12] | RW | Unknown | High ID + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low ID - lowid + * + * AxID for the protection rule. Incoming AxID needs to be greater than or equal + * to this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High ID - highid + * + * AxID for the protection rule. Incoming AxID needs to be less than or equal to + * this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEID. + */ +struct ALT_SDR_CTL_PROTRULEID_s +{ + uint32_t lowid : 12; /* Low ID */ + uint32_t highid : 12; /* High ID */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEID_OFST 0x94 + +/* + * Register : Memory Protection Rule Data Register - protruledata + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [1:0] | RW | Unknown | Security Bit Behavior + * [2] | RW | Unknown | Valid Rule + * [12:3] | RW | Unknown | Port Mask + * [13] | RW | Unknown | Rule Results + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Security Bit Behavior - security + * + * A value of 2'b00 will make the rule apply to secure transactions. + * + * A value of 2'b01 will make the rule apply to non-secure transactions. + * + * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure + * transactions. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Valid Rule - validrule + * + * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Port Mask - portmask + * + * Set bit x to a one to have this rule apply to port x, set bit x to a zero to + * have the rule not apply to a port. Note that port 0-port 5 are the FPGA + * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9 + * is CPU write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007 +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8) + +/* + * Field : Rule Results - ruleresult + * + * Set this bit to a one to force a protection failure, zero to allow the access + * the succeed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA. + */ +struct ALT_SDR_CTL_PROTRULEDATA_s +{ + uint32_t security : 2; /* Security Bit Behavior */ + uint32_t validrule : 1; /* Valid Rule */ + uint32_t portmask : 10; /* Port Mask */ + uint32_t ruleresult : 1; /* Rule Results */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98 + +/* + * Register : Memory Protection Rule Read-Write Register - protrulerdwr + * + * This register is used to perform read and write operations to the internal + * protection table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [4:0] | RW | Unknown | Rule Offset + * [5] | RW | Unknown | Rule Write + * [6] | RW | Unknown | Rule Read + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Rule Offset - ruleoffset + * + * This field defines which of the 20 rules in the protection table you want to + * read or write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Rule Write - writerule + * + * Write to this bit to have the memory_prot_data register to the table at the + * offset specified by port_offset. Bit automatically clears after a single cycle + * and the write operation is complete. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Rule Read - readrule + * + * Write to this bit to have the memory_prot_data register loaded with the value + * from the internal protection table at offset. Table value will be loaded before + * a rdy is returned so read data from the register will be correct for any follow- + * on reads to the memory_prot_data register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR. + */ +struct ALT_SDR_CTL_PROTRULERDWR_s +{ + uint32_t ruleoffset : 5; /* Rule Offset */ + uint32_t writerule : 1; /* Rule Write */ + uint32_t readrule : 1; /* Rule Read */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c + +/* + * Register : QOS Control Register - qoslowpri + * + * This register controls the mapping of AXI4 QOS received from the FPGA fabric to + * the internal priority used for traffic prioritization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:----------------------- + * [19:0] | RW | Unknown | Low Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Priority QoS Value - lowpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI. + */ +struct ALT_SDR_CTL_QOSLOWPRI_s +{ + uint32_t lowpriorityval : 20; /* Low Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0 + +/* + * Register : qoshighpri Register - qoshighpri + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------ + * [19:0] | RW | Unknown | High Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : High Priority QoS Value - highpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI. + */ +struct ALT_SDR_CTL_QOSHIGHPRI_s +{ + uint32_t highpriorityval : 20; /* High Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4 + +/* + * Register : qospriorityen Register - qospriorityen + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Per-Port QoS Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Per-Port QoS Enable - priorityen + * + * This 10 bit field is set to a one to enable QOS usage for a port. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9 +/* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN. + */ +struct ALT_SDR_CTL_QOSPRIORITYEN_s +{ + uint32_t priorityen : 10; /* Per-Port QoS Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */ +typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8 + +/* + * Register : Scheduler priority Register - mppriority + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [29:0] | RW | Unknown | Port User Priorities + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port User Priorities - userpriority + * + * Set absolute user priority of the port. Each port is represented by a 3 bit + * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port + * number offset corresponds to the control port assignment. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29 +/* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30 +/* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff +/* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000 +/* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPPRIORITY. + */ +struct ALT_SDR_CTL_MPPRIORITY_s +{ + uint32_t userpriority : 30; /* Port User Priorities */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_MPPRIORITY_OFST 0xac + +/* + * Register : Controller Command Pool Priority Remap Register - remappriority + * + * This register controls the priority for transactions in the controller command + * pool. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------- + * [7:0] | RW | Unknown | Priority Remap + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority Remap - priorityremap + * + * Set bit N of this register to the value to a one to enable the controller + * command pool priority bit of a transaction from MPFE priority N + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY. + */ +struct ALT_SDR_CTL_REMAPPRIORITY_s +{ + uint32_t priorityremap : 8; /* Priority Remap */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0 + +/* + * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT + * Port Sum of Weight Register + * + * This register is used to configure the DRAM burst operation scheduling. + * + */ +/* + * Register : Port Sum of Weight Register[1/4] - mpweight_0_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [31:0] | RW | Unknown | Port Static Weights[31:0] + * + */ +/* + * Field : Port Static Weights[31:0] - staticweight_31_0 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s +{ + uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST)) + +/* + * Register : Port Sum of Weight Register[2/4] - mpweight_1_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Static Weights[49:32] + * [31:18] | RW | Unknown | Port Sum of Weights[13:0] + * + */ +/* + * Field : Port Static Weights[49:32] - staticweight_49_32 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff) + +/* + * Field : Port Sum of Weights[13:0] - sumofweights_13_0 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000 +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s +{ + uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */ + uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST)) + +/* + * Register : Port Sum of Weight Register[3/4] - mpweight_2_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [31:0] | RW | Unknown | Port Sum of Weights[45:14] + * + */ +/* + * Field : Port Sum of Weights[45:14] - sumofweights_45_14 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s +{ + uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST)) + +/* + * Register : Port Sum of Weight Register[4/4] - mpweight_3_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Sum of Weights[63:46] + * [31:18] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Sum of Weights[63:46] - sumofweights_63_46 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s +{ + uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */ + uint32_t : 14; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL_MPWT. + */ +struct ALT_SDR_CTL_MPWT_s +{ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +struct ALT_SDR_CTL_MPWT_raw_s +{ + volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL. + */ +struct ALT_SDR_CTL_s +{ + volatile ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */ +struct ALT_SDR_CTL_raw_s +{ + volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR. + */ +struct ALT_SDR_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR. */ +typedef volatile struct ALT_SDR_s ALT_SDR_t; +/* The struct declaration for the raw register contents of register group ALT_SDR. */ +struct ALT_SDR_raw_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR. */ +typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SDR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h new file mode 100644 index 0000000000..fce6d6e11e --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h @@ -0,0 +1,24810 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SYSMGR */ + +#ifndef __ALTERA_ALT_SYSMGR_H__ +#define __ALTERA_ALT_SYSMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : System Manager Module - ALT_SYSMGR + * System Manager Module + * + * Registers in the System Manager module + * + */ +/* + * Register : Silicon ID1 Register - siliconid1 + * + * Specifies Silicon ID and revision number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | R | 0x1 | Silicon Revision + * [31:16] | R | 0x0 | Silicon ID + * + */ +/* + * Field : Silicon Revision - rev + * + * Silicon revision number. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV + * + * Revision 1 + */ +#define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_MSB 15 +/* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_RESET 0x1 +/* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */ +#define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Silicon ID - id + * + * Silicon ID + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID + * + * HPS in Cyclone V and Arria V SoC FPGA devices + */ +#define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff +/* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */ +#define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID1. + */ +struct ALT_SYSMGR_SILICONID1_s +{ + const uint32_t rev : 16; /* Silicon Revision */ + const uint32_t id : 16; /* Silicon ID */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID1. */ +typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID1_OFST 0x0 + +/* + * Register : Silicon ID2 Register - siliconid2 + * + * Reserved for future use. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Reserved + * + */ +/* + * Field : Reserved - rsv + * + * Reserved for future use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */ +#define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID2. + */ +struct ALT_SYSMGR_SILICONID2_s +{ + const uint32_t rsv : 32; /* Reserved */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID2. */ +typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID2_OFST 0x4 + +/* + * Register : L4 Watchdog Debug Register - wddbg + * + * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These + * control registers are used to drive the pause input signal of the L4 watchdogs. + * Note that the watchdogs built into the MPU automatically are paused when their + * associated CPU enters debug mode. Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x3 | Debug Mode + * [3:2] | RW | 0x3 | Debug Mode + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Mode - mode_0 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Mode - mode_1 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_WDDBG. + */ +struct ALT_SYSMGR_WDDBG_s +{ + uint32_t mode_0 : 2; /* Debug Mode */ + uint32_t mode_1 : 2; /* Debug Mode */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_WDDBG. */ +typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */ +#define ALT_SYSMGR_WDDBG_OFST 0x10 + +/* + * Register : Boot Info Register - bootinfo + * + * Provides access to boot configuration information. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [2:0] | R | Unknown | Boot Select + * [4:3] | R | Unknown | Clock Select + * [7:5] | R | Unknown | HPS Pin Boot Select + * [9:8] | R | Unknown | HPS Pin Clock Select + * [31:10] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : Boot Select - bsel + * + * The boot select field specifies the boot source. It is read by the Boot ROM code + * on a cold or warm reset to determine the boot source. + * + * The HPS BSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------------- + * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved + * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * Reserved + */ +#define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * FPGA (HPS2FPGA Bridge) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC External Transceiver (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC Internal Transceiver (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_BSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Clock Select - csel + * + * The clock select field specifies clock information for booting. The clock select + * encoding is a function of the CSEL value. The clock select field is read by the + * Boot ROM code on a cold or warm reset when booting from a flash device to get + * information about how to setup the HPS clocking to boot from the specified clock + * device. + * + * The encoding of the clock select field is specified by the enum associated with + * this field. + * + * The HPS CSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk divided by 25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2, + * : | | SD/MMC device clock is osc1_clk divided by 1, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 20/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1, + * : | | SD/MMC device clock is osc1_clk divided by 2, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 10/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 5/25 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk divided by 25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk + * divided by 1, NAND device operation is osc1_clk multiplied by 20/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk + * divided by 2, NAND device operation is osc1_clk multiplied by 10/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk multiplied by 5/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_MSB 4 +/* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018 +/* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7 +/* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_CSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3) +/* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018) + +/* + * Field : HPS Pin Boot Select - pinbsel + * + * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_MSB 7 +/* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f +/* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5) +/* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0) + +/* + * Field : HPS Pin Clock Select - pincsel + * + * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_MSB 9 +/* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_BOOT. + */ +struct ALT_SYSMGR_BOOT_s +{ + const uint32_t bsel : 3; /* Boot Select */ + const uint32_t csel : 2; /* Clock Select */ + const uint32_t pinbsel : 3; /* HPS Pin Boot Select */ + const uint32_t pincsel : 2; /* HPS Pin Clock Select */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_BOOT. */ +typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */ +#define ALT_SYSMGR_BOOT_OFST 0x14 + +/* + * Register : HPS Info Register - hpsinfo + * + * Provides information about the HPS capabilities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [0] | R | Unknown | Dual Core + * [1] | R | Unknown | CAN + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dual Core - dualcore + * + * Indicates if CPU1 is available in MPU or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available). + * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Not dual-core (only CPU0 available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Is dual-core (CPU0 and CPU1 both available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0 +/* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN - can + * + * Indicates if CAN0 and CAN1 controllers are available or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------- + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available. + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are not available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_MSB 1 +/* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */ +#define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_HPSINFO. + */ +struct ALT_SYSMGR_HPSINFO_s +{ + const uint32_t dualcore : 1; /* Dual Core */ + const uint32_t can : 1; /* CAN */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_HPSINFO. */ +typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */ +#define ALT_SYSMGR_HPSINFO_OFST 0x18 + +/* + * Register : Parity Fail Injection Register - parityinj + * + * Inject parity failures into the parity-protected RAMs in the MPU. Allows + * software to test the parity failure interrupt handler. The field array index + * corresponds to the CPU index. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------------- + * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_0 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_1 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_0 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_1 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_0 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_1 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PARITYINJ. + */ +struct ALT_SYSMGR_PARITYINJ_s +{ + uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */ +typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */ +#define ALT_SYSMGR_PARITYINJ_OFST 0x1c + +/* + * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF + * FPGA Interface Group + * + * Registers used to enable/disable interfaces between the FPGA and HPS. Required + * for either of the following situations:[list][*]Interfaces that cannot be + * disabled by putting an HPS module associated with the interface into + * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals + * might interfere with the normal operation of the module.[/list]. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Global Disable Register - gbl + * + * Used to disable all interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x1 | Global Interface + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Global Interface - intf + * + * Used to disable all interfaces between the FPGA and HPS. Software must ensure + * that all interfaces between the FPGA and HPS are inactive before disabling them. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are + * : | | disabled. + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all + * : | | disabled. Interfaces can be indivdually disabled + * : | | by putting the HPS module associated with the + * : | | interface in reset using registers in the Reset + * : | | Manager or by using registers in this register + * : | | group of the System Manager for interfaces + * : | | without an associated module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * All interfaces between FPGA and HPS are disabled. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * Interfaces between FPGA and HPS are not all disabled. Interfaces can be + * indivdually disabled by putting the HPS module associated with the interface in + * reset using registers in the Reset Manager or by using registers in this + * register group of the System Manager for interfaces without an associated + * module. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL. + */ +struct ALT_SYSMGR_FPGAINTF_GBL_s +{ + uint32_t intf : 1; /* Global Interface */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0 + +/* + * Register : Individual Disable Register - indiv + * + * Used to disable individual interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Reset Request Interface + * [1] | RW | 0x1 | JTAG Enable Interface + * [2] | RW | 0x1 | CONFIG_IO Interface + * [3] | RW | 0x1 | Boundary-Scan Interface + * [4] | RW | 0x1 | Trace Interface + * [5] | ??? | 0x1 | *UNDEFINED* + * [6] | RW | 0x1 | STM Event Interface + * [7] | RW | 0x1 | Cross Trigger Interface (CTI) + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Reset Request Interface - rstreqintf + * + * Used to disable the reset request interface. This interface allows logic in the + * FPGA fabric to request HPS resets. This field disables the following reset + * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - + * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of + * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list] + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in + * : | | the FPGA fabric cannot reset the HPS. + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the + * : | | FPGA fabric can reset the HPS. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the + * HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : JTAG Enable Interface - jtagenintf + * + * Used to disable the JTAG enable interface. This interface allows logic in the + * FPGA fabric to disable the HPS JTAG operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the + * : | | FPGA fabric cannot disable the HPS JTAG. + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the + * : | | FPGA fabric can disable the HPS JTAG. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the + * HPS JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS + * JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CONFIG_IO Interface - configiointf + * + * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP + * controller to execute the CONFIG_IO instruction and configure all device I/Os + * (FPGA and HPS). This is typically done before executing boundary-scan + * instructions. The CONFIG_IO interface must be enabled before attempting to send + * the CONFIG_IO instruction to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of + * : | | the CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is unsupported and produces undefined + * : | | results. + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the + * : | | CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Boundary-Scan Interface - bscanintf + * + * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG + * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, + * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting + * to send the boundary-scan instructions to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution + * : | | of boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is unsupported and produces + * : | | undefined results. + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of + * : | | the boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is disabled. Execution of boundary-scan instructions in + * the FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is enabled. Execution of the boundary-scan instructions + * in the FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Trace Interface - traceintf + * + * Used to disable the trace interface. This interface allows the HPS debug logic + * to send trace data to logic in the FPGA fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic + * : | | cannot send trace data to the FPGA fabric. + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in + * : | | the HPS debug logic must be programmmed to + * : | | actually send trace data to the FPGA fabric. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA + * fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is enabled. Other registers in the HPS debug logic must be + * programmmed to actually send trace data to the FPGA fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : STM Event Interface - stmeventintf + * + * Used to disable the STM event interface. This interface allows logic in the FPGA + * fabric to trigger events to the STM debug module in the HPS. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the + * : | | FPGA fabric cannot trigger STM events. + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the + * : | | FPGA fabric can trigger STM events. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is enabled. Logic in the FPGA fabric can trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Cross Trigger Interface (CTI) - crosstrigintf + * + * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note + * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA + * Fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:---------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers. + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric cannot send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric can send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV. + */ +struct ALT_SYSMGR_FPGAINTF_INDIV_s +{ + uint32_t rstreqintf : 1; /* Reset Request Interface */ + uint32_t jtagenintf : 1; /* JTAG Enable Interface */ + uint32_t configiointf : 1; /* CONFIG_IO Interface */ + uint32_t bscanintf : 1; /* Boundary-Scan Interface */ + uint32_t traceintf : 1; /* Trace Interface */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t stmeventintf : 1; /* STM Event Interface */ + uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4 + +/* + * Register : Module Disable Register - module + * + * Used to disable signals from the FPGA fabric to individual HPS modules. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | EMAC Module + * [3] | RW | 0x0 | EMAC Module + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC Module - emac_0 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC Module - emac_1 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE. + */ +struct ALT_SYSMGR_FPGAINTF_MODULE_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t emac_0 : 1; /* EMAC Module */ + uint32_t emac_1 : 1; /* EMAC Module */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FPGAINTF. + */ +struct ALT_SYSMGR_FPGAINTF_s +{ + volatile ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +struct ALT_SYSMGR_FPGAINTF_raw_s +{ + volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR + * Scan Manager Group + * + * Registers related to the Scan Manager that aren't located inside the Scan + * Manager itself. + * + */ +/* + * Register : Scan Manager Control Register - ctrl + * + * Controls behaviors of Scan Manager not controlled by registers in the Scan + * Manager itself. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | FPGA JTAG Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA JTAG Enable - fpgajtagen + * + * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA. + * + * Only reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * FPGA JTAG pins drive JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * Scan Manager drives JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0 +/* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0 +/* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL. + */ +struct ALT_SYSMGR_SCANMGR_CTL_s +{ + uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SCANMGR. + */ +struct ALT_SYSMGR_SCANMGR_s +{ + volatile ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +struct ALT_SYSMGR_SCANMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL + * Freeze Control Group + * + * Registers used to generate HPS IO freeze signals. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : VIO Control Register - vioctrl + * + * Used to drive freeze signals to HPS VIO banks. + * + * The register array index corresponds to the freeze channel. + * + * Freeze channel 0 provides freeze signals to VIO bank 0 and 1. + * + * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze + * signals when SRC.VIO1 is set to SW. + * + * Freeze channel 2 provides freeze signals to VIO bank 4. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_VIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 + +/* + * Register : HIO Control Register - hioctrl + * + * Used to drive freeze signals to HPS HIO bank (DDR SDRAM). + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [5] | RW | 0x1 | DLL Reset + * [6] | RW | 0x1 | OCT Reset + * [7] | RW | 0x1 | IO and DQS Reset + * [8] | RW | 0x0 | OCT Calibration and Configuration Enable + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLL Reset - dllrst + * + * Controls DLL (Delay-Locked Loop) reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating. + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL + * : | | clock. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * No reset or clock gating. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * Resets registers in the DLL and gates off DLL clock. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OCT Reset - octrst + * + * Controls OCT reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * Resets registers in the OCT. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IO and DQS Reset - regrst + * + * Controls IO and DQS reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * Resets all IO registers and DQS registers. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart + * + * Controls OCT calibration and OCT IO configuration enable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe + * : | | value) in OCT calibration block. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables + * : | | IO configuration in OCT calibration block. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Disables IO configuration (forced to a safe value) in OCT calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Starts OCT calibration state machine and enables IO configuration in OCT + * calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_HIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t dllrst : 1; /* DLL Reset */ + uint32_t octrst : 1; /* OCT Reset */ + uint32_t regrst : 1; /* IO and DQS Reset */ + uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 + +/* + * Register : Source Register - src + * + * Contains register field to choose between software state machine (vioctrl array + * index [1] register) or hardware state machine in the Freeze Controller as the + * freeze signal source for VIO channel 1. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | RW | 0x0 | VIO1 Freeze Signal Source + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO1 Freeze Signal Source - vio1 + * + * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software + * : | | writing to the VIOCTRL[1] register. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active but don't effect the VIO1 freeze signals. + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware + * : | | state machine in the Freeze Controller. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active and effect the VIO1 freeze signals. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. + * The VIO1-related fields in the hwctrl register are active but don't effect the + * VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by the hardware state machine in the Freeze + * Controller. The VIO1-related fields in the hwctrl register are active and effect + * the VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC. + */ +struct ALT_SYSMGR_FRZCTL_SRC_s +{ + uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14 + +/* + * Register : Hardware Control Register - hwctrl + * + * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) + * and monitor for completeness and the current state. + * + * These fields interact with the hardware state machine in the Freeze Controller. + * These fields can be accessed independent of the value of SRC1.VIO1 although they + * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup + * to have the hardware state machine be the freeze signal source. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request + * [2:1] | R | 0x2 | VIO channel 1 State + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO channel 1 Freeze/Thaw request - vio1req + * + * Requests hardware state machine to generate freeze signal sequence to transition + * between frozen and thawed states. + * + * If this field is read by software, it contains the value previously written by + * software (i.e. this field is not written by hardware). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a thaw (unfreeze) operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a freeze operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : VIO channel 1 State - vio1state + * + * Software reads this field to determine the current frozen/thawed state of the + * VIO channel 1 or to determine when a freeze/thaw request is made by writing the + * corresponding *REQ field in this register has completed. + * + * Reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os + * : | | must be configured by the Scan Manager before + * : | | entering this state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored. + * : | | Instead, I/Os are in tri-state mode with a weak + * : | | pull-up. Scan Manager can be used to configure + * : | | the I/Os while they are frozen. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from thawed state to frozen state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan + * Manager before entering this state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode + * with a weak pull-up. Scan Manager can be used to configure the I/Os while they + * are frozen. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from frozen state to thawed state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL. + */ +struct ALT_SYSMGR_FRZCTL_HWCTL_s +{ + uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */ + const uint32_t vio1state : 2; /* VIO channel 1 State */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FRZCTL. + */ +struct ALT_SYSMGR_FRZCTL_s +{ + volatile ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +struct ALT_SYSMGR_FRZCTL_raw_s +{ + volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC Group - ALT_SYSMGR_EMAC + * EMAC Group + * + * External control registers for the EMACs + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the EMACs. All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [1:0] | RW | 0x2 | PHY Interface Select + * [3:2] | RW | 0x2 | PHY Interface Select + * [4] | RW | 0x0 | PTP Clock Select + * [5] | RW | 0x0 | PTP Clock Select + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Interface Select - physel_0 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : PHY Interface Select - physel_1 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PTP Clock Select - ptpclksel_0 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PTP Clock Select - ptpclksel_1 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_CTL. + */ +struct ALT_SYSMGR_EMAC_CTL_s +{ + uint32_t physel_0 : 2; /* PHY Interface Select */ + uint32_t physel_1 : 2; /* PHY Interface Select */ + uint32_t ptpclksel_0 : 1; /* PTP Clock Select */ + uint32_t ptpclksel_1 : 1; /* PTP Clock Select */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */ +typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_CTL_OFST 0x0 + +/* + * Register : EMAC L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | EMAC ARCACHE + * [7:4] | RW | 0x0 | EMAC ARCACHE + * [11:8] | RW | 0x0 | EMAC AWCACHE + * [15:12] | RW | 0x0 | EMAC AWCACHE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC ARCACHE - arcache_0 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : EMAC ARCACHE - arcache_1 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0) + +/* + * Field : EMAC AWCACHE - awcache_0 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00) + +/* + * Field : EMAC AWCACHE - awcache_1 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_L3MST. + */ +struct ALT_SYSMGR_EMAC_L3MST_s +{ + uint32_t arcache_0 : 4; /* EMAC ARCACHE */ + uint32_t arcache_1 : 4; /* EMAC ARCACHE */ + uint32_t awcache_0 : 4; /* EMAC AWCACHE */ + uint32_t awcache_1 : 4; /* EMAC AWCACHE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */ +typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_EMAC. + */ +struct ALT_SYSMGR_EMAC_s +{ + volatile ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +struct ALT_SYSMGR_EMAC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA Controller Group - ALT_SYSMGR_DMA + * DMA Controller Group + * + * Registers used by the DMA Controller to enable secured system support and select + * DMA channels. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the DMA Controller. All fields are reset by a cold or warm + * reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Channel Select + * [1] | RW | 0x0 | Channel Select + * [2] | RW | 0x0 | Channel Select + * [3] | RW | 0x0 | Channel Select + * [4] | RW | 0x0 | Manager Thread Security + * [12:5] | RW | 0x0 | IRQ Security + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Select - chansel_0 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Select - chansel_1 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Channel Select - chansel_2 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Channel Select - chansel_3 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Manager Thread Security - mgrnonsecure + * + * Specifies the security state of the DMA manager thread. + * + * 0 = assigns DMA manager to the Secure state. + * + * 1 = assigns DMA manager to the Non-secure state. + * + * Sampled by the DMA controller when it exits from reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IRQ Security - irqnonsecure + * + * Specifies the security state of an event-interrupt resource. + * + * If bit index [x] is 0, the DMAC assigns event or irq[x] to the Secure state. + * + * If bit index [x] is 1, the DMAC assigns event or irq[x] to the Non-secure + * state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f +/* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5) +/* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_CTL. + */ +struct ALT_SYSMGR_DMA_CTL_s +{ + uint32_t chansel_0 : 1; /* Channel Select */ + uint32_t chansel_1 : 1; /* Channel Select */ + uint32_t chansel_2 : 1; /* Channel Select */ + uint32_t chansel_3 : 1; /* Channel Select */ + uint32_t mgrnonsecure : 1; /* Manager Thread Security */ + uint32_t irqnonsecure : 8; /* IRQ Security */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */ +typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_CTL_OFST 0x0 + +/* + * Register : Peripheral Security Register - persecurity + * + * Controls the security state of a peripheral request interface. Sampled by the + * DMA controller when it exits from reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [31:0] | RW | 0x0 | Peripheral Non-Secure + * + */ +/* + * Field : Peripheral Non-Secure - nonsecure + * + * If bit index [x] is 0, the DMA controller assigns peripheral request interface x + * to the Secure state. + * + * If bit index [x] is 1, the DMA controller assigns peripheral request interface x + * to the Non-secure state. + * + * Reset by a cold or warm reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31 +/* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY. + */ +struct ALT_SYSMGR_DMA_PERSECURITY_s +{ + uint32_t nonsecure : 32; /* Peripheral Non-Secure */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */ +typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_DMA. + */ +struct ALT_SYSMGR_DMA_s +{ + volatile ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +struct ALT_SYSMGR_DMA_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW + * Preloader (initial software) Group + * + * Registers used by preloader code and the OS. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Preloader to OS Handoff Information - handoff + * + * These registers are used to store handoff infomation between the preloader and + * the OS. These 8 registers can be used to store any information. The contents of + * these registers have no impact on the state of the HPS hardware. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Preloader Handoff Information + * + */ +/* + * Field : Preloader Handoff Information - value + * + * Preloader Handoff Information. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF. + */ +struct ALT_SYSMGR_ISW_HANDOFF_s +{ + uint32_t value : 32; /* Preloader Handoff Information */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */ +typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */ +#define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ISW. + */ +struct ALT_SYSMGR_ISW_s +{ + volatile ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +struct ALT_SYSMGR_ISW_raw_s +{ + volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE + * Boot ROM Code Register Group + * + * Registers used by the Boot ROM code. All fields are only reset by a cold reset + * (ignore warm reset). + * + */ +/* + * Register : Control Register - ctrl + * + * Contains information used to control Boot ROM code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins + * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux + * + * Specifies whether the Boot ROM code configures the pin mux for boot pins after a + * warm reset. Note that the Boot ROM code always configures the pin mux for boot + * pins after a cold reset. After the Boot ROM code configures the pin mux for boot + * pins, it always disables this field. It is up to user software to enable this + * field if it wants a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for + * : | | boot pins after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot + * : | | pins after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will not configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio + * + * Specifies whether the Boot ROM code configures the IOs used by boot after a warm + * reset. Note that the Boot ROM code always configures the IOs used by boot after + * a cold reset. After the Boot ROM code configures the IOs used by boot, it always + * disables this field. It is up to user software to enable this field if it wants + * a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by + * : | | boot after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot + * : | | after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will not configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL. + */ +struct ALT_SYSMGR_ROMCODE_CTL_s +{ + uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */ + uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0 + +/* + * Register : CPU1 Start Address Register - cpu1startaddr + * + * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset + * exception address (the typical case), the Boot ROM reset handler code reads the + * address stored in this register and jumps it to hand off execution to user + * software. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Address + * + */ +/* + * Field : Address - value + * + * Address for CPU1 to start executing at after coming out of reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. + */ +struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s +{ + uint32_t value : 32; /* Address */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4 + +/* + * Register : Preloader (initial software) State Register - initswstate + * + * The preloader software (loaded by the Boot ROM) writes the magic value + * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Value + * + */ +/* + * Field : Value - value + * + * Written with magic value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:-----------|:------------ + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 | + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 | + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s +{ + uint32_t value : 32; /* Value */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8 + +/* + * Register : Preloader (initial software) Last Image Loaded Register - initswlastld + * + * Contains the index of the last preloader software image loaded by the Boot ROM + * from the boot device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x0 | Index + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Index - index + * + * Index of last image loaded. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. + */ +struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s +{ + uint32_t index : 2; /* Index */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc + +/* + * Register : Boot ROM Software State Register - bootromswstate + * + * 32-bits general purpose register used by the Boot ROM code. Actual usage is + * defined in the Boot ROM source code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Boot ROM Software State + * + */ +/* + * Field : Boot ROM Software State - value + * + * Reserved for Boot ROM use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s +{ + uint32_t value : 32; /* Boot ROM Software State */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10 + +/* + * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM + * Warm Boot from On-Chip RAM Group + * + * Registers used by the Boot ROM code to support booting from the On-chip RAM on a + * warm reset. All these registers must be written by user software before a warm + * reset occurs to make use of this feature. + * + */ +/* + * Register : Enable Register - enable + * + * Enables or disables the warm reset from On-chip RAM feature. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM + * + */ +/* + * Field : Warm Reset from On-chip RAM - magic + * + * Controls whether Boot ROM will attempt to boot from the contents of the On-chip + * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not + * configure boot IOs, the pin mux, or clocks. + * + * Note that the enable value is a 32-bit magic value (provided by the enum). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:-----------|:------------------------------------------------ + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On- + * : | | chip RAM on a warm reset + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip + * : | | RAM on a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s +{ + uint32_t magic : 32; /* Warm Reset from On-chip RAM */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST)) + +/* + * Register : Data Start Register - datastart + * + * Offset into On-chip RAM of the start of the region for CRC validation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------ + * [15:0] | RW | 0x0 | Data Start Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Start Offset - offset + * + * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM + * region for the warm boot CRC validation. The offset must be an integer multiple + * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to + * 0xFFFF and clear the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s +{ + uint32_t offset : 16; /* Data Start Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST)) + +/* + * Register : Length Register - length + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Size - size + * + * Contains the length (in bytes) of the region in the On-chip RAM for the warm + * boot CRC validation. + * + * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to + * avoid overhead caused by CRC validation. + * + * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot + * ROM won't boot from the On-chip RAM. + * + * The length must be an integer multiple of 4. + * + * The Boot ROM code will clear the top 16 bits and the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s +{ + uint32_t size : 16; /* Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST)) + +/* + * Register : Execution Register - execution + * + * Offset into On-chip RAM to enter to on a warm boot. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | RW | 0x0 | Execution Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Execution Offset - offset + * + * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if + * the CRC validation succeeds. + * + * The Boot ROM code will set the top 16 bits to 0xFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s +{ + uint32_t offset : 16; /* Execution Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST)) + +/* + * Register : Expected CRC Register - crc + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------- + * [31:0] | RW | 0xe763552a | Expected CRC + * + */ +/* + * Field : Expected CRC - expected + * + * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code + * calculates the actual CRC for all bytes in the region specified by the DATA + * START an LENGTH registers. The contents of the EXECUTION register (after it has + * been read and modified by the Boot ROM code) is also included in the CRC + * calculation. The contents of the EXECUTION register is added to the CRC + * accumulator a byte at a time starting with the least significant byte. If the + * actual CRC doesn't match the expected CRC value in this register, the Boot ROM + * won't boot from the On-chip RAM. + * + * The CRC is a standard CRC32 with the polynomial: + * + * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + + * x^2 + x + 1 + * + * There is no reflection of the bits and the initial value of the remainder is + * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s +{ + uint32_t expected : 32; /* Expected CRC */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_s +{ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s +{ + volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE. + */ +struct ALT_SYSMGR_ROMCODE_s +{ + volatile ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +struct ALT_SYSMGR_ROMCODE_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW + * Boot ROM Hardware Register Group + * + * Registers used by the Boot ROM hardware, not the code within it. + * + */ +/* + * Register : Boot ROM Hardware Control Register - ctrl + * + * Controls behavior of Boot ROM hardware. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Wait State + * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Wait State - waitstate + * + * Controls the number of wait states applied to the Boot ROM's read operation. + * + * This field is cleared on a cold reset and optionally updated by hardware upon + * deassertion of warm reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's + * : | | read operation. + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's + * : | | read operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * No wait states are applied to the Boom ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * A single wait state is applied to the Boot ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable Safe Mode Warm Reset Update - ensfmdwru + * + * Controls whether the wait state bit is updated upon deassertion of warm reset. + * + * This field is set on a cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion + * : | | of warm reset. + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of + * : | | warm reset. It's value is updated based on the + * : | | control bit from clock manager which specifies + * : | | whether clock manager will be in safe mode or + * : | | not after warm reset. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is not updated upon deassertion of warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is updated upon deassertion of warm reset. + * + * It's value is updated based on the control bit from clock manager which + * specifies whether clock manager will be in safe mode or not after warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMHW_CTL. + */ +struct ALT_SYSMGR_ROMHW_CTL_s +{ + uint32_t waitstate : 1; /* Wait State */ + uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMHW. + */ +struct ALT_SYSMGR_ROMHW_s +{ + volatile ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +struct ALT_SYSMGR_ROMHW_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC + * SDMMC Controller Group + * + * Registers related to SDMMC Controller which aren't located inside the SDMMC + * itself. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the SDMMC Controller. All fields are reset by a cold or warm + * reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select + * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select + * [6] | RW | 0x0 | Feedback Clock Select + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Drive Clock Phase Shift Select - drvsel + * + * Select which phase shift of the clock for cclk_in_drv. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Sample Clock Phase Shift Select - smplsel + * + * Select which phase shift of the clock for cclk_in_sample. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : Feedback Clock Select - fbclksel + * + * Select which fb_clk to be used as cclk_in_sample. + * + * If 0, cclk_in_sample is driven by internal phase shifted cclk_in. + * + * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided + * internally on cclk_in_sample. + * + * Note: Using the feedback clock (setting this bit to 1) is not a supported use + * model. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_CTL. + */ +struct ALT_SYSMGR_SDMMC_CTL_s +{ + uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */ + uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */ + uint32_t fbclksel : 1; /* Feedback Clock Select */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */ +typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_CTL_OFST 0x0 + +/* + * Register : SD/MMC L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode + * [1] | RW | 0x1 | SD/MMC HPROT Privileged + * [2] | RW | 0x0 | SD/MMC HPROT Bufferable + * [3] | RW | 0x0 | SD/MMC HPROT Cacheable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SD/MMC HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the SD/MMC module. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SD/MMC HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the SD/MMC module are privileged. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SD/MMC HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the SD/MMC module are bufferable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SD/MMC HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the SD/MMC module are cacheable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST. + */ +struct ALT_SYSMGR_SDMMC_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */ +typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SDMMC. + */ +struct ALT_SYSMGR_SDMMC_s +{ + volatile ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +struct ALT_SYSMGR_SDMMC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND + * NAND Flash Controller Register Group + * + * Registers related to NAND Flash Controller which aren't located in the NAND + * Flash Controller itself. + * + */ +/* + * Register : Bootstrap Control Register - bootstrap + * + * Bootstrap fields sampled by NAND Flash Controller when released from reset. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Bootstrap Inhibit Initialization + * [1] | RW | 0x0 | Bootstrap 512 Byte Device + * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0 + * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bootstrap Inhibit Initialization - noinit + * + * If 1, inhibits NAND Flash Controller from performing initialization when coming + * out of reset. Instead, software must program all registers pertaining to device + * parameters like page size, width, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Bootstrap 512 Byte Device - page512 + * + * If 1, NAND device has a 512 byte page size. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0 + * + * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND + * device as part of the initialization procedure. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Bootstrap Two Row Address Cycles - tworowaddr + * + * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row + * address cycles. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. + */ +struct ALT_SYSMGR_NAND_BOOTSTRAP_s +{ + uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */ + uint32_t page512 : 1; /* Bootstrap 512 Byte Device */ + uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */ + uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */ +typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0 + +/* + * Register : NAND L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | NAND ARCACHE + * [7:4] | RW | 0x0 | NAND AWCACHE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND ARCACHE - arcache_0 + * + * Specifies the value of the module ARCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : NAND AWCACHE - awcache_0 + * + * Specifies the value of the module AWCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_L3MST. + */ +struct ALT_SYSMGR_NAND_L3MST_s +{ + uint32_t arcache_0 : 4; /* NAND ARCACHE */ + uint32_t awcache_0 : 4; /* NAND AWCACHE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */ +typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_NAND. + */ +struct ALT_SYSMGR_NAND_s +{ + volatile ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +struct ALT_SYSMGR_NAND_raw_s +{ + volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB Controller Group - ALT_SYSMGR_USB + * USB Controller Group + * + * Registers related to USB Controllers which aren't located inside the USB + * controllers themselves. + * + */ +/* + * Register : USB L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | USB HPROT Data/Opcode + * [1] | RW | 0x1 | USB HPROT Data/Opcode + * [2] | RW | 0x1 | USB HPROT Privileged + * [3] | RW | 0x1 | USB HPROT Privileged + * [4] | RW | 0x0 | USB HPROT Bufferable + * [5] | RW | 0x0 | USB HPROT Bufferable + * [6] | RW | 0x0 | USB HPROT Cacheable + * [7] | RW | 0x0 | USB HPROT Cacheable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB HPROT Data/Opcode - hprotdata_1 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB HPROT Privileged - hprotpriv_1 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : USB HPROT Bufferable - hprotbuff_1 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : USB HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : USB HPROT Cacheable - hprotcache_1 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_USB_L3MST. + */ +struct ALT_SYSMGR_USB_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */ + uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */ + uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */ + uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */ +typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_USB_L3MST_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_USB. + */ +struct ALT_SYSMGR_USB_s +{ + volatile ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +struct ALT_SYSMGR_USB_raw_s +{ + volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC + * ECC Management Register Group + * + * ECC error status and control for all ECC-protected HPS RAM blocks. + * + */ +/* + * Register : L2 Data RAM ECC Enable Register - l2 + * + * This register is used to enable ECC on the L2 Data RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------- + * [0] | RW | 0x0 | L2 Data RAM ECC Enable + * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L2 Data RAM ECC Enable - en + * + * Enable ECC for L2 Data RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */ +#define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L2 Data RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * L2 Data RAM. This only injects one error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_L2. + */ +struct ALT_SYSMGR_ECC_L2_s +{ + uint32_t en : 1; /* L2 Data RAM ECC Enable */ + uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_L2. */ +typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_L2_OFST 0x0 + +/* + * Register : On-chip RAM ECC Enable Register - ocram + * + * This register is used to enable ECC on the On-chip RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------- + * [0] | RW | 0x0 | On-chip RAM ECC Enable + * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM ECC Enable - en + * + * Enable ECC for On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * On-chip RAM. This only injects one error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : On-chip RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the On-chip RAM. This only injects one double bit error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : On-chip RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for On-chip RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in On-chip + * RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for On-chip RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_OCRAM. + */ +struct ALT_SYSMGR_ECC_OCRAM_s +{ + uint32_t en : 1; /* On-chip RAM ECC Enable */ + uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */ +typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_OCRAM_OFST 0x4 + +/* + * Register : USB0 RAM ECC Enable Register - usb0 + * + * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB0 RAM ECC Enable + * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 RAM ECC Enable - en + * + * Enable ECC for USB0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB0 RAM. This only injects one error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB0 RAM. This only injects one double bit error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB0. + */ +struct ALT_SYSMGR_ECC_USB0_s +{ + uint32_t en : 1; /* USB0 RAM ECC Enable */ + uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */ +typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB0_OFST 0x8 + +/* + * Register : USB1 RAM ECC Enable Register - usb1 + * + * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB1 RAM ECC Enable + * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 RAM ECC Enable - en + * + * Enable ECC for USB1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB1 RAM. This only injects one error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB1 RAM. This only injects one double bit error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB1. + */ +struct ALT_SYSMGR_ECC_USB1_s +{ + uint32_t en : 1; /* USB1 RAM ECC Enable */ + uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */ +typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB1_OFST 0xc + +/* + * Register : EMAC0 RAM ECC Enable Register - emac0 + * + * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC0 RAM ECC Enable + * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 RAM ECC Enable - en + * + * Enable ECC for EMAC0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC0. + */ +struct ALT_SYSMGR_ECC_EMAC0_s +{ + uint32_t en : 1; /* EMAC0 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10 + +/* + * Register : EMAC1 RAM ECC Enable Register - emac1 + * + * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC1 RAM ECC Enable + * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC1 RAM ECC Enable - en + * + * Enable ECC for EMAC1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC1. + */ +struct ALT_SYSMGR_ECC_EMAC1_s +{ + uint32_t en : 1; /* EMAC1 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC1_OFST 0x14 + +/* + * Register : DMA RAM ECC Enable Register - dma + * + * This register is used to enable ECC on the DMA RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------------- + * [0] | RW | 0x0 | DMA RAM ECC Enable + * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA RAM ECC Enable - en + * + * Enable ECC for DMA RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DMA RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * DMA RAM. This only injects one error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the DMA RAM. This only injects one double bit error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for DMA RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in DMA RAM. Software + * needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_DMA. + */ +struct ALT_SYSMGR_ECC_DMA_s +{ + uint32_t en : 1; /* DMA RAM ECC Enable */ + uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */ +typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_DMA_OFST 0x18 + +/* + * Register : CAN0 RAM ECC Enable Register - can0 + * + * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN0 RAM ECC Enable + * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN0 RAM ECC Enable - en + * + * Enable ECC for CAN0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN0 RAM. This only injects one error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN0. + */ +struct ALT_SYSMGR_ECC_CAN0_s +{ + uint32_t en : 1; /* CAN0 RAM ECC Enable */ + uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN0_OFST 0x1c + +/* + * Register : CAN1 RAM ECC Enable Register - can1 + * + * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN1 RAM ECC Enable + * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN1 RAM ECC Enable - en + * + * Enable ECC for CAN1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN1 RAM. This only injects one error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN1. + */ +struct ALT_SYSMGR_ECC_CAN1_s +{ + uint32_t en : 1; /* CAN1 RAM ECC Enable */ + uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN1_OFST 0x20 + +/* + * Register : NAND RAM ECC Enable Register - nand + * + * This register is used to enable ECC on the NAND RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------------------------------------- + * [0] | RW | 0x0 | NAND RAM ECC Enable + * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error + * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error + * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status + * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status + * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status + * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status + * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND RAM ECC Enable - en + * + * Enable ECC for NAND RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND + * ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, + * correctable error. It is set by hardware when single, correctable error occurs + * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear + * the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_NAND. + */ +struct ALT_SYSMGR_ECC_NAND_s +{ + uint32_t en : 1; /* NAND RAM ECC Enable */ + uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */ + uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */ + uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */ + uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */ + uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */ + uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */ + uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */ + uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */ +typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_NAND_OFST 0x24 + +/* + * Register : QSPI RAM ECC Enable Register - qspi + * + * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | QSPI RAM ECC Enable + * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI RAM ECC Enable - en + * + * Enable ECC for QSPI RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : QSPI RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * QSPI RAM. This only injects one error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the QSPI RAM. This only injects one double bit error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : QSPI RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in QSPI RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_QSPI. + */ +struct ALT_SYSMGR_ECC_QSPI_s +{ + uint32_t en : 1; /* QSPI RAM ECC Enable */ + uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */ +typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_QSPI_OFST 0x28 + +/* + * Register : SDMMC RAM ECC Enable Register - sdmmc + * + * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected + * into the write path using bits in this register. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | SDMMC RAM ECC Enable + * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A + * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A + * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B + * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B + * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC RAM ECC Enable - en + * + * Enable ECC for SDMMC RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC + * RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC + * RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * A RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * B RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_SDMMC. + */ +struct ALT_SYSMGR_ECC_SDMMC_s +{ + uint32_t en : 1; /* SDMMC RAM ECC Enable */ + uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */ + uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */ + uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */ + uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */ + uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */ + uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */ + uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */ + uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */ +typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ECC. + */ +struct ALT_SYSMGR_ECC_s +{ + volatile ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +struct ALT_SYSMGR_ECC_raw_s +{ + volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX + * Pin Mux Control Group + * + * Controls Pin Mux selections + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + */ +/* + * Register : emac0_tx_clk Mux Selection Register - EMACIO0 + * + * This register is used to control the peripherals connected to emac0_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 0. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0. + */ +struct ALT_SYSMGR_PINMUX_EMACIO0_s +{ + uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0 + +/* + * Register : emac0_tx_d0 Mux Selection Register - EMACIO1 + * + * This register is used to control the peripherals connected to emac0_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 1. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D0. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1. + */ +struct ALT_SYSMGR_PINMUX_EMACIO1_s +{ + uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4 + +/* + * Register : emac0_tx_d1 Mux Selection Register - EMACIO2 + * + * This register is used to control the peripherals connected to emac0_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 2. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D1. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2. + */ +struct ALT_SYSMGR_PINMUX_EMACIO2_s +{ + uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8 + +/* + * Register : emac0_tx_d2 Mux Selection Register - EMACIO3 + * + * This register is used to control the peripherals connected to emac0_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 3. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D2. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3. + */ +struct ALT_SYSMGR_PINMUX_EMACIO3_s +{ + uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc + +/* + * Register : emac0_tx_d3 Mux Selection Register - EMACIO4 + * + * This register is used to control the peripherals connected to emac0_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 4. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D3. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4. + */ +struct ALT_SYSMGR_PINMUX_EMACIO4_s +{ + uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10 + +/* + * Register : emac0_rx_d0 Mux Selection Register - EMACIO5 + * + * This register is used to control the peripherals connected to emac0_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 5. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D4. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5. + */ +struct ALT_SYSMGR_PINMUX_EMACIO5_s +{ + uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14 + +/* + * Register : emac0_mdio Mux Selection Register - EMACIO6 + * + * This register is used to control the peripherals connected to emac0_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 6. + * + * 1 : Pin is connected to Peripheral signal I2C2.SDA. + * + * 2 : Pin is connected to Peripheral signal USB1.D5. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6. + */ +struct ALT_SYSMGR_PINMUX_EMACIO6_s +{ + uint32_t sel : 2; /* emac0_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18 + +/* + * Register : emac0_mdc Mux Selection Register - EMACIO7 + * + * This register is used to control the peripherals connected to emac0_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 7. + * + * 1 : Pin is connected to Peripheral signal I2C2.SCL. + * + * 2 : Pin is connected to Peripheral signal USB1.D6. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7. + */ +struct ALT_SYSMGR_PINMUX_EMACIO7_s +{ + uint32_t sel : 2; /* emac0_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c + +/* + * Register : emac0_rx_ctl Mux Selection Register - EMACIO8 + * + * This register is used to control the peripherals connected to emac0_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 8. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D7. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8. + */ +struct ALT_SYSMGR_PINMUX_EMACIO8_s +{ + uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20 + +/* + * Register : emac0_tx_ctl Mux Selection Register - EMACIO9 + * + * This register is used to control the peripherals connected to emac0_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 9. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9. + */ +struct ALT_SYSMGR_PINMUX_EMACIO9_s +{ + uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24 + +/* + * Register : emac0_rx_clk Mux Selection Register - EMACIO10 + * + * This register is used to control the peripherals connected to emac0_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 10. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10. + */ +struct ALT_SYSMGR_PINMUX_EMACIO10_s +{ + uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28 + +/* + * Register : emac0_rx_d1 Mux Selection Register - EMACIO11 + * + * This register is used to control the peripherals connected to emac0_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 11. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.STP. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11. + */ +struct ALT_SYSMGR_PINMUX_EMACIO11_s +{ + uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c + +/* + * Register : emac0_rx_d2 Mux Selection Register - EMACIO12 + * + * This register is used to control the peripherals connected to emac0_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 12. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.DIR. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12. + */ +struct ALT_SYSMGR_PINMUX_EMACIO12_s +{ + uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30 + +/* + * Register : emac0_rx_d3 Mux Selection Register - EMACIO13 + * + * This register is used to control the peripherals connected to emac0_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 13. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.NXT. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13. + */ +struct ALT_SYSMGR_PINMUX_EMACIO13_s +{ + uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34 + +/* + * Register : emac1_tx_clk Mux Selection Register - EMACIO14 + * + * This register is used to control the peripherals connected to emac1_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14. + */ +struct ALT_SYSMGR_PINMUX_EMACIO14_s +{ + uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38 + +/* + * Register : emac1_tx_d0 Mux Selection Register - EMACIO15 + * + * This register is used to control the peripherals connected to emac1_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15. + */ +struct ALT_SYSMGR_PINMUX_EMACIO15_s +{ + uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c + +/* + * Register : emac1_tx_d1 Mux Selection Register - EMACIO16 + * + * This register is used to control the peripherals connected to emac1_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16. + */ +struct ALT_SYSMGR_PINMUX_EMACIO16_s +{ + uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40 + +/* + * Register : emac1_tx_ctl Mux Selection Register - EMACIO17 + * + * This register is used to control the peripherals connected to emac1_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17. + */ +struct ALT_SYSMGR_PINMUX_EMACIO17_s +{ + uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44 + +/* + * Register : emac1_rx_d0 Mux Selection Register - EMACIO18 + * + * This register is used to control the peripherals connected to emac1_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18. + */ +struct ALT_SYSMGR_PINMUX_EMACIO18_s +{ + uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48 + +/* + * Register : emac1_rx_d1 Mux Selection Register - EMACIO19 + * + * This register is used to control the peripherals connected to emac1_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19. + */ +struct ALT_SYSMGR_PINMUX_EMACIO19_s +{ + uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c + +/* + * Register : sdmmc_cmd Mux Selection Register - FLASHIO0 + * + * This register is used to control the peripherals connected to sdmmc_cmd + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_cmd Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_cmd. + * + * 0 : Pin is connected to GPIO/LoanIO number 36. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D0. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CMD. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO0_s +{ + uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50 + +/* + * Register : sdmmc_pwren Mux Selection Register - FLASHIO1 + * + * This register is used to control the peripherals connected to sdmmc_pwren + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_pwren Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_pwren. + * + * 0 : Pin is connected to GPIO/LoanIO number 37. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D1. + * + * 3 : Pin is connected to Peripheral signal SDMMC.PWREN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO1_s +{ + uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54 + +/* + * Register : sdmmc_d0 Mux Selection Register - FLASHIO2 + * + * This register is used to control the peripherals connected to sdmmc_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d0 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 38. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D2. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO2_s +{ + uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58 + +/* + * Register : sdmmc_d1 Mux Selection Register - FLASHIO3 + * + * This register is used to control the peripherals connected to sdmmc_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d1 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 39. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D3. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO3_s +{ + uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c + +/* + * Register : sdmmc_d4 Mux Selection Register - FLASHIO4 + * + * This register is used to control the peripherals connected to sdmmc_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d4 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 40. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D4. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO4_s +{ + uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60 + +/* + * Register : sdmmc_d5 Mux Selection Register - FLASHIO5 + * + * This register is used to control the peripherals connected to sdmmc_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d5 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 41. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D5. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO5_s +{ + uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64 + +/* + * Register : sdmmc_d6 Mux Selection Register - FLASHIO6 + * + * This register is used to control the peripherals connected to sdmmc_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d6 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 42. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D6. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO6_s +{ + uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68 + +/* + * Register : sdmmc_d7 Mux Selection Register - FLASHIO7 + * + * This register is used to control the peripherals connected to sdmmc_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d7 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 43. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D7. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO7_s +{ + uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c + +/* + * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8 + * + * This register is used to control the peripherals connected to sdmmc_clk_in + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk_in Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk_in. + * + * 0 : Pin is connected to GPIO/LoanIO number 44. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.CLK. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO8_s +{ + uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70 + +/* + * Register : sdmmc_clk Mux Selection Register - FLASHIO9 + * + * This register is used to control the peripherals connected to sdmmc_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 45. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.STP. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO9_s +{ + uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74 + +/* + * Register : sdmmc_d2 Mux Selection Register - FLASHIO10 + * + * This register is used to control the peripherals connected to sdmmc_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d2 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 46. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.DIR. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO10_s +{ + uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78 + +/* + * Register : sdmmc_d3 Mux Selection Register - FLASHIO11 + * + * This register is used to control the peripherals connected to sdmmc_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d3 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 47. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.NXT. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO11_s +{ + uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c + +/* + * Register : trace_clk Mux Selection Register - GENERALIO0 + * + * This register is used to control the peripherals connected to trace_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | trace_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_clk Mux Selection Field - sel + * + * Select peripheral signals connected trace_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal TRACE.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO0_s +{ + uint32_t sel : 2; /* trace_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80 + +/* + * Register : trace_d0 Mux Selection Register - GENERALIO1 + * + * This register is used to control the peripherals connected to trace_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d0 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal UART0.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO1_s +{ + uint32_t sel : 2; /* trace_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84 + +/* + * Register : trace_d1 Mux Selection Register - GENERALIO2 + * + * This register is used to control the peripherals connected to trace_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d1 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal UART0.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO2_s +{ + uint32_t sel : 2; /* trace_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88 + +/* + * Register : trace_d2 Mux Selection Register - GENERALIO3 + * + * This register is used to control the peripherals connected to trace_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d2 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO3_s +{ + uint32_t sel : 2; /* trace_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c + +/* + * Register : trace_d3 Mux Selection Register - GENERALIO4 + * + * This register is used to control the peripherals connected to trace_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d3 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO4_s +{ + uint32_t sel : 2; /* trace_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90 + +/* + * Register : trace_d4 Mux Selection Register - GENERALIO5 + * + * This register is used to control the peripherals connected to trace_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d4 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal CAN1.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO5_s +{ + uint32_t sel : 2; /* trace_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94 + +/* + * Register : trace_d5 Mux Selection Register - GENERALIO6 + * + * This register is used to control the peripherals connected to trace_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d5 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal CAN1.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO6_s +{ + uint32_t sel : 2; /* trace_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98 + +/* + * Register : trace_d6 Mux Selection Register - GENERALIO7 + * + * This register is used to control the peripherals connected to trace_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d6 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal I2C0.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO7_s +{ + uint32_t sel : 2; /* trace_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c + +/* + * Register : trace_d7 Mux Selection Register - GENERALIO8 + * + * This register is used to control the peripherals connected to trace_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d7 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal I2C0.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO8_s +{ + uint32_t sel : 2; /* trace_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0 + +/* + * Register : spim0_clk Mux Selection Register - GENERALIO9 + * + * This register is used to control the peripherals connected to spim0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spim0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal UART0.CTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 3 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO9_s +{ + uint32_t sel : 2; /* spim0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4 + +/* + * Register : spim0_mosi Mux Selection Register - GENERALIO10 + * + * This register is used to control the peripherals connected to spim0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spim0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal UART0.RTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO10_s +{ + uint32_t sel : 2; /* spim0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8 + +/* + * Register : spim0_miso Mux Selection Register - GENERALIO11 + * + * This register is used to control the peripherals connected to spim0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spim0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal UART1.CTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.RX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO11_s +{ + uint32_t sel : 2; /* spim0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac + +/* + * Register : spim0_ss0 Mux Selection Register - GENERALIO12 + * + * This register is used to control the peripherals connected to spim0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal UART1.RTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.TX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO12_s +{ + uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0 + +/* + * Register : uart0_rx Mux Selection Register - GENERALIO13 + * + * This register is used to control the peripherals connected to uart0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.RX. + * + * 3 : Pin is connected to Peripheral signal UART0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO13_s +{ + uint32_t sel : 2; /* uart0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4 + +/* + * Register : uart0_tx Mux Selection Register - GENERALIO14 + * + * This register is used to control the peripherals connected to uart0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.TX. + * + * 3 : Pin is connected to Peripheral signal UART0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO14_s +{ + uint32_t sel : 2; /* uart0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8 + +/* + * Register : i2c0_sda Mux Selection Register - GENERALIO15 + * + * This register is used to control the peripherals connected to i2c0_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal UART1.RX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO15_s +{ + uint32_t sel : 2; /* i2c0_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc + +/* + * Register : i2c0_scl Mux Selection Register - GENERALIO16 + * + * This register is used to control the peripherals connected to i2c0_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal UART1.TX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO16_s +{ + uint32_t sel : 2; /* i2c0_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0 + +/* + * Register : can0_rx Mux Selection Register - GENERALIO17 + * + * This register is used to control the peripherals connected to can0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_rx Mux Selection Field - sel + * + * Select peripheral signals connected can0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal UART0.RX. + * + * 3 : Pin is connected to Peripheral signal CAN0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO17_s +{ + uint32_t sel : 2; /* can0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4 + +/* + * Register : can0_tx Mux Selection Register - GENERALIO18 + * + * This register is used to control the peripherals connected to can0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_tx Mux Selection Field - sel + * + * Select peripheral signals connected can0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal UART0.TX. + * + * 3 : Pin is connected to Peripheral signal CAN0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO18_s +{ + uint32_t sel : 2; /* can0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8 + +/* + * Register : spis1_clk Mux Selection Register - GENERALIO19 + * + * This register is used to control the peripherals connected to spis1_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis1_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 3 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO19_s +{ + uint32_t sel : 2; /* spis1_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc + +/* + * Register : spis1_mosi Mux Selection Register - GENERALIO20 + * + * This register is used to control the peripherals connected to spis1_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis1_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO20_s +{ + uint32_t sel : 2; /* spis1_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0 + +/* + * Register : spis1_miso Mux Selection Register - GENERALIO21 + * + * This register is used to control the peripherals connected to spis1_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis1_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO21_s +{ + uint32_t sel : 2; /* spis1_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4 + +/* + * Register : spis1_ss0 Mux Selection Register - GENERALIO22 + * + * This register is used to control the peripherals connected to spis1_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis1_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 3 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO22_s +{ + uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8 + +/* + * Register : uart1_rx Mux Selection Register - GENERALIO23 + * + * This register is used to control the peripherals connected to uart1_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 3 : Pin is connected to Peripheral signal UART1.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO23_s +{ + uint32_t sel : 2; /* uart1_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc + +/* + * Register : uart1_tx Mux Selection Register - GENERALIO24 + * + * This register is used to control the peripherals connected to uart1_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal UART1.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO24_s +{ + uint32_t sel : 2; /* uart1_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0 + +/* + * Register : i2c1_sda Mux Selection Register - GENERALIO25 + * + * This register is used to control the peripherals connected to i2c1_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal I2C1.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO25_s +{ + uint32_t sel : 2; /* i2c1_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4 + +/* + * Register : i2c1_scl Mux Selection Register - GENERALIO26 + * + * This register is used to control the peripherals connected to i2c1_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal I2C1.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO26_s +{ + uint32_t sel : 2; /* i2c1_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8 + +/* + * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27 + * + * This register is used to control the peripherals connected to spim0_ss0_alt + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0_alt Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0_alt. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal not applicable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO27_s +{ + uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec + +/* + * Register : spis0_clk Mux Selection Register - GENERALIO28 + * + * This register is used to control the peripherals connected to spis0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 3 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO28_s +{ + uint32_t sel : 2; /* spis0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0 + +/* + * Register : spis0_mosi Mux Selection Register - GENERALIO29 + * + * This register is used to control the peripherals connected to spis0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO29_s +{ + uint32_t sel : 2; /* spis0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4 + +/* + * Register : spis0_miso Mux Selection Register - GENERALIO30 + * + * This register is used to control the peripherals connected to spis0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO30_s +{ + uint32_t sel : 2; /* spis0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8 + +/* + * Register : spis0_ss0 Mux Selection Register - GENERALIO31 + * + * This register is used to control the peripherals connected to spis0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO31_s +{ + uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc + +/* + * Register : nand_ale Mux Selection Register - MIXED1IO0 + * + * This register is used to control the peripherals connected to nand_ale + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_ale Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ale Mux Selection Field - sel + * + * Select peripheral signals connected nand_ale. + * + * 0 : Pin is connected to GPIO/LoanIO number 14. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.ale. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO0_s +{ + uint32_t sel : 2; /* nand_ale Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100 + +/* + * Register : nand_ce Mux Selection Register - MIXED1IO1 + * + * This register is used to control the peripherals connected to nand_ce + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_ce Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ce Mux Selection Field - sel + * + * Select peripheral signals connected nand_ce. + * + * 0 : Pin is connected to GPIO/LoanIO number 15. + * + * 1 : Pin is connected to Peripheral signal USB1.D0. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.ce. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO1_s +{ + uint32_t sel : 2; /* nand_ce Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104 + +/* + * Register : nand_cle Mux Selection Register - MIXED1IO2 + * + * This register is used to control the peripherals connected to nand_cle + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_cle Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_cle Mux Selection Field - sel + * + * Select peripheral signals connected nand_cle. + * + * 0 : Pin is connected to GPIO/LoanIO number 16. + * + * 1 : Pin is connected to Peripheral signal USB1.D1. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.cle. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO2_s +{ + uint32_t sel : 2; /* nand_cle Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108 + +/* + * Register : nand_re Mux Selection Register - MIXED1IO3 + * + * This register is used to control the peripherals connected to nand_re + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_re Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_re Mux Selection Field - sel + * + * Select peripheral signals connected nand_re. + * + * 0 : Pin is connected to GPIO/LoanIO number 17. + * + * 1 : Pin is connected to Peripheral signal USB1.D2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.re. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO3_s +{ + uint32_t sel : 2; /* nand_re Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c + +/* + * Register : nand_rb Mux Selection Register - MIXED1IO4 + * + * This register is used to control the peripherals connected to nand_rb + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_rb Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_rb Mux Selection Field - sel + * + * Select peripheral signals connected nand_rb. + * + * 0 : Pin is connected to GPIO/LoanIO number 18. + * + * 1 : Pin is connected to Peripheral signal USB1.D3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.rb. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO4_s +{ + uint32_t sel : 2; /* nand_rb Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110 + +/* + * Register : nand_dq0 Mux Selection Register - MIXED1IO5 + * + * This register is used to control the peripherals connected to nand_dq0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq0 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq0. + * + * 0 : Pin is connected to GPIO/LoanIO number 19. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.dq0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO5_s +{ + uint32_t sel : 2; /* nand_dq0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114 + +/* + * Register : nand_dq1 Mux Selection Register - MIXED1IO6 + * + * This register is used to control the peripherals connected to nand_dq1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq1 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq1. + * + * 0 : Pin is connected to GPIO/LoanIO number 20. + * + * 1 : Pin is connected to Peripheral signal I2C3.SDA. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * 3 : Pin is connected to Peripheral signal NAND.dq1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO6_s +{ + uint32_t sel : 2; /* nand_dq1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118 + +/* + * Register : nand_dq2 Mux Selection Register - MIXED1IO7 + * + * This register is used to control the peripherals connected to nand_dq2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq2 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq2. + * + * 0 : Pin is connected to GPIO/LoanIO number 21. + * + * 1 : Pin is connected to Peripheral signal I2C3.SCL. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * 3 : Pin is connected to Peripheral signal NAND.dq2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO7_s +{ + uint32_t sel : 2; /* nand_dq2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c + +/* + * Register : nand_dq3 Mux Selection Register - MIXED1IO8 + * + * This register is used to control the peripherals connected to nand_dq3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq3 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq3. + * + * 0 : Pin is connected to GPIO/LoanIO number 22. + * + * 1 : Pin is connected to Peripheral signal USB1.D4. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO8_s +{ + uint32_t sel : 2; /* nand_dq3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120 + +/* + * Register : nand_dq4 Mux Selection Register - MIXED1IO9 + * + * This register is used to control the peripherals connected to nand_dq4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq4 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq4. + * + * 0 : Pin is connected to GPIO/LoanIO number 23. + * + * 1 : Pin is connected to Peripheral signal USB1.D5. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO9_s +{ + uint32_t sel : 2; /* nand_dq4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124 + +/* + * Register : nand_dq5 Mux Selection Register - MIXED1IO10 + * + * This register is used to control the peripherals connected to nand_dq5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq5 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq5. + * + * 0 : Pin is connected to GPIO/LoanIO number 24. + * + * 1 : Pin is connected to Peripheral signal USB1.D6. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.dq5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO10_s +{ + uint32_t sel : 2; /* nand_dq5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128 + +/* + * Register : nand_dq6 Mux Selection Register - MIXED1IO11 + * + * This register is used to control the peripherals connected to nand_dq6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq6 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq6. + * + * 0 : Pin is connected to GPIO/LoanIO number 25. + * + * 1 : Pin is connected to Peripheral signal USB1.D7. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.dq6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO11_s +{ + uint32_t sel : 2; /* nand_dq6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c + +/* + * Register : nand_dq7 Mux Selection Register - MIXED1IO12 + * + * This register is used to control the peripherals connected to nand_dq7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq7 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq7. + * + * 0 : Pin is connected to GPIO/LoanIO number 26. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.dq7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO12_s +{ + uint32_t sel : 2; /* nand_dq7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130 + +/* + * Register : nand_wp Mux Selection Register - MIXED1IO13 + * + * This register is used to control the peripherals connected to nand_wp + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_wp Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_wp Mux Selection Field - sel + * + * Select peripheral signals connected nand_wp. + * + * 0 : Pin is connected to GPIO/LoanIO number 27. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.wp. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO13_s +{ + uint32_t sel : 2; /* nand_wp Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134 + +/* + * Register : nand_we Mux Selection Register - MIXED1IO14 + * + * This register is used to control the peripherals connected to nand_we + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_we Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_we Mux Selection Field - sel + * + * Select peripheral signals connected nand_we. + * + * 0 : Pin is connected to GPIO/LoanIO number 28. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal QSPI.SS1. + * + * 3 : Pin is connected to Peripheral signal NAND.we. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO14_s +{ + uint32_t sel : 2; /* nand_we Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138 + +/* + * Register : qspi_io0 Mux Selection Register - MIXED1IO15 + * + * This register is used to control the peripherals connected to qspi_io0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io0. + * + * 0 : Pin is connected to GPIO/LoanIO number 29. + * + * 1 : Pin is connected to Peripheral signal USB1.CLK. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO15_s +{ + uint32_t sel : 2; /* qspi_io0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c + +/* + * Register : qspi_io1 Mux Selection Register - MIXED1IO16 + * + * This register is used to control the peripherals connected to qspi_io1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io1. + * + * 0 : Pin is connected to GPIO/LoanIO number 30. + * + * 1 : Pin is connected to Peripheral signal USB1.STP. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO16_s +{ + uint32_t sel : 2; /* qspi_io1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140 + +/* + * Register : qspi_io2 Mux Selection Register - MIXED1IO17 + * + * This register is used to control the peripherals connected to qspi_io2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io2 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io2. + * + * 0 : Pin is connected to GPIO/LoanIO number 31. + * + * 1 : Pin is connected to Peripheral signal USB1.DIR. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO17_s +{ + uint32_t sel : 2; /* qspi_io2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144 + +/* + * Register : qspi_io3 Mux Selection Register - MIXED1IO18 + * + * This register is used to control the peripherals connected to qspi_io3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io3 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io3. + * + * 0 : Pin is connected to GPIO/LoanIO number 32. + * + * 1 : Pin is connected to Peripheral signal USB1.NXT. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO18_s +{ + uint32_t sel : 2; /* qspi_io3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148 + +/* + * Register : qspi_ss0 Mux Selection Register - MIXED1IO19 + * + * This register is used to control the peripherals connected to qspi_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 33. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO19_s +{ + uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c + +/* + * Register : qpsi_clk Mux Selection Register - MIXED1IO20 + * + * This register is used to control the peripherals connected to qpsi_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qpsi_clk Mux Selection Field - sel + * + * Select peripheral signals connected qpsi_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 34. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO20_s +{ + uint32_t sel : 2; /* qpsi_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150 + +/* + * Register : qspi_ss1 Mux Selection Register - MIXED1IO21 + * + * This register is used to control the peripherals connected to qspi_ss1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss1. + * + * 0 : Pin is connected to GPIO/LoanIO number 35. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO21_s +{ + uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154 + +/* + * Register : emac1_mdio Mux Selection Register - MIXED2IO0 + * + * This register is used to control the peripherals connected to emac1_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO0_s +{ + uint32_t sel : 2; /* emac1_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158 + +/* + * Register : emac1_mdc Mux Selection Register - MIXED2IO1 + * + * This register is used to control the peripherals connected to emac1_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO1_s +{ + uint32_t sel : 2; /* emac1_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c + +/* + * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2 + * + * This register is used to control the peripherals connected to emac1_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO2_s +{ + uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160 + +/* + * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3 + * + * This register is used to control the peripherals connected to emac1_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO3_s +{ + uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164 + +/* + * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4 + * + * This register is used to control the peripherals connected to emac1_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO4_s +{ + uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168 + +/* + * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5 + * + * This register is used to control the peripherals connected to emac1_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO5_s +{ + uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c + +/* + * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6 + * + * This register is used to control the peripherals connected to emac1_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO6_s +{ + uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170 + +/* + * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7 + * + * This register is used to control the peripherals connected to emac1_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO7_s +{ + uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174 + +/* + * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 48. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : Source for GPIO/LoanIO 48 is GENERALIO0. + * + * 1 : Source for GPIO/LoanIO 48 is EMACIO14. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178 + +/* + * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 49. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : Source for GPIO/LoanIO 49 is GENERALIO1. + * + * 1 : Source for GPIO/LoanIO 49 is EMACIO15. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c + +/* + * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 50. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : Source for GPIO/LoanIO 50 is GENERALIO2. + * + * 1 : Source for GPIO/LoanIO 50 is EMACIO16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180 + +/* + * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 51. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : Source for GPIO/LoanIO 51 is GENERALIO3. + * + * 1 : Source for GPIO/LoanIO 51 is EMACIO17. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184 + +/* + * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 52. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : Source for GPIO/LoanIO 52 is GENERALIO4. + * + * 1 : Source for GPIO/LoanIO 52 is EMACIO18. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188 + +/* + * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 53. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : Source for GPIO/LoanIO 53 is GENERALIO5. + * + * 1 : Source for GPIO/LoanIO 53 is EMACIO19. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c + +/* + * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 54. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : Source for GPIO/LoanIO 54 is GENERALIO6. + * + * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190 + +/* + * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 55. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : Source for GPIO/LoanIO 55 is GENERALIO7. + * + * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194 + +/* + * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 56. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : Source for GPIO/LoanIO 56 is GENERALIO8. + * + * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198 + +/* + * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 57. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : Source for GPIO/LoanIO 57 is GENERALIO9. + * + * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c + +/* + * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 58. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : Source for GPIO/LoanIO 58 is GENERALIO10. + * + * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0 + +/* + * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 59. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : Source for GPIO/LoanIO 59 is GENERALIO11. + * + * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4 + +/* + * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 60. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : Source for GPIO/LoanIO 60 is GENERALIO12. + * + * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8 + +/* + * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 61. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : Source for GPIO/LoanIO 61 is GENERALIO13. + * + * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac + +/* + * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 62. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : Source for GPIO/LoanIO 62 is GENERALIO14. + * + * 1 : Source for GPIO/LoanIO 62 is GENERALIO23. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0 + +/* + * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 63. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : Source for GPIO/LoanIO 63 is GENERALIO15. + * + * 1 : Source for GPIO/LoanIO 63 is GENERALIO24. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4 + +/* + * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 64. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : Source for GPIO/LoanIO 64 is GENERALIO16. + * + * 1 : Source for GPIO/LoanIO 64 is GENERALIO25. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8 + +/* + * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 65. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : Source for GPIO/LoanIO 65 is GENERALIO17. + * + * 1 : Source for GPIO/LoanIO 65 is GENERALIO26. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc + +/* + * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 66. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : Source for GPIO/LoanIO 66 is GENERALIO18. + * + * 1 : Source for GPIO/LoanIO 66 is GENERALIO27. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0 + +/* + * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 67. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : Source for GPIO/LoanIO 67 is GENERALIO19. + * + * 1 : Source for GPIO/LoanIO 67 is GENERALIO28. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4 + +/* + * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 68. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : Source for GPIO/LoanIO 68 is GENERALIO20. + * + * 1 : Source for GPIO/LoanIO 68 is GENERALIO29. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8 + +/* + * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 69. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : Source for GPIO/LoanIO 69 is GENERALIO21. + * + * 1 : Source for GPIO/LoanIO 69 is GENERALIO30. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc + +/* + * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 70. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : Source for GPIO/LoanIO 70 is GENERALIO22. + * + * 1 : Source for GPIO/LoanIO 70 is GENERALIO31. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0 + +/* + * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0 + * + * Selection between GPIO and LoanIO output and output enable for GPIO0 and + * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO0Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 0. + * + * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals. + * + * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX0_s +{ + uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4 + +/* + * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1 + * + * Selection between GPIO and LoanIO output and output enable for GPIO1 and + * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO1Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 1. + * + * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals. + * + * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX1_s +{ + uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8 + +/* + * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2 + * + * Selection between GPIO and LoanIO output and output enable for GPIO2 and + * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO2Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 2. + * + * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals. + * + * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX2_s +{ + uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc + +/* + * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3 + * + * Selection between GPIO and LoanIO output and output enable for GPIO3 and + * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO3Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 3. + * + * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals. + * + * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX3_s +{ + uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0 + +/* + * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4 + * + * Selection between GPIO and LoanIO output and output enable for GPIO4 and + * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO4Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 4. + * + * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals. + * + * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX4_s +{ + uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4 + +/* + * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5 + * + * Selection between GPIO and LoanIO output and output enable for GPIO5 and + * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO5Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 5. + * + * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals. + * + * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX5_s +{ + uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8 + +/* + * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6 + * + * Selection between GPIO and LoanIO output and output enable for GPIO6 and + * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO6Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 6. + * + * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals. + * + * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX6_s +{ + uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec + +/* + * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7 + * + * Selection between GPIO and LoanIO output and output enable for GPIO7 and + * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO7Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 7. + * + * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals. + * + * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX7_s +{ + uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0 + +/* + * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8 + * + * Selection between GPIO and LoanIO output and output enable for GPIO8 and + * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO8Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 8. + * + * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals. + * + * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX8_s +{ + uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4 + +/* + * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9 + * + * Selection between GPIO and LoanIO output and output enable for GPIO9 and + * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO9Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 9. + * + * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals. + * + * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX9_s +{ + uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8 + +/* + * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10 + * + * Selection between GPIO and LoanIO output and output enable for GPIO10 and + * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO10Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 10. + * + * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals. + * + * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX10_s +{ + uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc + +/* + * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11 + * + * Selection between GPIO and LoanIO output and output enable for GPIO11 and + * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO11Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 11. + * + * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals. + * + * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX11_s +{ + uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200 + +/* + * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12 + * + * Selection between GPIO and LoanIO output and output enable for GPIO12 and + * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO12Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 12. + * + * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals. + * + * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX12_s +{ + uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204 + +/* + * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13 + * + * Selection between GPIO and LoanIO output and output enable for GPIO13 and + * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO13Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 13. + * + * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals. + * + * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX13_s +{ + uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208 + +/* + * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14 + * + * Selection between GPIO and LoanIO output and output enable for GPIO14 and + * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO14Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 14. + * + * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals. + * + * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX14_s +{ + uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c + +/* + * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15 + * + * Selection between GPIO and LoanIO output and output enable for GPIO15 and + * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO15Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 15. + * + * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals. + * + * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX15_s +{ + uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210 + +/* + * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16 + * + * Selection between GPIO and LoanIO output and output enable for GPIO16 and + * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO16Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 16. + * + * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals. + * + * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX16_s +{ + uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214 + +/* + * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17 + * + * Selection between GPIO and LoanIO output and output enable for GPIO17 and + * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO17Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 17. + * + * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals. + * + * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX17_s +{ + uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218 + +/* + * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18 + * + * Selection between GPIO and LoanIO output and output enable for GPIO18 and + * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO18Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 18. + * + * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals. + * + * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX18_s +{ + uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c + +/* + * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19 + * + * Selection between GPIO and LoanIO output and output enable for GPIO19 and + * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO19Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 19. + * + * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals. + * + * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX19_s +{ + uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220 + +/* + * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20 + * + * Selection between GPIO and LoanIO output and output enable for GPIO20 and + * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO20Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 20. + * + * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals. + * + * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX20_s +{ + uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224 + +/* + * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21 + * + * Selection between GPIO and LoanIO output and output enable for GPIO21 and + * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO21Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 21. + * + * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals. + * + * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX21_s +{ + uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228 + +/* + * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22 + * + * Selection between GPIO and LoanIO output and output enable for GPIO22 and + * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO22Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 22. + * + * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals. + * + * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX22_s +{ + uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c + +/* + * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23 + * + * Selection between GPIO and LoanIO output and output enable for GPIO23 and + * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO23Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 23. + * + * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals. + * + * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX23_s +{ + uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230 + +/* + * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24 + * + * Selection between GPIO and LoanIO output and output enable for GPIO24 and + * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO24Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 24. + * + * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals. + * + * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX24_s +{ + uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234 + +/* + * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25 + * + * Selection between GPIO and LoanIO output and output enable for GPIO25 and + * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO25Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 25. + * + * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals. + * + * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX25_s +{ + uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238 + +/* + * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26 + * + * Selection between GPIO and LoanIO output and output enable for GPIO26 and + * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO26Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 26. + * + * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals. + * + * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX26_s +{ + uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c + +/* + * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27 + * + * Selection between GPIO and LoanIO output and output enable for GPIO27 and + * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO27Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 27. + * + * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals. + * + * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX27_s +{ + uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240 + +/* + * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28 + * + * Selection between GPIO and LoanIO output and output enable for GPIO28 and + * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO28Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 28. + * + * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals. + * + * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX28_s +{ + uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244 + +/* + * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29 + * + * Selection between GPIO and LoanIO output and output enable for GPIO29 and + * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO29Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 29. + * + * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals. + * + * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX29_s +{ + uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248 + +/* + * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30 + * + * Selection between GPIO and LoanIO output and output enable for GPIO30 and + * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO30Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 30. + * + * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals. + * + * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX30_s +{ + uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c + +/* + * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31 + * + * Selection between GPIO and LoanIO output and output enable for GPIO31 and + * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO31Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 31. + * + * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals. + * + * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX31_s +{ + uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250 + +/* + * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32 + * + * Selection between GPIO and LoanIO output and output enable for GPIO32 and + * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO32Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 32. + * + * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals. + * + * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX32_s +{ + uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254 + +/* + * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33 + * + * Selection between GPIO and LoanIO output and output enable for GPIO33 and + * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO33Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 33. + * + * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals. + * + * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX33_s +{ + uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258 + +/* + * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34 + * + * Selection between GPIO and LoanIO output and output enable for GPIO34 and + * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO34Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 34. + * + * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals. + * + * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX34_s +{ + uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c + +/* + * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35 + * + * Selection between GPIO and LoanIO output and output enable for GPIO35 and + * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO35Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 35. + * + * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals. + * + * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX35_s +{ + uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260 + +/* + * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36 + * + * Selection between GPIO and LoanIO output and output enable for GPIO36 and + * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO36Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 36. + * + * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals. + * + * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX36_s +{ + uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264 + +/* + * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37 + * + * Selection between GPIO and LoanIO output and output enable for GPIO37 and + * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO37Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 37. + * + * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals. + * + * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX37_s +{ + uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268 + +/* + * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38 + * + * Selection between GPIO and LoanIO output and output enable for GPIO38 and + * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO38Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 38. + * + * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals. + * + * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX38_s +{ + uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c + +/* + * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39 + * + * Selection between GPIO and LoanIO output and output enable for GPIO39 and + * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO39Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 39. + * + * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals. + * + * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX39_s +{ + uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270 + +/* + * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40 + * + * Selection between GPIO and LoanIO output and output enable for GPIO40 and + * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO40Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 40. + * + * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals. + * + * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX40_s +{ + uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274 + +/* + * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41 + * + * Selection between GPIO and LoanIO output and output enable for GPIO41 and + * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO41Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 41. + * + * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals. + * + * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX41_s +{ + uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278 + +/* + * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42 + * + * Selection between GPIO and LoanIO output and output enable for GPIO42 and + * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO42Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 42. + * + * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals. + * + * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX42_s +{ + uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c + +/* + * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43 + * + * Selection between GPIO and LoanIO output and output enable for GPIO43 and + * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO43Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 43. + * + * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals. + * + * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX43_s +{ + uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280 + +/* + * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44 + * + * Selection between GPIO and LoanIO output and output enable for GPIO44 and + * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO44Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 44. + * + * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals. + * + * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX44_s +{ + uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284 + +/* + * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45 + * + * Selection between GPIO and LoanIO output and output enable for GPIO45 and + * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO45Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 45. + * + * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals. + * + * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX45_s +{ + uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288 + +/* + * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46 + * + * Selection between GPIO and LoanIO output and output enable for GPIO46 and + * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO46Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 46. + * + * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals. + * + * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX46_s +{ + uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c + +/* + * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47 + * + * Selection between GPIO and LoanIO output and output enable for GPIO47 and + * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO47Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 47. + * + * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals. + * + * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX47_s +{ + uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290 + +/* + * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48 + * + * Selection between GPIO and LoanIO output and output enable for GPIO48 and + * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals. + * + * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294 + +/* + * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49 + * + * Selection between GPIO and LoanIO output and output enable for GPIO49 and + * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals. + * + * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298 + +/* + * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50 + * + * Selection between GPIO and LoanIO output and output enable for GPIO50 and + * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals. + * + * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c + +/* + * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51 + * + * Selection between GPIO and LoanIO output and output enable for GPIO51 and + * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals. + * + * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0 + +/* + * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52 + * + * Selection between GPIO and LoanIO output and output enable for GPIO52 and + * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals. + * + * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4 + +/* + * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53 + * + * Selection between GPIO and LoanIO output and output enable for GPIO53 and + * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. + * + * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8 + +/* + * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54 + * + * Selection between GPIO and LoanIO output and output enable for GPIO54 and + * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals. + * + * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac + +/* + * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55 + * + * Selection between GPIO and LoanIO output and output enable for GPIO55 and + * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals. + * + * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0 + +/* + * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56 + * + * Selection between GPIO and LoanIO output and output enable for GPIO56 and + * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals. + * + * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4 + +/* + * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57 + * + * Selection between GPIO and LoanIO output and output enable for GPIO57 and + * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals. + * + * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8 + +/* + * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58 + * + * Selection between GPIO and LoanIO output and output enable for GPIO58 and + * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals. + * + * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc + +/* + * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59 + * + * Selection between GPIO and LoanIO output and output enable for GPIO59 and + * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals. + * + * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0 + +/* + * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60 + * + * Selection between GPIO and LoanIO output and output enable for GPIO60 and + * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals. + * + * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4 + +/* + * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61 + * + * Selection between GPIO and LoanIO output and output enable for GPIO61 and + * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals. + * + * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8 + +/* + * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62 + * + * Selection between GPIO and LoanIO output and output enable for GPIO62 and + * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals. + * + * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc + +/* + * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63 + * + * Selection between GPIO and LoanIO output and output enable for GPIO63 and + * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals. + * + * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0 + +/* + * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64 + * + * Selection between GPIO and LoanIO output and output enable for GPIO64 and + * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals. + * + * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4 + +/* + * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65 + * + * Selection between GPIO and LoanIO output and output enable for GPIO65 and + * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals. + * + * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8 + +/* + * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66 + * + * Selection between GPIO and LoanIO output and output enable for GPIO66 and + * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals. + * + * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc + +/* + * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67 + * + * Selection between GPIO and LoanIO output and output enable for GPIO67 and + * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals. + * + * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0 + +/* + * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68 + * + * Selection between GPIO and LoanIO output and output enable for GPIO68 and + * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals. + * + * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4 + +/* + * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69 + * + * Selection between GPIO and LoanIO output and output enable for GPIO69 and + * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals. + * + * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8 + +/* + * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70 + * + * Selection between GPIO and LoanIO output and output enable for GPIO70 and + * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals. + * + * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec + +/* + * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA + * + * Selection between HPS Pins and FPGA Interface for NAND signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for NAND signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for NAND signals - sel + * + * Select connection for NAND. + * + * 0 : NAND uses HPS Pins. + * + * 1 : NAND uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. + */ +struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s +{ + uint32_t sel : 1; /* Selection for NAND signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0 + +/* + * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII1 signals - sel + * + * Select connection for RGMII1. + * + * 0 : RGMII1 uses HPS Pins. + * + * 1 : RGMII1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8 + +/* + * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C0 signals - sel + * + * Select connection for I2C0. + * + * 0 : I2C0 uses HPS Pins. + * + * 1 : I2C0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304 + +/* + * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII0 signals - sel + * + * Select connection for RGMII0. + * + * 0 : RGMII0 uses HPS Pins. + * + * 1 : RGMII0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314 + +/* + * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C3 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C3 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C3 signals - sel + * + * Select connection for I2C3. + * + * 0 : I2C3 uses HPS Pins. + * + * 1 : I2C3 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C3 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324 + +/* + * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C2 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C2 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C2 signals - sel + * + * Select connection for I2C2. + * + * 0 : I2C2 uses HPS Pins. + * + * 1 : I2C2 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C2 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328 + +/* + * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C1 signals - sel + * + * Select connection for I2C1. + * + * 0 : I2C1 uses HPS Pins. + * + * 1 : I2C1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c + +/* + * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM1 signals - sel + * + * Select connection for SPIM1. + * + * 0 : SPIM1 uses HPS Pins. + * + * 1 : SPIM1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330 + +/* + * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM0 signals - sel + * + * Select connection for SPIM0. + * + * 0 : SPIM0 uses HPS Pins. + * + * 1 : SPIM0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_PINMUX. + */ +struct ALT_SYSMGR_PINMUX_s +{ + volatile ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +struct ALT_SYSMGR_PINMUX_raw_s +{ + volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR. + */ +struct ALT_SYSMGR_s +{ + volatile ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR. */ +struct ALT_SYSMGR_raw_s +{ + volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SYSMGR_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h new file mode 100644 index 0000000000..b64111960b --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h @@ -0,0 +1,5158 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_UART */ + +#ifndef __ALTERA_ALT_UART_H__ +#define __ALTERA_ALT_UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : UART Module - ALT_UART + * UART Module + * + * Registers in the UART module + * + */ +/* + * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll + * + * This is a multi-function register. This register holds receives and transmit + * data and controls the least-signficant 8 bits of the baud rate divisor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Value - value + * + * Receive Buffer Register: + * + * This register contains the data byte received on the serial input port + * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0] + * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of + * Register FCR is set to 0) the data in the RBR must be read before the next data + * arrives, otherwise it will be overwritten, resulting in an overrun error. If + * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses + * the head of the receive FIFO. If the receive FIFO is full, and this register is + * not read before the next data character arrives, then the data already in the + * FIFO will be preserved but any incoming data will be lost. An overrun error will + * also occur. + * + * Transmit Holding Register: + * + * This register contains data to be transmitted on the serial output port. Data + * should only be written to the THR when the THR Empty bit [5] of the LSR Register + * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and + * THRE is set to 1, writing a single character to the THR clears the THRE. Any + * additional writes to the THR before the THRE is set again causes the THR data to + * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and + * THRE is set up to 128 characters of data may be written to the THR before the + * FIFO is full. Any attempt to write data when the FIFO is full results in the + * write data being lost. + * + * Divisor Latch Low: + * + * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch + * register that contains the baud rate divisor for the UART. This register may + * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The + * output baud rate is equal to the serial clock l4_sp_clk frequency divided by + * sixteen times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor) + * + * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7 +/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 +/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 +/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RBR_THR_DLL. + */ +struct ALT_UART_RBR_THR_DLL_s +{ + uint32_t value : 8; /* Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */ +typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */ +#define ALT_UART_RBR_THR_DLL_OFST 0x0 +/* The address of the ALT_UART_RBR_THR_DLL register. */ +#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) + +/* + * Register : Interrupt Enable and Divisor Latch High - ier_dlh + * + * This is a multi-function register. This register enables/disables receive and + * transmit interrupts and also controls the most-significant 8-bits of the baud + * rate divisor. + * + * Divisor Latch High Register: + * + * This register is accessed when the DLAB bit [7] of the LCR Register is set to + * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output + * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen + * times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor): + * + * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Interrupt Enable Register: + * + * This register may only be accessed when the DLAB bit [7] of the LCR Register is + * set to 0.Allows control of the Interrupt Enables for transmit and receive + * functions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable + * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control + * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status + * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt + * [4] | RW | 0x0 | DLH[4] + * [5] | RW | 0x0 | DLH[5] + * [6] | RW | 0x0 | DLH[6] + * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0 + * + * Divisor Latch High Register: + * + * Bit 0 of DLH value. + * + * Interrupt Enable Register: + * + * Used to enable/disable the generation of the Receive Data Available Interrupt + * and the Character Timeout Interrupt(if FIFO's enabled). These are the second + * highest priority interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------ + * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable + * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Disable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Enable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0 +/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl + * + * Divisor Latch High Register: + * + * Bit 1 of DLH value. + * + * Interrupt Enable Register: + * + * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable + * the generation of Transmitter Holding Register Empty Interrupt. This is the + * third highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable + * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx disable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx enable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1 +/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2 + * + * Divisor Latch High Register: + * + * Bit 2 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Receiver Line Status Interrupt. + * This is the highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat + * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Disable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Enable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2 +/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3 + * + * Divisor Latch High Register: + * + * Bit 3 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Modem Status Interrupts. This + * is the fourth highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt + * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * disable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * enable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3 +/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DLH[4] - dlh4 + * + * Bit 4 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_MSB 4 +/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */ +#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLH[5] - dlh5 + * + * Bit 5 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_MSB 5 +/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */ +#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : DLH[6] - dlh6 + * + * Bit 6 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_MSB 6 +/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */ +#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7 + * + * Divisor Latch High Register: + * + * Bit 7 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of THRE Interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------ + * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt + * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * disable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * enable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7 +/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IER_DLH. + */ +struct ALT_UART_IER_DLH_s +{ + uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */ + uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */ + uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */ + uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */ + uint32_t dlh4 : 1; /* DLH[4] */ + uint32_t dlh5 : 1; /* DLH[5] */ + uint32_t dlh6 : 1; /* DLH[6] */ + uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IER_DLH. */ +typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */ +#define ALT_UART_IER_DLH_OFST 0x4 +/* The address of the ALT_UART_IER_DLH register. */ +#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST)) + +/* + * Register : Interrupt Identity Register (when read) - iir + * + * Returns interrupt identification and FIFO enable/disable when read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | R | 0x1 | Interrupt ID + * [5:4] | ??? | 0x0 | *UNDEFINED* + * [7:6] | R | 0x0 | FIFO Enabled + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt ID - id + * + * This indicates the highest priority pending interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status + * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending + * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty + * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available + * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status + * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Modem status + */ +#define ALT_UART_IIR_ID_E_MODMSTAT 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * No Interrupt pending + */ +#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * THR empty + */ +#define ALT_UART_IIR_ID_E_THREMPTY 0x2 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive data available + */ +#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive line status + */ +#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Character timeout + */ +#define ALT_UART_IIR_ID_E_CHARTMO 0xc + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_MSB 3 +/* The width in bits of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_WIDTH 4 +/* The mask used to set the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_SET_MSK 0x0000000f +/* The mask used to clear the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_RESET 0x1 +/* Extracts the ALT_UART_IIR_ID field value from a register. */ +#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */ +#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : FIFO Enabled - fifoen + * + * This is used to indicate whether the FIFO's are enabled or disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled + * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO disabled + */ +#define ALT_UART_IIR_FIFOEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO enabled + */ +#define ALT_UART_IIR_FIFOEN_E_END 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_MSB 7 +/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_WIDTH 2 +/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_RESET 0x0 +/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */ +#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */ +#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IIR. + */ +struct ALT_UART_IIR_s +{ + const uint32_t id : 4; /* Interrupt ID */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifoen : 2; /* FIFO Enabled */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IIR. */ +typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */ +#define ALT_UART_IIR_OFST 0x8 +/* The address of the ALT_UART_IIR register. */ +#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST)) + +/* + * Register : FIFO Control (when written) - fcr + * + * Controls FIFO Operations when written. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [0] | W | Unknown | FIFO Enable + * [1] | W | Unknown | Rx FIFO Reset + * [2] | W | Unknown | Tx FIFO Reset + * [3] | W | Unknown | DMA Mode + * [5:4] | W | Unknown | Tx Empty Trigger Level + * [7:6] | W | Unknown | Rx Trigger Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO Enable - fifoe + * + * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value + * of this bit is changed both the Tx and Rx controller portion of FIFO's will be + * reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------- + * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled + * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs disabled + */ +#define ALT_UART_FCR_FIFOE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs enabled + */ +#define ALT_UART_FCR_FIFOE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_MSB 0 +/* The width in bits of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */ +#define ALT_UART_FCR_FIFOE_RESET 0x0 +/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */ +#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */ +#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfifor + * + * Resets the control portion of the receive FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Rxrequest and single signals. Note that this + * bit is self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control + * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * No Reset of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * Resets of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_MSB 1 +/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_RFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */ +#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfifor + * + * Resets the control portion of the transmit FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Tx request and single signals when additional + * DMA handshaking is used. + * + * Note that this bit is 'self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control + * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * No Reset of Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * Resets Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_MSB 2 +/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_XFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */ +#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Mode - dmam + * + * This determines the DMA signalling mode used for the uart_dma_tx_req_n and + * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not + * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, + * the uart_dma_tx_req_n signal goes active low under the following conditions: + * + * * When the Transmitter Holding Register is empty in non-FIFO mode. + * + * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE + * interrupt mode disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * It goes inactive under the following conditions + * + * * When a single character has been written into the Transmitter Holding + * Register or transmitter FIFO with Programmable THRE interrupt mode disabled. + * + * * When the transmitter FIFO is above the threshold with Programmable THRE + * interrupt mode enabled. + * + * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made + * continuously until the receiver FIFO has been emptied or the transmit FIFO has + * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the + * following conditions: + * + * * When the transmitter FIFO is empty with Programmable THRE interrupt mode + * disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------- + * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_MSB 3 +/* The width in bits of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */ +#define ALT_UART_FCR_DMAM_RESET 0x0 +/* Extracts the ALT_UART_FCR_DMAM field value from a register. */ +#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */ +#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Tx Empty Trigger Level - tet + * + * This is used to select the empty threshold level at which the THRE Interrupts + * will be generated when the mode is active. It also determines when the uart DMA + * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes + * of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------- + * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full + * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO empty + */ +#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * Two characters in FIFO + */ +#define ALT_UART_FCR_TET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_TET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_MSB 5 +/* The width in bits of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_SET_MSK 0x00000030 +/* The mask used to clear the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf +/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */ +#define ALT_UART_FCR_TET_RESET 0x0 +/* Extracts the ALT_UART_FCR_TET field value from a register. */ +#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */ +#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Rx Trigger Level - rt + * + * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): + * This is used to select the trigger level in the receiver FIFO at which the + * Received Data Available Interrupt will be generated. In auto flow control mode + * it is used to determine when the uart_rts_n signal will be de-asserted. It also + * determines when the uart_dma_rx_req_n signal will be asserted when in certain + * modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------- + * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * one character in fifo + */ +#define ALT_UART_FCR_RT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_RT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 2 less than full + */ +#define ALT_UART_FCR_RT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_MSB 7 +/* The width in bits of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */ +#define ALT_UART_FCR_RT_RESET 0x0 +/* Extracts the ALT_UART_FCR_RT field value from a register. */ +#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */ +#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FCR. + */ +struct ALT_UART_FCR_s +{ + uint32_t fifoe : 1; /* FIFO Enable */ + uint32_t rfifor : 1; /* Rx FIFO Reset */ + uint32_t xfifor : 1; /* Tx FIFO Reset */ + uint32_t dmam : 1; /* DMA Mode */ + uint32_t tet : 2; /* Tx Empty Trigger Level */ + uint32_t rt : 2; /* Rx Trigger Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FCR. */ +typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */ +#define ALT_UART_FCR_OFST 0x8 +/* The address of the ALT_UART_FCR register. */ +#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST)) + +/* + * Register : Line Control Register (When Written) - lcr + * + * Formats serial data. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [1:0] | RW | 0x0 | Data Length Select + * [2] | RW | 0x0 | Stop Bits + * [3] | RW | 0x0 | Parity Enable + * [4] | RW | 0x0 | Even Parity Select + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Break Control Bit + * [7] | RW | 0x0 | Divisor Latch Access Bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Length Select - dls + * + * Data Length Select.Selects the number of data bits per character that the + * peripheral will transmit and receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:------------ + * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits + * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits + * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits + * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 5 bits + */ +#define ALT_UART_LCR_DLS_E_LEN5 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 6 bits + */ +#define ALT_UART_LCR_DLS_E_LEN6 0x1 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 7 bits + */ +#define ALT_UART_LCR_DLS_E_LEN7 0x2 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 8 bits + */ +#define ALT_UART_LCR_DLS_E_LEN8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_MSB 1 +/* The width in bits of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_WIDTH 2 +/* The mask used to set the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLS field value from a register. */ +#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Stop Bits - stop + * + * Number of stop bits. Used to select the number of stop bits per character that + * the peripheral will transmit and receive.Note that regardless of the number of + * stop bits selected the receiver will only check the first stop bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------ + * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit + * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * one stop bit + */ +#define ALT_UART_LCR_STOP_E_ONESTOP 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * 1.5 stop bits when DLS (LCR[1:0]) is zero + */ +#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_MSB 2 +/* The width in bits of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_RESET 0x0 +/* Extracts the ALT_UART_LCR_STOP field value from a register. */ +#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */ +#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Enable - pen + * + * This bit is used to enable and disable parity generation and detection in a + * transmitted and received data character. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:---------------- + * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled + * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity disabled + */ +#define ALT_UART_LCR_PEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity enabled + */ +#define ALT_UART_LCR_PEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_MSB 3 +/* The width in bits of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_RESET 0x0 +/* Extracts the ALT_UART_LCR_PEN field value from a register. */ +#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */ +#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Even Parity Select - eps + * + * This is used to select between even and odd parity, when parity is enabled (PEN + * set to one). If set to one, an even number of logic '1's is transmitted or + * checked. If set to zero, an odd number of logic '1's is transmitted or checked. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------ + * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity + * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * odd parity + */ +#define ALT_UART_LCR_EPS_E_ODDPAR 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * even parity + */ +#define ALT_UART_LCR_EPS_E_EVENPAR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_MSB 4 +/* The width in bits of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_RESET 0x0 +/* Extracts the ALT_UART_LCR_EPS field value from a register. */ +#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */ +#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Break Control Bit - break + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the sout line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver and the sir_out_n line is + * forced low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_MSB 6 +/* The width in bits of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_RESET 0x0 +/* Extracts the ALT_UART_LCR_BREAK field value from a register. */ +#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */ +#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Divisor Latch Access Bit - dlab + * + * Used to enable reading and writing of the Divisor Latch register (DLL and DLH) + * to set the baud rate of the UART. This bit must be cleared after initial baud + * rate setup in order to access other registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_MSB 7 +/* The width in bits of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLAB field value from a register. */ +#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LCR. + */ +struct ALT_UART_LCR_s +{ + uint32_t dls : 2; /* Data Length Select */ + uint32_t stop : 1; /* Stop Bits */ + uint32_t pen : 1; /* Parity Enable */ + uint32_t eps : 1; /* Even Parity Select */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t break_ : 1; /* Break Control Bit */ + uint32_t dlab : 1; /* Divisor Latch Access Bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LCR. */ +typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */ +#define ALT_UART_LCR_OFST 0xc +/* The address of the ALT_UART_LCR register. */ +#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST)) + +/* + * Register : Modem Control Register - mcr + * + * Reports various operations of the modem signals + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Data Terminal Ready + * [1] | RW | 0x0 | Request to Send + * [2] | RW | 0x0 | Out1 + * [3] | RW | 0x0 | out2 + * [4] | RW | 0x0 | LoopBack Bit + * [5] | RW | 0x0 | Auto Flow Control Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Terminal Ready - dtr + * + * This is used to directly control the Data Terminal Ready output. The value + * written to this location is inverted and driven out on uart_dtr_n, that is: The + * Data Terminal Ready output is used to inform the modem or data set that the UART + * is ready to establish communications. + * + * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is + * held inactive high while the value of this location is internally looped back + * to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1) + * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_DTR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n asserted (logic 0) + */ +#define ALT_UART_MCR_DTR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_MSB 0 +/* The width in bits of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_RESET 0x0 +/* Extracts the ALT_UART_MCR_DTR field value from a register. */ +#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */ +#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Request to Send - rts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled + * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1] + * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's + * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way, + * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is + * inactive high when above the threshold). The uart_rts_n signal will be de- + * asserted when MCR[1] is set low. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1) + * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_RTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n asserted (logic 0) + */ +#define ALT_UART_MCR_RTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_MSB 1 +/* The width in bits of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_RESET 0x0 +/* Extracts the ALT_UART_MCR_RTS field value from a register. */ +#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */ +#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Out1 - out1 + * + * The value written to this location is inverted and driven out on uart_out1_n + * pin. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1) + * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_MSB 2 +/* The width in bits of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */ +#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : out2 - out2 + * + * This is used to directly control the user-designated uart_out2_n output. The + * value written to this location is inverted and driven out on uart_out2_n + * + * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one, + * the uart_out2_n output is held inactive high while the value of this location is + * internally looped back to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1) + * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_MSB 3 +/* The width in bits of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */ +#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LoopBack Bit - loopback + * + * This is used to put the UART into a diagnostic mode for test purposes. If UART + * mode is NOT active, bit [6] of the modem control register MCR is set to zero, + * data on the sout line is held high, while serial data output is looped back to + * the sin line, internally. In this mode all the interrupts are fully functional. + * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n, + * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs + * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs, + * internally. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_MSB 4 +/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_RESET 0x0 +/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */ +#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */ +#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Auto Flow Control Enable - afce + * + * When FIFOs are enabled, the Auto Flow Control enable bits are active. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------------------- + * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled + * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode disabled + */ +#define ALT_UART_MCR_AFCE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode enabled + */ +#define ALT_UART_MCR_AFCE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_MSB 5 +/* The width in bits of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_RESET 0x0 +/* Extracts the ALT_UART_MCR_AFCE field value from a register. */ +#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */ +#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MCR. + */ +struct ALT_UART_MCR_s +{ + uint32_t dtr : 1; /* Data Terminal Ready */ + uint32_t rts : 1; /* Request to Send */ + uint32_t out1 : 1; /* Out1 */ + uint32_t out2 : 1; /* out2 */ + uint32_t loopback : 1; /* LoopBack Bit */ + uint32_t afce : 1; /* Auto Flow Control Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MCR. */ +typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */ +#define ALT_UART_MCR_OFST 0x10 +/* The address of the ALT_UART_MCR register. */ +#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST)) + +/* + * Register : Line Status Register - lsr + * + * Reports status of transmit and receive. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Data Ready bit + * [1] | R | 0x0 | Overrun error + * [2] | R | 0x0 | Parity Error + * [3] | R | 0x0 | Framing Error + * [4] | R | 0x0 | Break Interrupt + * [5] | R | 0x1 | Transmit Holding Register Empty bit + * [6] | R | 0x1 | Transmitter Empty bit + * [7] | R | 0x0 | Receiver FIFO Error bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Ready bit - dr + * + * This is used to indicate that the receiver contains at least one character in + * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the + * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------- + * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready + * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * no data ready + */ +#define ALT_UART_LSR_DR_E_NODATARDY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * data ready + */ +#define ALT_UART_LSR_DR_E_DATARDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_MSB 0 +/* The width in bits of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_RESET 0x0 +/* Extracts the ALT_UART_LSR_DR field value from a register. */ +#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */ +#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Overrun error - oe + * + * This is used to indicate the occurrence of an overrun error. This occurs if a + * new data character was received before the previous data was read. In the non- + * FIFO mode, the OE bit is set when a new character arrives in the receiver before + * the previous character was read from the RBR. When this happens, the data in the + * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is + * full and new character arrives at the receiver. The data in the FIFO is retained + * and the data in the receive shift register is lost.Reading the LSR clears the OE + * bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------- + * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error + * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * no overrun error + */ +#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * overrun error + */ +#define ALT_UART_LSR_OE_E_OVERRUN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_MSB 1 +/* The width in bits of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_RESET 0x0 +/* Extracts the ALT_UART_LSR_OE field value from a register. */ +#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */ +#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Error - pe + * + * This is used to indicate the occurrence of a parity error in the receiver if the + * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated + * with a character received, it is revealed when the character with the parity + * error arrives at the top of the FIFO. It should be noted that the Parity Error + * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by + * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------- + * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error + * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_PARITYERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_MSB 2 +/* The width in bits of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_RESET 0x0 +/* Extracts the ALT_UART_LSR_PE field value from a register. */ +#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */ +#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Framing Error - fe + * + * This is used to indicate the occurrence of a framing error in the receiver. A + * framing error occurs when the receiver does not detect a valid STOP bit in the + * received data. In the FIFO mode, since the framing error is associated with a + * character received, it is revealed when the character with the framing error is + * at the top of the FIFO. When a framing error occurs the UART will try to + * resynchronize. It does this by assuming that the error was due to the start bit + * of the next character and then continues receiving the other bit i.e. data, + * and/or parity and stop. It should be noted that the Framing Error (FE) + * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a + * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------- + * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error + * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * no framing error + */ +#define ALT_UART_LSR_FE_E_NOFRMERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * framing error + */ +#define ALT_UART_LSR_FE_E_FRMERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_MSB 3 +/* The width in bits of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_RESET 0x0 +/* Extracts the ALT_UART_LSR_FE field value from a register. */ +#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */ +#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Break Interrupt - bi + * + * This is used to indicate the detection of a break sequence on the serial input + * data. Set whenever the serial input, sin, is held in a logic 0 state for longer + * than the sum of start time + data bits + parity + stop bits. A break condition + * on serial input causes one and only one character, consisting of all zeros, to + * be received by the UART. The character associated with the break condition is + * carried through the FIFO and is revealed when the character is at the top of the + * FIFO. Reading the LSR clears the BI bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_MSB 4 +/* The width in bits of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_RESET 0x0 +/* Extracts the ALT_UART_LSR_BI field value from a register. */ +#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */ +#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmit Holding Register Empty bit - thre + * + * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or + * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or + * Tx FIFO to the transmitter shift register and no new data has been written to + * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE + * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to + * one and FCR[0] set to one respectively), the functionality will indicate the + * transmitter FIFO is full, and no longer controls THRE interrupts, which are then + * controlled by the FCR[5:4] thresholdsetting. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_MSB 5 +/* The width in bits of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_RESET 0x1 +/* Extracts the ALT_UART_LSR_THRE field value from a register. */ +#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */ +#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transmitter Empty bit - temt + * + * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever + * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are + * disabled, this bit is set whenever the Transmitter Holding Register and the + * Transmitter Shift Register are both empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------- + * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set + * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty not set + */ +#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty set + */ +#define ALT_UART_LSR_TEMT_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_MSB 6 +/* The width in bits of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_RESET 0x1 +/* Extracts the ALT_UART_LSR_TEMT field value from a register. */ +#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */ +#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receiver FIFO Error bit - rfe + * + * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is + * used to indicate if there is at least one parity error, framing error, or break + * indication in the FIFO. This bit is cleared when the LSR is read and the + * character with the error is at the top of the receiver FIFO and there are no + * subsequent errors in the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------- + * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO + * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * no error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_NOERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_ERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_MSB 7 +/* The width in bits of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_RESET 0x0 +/* Extracts the ALT_UART_LSR_RFE field value from a register. */ +#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */ +#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LSR. + */ +struct ALT_UART_LSR_s +{ + const uint32_t dr : 1; /* Data Ready bit */ + const uint32_t oe : 1; /* Overrun error */ + const uint32_t pe : 1; /* Parity Error */ + const uint32_t fe : 1; /* Framing Error */ + const uint32_t bi : 1; /* Break Interrupt */ + const uint32_t thre : 1; /* Transmit Holding Register Empty bit */ + const uint32_t temt : 1; /* Transmitter Empty bit */ + const uint32_t rfe : 1; /* Receiver FIFO Error bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LSR. */ +typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */ +#define ALT_UART_LSR_OFST 0x14 +/* The address of the ALT_UART_LSR register. */ +#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST)) + +/* + * Register : Modem Status Register - msr + * + * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to + * indicate a change on the modem control inputs, a modem status interrupt will be + * generated if enabled via the IER regardless of when the change occurred. Since + * the delta bits (bits 0, 1, 3) can get set after a reset if their respective + * modem signals are active (see individual bits for details), a read of the MSR + * after reset can be performed to prevent unwanted interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | R | 0x0 | Delta Clear to Send + * [1] | R | 0x0 | Delta Data Set Ready + * [2] | R | 0x0 | Trailing Edge of Ring Indicator + * [3] | R | 0x0 | Delta Data Carrier Detect + * [4] | R | 0x0 | Clear to Send + * [5] | R | 0x0 | Data Set Ready + * [6] | R | 0x0 | Ring Indicator + * [7] | R | 0x0 | Data Carrier Detect + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Delta Clear to Send - dcts + * + * This is used to indicate that the modem control line uart_cts_n has changed + * since the last time the MSR was read. That is: Reading the MSR clears the DCTS + * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit + * [1] RTS of register MCR. + * + * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DCTS bit will get set when the + * reset is removed if the uart_cts_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR + * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * no change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_MSB 0 +/* The width in bits of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCTS field value from a register. */ +#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Delta Data Set Ready - ddsr + * + * This is used to indicate that the modem control line uart_dsr_n has changed + * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In + * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of + * register MCR . + * + * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDSR bit will get set when the + * reset is removed if the uart_dsr_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR + * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * no change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_MSB 1 +/* The width in bits of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDSR field value from a register. */ +#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Trailing Edge of Ring Indicator - teri + * + * This is used to indicate that a change on the input uart_ri_n (from an active + * low, to an inactive high state) has occurred since the last time the MSR was + * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register + * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state + * from a high to a low. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------------------------- + * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR + * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * no change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_MSB 2 +/* The width in bits of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_RESET 0x0 +/* Extracts the ALT_UART_MSR_TERI field value from a register. */ +#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */ +#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Delta Data Carrier Detect - ddcd + * + * This is used to indicate that the modem control line dcd_n has changed since the + * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback + * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3] + * uart_out2 of register MCR. + * + * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDCD bit will get set when the + * reset is removed if the uart_dcd_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR + * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * no change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_MSB 3 +/* The width in bits of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDCD field value from a register. */ +#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear to Send - cts + * + * This is used to indicate the current state of the modem control line uart_cts_n. + * That is, this bit is the complement uart_cts_n. When the Clear to Send input + * (uart_cts_n) is asserted it is an indication that the modem or data set is ready + * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set + * to one, CTS is the same as bit [1] RTS of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1) + * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_CTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_CTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_MSB 4 +/* The width in bits of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_CTS field value from a register. */ +#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Data Set Ready - dsr + * + * This is used to indicate the current state of the modem control line uart_dsr_n. + * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input + * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready + * to establish communications with the uart. In Loopback Mode bit [4] of register + * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1) + * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DSR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DSR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_MSB 5 +/* The width in bits of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DSR field value from a register. */ +#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Ring Indicator - ri + * + * This bit is used to indicate the current state of the modem control line + * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator + * input (uart_ri_n) is asserted it is an indication that a telephone ringing + * signal has been received by the modem or data set. In Loopback Mode bit [4] of + * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------------------------------- + * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1) + * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_RI_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_RI_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_MSB 6 +/* The width in bits of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_RESET 0x0 +/* Extracts the ALT_UART_MSR_RI field value from a register. */ +#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */ +#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data Carrier Detect - dcd + * + * This is used to indicate the current state of the modem control line uart_dcd_n. + * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect + * input (uart_dcd_n) is asserted it is an indication that the carrier has been + * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is + * the same as MCR[3] (uart_out2). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1) + * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DCD_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DCD_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_MSB 7 +/* The width in bits of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCD field value from a register. */ +#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MSR. + */ +struct ALT_UART_MSR_s +{ + const uint32_t dcts : 1; /* Delta Clear to Send */ + const uint32_t ddsr : 1; /* Delta Data Set Ready */ + const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */ + const uint32_t ddcd : 1; /* Delta Data Carrier Detect */ + const uint32_t cts : 1; /* Clear to Send */ + const uint32_t dsr : 1; /* Data Set Ready */ + const uint32_t ri : 1; /* Ring Indicator */ + const uint32_t dcd : 1; /* Data Carrier Detect */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MSR. */ +typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */ +#define ALT_UART_MSR_OFST 0x18 +/* The address of the ALT_UART_MSR register. */ +#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) + +/* + * Register : Scratchpad Register - scr + * + * Scratchpad Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [7:0] | RW | 0x0 | Scratchpad Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Scratchpad Register - scr + * + * This register is for programmers to use as a temporary storage space. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_MSB 7 +/* The width in bits of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_WIDTH 8 +/* The mask used to set the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_RESET 0x0 +/* Extracts the ALT_UART_SCR_SCR field value from a register. */ +#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */ +#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SCR. + */ +struct ALT_UART_SCR_s +{ + uint32_t scr : 8; /* Scratchpad Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SCR. */ +typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */ +#define ALT_UART_SCR_OFST 0x1c +/* The address of the ALT_UART_SCR register. */ +#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST)) + +/* + * Register : Shadow Receive Buffer Register - srbr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [7:0] | RW | 0x0 | Shadow Receive Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Receive Buffer - srbr + * + * This is a shadow register for the RBR and has been allocated one 32-bit location + * so as to accommodate burst accesses from the master.This register contains the + * data byte received on the serial input port (sin). The data in this register is + * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. + * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR + * must be read before the next data arrives, otherwise it will be overwritten, + * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this + * register accesses the head of the receive FIFO. If the receive FIFO is full and + * this register is not read before the next data character arrives, then the data + * already in the FIFO will be preserved but any incoming data will be lost. An + * overrun error will also occur. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_MSB 7 +/* The width in bits of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_WIDTH 8 +/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_RESET 0x0 +/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */ +#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */ +#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRBR. + */ +struct ALT_UART_SRBR_s +{ + uint32_t srbr : 8; /* Shadow Receive Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRBR. */ +typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */ +#define ALT_UART_SRBR_OFST 0x30 +/* The address of the ALT_UART_SRBR register. */ +#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST)) + +/* + * Register : Shadow Transmit Buffer Register - sthr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [7:0] | RW | 0x0 | Shadow Transmit Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Transmit Buffer - sthr + * + * This is a shadow register for the THR and has been allocated sixteen 32-bit + * locations so as to accommodate burst accesses from the master. This register + * contains data to be transmitted on the serial output port (sout). Data should + * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If + * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing + * a single character to the THR clears the THRE. Any additional writes to the THR + * before the THRE is set again causes the THR data to be overwritten. If FIFO's + * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters + * of data may be written to the THR before the FIFO is full. The UART FIFO depth + * is configured for 128 characters. Any attempt to write data when the FIFO is + * full results in the write data being lost. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_MSB 7 +/* The width in bits of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_WIDTH 8 +/* The mask used to set the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_RESET 0x0 +/* Extracts the ALT_UART_STHR_STHR field value from a register. */ +#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */ +#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STHR. + */ +struct ALT_UART_STHR_s +{ + uint32_t sthr : 8; /* Shadow Transmit Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STHR. */ +typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */ +#define ALT_UART_STHR_OFST 0x34 +/* The address of the ALT_UART_STHR register. */ +#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST)) + +/* + * Register : FIFO Access Register - far + * + * This register is used in FIFO access testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | FIFO ACCESS Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO ACCESS Bit - srbr_sthr + * + * This register is used to enable a FIFO access mode for testing, so that the + * receive FIFO can be written by the master and the transmit FIFO can be read by + * the master when FIFO's are enabled. When FIFO's are not enabled it allows the + * RBR to be written by the master and the THR to be read by the master + * + * Note: That when the FIFO access mode is enabled/disabled, the control portion of + * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:-------------------------- + * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled + * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode disabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode enabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_MSB 0 +/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_WIDTH 1 +/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_RESET 0x0 +/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */ +#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */ +#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FAR. + */ +struct ALT_UART_FAR_s +{ + uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FAR. */ +typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */ +#define ALT_UART_FAR_OFST 0x70 +/* The address of the ALT_UART_FAR register. */ +#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST)) + +/* + * Register : Transmit FIFO Read Register - tfr + * + * Used in FIFO Access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [7:0] | R | 0x0 | Transmit FIFO Read + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Read - tfr + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, reading this register gives the data at the top + * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the + * next data value that is currently at the top of the FIFO. When FIFO's are not + * enabled, reading this register gives the data in the THR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_MSB 7 +/* The width in bits of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_WIDTH 8 +/* The mask used to set the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_RESET 0x0 +/* Extracts the ALT_UART_TFR_TFR field value from a register. */ +#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */ +#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFR. + */ +struct ALT_UART_TFR_s +{ + const uint32_t tfr : 8; /* Transmit FIFO Read */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFR. */ +typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */ +#define ALT_UART_TFR_OFST 0x74 +/* The address of the ALT_UART_TFR register. */ +#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST)) + +/* + * Register : Receive FIFO Write - RFW + * + * Used only with FIFO access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [7:0] | W | 0x0 | Receive FIFO Write Field + * [8] | W | 0x0 | Receive FIFO Parity Error + * [9] | W | 0x0 | Receive FIFO Framing Error + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Write Field - rfwd + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, the data that is written to the RFWD is pushed + * into the receive FIFO. Each consecutive write pushes the new data to the next + * write location in the receive FIFO. When FIFO's are not enabled, the data that + * is written to the RFWD is pushed into the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_MSB 7 +/* The width in bits of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_WIDTH 8 +/* The mask used to set the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFWD field value from a register. */ +#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Receive FIFO Parity Error - rfpe + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write parity error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write parity error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_MSB 8 +/* The width in bits of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFPE field value from a register. */ +#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive FIFO Framing Error - RFFE + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write framing error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write framing error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_MSB 9 +/* The width in bits of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFFE field value from a register. */ +#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFW. + */ +struct ALT_UART_RFW_s +{ + uint32_t rfwd : 8; /* Receive FIFO Write Field */ + uint32_t rfpe : 1; /* Receive FIFO Parity Error */ + uint32_t RFFE : 1; /* Receive FIFO Framing Error */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFW. */ +typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */ +#define ALT_UART_RFW_OFST 0x78 +/* The address of the ALT_UART_RFW register. */ +#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST)) + +/* + * Register : UART Status Register - usr + * + * Status of FIFO Operations. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | R | 0x1 | Transmit FIFO Not Full + * [2] | R | 0x1 | Transmit FIFO Empty + * [3] | R | 0x0 | Receive FIFO Not Empty + * [4] | R | 0x0 | Receive FIFO Full + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Not Full - tfnf + * + * This Bit is used to indicate that the transmit FIFO in not full. This bit is + * cleared when the Tx FIFO is full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_UART_USR_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_MSB 1 +/* The width in bits of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_RESET 0x1 +/* Extracts the ALT_UART_USR_TFNF field value from a register. */ +#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */ +#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit FIFO Empty - tfe + * + * This is used to indicate that the transmit FIFO is completely empty. This bit is + * cleared when the Tx FIFO is no longer empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is empty + */ +#define ALT_UART_USR_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_MSB 2 +/* The width in bits of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_RESET 0x1 +/* Extracts the ALT_UART_USR_TFE field value from a register. */ +#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */ +#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Not Empty - rfne + * + * This Bit is used to indicate that the receive FIFO contains one or more entries. + * This bit is cleared when the Rx FIFO is empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty + * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receiive FIFO is empty + */ +#define ALT_UART_USR_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_MSB 3 +/* The width in bits of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_RESET 0x0 +/* Extracts the ALT_UART_USR_RFNE field value from a register. */ +#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */ +#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full - rff + * + * This Bit is used to indicate that the receive FIFO is completely full. This bit + * is cleared when the Rx FIFO is no longer full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------- + * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full + * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Receiive FIFO not full + */ +#define ALT_UART_USR_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_MSB 4 +/* The width in bits of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_RESET 0x0 +/* Extracts the ALT_UART_USR_RFF field value from a register. */ +#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */ +#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_USR. + */ +struct ALT_UART_USR_s +{ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ + const uint32_t tfe : 1; /* Transmit FIFO Empty */ + const uint32_t rfne : 1; /* Receive FIFO Not Empty */ + const uint32_t rff : 1; /* Receive FIFO Full */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_USR. */ +typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_USR register from the beginning of the component. */ +#define ALT_UART_USR_OFST 0x7c +/* The address of the ALT_UART_USR register. */ +#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST)) + +/* + * Register : Transmit FIFO Level - tfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [4:0] | R | 0x0 | Transmit FIFO Level + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level - tfl + * + * This indicates the number of data entries in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_MSB 4 +/* The width in bits of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_WIDTH 5 +/* The mask used to set the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_RESET 0x0 +/* Extracts the ALT_UART_TFL_TFL field value from a register. */ +#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */ +#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFL. + */ +struct ALT_UART_TFL_s +{ + const uint32_t tfl : 5; /* Transmit FIFO Level */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFL. */ +typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */ +#define ALT_UART_TFL_OFST 0x80 +/* The address of the ALT_UART_TFL register. */ +#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST)) + +/* + * Register : Receive FIFO Level Write - rfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [4:0] | R | 0x0 | Receive FIFO Level Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Status - rfl + * + * This indicates the number of data entries in the receive FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_MSB 4 +/* The width in bits of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_WIDTH 5 +/* The mask used to set the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_RESET 0x0 +/* Extracts the ALT_UART_RFL_RFL field value from a register. */ +#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */ +#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFL. + */ +struct ALT_UART_RFL_s +{ + const uint32_t rfl : 5; /* Receive FIFO Level Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFL. */ +typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */ +#define ALT_UART_RFL_OFST 0x84 +/* The address of the ALT_UART_RFL register. */ +#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST)) + +/* + * Register : Software Reset Register - srr + * + * Provides Software Resets for Tx/Rx FIFO's and the uart. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [0] | W | 0x0 | UART Reset + * [1] | W | 0x0 | Rx FIFO Reset + * [2] | W | 0x0 | Tx FIFO Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : UART Reset - ur + * + * This asynchronously resets the UART and synchronously removes the reset + * assertion. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart + * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * No reset Uart + */ +#define ALT_UART_SRR_UR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * Reset Uart + */ +#define ALT_UART_SRR_UR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_MSB 0 +/* The width in bits of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_RESET 0x0 +/* Extracts the ALT_UART_SRR_UR field value from a register. */ +#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */ +#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfr + * + * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the receive FIFO. This resets the + * control portion of the receive FIFO and treats the FIFO as empty. This will also + * de-assert the DMA Rx request and single signals. Note that this bit is 'self- + * clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO + * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * No reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * Reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_MSB 1 +/* The width in bits of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_RFR field value from a register. */ +#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfr + * + * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the transmit FIFO.This resets the + * control portion of the transmit FIFO and treats the FIFO as empty. This will + * also de-assert the DMA Tx request and single signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO + * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * No reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * Reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_MSB 2 +/* The width in bits of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_XFR field value from a register. */ +#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRR. + */ +struct ALT_UART_SRR_s +{ + uint32_t ur : 1; /* UART Reset */ + uint32_t rfr : 1; /* Rx FIFO Reset */ + uint32_t xfr : 1; /* Tx FIFO Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRR. */ +typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */ +#define ALT_UART_SRR_OFST 0x88 +/* The address of the ALT_UART_SRR register. */ +#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) + +/* + * Register : Shadow Request to Send - srts + * + * This is a shadow register for the RTS status (MCR[1]), this can be used to + * remove the burden of having to performing a read modify write on the MCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | RW | 0x0 | Shadow Request to Send + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Request to Send - srts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is read to exchange data. The uart_rts_n signal is set low by + * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one) + * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled + * in the same way, but is also gated with the receiver FIFO threshold trigger + * (uart_rts_n is inactive high when above the threshold). + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0 + * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic0 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1 +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic1 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_MSB 0 +/* The width in bits of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_WIDTH 1 +/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_RESET 0x0 +/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */ +#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */ +#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRTS. + */ +struct ALT_UART_SRTS_s +{ + uint32_t srts : 1; /* Shadow Request to Send */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRTS. */ +typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */ +#define ALT_UART_SRTS_OFST 0x8c +/* The address of the ALT_UART_SRTS register. */ +#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST)) + +/* + * Register : Shadow Break Control Register - sbcr + * + * This is a shadow register for the Break bit [6] of the register LCR. This can be + * used to remove the burden of having to performing a read modify write on the + * LCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x0 | Shadow Break Control + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Break Control - sbcr + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------- + * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break + * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * no break + */ +#define ALT_UART_SBCR_SBCR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * break serial output spacing + */ +#define ALT_UART_SBCR_SBCR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_MSB 0 +/* The width in bits of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_WIDTH 1 +/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_RESET 0x0 +/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */ +#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */ +#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SBCR. + */ +struct ALT_UART_SBCR_s +{ + uint32_t sbcr : 1; /* Shadow Break Control */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SBCR. */ +typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */ +#define ALT_UART_SBCR_OFST 0x90 +/* The address of the ALT_UART_SBCR register. */ +#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST)) + +/* + * Register : Shadow DMA Mode - sdmam + * + * This is a shadow register for the DMA mode bit (FCR[3]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | Shadow DMA Mode + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow DMA Mode - sdmam + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the DMA + * Mode bit gets updated. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------- + * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_MSB 0 +/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_WIDTH 1 +/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_RESET 0x0 +/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */ +#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */ +#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SDMAM. + */ +struct ALT_UART_SDMAM_s +{ + uint32_t sdmam : 1; /* Shadow DMA Mode */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SDMAM. */ +typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */ +#define ALT_UART_SDMAM_OFST 0x94 +/* The address of the ALT_UART_SDMAM register. */ +#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST)) + +/* + * Register : Shadow FIFO Enable - sfe + * + * This is a shadow register for the FIFO enable bit [0] of register FCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [0] | RW | 0x0 | Shadow FIFO Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow FIFO Enable - sfe + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the FIFO + * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx + * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both + * the Tx and Rx controller portion of FIFO's will be reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx + * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Disable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Enable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_MSB 0 +/* The width in bits of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_WIDTH 1 +/* The mask used to set the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_RESET 0x0 +/* Extracts the ALT_UART_SFE_SFE field value from a register. */ +#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */ +#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SFE. + */ +struct ALT_UART_SFE_s +{ + uint32_t sfe : 1; /* Shadow FIFO Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SFE. */ +typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */ +#define ALT_UART_SFE_OFST 0x98 +/* The address of the ALT_UART_SFE register. */ +#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST)) + +/* + * Register : Shadow Rx Trigger - srt + * + * This is a shadow register for the Rx trigger bits (FCR[7:6]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Rx Trigger Bits - srt + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Rx + * trigger bit gets updated. This is used to select the trigger level in the + * receiver FIFO at which the Received Data Available Interrupt will be generated. + * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA + * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are + * supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * one character in fifo + */ +#define ALT_UART_SRT_SRT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/4 full + */ +#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/2 full + */ +#define ALT_UART_SRT_SRT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 2 less than full + */ +#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_MSB 1 +/* The width in bits of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_WIDTH 2 +/* The mask used to set the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_RESET 0x0 +/* Extracts the ALT_UART_SRT_SRT field value from a register. */ +#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */ +#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRT. + */ +struct ALT_UART_SRT_s +{ + uint32_t srt : 2; /* Shadow Rx Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRT. */ +typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */ +#define ALT_UART_SRT_OFST 0x9c +/* The address of the ALT_UART_SRT register. */ +#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST)) + +/* + * Register : Shadow Tx Empty Trigger - stet + * + * This is a shadow register for the Tx empty trigger bits (FCR[5:4]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Tx Empty Trigger Bits - stet + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Tx + * empty trigger bit gets updated. This is used to select the empty threshold level + * at which the THRE Interrupts will be generated when the mode is active. These + * threshold levels are also described in. The enum trigger levels are supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full + * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO empty + */ +#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * Two characters in FIFO + */ +#define ALT_UART_STET_STET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO quarter full + */ +#define ALT_UART_STET_STET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO half full + */ +#define ALT_UART_STET_STET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_MSB 1 +/* The width in bits of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_WIDTH 2 +/* The mask used to set the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_RESET 0x0 +/* Extracts the ALT_UART_STET_STET field value from a register. */ +#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */ +#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STET. + */ +struct ALT_UART_STET_s +{ + uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STET. */ +typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STET register from the beginning of the component. */ +#define ALT_UART_STET_OFST 0xa0 +/* The address of the ALT_UART_STET register. */ +#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST)) + +/* + * Register : Halt Tx - htx + * + * Used to halt transmission for testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Halt Tx Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Halt Tx Bits - htx + * + * This register is use to halt transmissions for testing, so that the transmit + * FIFO can be filled by the master when FIFO's are enabled. + * + * Note, if FIFO's are not enabled, the setting of the halt Tx register will have + * no effect on operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:----------------- + * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled + * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx disabled + */ +#define ALT_UART_HTX_HTX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx enabled + */ +#define ALT_UART_HTX_HTX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_MSB 0 +/* The width in bits of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_WIDTH 1 +/* The mask used to set the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_RESET 0x0 +/* Extracts the ALT_UART_HTX_HTX field value from a register. */ +#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */ +#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_HTX. + */ +struct ALT_UART_HTX_s +{ + uint32_t htx : 1; /* Halt Tx Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_HTX. */ +typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */ +#define ALT_UART_HTX_OFST 0xa4 +/* The address of the ALT_UART_HTX register. */ +#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST)) + +/* + * Register : DMA Software Acknowledge - dmasa + * + * DMA Operation Control + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | W | 0x0 | DMA Software Acknowledge Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Software Acknowledge Bits - dmasa + * + * This register is used to perform DMA software acknowledge if a transfer needs to + * be terminated due to an error condition. For example, if the DMA disables the + * channel, then the uart should clear its request. This will cause the Tx request, + * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is + * 'self-clearing' and it is not necessary to clear this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_MSB 0 +/* The width in bits of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_WIDTH 1 +/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_RESET 0x0 +/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */ +#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */ +#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_DMASA. + */ +struct ALT_UART_DMASA_s +{ + uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_DMASA. */ +typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */ +#define ALT_UART_DMASA_OFST 0xa8 +/* The address of the ALT_UART_DMASA register. */ +#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST)) + +/* + * Register : Component Parameter Register - cpr + * + * Describes various fixed hardware setups states. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x1 | Auto Flow Control + * [5] | R | 0x1 | THRE MODE + * [6] | R | 0x0 | SIR MODE Unsupported + * [7] | R | 0x0 | SIR LP MODE Unsupported + * [8] | R | 0x1 | ADDITIONAL FEATURES Supported + * [9] | R | 0x1 | FIFO ACCESS Supported + * [10] | R | 0x1 | FIFO STAT Supported + * [11] | R | 0x1 | SHADOW Supported + * [12] | R | 0x1 | Configuartion ID Register Present + * [13] | R | 0x1 | DMA EXTRA Supported + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [23:16] | R | 0x37 | FIFO Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apbdatawidth + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_MSB 1 +/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 +/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */ +#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Auto Flow Control - afce_mode + * + * Allows auto flow control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------ + * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_AFCE_MOD + * + * Auto Flow + */ +#define ALT_UART_CPR_AFCE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_MSB 4 +/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */ +#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : THRE MODE - thre_mode + * + * Programmable Transmitter Hold Register Empty interrupt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------------ + * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt + * : | | present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_THRE_MOD + * + * Programmable Tx Hold Reg. Empty interrupt present + */ +#define ALT_UART_CPR_THRE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_MSB 5 +/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */ +#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SIR MODE Unsupported - sir_mode + * + * Sir mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------- + * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_MOD + * + * Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_MSB 6 +/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SIR LP MODE Unsupported - sir_lp_mode + * + * LP Sir Mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------- + * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD + * + * LP Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_MSB 7 +/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : ADDITIONAL FEATURES Supported - additional_feat + * + * Configures the uart to include fifo status register, shadow registers and + * encoded parameter register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------ + * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT + * + * Additional Features Supported + */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 +/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FIFO ACCESS Supported - fifo_access + * + * Configures the peripheral to have a programmable FIFO access mode. This is used + * for test purposes, to allow the receiver FIFO to be written and the transmit + * FIFO to be read when FIFOs are implemented and enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS + * + * FIFO Access Supported + */ +#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_MSB 9 +/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */ +#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FIFO STAT Supported - fifo_stat + * + * Configures the peripheral to have three additional FIFO status registers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_STAT + * + * FIFO Stat Supported + */ +#define ALT_UART_CPR_FIFO_STAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_MSB 10 +/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */ +#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SHADOW Supported - shadow + * + * Configures the peripheral to have seven additional registers that shadow some of + * the existing register bits that are regularly modified by software. These can be + * used to reduce the software overhead that is introduced by having to perform + * read-modify writes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------- + * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SHADOW + * + * Shadow Supported + */ +#define ALT_UART_CPR_SHADOW_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_MSB 11 +/* The width in bits of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 +/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_RESET 0x1 +/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */ +#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */ +#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Configuartion ID Register Present - uart_add_encoded_param + * + * Configures the peripheral to have a configuration identification register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM + * + * ID register present + */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 +/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff +/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 +/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : DMA EXTRA Supported - dma_extra + * + * Configures the peripheral to have four additional DMA signals on the interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA + * + * DMA Extra Supported + */ +#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_MSB 13 +/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 +/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff +/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1 +/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */ +#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */ +#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : FIFO Depth - fifo_mode + * + * Receiver and Transmitter FIFO depth in bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_MOD + * + * FIFO Depth 128 bytes + */ +#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_MSB 23 +/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_WIDTH 8 +/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff +/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_RESET 0x37 +/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */ +#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CPR. + */ +struct ALT_UART_CPR_s +{ + const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t afce_mode : 1; /* Auto Flow Control */ + const uint32_t thre_mode : 1; /* THRE MODE */ + const uint32_t sir_mode : 1; /* SIR MODE Unsupported */ + const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */ + const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */ + const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */ + const uint32_t fifo_stat : 1; /* FIFO STAT Supported */ + const uint32_t shadow : 1; /* SHADOW Supported */ + const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */ + const uint32_t dma_extra : 1; /* DMA EXTRA Supported */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifo_mode : 8; /* FIFO Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_CPR. */ +typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */ +#define ALT_UART_CPR_OFST 0xf4 +/* The address of the ALT_UART_CPR register. */ +#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) + +/* + * Register : Component Version - ucv + * + * Used only with Additional Features + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x3331312a | ASCII version + * + */ +/* + * Field : ASCII version - uart_component_version + * + * ASCII value for each number in the version, followed by *For example 32_30_31_2A + * represents the version 2.01a + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31 +/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32 +/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a +/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_UCV. + */ +struct ALT_UART_UCV_s +{ + const uint32_t uart_component_version : 32; /* ASCII version */ +}; + +/* The typedef declaration for register ALT_UART_UCV. */ +typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */ +#define ALT_UART_UCV_OFST 0xf8 +/* The address of the ALT_UART_UCV register. */ +#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST)) + +/* + * Register : Component Type Register - ctr + * + * Describes a hex value associated with the component. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x44570110 | Peripheral ID + * + */ +/* + * Field : Peripheral ID - peripheral_id + * + * This register contains the peripherals identification code. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31 +/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32 +/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110 +/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CTR. + */ +struct ALT_UART_CTR_s +{ + const uint32_t peripheral_id : 32; /* Peripheral ID */ +}; + +/* The typedef declaration for register ALT_UART_CTR. */ +typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */ +#define ALT_UART_CTR_OFST 0xfc +/* The address of the ALT_UART_CTR register. */ +#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_UART. + */ +struct ALT_UART_s +{ + volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */ + volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */ + volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */ + volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */ + volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */ + volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */ + volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */ + volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */ + volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */ + volatile ALT_UART_USR_t usr; /* ALT_UART_USR */ + volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */ + volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */ + volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */ + volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */ + volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */ + volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */ + volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */ + volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */ + volatile ALT_UART_STET_t stet; /* ALT_UART_STET */ + volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */ + volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */ + volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */ + volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for register group ALT_UART. */ +typedef volatile struct ALT_UART_s ALT_UART_t; +/* The struct declaration for the raw register contents of register group ALT_UART. */ +struct ALT_UART_raw_s +{ + volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile uint32_t iir; /* ALT_UART_IIR */ + volatile uint32_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile uint32_t lcr; /* ALT_UART_LCR */ + volatile uint32_t mcr; /* ALT_UART_MCR */ + volatile uint32_t lsr; /* ALT_UART_LSR */ + volatile uint32_t msr; /* ALT_UART_MSR */ + volatile uint32_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile uint32_t srbr; /* ALT_UART_SRBR */ + volatile uint32_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile uint32_t far; /* ALT_UART_FAR */ + volatile uint32_t tfr; /* ALT_UART_TFR */ + volatile uint32_t RFW; /* ALT_UART_RFW */ + volatile uint32_t usr; /* ALT_UART_USR */ + volatile uint32_t tfl; /* ALT_UART_TFL */ + volatile uint32_t rfl; /* ALT_UART_RFL */ + volatile uint32_t srr; /* ALT_UART_SRR */ + volatile uint32_t srts; /* ALT_UART_SRTS */ + volatile uint32_t sbcr; /* ALT_UART_SBCR */ + volatile uint32_t sdmam; /* ALT_UART_SDMAM */ + volatile uint32_t sfe; /* ALT_UART_SFE */ + volatile uint32_t srt; /* ALT_UART_SRT */ + volatile uint32_t stet; /* ALT_UART_STET */ + volatile uint32_t htx; /* ALT_UART_HTX */ + volatile uint32_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile uint32_t cpr; /* ALT_UART_CPR */ + volatile uint32_t ucv; /* ALT_UART_UCV */ + volatile uint32_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_UART. */ +typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_UART_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h new file mode 100644 index 0000000000..c6b312b415 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h @@ -0,0 +1,8026 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - hps */ + +#ifndef __ALTERA_HPS_H__ +#define __ALTERA_HPS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#define ALT_HPS_ADDR 0 +/* + * Address Space : ALT_HPS + * + */ +/* + * Component Instance : stm + * + * Instance stm of component ALT_STM. + * + * + */ +/* The address of the ALT_STM_REG register for the ALT_STM instance. */ +#define ALT_STM_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_STM_ADDR) + ALT_STM_REG_OFST)) +/* The base address byte offset for the start of the ALT_STM component. */ +#define ALT_STM_OFST 0xfc000000 +/* The start address of the ALT_STM component. */ +#define ALT_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_STM_OFST)) +/* The lower bound address range of the ALT_STM component. */ +#define ALT_STM_LB_ADDR ALT_STM_ADDR +/* The upper bound address range of the ALT_STM component. */ +#define ALT_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_STM_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dap + * + * Instance dap of component ALT_DAP. + * + * + */ +/* The address of the ALT_DAP_REG register for the ALT_DAP instance. */ +#define ALT_DAP_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DAP_ADDR) + ALT_DAP_REG_OFST)) +/* The base address byte offset for the start of the ALT_DAP component. */ +#define ALT_DAP_OFST 0xff000000 +/* The start address of the ALT_DAP component. */ +#define ALT_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DAP_OFST)) +/* The lower bound address range of the ALT_DAP component. */ +#define ALT_DAP_LB_ADDR ALT_DAP_ADDR +/* The upper bound address range of the ALT_DAP component. */ +#define ALT_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DAP_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : lwfpgaslaves + * + * Instance lwfpgaslaves of component ALT_LWFPGASLVS. + * + * + */ +/* The base address byte offset for the start of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_OFST 0xff200000 +/* The start address of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWFPGASLVS_OFST)) +/* The lower bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_LB_ADDR ALT_LWFPGASLVS_ADDR +/* The upper bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWFPGASLVS_ADDR) + 0x200000) - 1)) + + +/* + * Component Instance : lwhps2fpgaregs + * + * Instance lwhps2fpgaregs of component ALT_LWH2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_LWH2F_ID. + * + * + */ +/* The address of the ALT_LWH2F_ID_PERIPH_ID_4 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_OFST 0x1000 +/* The start address of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_ID_OFST)) +/* The lower bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_LB_ADDR ALT_LWH2F_ID_ADDR +/* The upper bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_LWH2F_MST. + * + * + */ +/* + * Register Group Instance : mastergrp_fpga2hpsregs + * + * Instance mastergrp_fpga2hpsregs of register group ALT_LWH2F_MST_F2H. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_OFST 0x0 +/* The start address of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_F2H_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_LB_ADDR ALT_LWH2F_MST_MST_F2H_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_F2H_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpgaregs + * + * Instance mastergrp_hps2fpgaregs of register group ALT_LWH2F_MST_H2F. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_OFST 0x1000 +/* The start address of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_LB_ADDR ALT_LWH2F_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_H2F_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_LWH2F_MST_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_WR_TIDEMARK register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_WR_TIDEMARK_ADDR ALT_LWH2F_WR_TIDEMARK_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_LB_ADDR ALT_LWH2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_OFST 0x2000 +/* The start address of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_MST_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_LB_ADDR ALT_LWH2F_MST_ADDR +/* The upper bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + 0x310c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_LWH2F_SLV. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_LWH2F_SLV_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_SLV_SLV_B32 instance. */ +#define ALT_LWH2F_SLV_SLV_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + ALT_LWH2F_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_LB_ADDR ALT_LWH2F_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_OFST 0x42000 +/* The start address of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_SLV_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_LB_ADDR ALT_LWH2F_SLV_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + 0x310c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F component. */ +#define ALT_LWH2F_OFST 0xff400000 +/* The start address of the ALT_LWH2F component. */ +#define ALT_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWH2F_OFST)) +/* The lower bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_LB_ADDR ALT_LWH2F_ADDR +/* The upper bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : hps2fpgaregs + * + * Instance hps2fpgaregs of component ALT_H2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_H2F_IDGRP. + * + * + */ +/* The address of the ALT_H2F_ID_PERIPH_ID_4 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_OFST 0x1000 +/* The start address of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_IDGRP_OFST)) +/* The lower bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_LB_ADDR ALT_H2F_IDGRP_ADDR +/* The upper bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_H2F_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_H2F_MST_B32. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_OFST 0x0 +/* The start address of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_LB_ADDR ALT_H2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_b128 + * + * Instance mastergrp_b128 of register group ALT_H2F_MST_B128. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_OFST 0x2000 +/* The start address of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B128_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_LB_ADDR ALT_H2F_MST_MST_B128_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_OFST 0x2000 +/* The start address of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_MSTGRP_OFST)) +/* The lower bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_LB_ADDR ALT_H2F_MSTGRP_ADDR +/* The upper bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F component. */ +#define ALT_H2F_OFST 0xff500000 +/* The start address of the ALT_H2F component. */ +#define ALT_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_H2F_OFST)) +/* The lower bound address range of the ALT_H2F component. */ +#define ALT_H2F_LB_ADDR ALT_H2F_ADDR +/* The upper bound address range of the ALT_H2F component. */ +#define ALT_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_ADDR) + 0x8000) - 1)) + + +/* + * Component Instance : fpga2hpsregs + * + * Instance fpga2hpsregs of component ALT_F2H. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_F2H_IDGRP. + * + * + */ +/* The address of the ALT_F2H_ID_PERIPH_ID_4 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_0_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_1_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_2_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_OFST 0x1000 +/* The start address of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_IDGRP_OFST)) +/* The lower bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_LB_ADDR ALT_F2H_IDGRP_ADDR +/* The upper bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_F2H_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_F2H_SLV_B32. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_OFST 0x0 +/* The start address of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_LB_ADDR ALT_F2H_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_b128 + * + * Instance slavegrp_b128 of register group ALT_F2H_SLV_B128. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_OFST 0x2000 +/* The start address of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B128_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_LB_ADDR ALT_F2H_SLV_SLV_B128_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_OFST 0x42000 +/* The start address of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_SLVGRP_OFST)) +/* The lower bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_LB_ADDR ALT_F2H_SLVGRP_ADDR +/* The upper bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H component. */ +#define ALT_F2H_OFST 0xff600000 +/* The start address of the ALT_F2H component. */ +#define ALT_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_F2H_OFST)) +/* The lower bound address range of the ALT_F2H component. */ +#define ALT_F2H_LB_ADDR ALT_F2H_ADDR +/* The upper bound address range of the ALT_F2H component. */ +#define ALT_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : emac0 + * + * Instance emac0 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_LB_ADDR ALT_EMAC0_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_LB_ADDR ALT_EMAC0_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC0 component. */ +#define ALT_EMAC0_OFST 0xff700000 +/* The start address of the ALT_EMAC0 component. */ +#define ALT_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC0_OFST)) +/* The lower bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_LB_ADDR ALT_EMAC0_ADDR +/* The upper bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : emac1 + * + * Instance emac1 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_LB_ADDR ALT_EMAC1_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_LB_ADDR ALT_EMAC1_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC1 component. */ +#define ALT_EMAC1_OFST 0xff702000 +/* The start address of the ALT_EMAC1 component. */ +#define ALT_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC1_OFST)) +/* The lower bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_LB_ADDR ALT_EMAC1_ADDR +/* The upper bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : sdmmc + * + * Instance sdmmc of component ALT_SDMMC. + * + * + */ +/* The address of the ALT_SDMMC_CTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTL_OFST)) +/* The address of the ALT_SDMMC_PWREN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PWREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PWREN_OFST)) +/* The address of the ALT_SDMMC_CLKDIV register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKDIV_OFST)) +/* The address of the ALT_SDMMC_CLKSRC register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKSRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKSRC_OFST)) +/* The address of the ALT_SDMMC_CLKENA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKENA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKENA_OFST)) +/* The address of the ALT_SDMMC_TMOUT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TMOUT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TMOUT_OFST)) +/* The address of the ALT_SDMMC_CTYPE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTYPE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTYPE_OFST)) +/* The address of the ALT_SDMMC_BLKSIZ register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BLKSIZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BLKSIZ_OFST)) +/* The address of the ALT_SDMMC_BYTCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BYTCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BYTCNT_OFST)) +/* The address of the ALT_SDMMC_INTMSK register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_INTMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_INTMSK_OFST)) +/* The address of the ALT_SDMMC_CMDARG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMDARG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMDARG_OFST)) +/* The address of the ALT_SDMMC_CMD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMD_OFST)) +/* The address of the ALT_SDMMC_RESP0 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP0_OFST)) +/* The address of the ALT_SDMMC_RESP1 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP1_OFST)) +/* The address of the ALT_SDMMC_RESP2 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP2_OFST)) +/* The address of the ALT_SDMMC_RESP3 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP3_OFST)) +/* The address of the ALT_SDMMC_MINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_MINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_MINTSTS_OFST)) +/* The address of the ALT_SDMMC_RINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RINTSTS_OFST)) +/* The address of the ALT_SDMMC_STAT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_STAT_OFST)) +/* The address of the ALT_SDMMC_FIFOTH register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_FIFOTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_FIFOTH_OFST)) +/* The address of the ALT_SDMMC_CDETECT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CDETECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CDETECT_OFST)) +/* The address of the ALT_SDMMC_WRTPRT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_WRTPRT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_WRTPRT_OFST)) +/* The address of the ALT_SDMMC_TCBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TCBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TCBCNT_OFST)) +/* The address of the ALT_SDMMC_TBBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TBBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TBBCNT_OFST)) +/* The address of the ALT_SDMMC_DEBNCE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DEBNCE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DEBNCE_OFST)) +/* The address of the ALT_SDMMC_USRID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_USRID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_USRID_OFST)) +/* The address of the ALT_SDMMC_VERID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_VERID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_VERID_OFST)) +/* The address of the ALT_SDMMC_HCON register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_HCON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_HCON_OFST)) +/* The address of the ALT_SDMMC_UHS_REG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_UHS_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_UHS_REG_OFST)) +/* The address of the ALT_SDMMC_RST_N register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RST_N_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RST_N_OFST)) +/* The address of the ALT_SDMMC_BMOD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BMOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BMOD_OFST)) +/* The address of the ALT_SDMMC_PLDMND register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PLDMND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PLDMND_OFST)) +/* The address of the ALT_SDMMC_DBADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DBADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DBADDR_OFST)) +/* The address of the ALT_SDMMC_IDSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDSTS_OFST)) +/* The address of the ALT_SDMMC_IDINTEN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDINTEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDINTEN_OFST)) +/* The address of the ALT_SDMMC_DSCADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DSCADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DSCADDR_OFST)) +/* The address of the ALT_SDMMC_BUFADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BUFADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BUFADDR_OFST)) +/* The address of the ALT_SDMMC_CARDTHRCTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CARDTHRCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CARDTHRCTL_OFST)) +/* The address of the ALT_SDMMC_BACK_END_POWER_R register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BACK_END_POWER_R_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BACK_END_POWER_R_OFST)) +/* The address of the ALT_SDMMC_DATA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DATA_OFST)) +/* The base address byte offset for the start of the ALT_SDMMC component. */ +#define ALT_SDMMC_OFST 0xff704000 +/* The start address of the ALT_SDMMC component. */ +#define ALT_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDMMC_OFST)) +/* The lower bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_LB_ADDR ALT_SDMMC_ADDR +/* The upper bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDMMC_ADDR) + 0x400) - 1)) + + +/* + * Component Instance : qspiregs + * + * Instance qspiregs of component ALT_QSPI. + * + * + */ +/* The address of the ALT_QSPI_CFG register for the ALT_QSPI instance. */ +#define ALT_QSPI_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_CFG_OFST)) +/* The address of the ALT_QSPI_DEVRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVRD_OFST)) +/* The address of the ALT_QSPI_DEVWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVWR_OFST)) +/* The address of the ALT_QSPI_DELAY register for the ALT_QSPI instance. */ +#define ALT_QSPI_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DELAY_OFST)) +/* The address of the ALT_QSPI_RDDATACAP register for the ALT_QSPI instance. */ +#define ALT_QSPI_RDDATACAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RDDATACAP_OFST)) +/* The address of the ALT_QSPI_DEVSZ register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVSZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVSZ_OFST)) +/* The address of the ALT_QSPI_SRAMPART register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMPART_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMPART_OFST)) +/* The address of the ALT_QSPI_INDADDRTRIG register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDADDRTRIG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDADDRTRIG_OFST)) +/* The address of the ALT_QSPI_DMAPER register for the ALT_QSPI instance. */ +#define ALT_QSPI_DMAPER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DMAPER_OFST)) +/* The address of the ALT_QSPI_REMAPADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_REMAPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_REMAPADDR_OFST)) +/* The address of the ALT_QSPI_MODBIT register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODBIT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODBIT_OFST)) +/* The address of the ALT_QSPI_SRAMFILL register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMFILL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMFILL_OFST)) +/* The address of the ALT_QSPI_TXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_TXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_TXTHRESH_OFST)) +/* The address of the ALT_QSPI_RXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_RXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RXTHRESH_OFST)) +/* The address of the ALT_QSPI_IRQSTAT register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQSTAT_OFST)) +/* The address of the ALT_QSPI_IRQMSK register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQMSK_OFST)) +/* The address of the ALT_QSPI_LOWWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_LOWWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_LOWWRPROT_OFST)) +/* The address of the ALT_QSPI_UPPWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_UPPWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_UPPWRPROT_OFST)) +/* The address of the ALT_QSPI_WRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_WRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_WRPROT_OFST)) +/* The address of the ALT_QSPI_INDRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRD_OFST)) +/* The address of the ALT_QSPI_INDRDWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDWATER_OFST)) +/* The address of the ALT_QSPI_INDRDSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDSTADDR_OFST)) +/* The address of the ALT_QSPI_INDRDCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDCNT_OFST)) +/* The address of the ALT_QSPI_INDWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWR_OFST)) +/* The address of the ALT_QSPI_INDWRWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRWATER_OFST)) +/* The address of the ALT_QSPI_INDWRSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRSTADDR_OFST)) +/* The address of the ALT_QSPI_INDWRCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRCNT_OFST)) +/* The address of the ALT_QSPI_FLSHCMD register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMD_OFST)) +/* The address of the ALT_QSPI_FLSHCMDADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDADDR_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATAUP_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATAUP_OFST)) +/* The address of the ALT_QSPI_MODULEID register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODULEID_OFST)) +/* The base address byte offset for the start of the ALT_QSPI component. */ +#define ALT_QSPI_OFST 0xff705000 +/* The start address of the ALT_QSPI component. */ +#define ALT_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPI_OFST)) +/* The lower bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_LB_ADDR ALT_QSPI_ADDR +/* The upper bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPI_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : fpgamgrregs + * + * Instance fpgamgrregs of component ALT_FPGAMGR. + * + * + */ +/* The address of the ALT_FPGAMGR_STAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_STAT_OFST)) +/* The address of the ALT_FPGAMGR_CTL register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_CTL_OFST)) +/* The address of the ALT_FPGAMGR_DCLKCNT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKCNT_OFST)) +/* The address of the ALT_FPGAMGR_DCLKSTAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKSTAT_OFST)) +/* The address of the ALT_FPGAMGR_GPO register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPO_OFST)) +/* The address of the ALT_FPGAMGR_GPI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPI_OFST)) +/* The address of the ALT_FPGAMGR_MISCI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_MISCI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MISCI_OFST)) +/* + * Register Group Instance : mon + * + * Instance mon of register group ALT_MON. + * + * + */ +/* The address of the ALT_MON_GPIO_INTEN register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTEN_ADDR ALT_MON_GPIO_INTEN_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTMSK register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTMSK_ADDR ALT_MON_GPIO_INTMSK_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTTYPE_LEVEL_ADDR ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INT_POL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INT_POL_ADDR ALT_MON_GPIO_INT_POL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTSTAT_ADDR ALT_MON_GPIO_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_RAW_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_RAW_INTSTAT_ADDR ALT_MON_GPIO_RAW_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_PORTA_EOI register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_PORTA_EOI_ADDR ALT_MON_GPIO_PORTA_EOI_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_EXT_PORTA register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_EXT_PORTA_ADDR ALT_MON_GPIO_EXT_PORTA_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_LS_SYNC register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_LS_SYNC_ADDR ALT_MON_GPIO_LS_SYNC_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_VER_ID_CODE register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_VER_ID_CODE_ADDR ALT_MON_GPIO_VER_ID_CODE_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG2 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG2_ADDR ALT_MON_GPIO_CFG_REG2_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG1 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG1_ADDR ALT_MON_GPIO_CFG_REG1_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The base address byte offset for the start of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_OFST 0x800 +/* The start address of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MON_OFST)) +/* The lower bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_LB_ADDR ALT_FPGAMGR_MON_ADDR +/* The upper bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_MON_ADDR) + 0x80) - 1)) + + +/* The base address byte offset for the start of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_OFST 0xff706000 +/* The start address of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGR_OFST)) +/* The lower bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_LB_ADDR ALT_FPGAMGR_ADDR +/* The upper bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : acpidmap + * + * Instance acpidmap of component ALT_ACPIDMAP. + * + * + */ +/* The address of the ALT_ACPIDMAP_VID2RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_OFST)) +/* The address of the ALT_ACPIDMAP_VID2RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_S_OFST)) +/* The base address byte offset for the start of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_OFST 0xff707000 +/* The start address of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ACPIDMAP_OFST)) +/* The lower bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_LB_ADDR ALT_ACPIDMAP_ADDR +/* The upper bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : gpio0 + * + * Instance gpio0 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO0_ADDR) +/* The base address byte offset for the start of the ALT_GPIO0 component. */ +#define ALT_GPIO0_OFST 0xff708000 +/* The start address of the ALT_GPIO0 component. */ +#define ALT_GPIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO0_OFST)) +/* The lower bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_LB_ADDR ALT_GPIO0_ADDR +/* The upper bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio1 + * + * Instance gpio1 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO1_ADDR) +/* The base address byte offset for the start of the ALT_GPIO1 component. */ +#define ALT_GPIO1_OFST 0xff709000 +/* The start address of the ALT_GPIO1 component. */ +#define ALT_GPIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO1_OFST)) +/* The lower bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_LB_ADDR ALT_GPIO1_ADDR +/* The upper bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio2 + * + * Instance gpio2 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO2_ADDR) +/* The base address byte offset for the start of the ALT_GPIO2 component. */ +#define ALT_GPIO2_OFST 0xff70a000 +/* The start address of the ALT_GPIO2 component. */ +#define ALT_GPIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO2_OFST)) +/* The lower bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_LB_ADDR ALT_GPIO2_ADDR +/* The upper bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO2_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : l3regs + * + * Instance l3regs of component ALT_L3. + * + * + */ +/* The address of the ALT_L3_REMAP register for the ALT_L3 instance. */ +#define ALT_L3_REMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_REMAP_OFST)) +/* + * Register Group Instance : secgrp + * + * Instance secgrp of register group ALT_L3_SECGRP. + * + * + */ +/* The address of the ALT_L3_SEC_L4MAIN register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MAIN_OFST)) +/* The address of the ALT_L3_SEC_L4SP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SP_OFST)) +/* The address of the ALT_L3_SEC_L4MP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MP_OFST)) +/* The address of the ALT_L3_SEC_L4OSC1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4OSC1_OFST)) +/* The address of the ALT_L3_SEC_L4SPIM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SPIM_OFST)) +/* The address of the ALT_L3_SEC_STM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_STM_OFST)) +/* The address of the ALT_L3_SEC_LWH2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_LWH2F_OFST)) +/* The address of the ALT_L3_SEC_USB1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB1_OFST)) +/* The address of the ALT_L3_SEC_NANDDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NANDDATA_OFST)) +/* The address of the ALT_L3_SEC_USB0 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB0_OFST)) +/* The address of the ALT_L3_SEC_NAND register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NAND_OFST)) +/* The address of the ALT_L3_SEC_QSPIDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_QSPIDATA_OFST)) +/* The address of the ALT_L3_SEC_FPGAMGRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_FPGAMGRDATA_OFST)) +/* The address of the ALT_L3_SEC_H2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_H2F_OFST)) +/* The address of the ALT_L3_SEC_ACP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ACP_OFST)) +/* The address of the ALT_L3_SEC_ROM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ROM_OFST)) +/* The address of the ALT_L3_SEC_OCRAM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_OCRAM_OFST)) +/* The address of the ALT_L3_SEC_SDRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_SDRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_SDRDATA_OFST)) +/* The base address byte offset for the start of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_OFST 0x8 +/* The start address of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SECGRP_OFST)) +/* The lower bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_LB_ADDR ALT_L3_SECGRP_ADDR +/* The upper bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + 0x9c) - 1)) + + +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_L3_IDGRP. + * + * + */ +/* The address of the ALT_L3_ID_PERIPH_ID_4 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_0_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_1_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_2_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_OFST 0x1000 +/* The start address of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_IDGRP_OFST)) +/* The lower bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_LB_ADDR ALT_L3_IDGRP_ADDR +/* The upper bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_L3_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_l4main + * + * Instance mastergrp_l4main of register group ALT_L3_MST_L4MAIN. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MAIN instance. */ +#define ALT_L3_MST_MST_L4MAIN_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MAIN_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_OFST 0x0 +/* The start address of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MAIN_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_LB_ADDR ALT_L3_MST_MST_L4MAIN_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MAIN_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4sp + * + * Instance mastergrp_l4sp of register group ALT_L3_MST_L4SP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SP instance. */ +#define ALT_L3_MST_MST_L4SP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_OFST 0x1000 +/* The start address of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_LB_ADDR ALT_L3_MST_MST_L4SP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4mp + * + * Instance mastergrp_l4mp of register group ALT_L3_MST_L4MP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MP instance. */ +#define ALT_L3_MST_MST_L4MP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_OFST 0x2000 +/* The start address of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_LB_ADDR ALT_L3_MST_MST_L4MP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4osc1 + * + * Instance mastergrp_l4osc1 of register group ALT_L3_MST_L4OSC1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4OSC1 instance. */ +#define ALT_L3_MST_MST_L4OSC1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4OSC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_OFST 0x3000 +/* The start address of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4OSC1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_LB_ADDR ALT_L3_MST_MST_L4OSC1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4OSC1_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4spim + * + * Instance mastergrp_l4spim of register group ALT_L3_MST_L4SPIM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SPIM instance. */ +#define ALT_L3_MST_MST_L4SPIM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SPIM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_OFST 0x4000 +/* The start address of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SPIM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_LB_ADDR ALT_L3_MST_MST_L4SPIM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SPIM_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_stm + * + * Instance mastergrp_stm of register group ALT_L3_MST_STM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_OFST 0x5000 +/* The start address of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_STM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_LB_ADDR ALT_L3_MST_MST_STM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_STM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_lwhps2fpga + * + * Instance mastergrp_lwhps2fpga of register group ALT_L3_MST_LWH2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_OFST 0x6000 +/* The start address of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_LWH2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_LB_ADDR ALT_L3_MST_MST_LWH2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_LWH2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb1 + * + * Instance mastergrp_usb1 of register group ALT_L3_MST_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_OFST 0x8000 +/* The start address of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_LB_ADDR ALT_L3_MST_MST_USB1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB1_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nanddata + * + * Instance mastergrp_nanddata of register group ALT_L3_MST_NANDDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_OFST 0x9000 +/* The start address of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NANDDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_LB_ADDR ALT_L3_MST_MST_NANDDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NANDDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb0 + * + * Instance mastergrp_usb0 of register group ALT_L3_MST_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_OFST 0x1e000 +/* The start address of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB0_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_LB_ADDR ALT_L3_MST_MST_USB0_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB0_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nandregs + * + * Instance mastergrp_nandregs of register group ALT_L3_MST_NAND. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_OFST 0x1f000 +/* The start address of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NAND_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_LB_ADDR ALT_L3_MST_MST_NAND_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_qspidata + * + * Instance mastergrp_qspidata of register group ALT_L3_MST_QSPIDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_OFST 0x20000 +/* The start address of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_LB_ADDR ALT_L3_MST_MST_QSPIDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_QSPIDATA_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_fpgamgrdata + * + * Instance mastergrp_fpgamgrdata of register group ALT_L3_MST_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_OFST 0x21000 +/* The start address of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_LB_ADDR ALT_L3_MST_MST_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_FPGAMGRDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpga + * + * Instance mastergrp_hps2fpga of register group ALT_L3_MST_H2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_OFST 0x22000 +/* The start address of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_LB_ADDR ALT_L3_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_H2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_acp + * + * Instance mastergrp_acp of register group ALT_L3_MST_ACP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_OFST 0x23000 +/* The start address of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ACP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_LB_ADDR ALT_L3_MST_MST_ACP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ACP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_rom + * + * Instance mastergrp_rom of register group ALT_L3_MST_ROM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_OFST 0x24000 +/* The start address of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ROM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_LB_ADDR ALT_L3_MST_MST_ROM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ROM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_ocram + * + * Instance mastergrp_ocram of register group ALT_L3_MST_OCRAM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_OFST 0x25000 +/* The start address of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_OCRAM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_LB_ADDR ALT_L3_MST_MST_OCRAM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_OCRAM_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_OFST 0x2000 +/* The start address of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_MSTGRP_OFST)) +/* The lower bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_LB_ADDR ALT_L3_MSTGRP_ADDR +/* The upper bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + 0x2510c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_L3_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_dap + * + * Instance slavegrp_dap of register group ALT_L3_SLV_DAP. + * + * + */ +/* The address of the ALT_L3_FN_MOD2 register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD2_ADDR ALT_L3_FN_MOD2_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_OFST 0x0 +/* The start address of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DAP_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_LB_ADDR ALT_L3_SLV_SLV_DAP_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DAP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_mpu + * + * Instance slavegrp_mpu of register group ALT_L3_SLV_MPU. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_OFST 0x1000 +/* The start address of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_MPU_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_LB_ADDR ALT_L3_SLV_SLV_MPU_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_MPU_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_sdmmc + * + * Instance slavegrp_sdmmc of register group ALT_L3_SLV_SDMMC. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_OFST 0x2000 +/* The start address of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_SDMMC_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_LB_ADDR ALT_L3_SLV_SLV_SDMMC_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_SDMMC_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_dma + * + * Instance slavegrp_dma of register group ALT_L3_SLV_DMA. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_OFST 0x3000 +/* The start address of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DMA_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_LB_ADDR ALT_L3_SLV_SLV_DMA_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DMA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_fpga2hps + * + * Instance slavegrp_fpga2hps of register group ALT_L3_SLV_F2H. + * + * + */ +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_OFST 0x4000 +/* The start address of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_F2H_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_LB_ADDR ALT_L3_SLV_SLV_F2H_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_F2H_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_etr + * + * Instance slavegrp_etr of register group ALT_L3_SLV_ETR. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_OFST 0x5000 +/* The start address of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_ETR_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_LB_ADDR ALT_L3_SLV_SLV_ETR_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_ETR_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac0 + * + * Instance slavegrp_emac0 of register group ALT_L3_SLV_EMAC0. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_OFST 0x6000 +/* The start address of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_LB_ADDR ALT_L3_SLV_SLV_EMAC0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac1 + * + * Instance slavegrp_emac1 of register group ALT_L3_SLV_EMAC1. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_OFST 0x7000 +/* The start address of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_LB_ADDR ALT_L3_SLV_SLV_EMAC1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC1_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb0 + * + * Instance slavegrp_usb0 of register group ALT_L3_SLV_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_OFST 0x8000 +/* The start address of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_LB_ADDR ALT_L3_SLV_SLV_USB0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_nand + * + * Instance slavegrp_nand of register group ALT_L3_SLV_NAND. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_OFST 0x9000 +/* The start address of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_NAND_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_LB_ADDR ALT_L3_SLV_SLV_NAND_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb1 + * + * Instance slavegrp_usb1 of register group ALT_L3_SLV_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_OFST 0xa000 +/* The start address of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_LB_ADDR ALT_L3_SLV_SLV_USB1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB1_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_OFST 0x42000 +/* The start address of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SLVGRP_OFST)) +/* The lower bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_LB_ADDR ALT_L3_SLVGRP_ADDR +/* The upper bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + 0xa10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3 component. */ +#define ALT_L3_OFST 0xff800000 +/* The start address of the ALT_L3 component. */ +#define ALT_L3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L3_OFST)) +/* The lower bound address range of the ALT_L3 component. */ +#define ALT_L3_LB_ADDR ALT_L3_ADDR +/* The upper bound address range of the ALT_L3 component. */ +#define ALT_L3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : nanddata + * + * Instance nanddata of component ALT_NANDDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_OFST 0xff900000 +/* The start address of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NANDDATA_OFST)) +/* The lower bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_LB_ADDR ALT_NANDDATA_ADDR +/* The upper bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NANDDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : qspidata + * + * Instance qspidata of component ALT_QSPIDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_OFST 0xffa00000 +/* The start address of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_LB_ADDR ALT_QSPIDATA_ADDR +/* The upper bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPIDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : usb0 + * + * Instance usb0 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_LB_ADDR ALT_USB0_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_LB_ADDR ALT_USB0_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_LB_ADDR ALT_USB0_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB0_PWRCLKGRP instance. */ +#define ALT_USB0_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB0_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_LB_ADDR ALT_USB0_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB0 component. */ +#define ALT_USB0_OFST 0xffb00000 +/* The start address of the ALT_USB0 component. */ +#define ALT_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB0_OFST)) +/* The lower bound address range of the ALT_USB0 component. */ +#define ALT_USB0_LB_ADDR ALT_USB0_ADDR +/* The upper bound address range of the ALT_USB0 component. */ +#define ALT_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : usb1 + * + * Instance usb1 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_LB_ADDR ALT_USB1_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_LB_ADDR ALT_USB1_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_LB_ADDR ALT_USB1_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB1_PWRCLKGRP instance. */ +#define ALT_USB1_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB1_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_LB_ADDR ALT_USB1_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB1 component. */ +#define ALT_USB1_OFST 0xffb40000 +/* The start address of the ALT_USB1 component. */ +#define ALT_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB1_OFST)) +/* The lower bound address range of the ALT_USB1 component. */ +#define ALT_USB1_LB_ADDR ALT_USB1_ADDR +/* The upper bound address range of the ALT_USB1 component. */ +#define ALT_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : nandregs + * + * Instance nandregs of component ALT_NAND. + * + * + */ +/* + * Register Group Instance : config + * + * Instance config of register group ALT_NAND_CFG. + * + * + */ +/* The address of the ALT_NAND_CFG_DEVICE_RST register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_RST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_RST_OFST)) +/* The address of the ALT_NAND_CFG_TFR_SPARE_REG register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TFR_SPARE_REG_OFST)) +/* The address of the ALT_NAND_CFG_LD_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_LD_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_ERASE_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_INT_MON_CYCCNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST)) +/* The address of the ALT_NAND_CFG_RB_PIN_END register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RB_PIN_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RB_PIN_END_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_OP register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_OP_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_DIS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_DIS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_DIS_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_WR_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_WR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_WR_EN_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_PREFETCH_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PREFETCH_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PREFETCH_MOD_OFST)) +/* The address of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST)) +/* The address of the ALT_NAND_CFG_ECC_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_EN_OFST)) +/* The address of the ALT_NAND_CFG_GLOB_INT_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_GLOB_INT_EN_OFST)) +/* The address of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_WE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_WE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_WE_OFST)) +/* The address of the ALT_NAND_CFG_ACC_CLKS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ACC_CLKS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ACC_CLKS_OFST)) +/* The address of the ALT_NAND_CFG_NUMBER_OF_PLANES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST)) +/* The address of the ALT_NAND_CFG_PAGES_PER_BLOCK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_WIDTH register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_WIDTH_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST)) +/* The address of the ALT_NAND_CFG_ECC_CORRECTION register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_CORRECTION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_CORRECTION_OFST)) +/* The address of the ALT_NAND_CFG_RD_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RD_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RD_MOD_OFST)) +/* The address of the ALT_NAND_CFG_WR_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_MOD_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_MOD_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_LO_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_HI_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST)) +/* The address of the ALT_NAND_CFG_MAX_RD_DELAY register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MAX_RD_DELAY_OFST)) +/* The address of the ALT_NAND_CFG_CS_SETUP_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CS_SETUP_CNT_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_MARKER register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST)) +/* The address of the ALT_NAND_CFG_DEVICES_CONNECTED register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST)) +/* The address of the ALT_NAND_CFG_DIE_MSK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DIE_MSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DIE_MSK_OFST)) +/* The address of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST)) +/* The address of the ALT_NAND_CFG_WR_PROTECT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_PROTECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_PROTECT_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_POR_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_POR_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_POR_RST_COUNT_OFST)) +/* The address of the ALT_NAND_CFG_WD_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WD_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WD_RST_COUNT_OFST)) +/* The base address byte offset for the start of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_OFST 0x0 +/* The start address of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_CFG_OFST)) +/* The lower bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_LB_ADDR ALT_NAND_CFG_ADDR +/* The upper bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_CFG_ADDR) + 0x2b4) - 1)) + + +/* + * Register Group Instance : param + * + * Instance param of register group ALT_NAND_PARAM. + * + * + */ +/* The address of the ALT_NAND_PARAM_MANUFACTURER_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_0 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_1 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_2 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_REVISION register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_REVISION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_REVISION_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST)) +/* The address of the ALT_NAND_PARAM_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_FEATURES_OFST)) +/* The base address byte offset for the start of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_OFST 0x300 +/* The start address of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_PARAM_OFST)) +/* The lower bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_LB_ADDR ALT_NAND_PARAM_ADDR +/* The upper bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + 0xf4) - 1)) + + +/* + * Register Group Instance : status + * + * Instance status of register group ALT_NAND_STAT. + * + * + */ +/* The address of the ALT_NAND_STAT_TFR_MOD register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_TFR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_TFR_MOD_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN0_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN1_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN2_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT3_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN3_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST)) +/* The base address byte offset for the start of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_OFST 0x400 +/* The start address of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_STAT_OFST)) +/* The lower bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_LB_ADDR ALT_NAND_STAT_ADDR +/* The upper bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_STAT_ADDR) + 0x144) - 1)) + + +/* + * Register Group Instance : ecc + * + * Instance ecc of register group ALT_NAND_ECC. + * + * + */ +/* The address of the ALT_NAND_ECC_ECCCORINFO_B01 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B01_OFST)) +/* The address of the ALT_NAND_ECC_ECCCORINFO_B23 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B23_OFST)) +/* The base address byte offset for the start of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_OFST 0x650 +/* The start address of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_ECC_OFST)) +/* The lower bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_LB_ADDR ALT_NAND_ECC_ADDR +/* The upper bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ECC_ADDR) + 0x14) - 1)) + + +/* + * Register Group Instance : dma + * + * Instance dma of register group ALT_NAND_DMA. + * + * + */ +/* The address of the ALT_NAND_DMA_DMA_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_EN_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_EN_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST)) +/* The address of the ALT_NAND_DMA_FLSH_BURST_LEN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_FLSH_BURST_LEN_OFST)) +/* The address of the ALT_NAND_DMA_INTRLV register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_INTRLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_INTRLV_OFST)) +/* The address of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST)) +/* The address of the ALT_NAND_DMA_LUN_STAT_CMD register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_LUN_STAT_CMD_OFST)) +/* The base address byte offset for the start of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_OFST 0x700 +/* The start address of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_DMA_OFST)) +/* The lower bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_LB_ADDR ALT_NAND_DMA_ADDR +/* The upper bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_DMA_ADDR) + 0xa4) - 1)) + + +/* The base address byte offset for the start of the ALT_NAND component. */ +#define ALT_NAND_OFST 0xffb80000 +/* The start address of the ALT_NAND component. */ +#define ALT_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NAND_OFST)) +/* The lower bound address range of the ALT_NAND component. */ +#define ALT_NAND_LB_ADDR ALT_NAND_ADDR +/* The upper bound address range of the ALT_NAND component. */ +#define ALT_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ADDR) + 0x800) - 1)) + + +/* + * Component Instance : fpgamgrdata + * + * Instance fpgamgrdata of component ALT_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_FPGAMGRDATA_DATA register for the ALT_FPGAMGRDATA instance. */ +#define ALT_FPGAMGRDATA_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + ALT_FPGAMGRDATA_DATA_OFST)) +/* The base address byte offset for the start of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_OFST 0xffb90000 +/* The start address of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_LB_ADDR ALT_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : can0 + * + * Instance can0 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_LB_ADDR ALT_CAN0_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_LB_ADDR ALT_CAN0_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_LB_ADDR ALT_CAN0_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN0 component. */ +#define ALT_CAN0_OFST 0xffc00000 +/* The start address of the ALT_CAN0 component. */ +#define ALT_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN0_OFST)) +/* The lower bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_LB_ADDR ALT_CAN0_ADDR +/* The upper bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : can1 + * + * Instance can1 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_LB_ADDR ALT_CAN1_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_LB_ADDR ALT_CAN1_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_LB_ADDR ALT_CAN1_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN1 component. */ +#define ALT_CAN1_OFST 0xffc01000 +/* The start address of the ALT_CAN1 component. */ +#define ALT_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN1_OFST)) +/* The lower bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_LB_ADDR ALT_CAN1_ADDR +/* The upper bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : uart0 + * + * Instance uart0 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART0 instance. */ +#define ALT_UART0_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART0 instance. */ +#define ALT_UART0_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART0 instance. */ +#define ALT_UART0_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART0 instance. */ +#define ALT_UART0_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART0 instance. */ +#define ALT_UART0_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART0 instance. */ +#define ALT_UART0_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART0 instance. */ +#define ALT_UART0_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART0 instance. */ +#define ALT_UART0_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART0 instance. */ +#define ALT_UART0_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART0 instance. */ +#define ALT_UART0_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART0 instance. */ +#define ALT_UART0_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART0 instance. */ +#define ALT_UART0_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART0 instance. */ +#define ALT_UART0_USR_ADDR ALT_UART_USR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART0 instance. */ +#define ALT_UART0_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART0 instance. */ +#define ALT_UART0_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART0 instance. */ +#define ALT_UART0_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART0 instance. */ +#define ALT_UART0_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART0 instance. */ +#define ALT_UART0_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART0 instance. */ +#define ALT_UART0_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART0 instance. */ +#define ALT_UART0_STET_ADDR ALT_UART_STET_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART0 instance. */ +#define ALT_UART0_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART0 instance. */ +#define ALT_UART0_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART0 instance. */ +#define ALT_UART0_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART0 instance. */ +#define ALT_UART0_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART0 instance. */ +#define ALT_UART0_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART0_ADDR) +/* The base address byte offset for the start of the ALT_UART0 component. */ +#define ALT_UART0_OFST 0xffc02000 +/* The start address of the ALT_UART0 component. */ +#define ALT_UART0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART0_OFST)) +/* The lower bound address range of the ALT_UART0 component. */ +#define ALT_UART0_LB_ADDR ALT_UART0_ADDR +/* The upper bound address range of the ALT_UART0 component. */ +#define ALT_UART0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : uart1 + * + * Instance uart1 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART1 instance. */ +#define ALT_UART1_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART1 instance. */ +#define ALT_UART1_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART1 instance. */ +#define ALT_UART1_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART1 instance. */ +#define ALT_UART1_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART1 instance. */ +#define ALT_UART1_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART1 instance. */ +#define ALT_UART1_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART1 instance. */ +#define ALT_UART1_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART1 instance. */ +#define ALT_UART1_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART1 instance. */ +#define ALT_UART1_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART1 instance. */ +#define ALT_UART1_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART1 instance. */ +#define ALT_UART1_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART1 instance. */ +#define ALT_UART1_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART1 instance. */ +#define ALT_UART1_USR_ADDR ALT_UART_USR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART1 instance. */ +#define ALT_UART1_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART1 instance. */ +#define ALT_UART1_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART1 instance. */ +#define ALT_UART1_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART1 instance. */ +#define ALT_UART1_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART1 instance. */ +#define ALT_UART1_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART1 instance. */ +#define ALT_UART1_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART1 instance. */ +#define ALT_UART1_STET_ADDR ALT_UART_STET_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART1 instance. */ +#define ALT_UART1_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART1 instance. */ +#define ALT_UART1_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART1 instance. */ +#define ALT_UART1_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART1 instance. */ +#define ALT_UART1_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART1 instance. */ +#define ALT_UART1_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART1_ADDR) +/* The base address byte offset for the start of the ALT_UART1 component. */ +#define ALT_UART1_OFST 0xffc03000 +/* The start address of the ALT_UART1 component. */ +#define ALT_UART1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART1_OFST)) +/* The lower bound address range of the ALT_UART1 component. */ +#define ALT_UART1_LB_ADDR ALT_UART1_ADDR +/* The upper bound address range of the ALT_UART1 component. */ +#define ALT_UART1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c0 + * + * Instance i2c0 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C0_ADDR) +/* The base address byte offset for the start of the ALT_I2C0 component. */ +#define ALT_I2C0_OFST 0xffc04000 +/* The start address of the ALT_I2C0 component. */ +#define ALT_I2C0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C0_OFST)) +/* The lower bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_LB_ADDR ALT_I2C0_ADDR +/* The upper bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c1 + * + * Instance i2c1 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C1_ADDR) +/* The base address byte offset for the start of the ALT_I2C1 component. */ +#define ALT_I2C1_OFST 0xffc05000 +/* The start address of the ALT_I2C1 component. */ +#define ALT_I2C1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C1_OFST)) +/* The lower bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_LB_ADDR ALT_I2C1_ADDR +/* The upper bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c2 + * + * Instance i2c2 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C2_ADDR) +/* The base address byte offset for the start of the ALT_I2C2 component. */ +#define ALT_I2C2_OFST 0xffc06000 +/* The start address of the ALT_I2C2 component. */ +#define ALT_I2C2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C2_OFST)) +/* The lower bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_LB_ADDR ALT_I2C2_ADDR +/* The upper bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C2_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c3 + * + * Instance i2c3 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C3_ADDR) +/* The base address byte offset for the start of the ALT_I2C3 component. */ +#define ALT_I2C3_OFST 0xffc07000 +/* The start address of the ALT_I2C3 component. */ +#define ALT_I2C3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C3_OFST)) +/* The lower bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_LB_ADDR ALT_I2C3_ADDR +/* The upper bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C3_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer0 + * + * Instance sptimer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR0_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_OFST 0xffc08000 +/* The start address of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR0_OFST)) +/* The lower bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_LB_ADDR ALT_SPTMR0_ADDR +/* The upper bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer1 + * + * Instance sptimer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR1_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_OFST 0xffc09000 +/* The start address of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR1_OFST)) +/* The lower bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_LB_ADDR ALT_SPTMR1_ADDR +/* The upper bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sdr + * + * Instance sdr of component ALT_SDR. + * + * + */ +/* + * Register Group Instance : ctrlgrp + * + * Instance ctrlgrp of register group ALT_SDR_CTL. + * + * + */ +/* The address of the ALT_SDR_CTL_CTLCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLCFG_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING1 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING1_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING2 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING2_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING3 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING3_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING4 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING4_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRTIMING register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRTIMING_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRTIMING_OFST)) +/* The address of the ALT_SDR_CTL_DRAMODT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMODT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMODT_OFST)) +/* The address of the ALT_SDR_CTL_DRAMADDRW register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMADDRW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMADDRW_OFST)) +/* The address of the ALT_SDR_CTL_DRAMIFWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMIFWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMDEVWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMDEVWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMSTS register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMSTS_OFST)) +/* The address of the ALT_SDR_CTL_DRAMINTR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMINTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMINTR_OFST)) +/* The address of the ALT_SDR_CTL_SBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_SBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_SBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_ERRADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_ERRADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_ERRADDR_OFST)) +/* The address of the ALT_SDR_CTL_DROPCOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPCOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPCOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DROPADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPADDR_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWREQ register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWREQ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWREQ_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRACK register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRACK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRACK_OFST)) +/* The address of the ALT_SDR_CTL_STATICCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_STATICCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_STATICCFG_OFST)) +/* The address of the ALT_SDR_CTL_CTLWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_PORTCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PORTCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PORTCFG_OFST)) +/* The address of the ALT_SDR_CTL_FPGAPORTRST register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_FPGAPORTRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_FPGAPORTRST_OFST)) +/* The address of the ALT_SDR_CTL_PROTPORTDEFAULT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTPORTDEFAULT_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEADDR_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEID register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEID_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEDATA register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEDATA_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULERDWR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULERDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULERDWR_OFST)) +/* The address of the ALT_SDR_CTL_QOSLOWPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSLOWPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSLOWPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSHIGHPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSHIGHPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSHIGHPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSPRIORITYEN register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSPRIORITYEN_OFST)) +/* The address of the ALT_SDR_CTL_MPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_MPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_MPPRIORITY_OFST)) +/* The address of the ALT_SDR_CTL_REMAPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_REMAPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_REMAPPRIORITY_OFST)) +/* + * Register Group Instance : ctrlgrp_mpweight + * + * Instance ctrlgrp_mpweight of register group ALT_SDR_CTL_MPWT. + * + * + */ +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_0_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_1_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_2_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_3_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The base address byte offset for the start of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_OFST 0xb0 +/* The start address of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTL_MPWEIGHT_OFST)) +/* The lower bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_LB_ADDR ALT_SDR_CTL_CTL_MPWEIGHT_ADDR +/* The upper bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) + 0x10) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_OFST 0x5000 +/* The start address of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_ADDR) + ALT_SDR_CTL_OFST)) +/* The lower bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_LB_ADDR ALT_SDR_CTL_ADDR +/* The upper bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_ADDR) + 0x1000) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR component. */ +#define ALT_SDR_OFST 0xffc20000 +/* The start address of the ALT_SDR component. */ +#define ALT_SDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDR_OFST)) +/* The lower bound address range of the ALT_SDR component. */ +#define ALT_SDR_LB_ADDR ALT_SDR_ADDR +/* The upper bound address range of the ALT_SDR component. */ +#define ALT_SDR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_ADDR) + 0x20000) - 1)) + + +/* + * Component Instance : osc1timer0 + * + * Instance osc1timer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR0_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_OFST 0xffd00000 +/* The start address of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR0_OFST)) +/* The lower bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_LB_ADDR ALT_OSC1TMR0_ADDR +/* The upper bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : osc1timer1 + * + * Instance osc1timer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR1_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_OFST 0xffd01000 +/* The start address of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR1_OFST)) +/* The lower bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_LB_ADDR ALT_OSC1TMR1_ADDR +/* The upper bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd0 + * + * Instance l4wd0 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD0_ADDR) +/* The base address byte offset for the start of the ALT_L4WD0 component. */ +#define ALT_L4WD0_OFST 0xffd02000 +/* The start address of the ALT_L4WD0 component. */ +#define ALT_L4WD0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD0_OFST)) +/* The lower bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_LB_ADDR ALT_L4WD0_ADDR +/* The upper bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd1 + * + * Instance l4wd1 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD1_ADDR) +/* The base address byte offset for the start of the ALT_L4WD1 component. */ +#define ALT_L4WD1_OFST 0xffd03000 +/* The start address of the ALT_L4WD1 component. */ +#define ALT_L4WD1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD1_OFST)) +/* The lower bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_LB_ADDR ALT_L4WD1_ADDR +/* The upper bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : clkmgr + * + * Instance clkmgr of component ALT_CLKMGR. + * + * + */ +/* The address of the ALT_CLKMGR_CTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_CTL_OFST)) +/* The address of the ALT_CLKMGR_BYPASS register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_BYPASS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_BYPASS_OFST)) +/* The address of the ALT_CLKMGR_INTER register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTER_OFST)) +/* The address of the ALT_CLKMGR_INTREN register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTREN_OFST)) +/* The address of the ALT_CLKMGR_DBCTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_DBCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_DBCTL_OFST)) +/* The address of the ALT_CLKMGR_STAT register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_STAT_OFST)) +/* + * Register Group Instance : mainpllgrp + * + * Instance mainpllgrp of register group ALT_CLKMGR_MAINPLL. + * + * + */ +/* The address of the ALT_CLKMGR_MAINPLL_VCO register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MISC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MPUCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MPUCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGATCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGATCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_EN register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_TRACEDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_TRACEDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_L4SRC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_L4SRC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_STAT register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_OFST 0x40 +/* The start address of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_MAINPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_LB_ADDR ALT_CLKMGR_MAINPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : perpllgrp + * + * Instance perpllgrp of register group ALT_CLKMGR_PERPLL. + * + * + */ +/* The address of the ALT_CLKMGR_PERPLL_VCO register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_MISC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC0CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC0CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERQSPICLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERBASECLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERBASECLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EN register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_DIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_DIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_DIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_GPIODIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_GPIODIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_SRC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_SRC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_STAT register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_OFST 0x80 +/* The start address of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_PERPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_LB_ADDR ALT_CLKMGR_PERPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : sdrpllgrp + * + * Instance sdrpllgrp of register group ALT_CLKMGR_SDRPLL. + * + * + */ +/* The address of the ALT_CLKMGR_SDRPLL_VCO register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_CTL register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_CTL_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_EN register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_STAT register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_OFST 0xc0 +/* The start address of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_SDRPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_LB_ADDR ALT_CLKMGR_SDRPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_OFST 0xffd04000 +/* The start address of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CLKMGR_OFST)) +/* The lower bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_LB_ADDR ALT_CLKMGR_ADDR +/* The upper bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : rstmgr + * + * Instance rstmgr of component ALT_RSTMGR. + * + * + */ +/* The address of the ALT_RSTMGR_STAT register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_STAT_OFST)) +/* The address of the ALT_RSTMGR_CTL register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_CTL_OFST)) +/* The address of the ALT_RSTMGR_COUNTS register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_COUNTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_COUNTS_OFST)) +/* The address of the ALT_RSTMGR_MPUMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MPUMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MPUMODRST_OFST)) +/* The address of the ALT_RSTMGR_PERMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PERMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PERMODRST_OFST)) +/* The address of the ALT_RSTMGR_PER2MODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PER2MODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PER2MODRST_OFST)) +/* The address of the ALT_RSTMGR_BRGMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_BRGMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_BRGMODRST_OFST)) +/* The address of the ALT_RSTMGR_MISCMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MISCMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MISCMODRST_OFST)) +/* The base address byte offset for the start of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_OFST 0xffd05000 +/* The start address of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_RSTMGR_OFST)) +/* The lower bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_LB_ADDR ALT_RSTMGR_ADDR +/* The upper bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_RSTMGR_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sysmgr + * + * Instance sysmgr of component ALT_SYSMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SILICONID1 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID1_OFST)) +/* The address of the ALT_SYSMGR_SILICONID2 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID2_OFST)) +/* The address of the ALT_SYSMGR_WDDBG register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_WDDBG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_WDDBG_OFST)) +/* The address of the ALT_SYSMGR_BOOT register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_BOOT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_BOOT_OFST)) +/* The address of the ALT_SYSMGR_HPSINFO register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_HPSINFO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_HPSINFO_OFST)) +/* The address of the ALT_SYSMGR_PARITYINJ register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_PARITYINJ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PARITYINJ_OFST)) +/* + * Register Group Instance : fpgaintfgrp + * + * Instance fpgaintfgrp of register group ALT_SYSMGR_FPGAINTF. + * + * + */ +/* The address of the ALT_SYSMGR_FPGAINTF_GBL register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_GBL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_GBL_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_INDIV register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_INDIV_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_MODULE register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_MODULE_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_OFST 0x20 +/* The start address of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FPGAINTF_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_LB_ADDR ALT_SYSMGR_FPGAINTF_ADDR +/* The upper bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : scanmgrgrp + * + * Instance scanmgrgrp of register group ALT_SYSMGR_SCANMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SCANMGR_CTL register for the ALT_SYSMGR_SCANMGR instance. */ +#define ALT_SYSMGR_SCANMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + ALT_SYSMGR_SCANMGR_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_OFST 0x30 +/* The start address of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_LB_ADDR ALT_SYSMGR_SCANMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : frzctrl + * + * Instance frzctrl of register group ALT_SYSMGR_FRZCTL. + * + * + */ +/* The address of the ALT_SYSMGR_FRZCTL_VIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_VIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_SRC register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_SRC_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HWCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HWCTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_OFST 0x40 +/* The start address of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FRZCTL_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_LB_ADDR ALT_SYSMGR_FRZCTL_ADDR +/* The upper bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : emacgrp + * + * Instance emacgrp of register group ALT_SYSMGR_EMAC. + * + * + */ +/* The address of the ALT_SYSMGR_EMAC_CTL register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_CTL_OFST)) +/* The address of the ALT_SYSMGR_EMAC_L3MST register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_OFST 0x60 +/* The start address of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_EMAC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_LB_ADDR ALT_SYSMGR_EMAC_ADDR +/* The upper bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_SYSMGR_DMA. + * + * + */ +/* The address of the ALT_SYSMGR_DMA_CTL register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_CTL_OFST)) +/* The address of the ALT_SYSMGR_DMA_PERSECURITY register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_PERSECURITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_PERSECURITY_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_OFST 0x70 +/* The start address of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_DMA_OFST)) +/* The lower bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_LB_ADDR ALT_SYSMGR_DMA_ADDR +/* The upper bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : iswgrp + * + * Instance iswgrp of register group ALT_SYSMGR_ISW. + * + * + */ +/* The address of the ALT_SYSMGR_ISW_HANDOFF register for the ALT_SYSMGR_ISW instance. */ +#define ALT_SYSMGR_ISW_HANDOFF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + ALT_SYSMGR_ISW_HANDOFF_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_OFST 0x80 +/* The start address of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ISW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_LB_ADDR ALT_SYSMGR_ISW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : romcodegrp + * + * Instance romcodegrp of register group ALT_SYSMGR_ROMCODE. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_CTL register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CTL_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST)) +/* + * Register Group Instance : romcodegrp_warmramgrp + * + * Instance romcodegrp_warmramgrp of register group ALT_SYSMGR_ROMCODE_WARMRAM. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_DATASTART_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_LEN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EXECUTION_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_CRC_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST 0x20 +/* The start address of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_LB_ADDR ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_OFST 0xc0 +/* The start address of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMCODE_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_LB_ADDR ALT_SYSMGR_ROMCODE_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : romhwgrp + * + * Instance romhwgrp of register group ALT_SYSMGR_ROMHW. + * + * + */ +/* The address of the ALT_SYSMGR_ROMHW_CTL register for the ALT_SYSMGR_ROMHW instance. */ +#define ALT_SYSMGR_ROMHW_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + ALT_SYSMGR_ROMHW_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_OFST 0x100 +/* The start address of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMHW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_LB_ADDR ALT_SYSMGR_ROMHW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : sdmmcgrp + * + * Instance sdmmcgrp of register group ALT_SYSMGR_SDMMC. + * + * + */ +/* The address of the ALT_SYSMGR_SDMMC_CTL register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_CTL_OFST)) +/* The address of the ALT_SYSMGR_SDMMC_L3MST register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_OFST 0x108 +/* The start address of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SDMMC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_LB_ADDR ALT_SYSMGR_SDMMC_ADDR +/* The upper bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : nandgrp + * + * Instance nandgrp of register group ALT_SYSMGR_NAND. + * + * + */ +/* The address of the ALT_SYSMGR_NAND_BOOTSTRAP register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_BOOTSTRAP_OFST)) +/* The address of the ALT_SYSMGR_NAND_L3MST register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_OFST 0x110 +/* The start address of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_NAND_OFST)) +/* The lower bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_LB_ADDR ALT_SYSMGR_NAND_ADDR +/* The upper bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : usbgrp + * + * Instance usbgrp of register group ALT_SYSMGR_USB. + * + * + */ +/* The address of the ALT_SYSMGR_USB_L3MST register for the ALT_SYSMGR_USB instance. */ +#define ALT_SYSMGR_USB_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + ALT_SYSMGR_USB_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_OFST 0x118 +/* The start address of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_USB_OFST)) +/* The lower bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_LB_ADDR ALT_SYSMGR_USB_ADDR +/* The upper bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : eccgrp + * + * Instance eccgrp of register group ALT_SYSMGR_ECC. + * + * + */ +/* The address of the ALT_SYSMGR_ECC_L2 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_L2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_L2_OFST)) +/* The address of the ALT_SYSMGR_ECC_OCRAM register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_OCRAM_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB0_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB1_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC0_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC1_OFST)) +/* The address of the ALT_SYSMGR_ECC_DMA register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_DMA_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN0_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN1_OFST)) +/* The address of the ALT_SYSMGR_ECC_NAND register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_NAND_OFST)) +/* The address of the ALT_SYSMGR_ECC_QSPI register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_QSPI_OFST)) +/* The address of the ALT_SYSMGR_ECC_SDMMC register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_SDMMC_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_OFST 0x140 +/* The start address of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ECC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_LB_ADDR ALT_SYSMGR_ECC_ADDR +/* The upper bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : pinmuxgrp + * + * Instance pinmuxgrp of register group ALT_SYSMGR_PINMUX. + * + * + */ +/* The address of the ALT_SYSMGR_PINMUX_EMACIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX32 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX32_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX33 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX33_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX34 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX34_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX35 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX35_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX36 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX36_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX37 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX37_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX38 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX38_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX39 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX39_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX40 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX40_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX41 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX41_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX42 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX42_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX43 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX43_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX44 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX44_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX45 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX45_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX46 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX46_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX47 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX47_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_OFST 0x400 +/* The start address of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PINMUX_OFST)) +/* The lower bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_LB_ADDR ALT_SYSMGR_PINMUX_ADDR +/* The upper bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + 0x400) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_OFST 0xffd08000 +/* The start address of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SYSMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_LB_ADDR ALT_SYSMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ADDR) + 0x4000) - 1)) + + +/* + * Component Instance : dmanonsecure + * + * Instance dmanonsecure of component ALT_DMANONSECURE. + * + * + */ +/* The address of the ALT_DMANONSECURE_REG register for the ALT_DMANONSECURE instance. */ +#define ALT_DMANONSECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + ALT_DMANONSECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_OFST 0xffe00000 +/* The start address of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMANONSECURE_OFST)) +/* The lower bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_LB_ADDR ALT_DMANONSECURE_ADDR +/* The upper bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dmasecure + * + * Instance dmasecure of component ALT_DMASECURE. + * + * + */ +/* The address of the ALT_DMASECURE_REG register for the ALT_DMASECURE instance. */ +#define ALT_DMASECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMASECURE_ADDR) + ALT_DMASECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_OFST 0xffe01000 +/* The start address of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMASECURE_OFST)) +/* The lower bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_LB_ADDR ALT_DMASECURE_ADDR +/* The upper bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMASECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : spis0 + * + * Instance spis0 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS0_ADDR) +/* The base address byte offset for the start of the ALT_SPIS0 component. */ +#define ALT_SPIS0_OFST 0xffe02000 +/* The start address of the ALT_SPIS0 component. */ +#define ALT_SPIS0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS0_OFST)) +/* The lower bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_LB_ADDR ALT_SPIS0_ADDR +/* The upper bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spis1 + * + * Instance spis1 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS1_ADDR) +/* The base address byte offset for the start of the ALT_SPIS1 component. */ +#define ALT_SPIS1_OFST 0xffe03000 +/* The start address of the ALT_SPIS1 component. */ +#define ALT_SPIS1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS1_OFST)) +/* The lower bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_LB_ADDR ALT_SPIS1_ADDR +/* The upper bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spim0 + * + * Instance spim0 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM0_ADDR) +/* The base address byte offset for the start of the ALT_SPIM0 component. */ +#define ALT_SPIM0_OFST 0xfff00000 +/* The start address of the ALT_SPIM0 component. */ +#define ALT_SPIM0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM0_OFST)) +/* The lower bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_LB_ADDR ALT_SPIM0_ADDR +/* The upper bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : spim1 + * + * Instance spim1 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM1_ADDR) +/* The base address byte offset for the start of the ALT_SPIM1 component. */ +#define ALT_SPIM1_OFST 0xfff01000 +/* The start address of the ALT_SPIM1 component. */ +#define ALT_SPIM1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM1_OFST)) +/* The lower bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_LB_ADDR ALT_SPIM1_ADDR +/* The upper bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : scanmgr + * + * Instance scanmgr of component ALT_SCANMGR. + * + * + */ +/* The address of the ALT_SCANMGR_STAT register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_STAT_OFST)) +/* The address of the ALT_SCANMGR_EN register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_EN_OFST)) +/* The address of the ALT_SCANMGR_FIFOSINGLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOSINGLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFODOUBLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFODOUBLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOTRIPLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOTRIPLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOQUADBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOQUADBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOQUADBYTE_OFST)) +/* The base address byte offset for the start of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_OFST 0xfff02000 +/* The start address of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_LB_ADDR ALT_SCANMGR_ADDR +/* The upper bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SCANMGR_ADDR) + 0x20) - 1)) + + +/* + * Component Instance : rom + * + * Instance rom of component ALT_ROM. + * + * + */ +/* The base address byte offset for the start of the ALT_ROM component. */ +#define ALT_ROM_OFST 0xfffd0000 +/* The start address of the ALT_ROM component. */ +#define ALT_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ROM_OFST)) +/* The lower bound address range of the ALT_ROM component. */ +#define ALT_ROM_LB_ADDR ALT_ROM_ADDR +/* The upper bound address range of the ALT_ROM component. */ +#define ALT_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ROM_ADDR) + 0x10000) - 1)) + + +/* + * Component Instance : mpuscu + * + * Instance mpuscu of component ALT_MPUSCU. + * + * + */ +/* The address of the ALT_MPUSCU_REG register for the ALT_MPUSCU instance. */ +#define ALT_MPUSCU_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUSCU_ADDR) + ALT_MPUSCU_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_OFST 0xfffec000 +/* The start address of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUSCU_OFST)) +/* The lower bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_LB_ADDR ALT_MPUSCU_ADDR +/* The upper bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUSCU_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : mpul2 + * + * Instance mpul2 of component ALT_MPUL2. + * + * + */ +/* The address of the ALT_MPUL2_REG register for the ALT_MPUL2 instance. */ +#define ALT_MPUL2_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUL2 component. */ +#define ALT_MPUL2_OFST 0xfffef000 +/* The start address of the ALT_MPUL2 component. */ +#define ALT_MPUL2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUL2_OFST)) +/* The lower bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_LB_ADDR ALT_MPUL2_ADDR +/* The upper bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUL2_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : ocram + * + * Instance ocram of component ALT_OCRAM. + * + * + */ +/* The base address byte offset for the start of the ALT_OCRAM component. */ +#define ALT_OCRAM_OFST 0xffff0000 +/* The start address of the ALT_OCRAM component. */ +#define ALT_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OCRAM_OFST)) +/* The lower bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_LB_ADDR ALT_OCRAM_ADDR +/* The upper bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OCRAM_ADDR) + 0x10000) - 1)) + + +/* + * Address Space : ALT_HPS + * + * Address Map + * + * Address Range | Component + * :------------------------|:----------------- + * 0x00000000 - 0xfbffffff | Undefined + * 0xfc000000 - 0xfc000003 | ALT_STM + * 0xfc000004 - 0xfeffffff | Undefined + * 0xff000000 - 0xff000003 | ALT_DAP + * 0xff000004 - 0xff1fffff | Undefined + * 0xff200000 - 0xff3fffff | ALT_LWFPGASLVS + * 0xff400000 - 0xff47ffff | ALT_LWH2F + * 0xff480000 - 0xff4fffff | Undefined + * 0xff500000 - 0xff507fff | ALT_H2F + * 0xff508000 - 0xff5fffff | Undefined + * 0xff600000 - 0xff67ffff | ALT_F2H + * 0xff680000 - 0xff6fffff | Undefined + * 0xff700000 - 0xff701fff | ALT_EMAC0 + * 0xff702000 - 0xff703fff | ALT_EMAC1 + * 0xff704000 - 0xff7043ff | ALT_SDMMC + * 0xff704400 - 0xff704fff | Undefined + * 0xff705000 - 0xff7050ff | ALT_QSPI + * 0xff705100 - 0xff705fff | Undefined + * 0xff706000 - 0xff706fff | ALT_FPGAMGR + * 0xff707000 - 0xff707fff | ALT_ACPIDMAP + * 0xff708000 - 0xff70807f | ALT_GPIO0 + * 0xff708080 - 0xff708fff | Undefined + * 0xff709000 - 0xff70907f | ALT_GPIO1 + * 0xff709080 - 0xff709fff | Undefined + * 0xff70a000 - 0xff70a07f | ALT_GPIO2 + * 0xff70a080 - 0xff7fffff | Undefined + * 0xff800000 - 0xff87ffff | ALT_L3 + * 0xff880000 - 0xff8fffff | Undefined + * 0xff900000 - 0xff9fffff | ALT_NANDDATA + * 0xffa00000 - 0xffafffff | ALT_QSPIDATA + * 0xffb00000 - 0xffb3ffff | ALT_USB0 + * 0xffb40000 - 0xffb7ffff | ALT_USB1 + * 0xffb80000 - 0xffb807ff | ALT_NAND + * 0xffb80800 - 0xffb8ffff | Undefined + * 0xffb90000 - 0xffb90003 | ALT_FPGAMGRDATA + * 0xffb90004 - 0xffbfffff | Undefined + * 0xffc00000 - 0xffc001ff | ALT_CAN0 + * 0xffc00200 - 0xffc00fff | Undefined + * 0xffc01000 - 0xffc011ff | ALT_CAN1 + * 0xffc01200 - 0xffc01fff | Undefined + * 0xffc02000 - 0xffc020ff | ALT_UART0 + * 0xffc02100 - 0xffc02fff | Undefined + * 0xffc03000 - 0xffc030ff | ALT_UART1 + * 0xffc03100 - 0xffc03fff | Undefined + * 0xffc04000 - 0xffc040ff | ALT_I2C0 + * 0xffc04100 - 0xffc04fff | Undefined + * 0xffc05000 - 0xffc050ff | ALT_I2C1 + * 0xffc05100 - 0xffc05fff | Undefined + * 0xffc06000 - 0xffc060ff | ALT_I2C2 + * 0xffc06100 - 0xffc06fff | Undefined + * 0xffc07000 - 0xffc070ff | ALT_I2C3 + * 0xffc07100 - 0xffc07fff | Undefined + * 0xffc08000 - 0xffc080ff | ALT_SPTMR0 + * 0xffc08100 - 0xffc08fff | Undefined + * 0xffc09000 - 0xffc090ff | ALT_SPTMR1 + * 0xffc09100 - 0xffc1ffff | Undefined + * 0xffc20000 - 0xffc3ffff | ALT_SDR + * 0xffc40000 - 0xffcfffff | Undefined + * 0xffd00000 - 0xffd000ff | ALT_OSC1TMR0 + * 0xffd00100 - 0xffd00fff | Undefined + * 0xffd01000 - 0xffd010ff | ALT_OSC1TMR1 + * 0xffd01100 - 0xffd01fff | Undefined + * 0xffd02000 - 0xffd020ff | ALT_L4WD0 + * 0xffd02100 - 0xffd02fff | Undefined + * 0xffd03000 - 0xffd030ff | ALT_L4WD1 + * 0xffd03100 - 0xffd03fff | Undefined + * 0xffd04000 - 0xffd041ff | ALT_CLKMGR + * 0xffd04200 - 0xffd04fff | Undefined + * 0xffd05000 - 0xffd050ff | ALT_RSTMGR + * 0xffd05100 - 0xffd07fff | Undefined + * 0xffd08000 - 0xffd0bfff | ALT_SYSMGR + * 0xffd0c000 - 0xffdfffff | Undefined + * 0xffe00000 - 0xffe00003 | ALT_DMANONSECURE + * 0xffe00004 - 0xffe00fff | Undefined + * 0xffe01000 - 0xffe01003 | ALT_DMASECURE + * 0xffe01004 - 0xffe01fff | Undefined + * 0xffe02000 - 0xffe0207f | ALT_SPIS0 + * 0xffe02080 - 0xffe02fff | Undefined + * 0xffe03000 - 0xffe0307f | ALT_SPIS1 + * 0xffe03080 - 0xffefffff | Undefined + * 0xfff00000 - 0xfff000ff | ALT_SPIM0 + * 0xfff00100 - 0xfff00fff | Undefined + * 0xfff01000 - 0xfff010ff | ALT_SPIM1 + * 0xfff01100 - 0xfff01fff | Undefined + * 0xfff02000 - 0xfff0201f | ALT_SCANMGR + * 0xfff02020 - 0xfffcffff | Undefined + * 0xfffd0000 - 0xfffdffff | ALT_ROM + * 0xfffe0000 - 0xfffebfff | Undefined + * 0xfffec000 - 0xfffec003 | ALT_MPUSCU + * 0xfffec004 - 0xfffeefff | Undefined + * 0xfffef000 - 0xfffef003 | ALT_MPUL2 + * 0xfffef004 - 0xfffeffff | Undefined + * 0xffff0000 - 0xffffffff | ALT_OCRAM + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_HPS_H__ */ + diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h new file mode 100644 index 0000000000..f6090cd0ca --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h @@ -0,0 +1,259 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + + +/*! \file Altera - ALT_SOCAL */ + +#ifndef __ALTERA_SOCAL_H__ +#define __ALTERA_SOCAL_H__ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_SOCAL_UTIL SoCAL Utilities + * + * This file contains utility and support functions for the Altera SoCAL. + * @{ + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +/*! Cast the pointer to specified pointer type. + * + * Note: This macro expands to \e ptr value only for assembler language + * targets. + * + * \param type The pointer type to cast to + * \param ptr The pointer to apply the type cast to + */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities + * + * This section implements read and write functionality for various + * memory untis. The memory unit terms used for these functions are + * consistent with those used in the ARM Architecture Reference Manual + * ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are: + * + * Unit of Memory | Abbreviation | Size in Bits + * :---------------|:-------------|:------------: + * Byte | byte | 8 + * Half Word | hword | 16 + * Word | word | 32 + * Double Word | dword | 64 + * + * @{ + */ + +/*! Write the 8 bit byte to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 8 bit data byte to write to memory + */ +#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src)) + +/*! Read and return the 8 bit byte from the source address in device memory. + * \param src Read source pointer address + * \returns 8 bit data byte value + */ +#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src))) + +/*! Write the 16 bit half word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 16 bit data half word to write to memory + */ +#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src)) + +/*! Read and return the 16 bit half word from the source address in device memory. + * \param src Read source pointer address + * \returns 16 bit data half word value + */ +#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src))) + +/*! Write the 32 bit word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 32 bit data word to write to memory + */ +#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src)) + +/*! Read and return the 32 bit word from the source address in device memory. + * \param src Read source pointer address + * \returns 32 bit data word value + */ +#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src))) + +/*! Write the 64 bit double word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 64 bit data double word to write to memory + */ +#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src)) + +/*! Read and return the 64 bit double word from the source address in device memory. + * \param src Read source pointer address + * \returns 64 bit data double word value + */ +#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src))) + +/*! @} */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities + * + * This section implements useful macros to set, clear, change, and replace + * selected bits within a word in memory or a memory-mapped register. + * @{ + * + */ + +/*! Set selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination byte + */ +#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits))) + +/*! Clear selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination byte + */ +#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination byte + */ +#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits))) + +/*! Replace selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination byte + * \param src - Source bits to write to cleared bits in destination byte + */ +#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination halfword + */ +#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits))) + +/*! Clear selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination halfword + */ +#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination halfword + */ +#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits))) + +/*! Replace selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination halfword + * \param src - Source bits to write to cleared bits in destination halfword + */ +#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination word + */ +#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits))) + +/*! Clear selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination word + */ +#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination word + */ +#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits))) + +/*! Replace selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination word + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination doubleword + */ +#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits))) + +/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination doubleword + */ +#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination doubleword + */ +#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits))) + +/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination doubleword + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_SOCAL_H__ */ diff --git a/bsps/arm/altera-cyclone-v/include/tm27.h b/bsps/arm/altera-cyclone-v/include/tm27.h new file mode 100644 index 0000000000..c17c0107b4 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/atsam/headers.am b/bsps/arm/atsam/headers.am new file mode 100644 index 0000000000..1ec34a2e69 --- /dev/null +++ b/bsps/arm/atsam/headers.am @@ -0,0 +1,269 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/atsam/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/atsam-spi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/pin-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/power.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/sc16is752.h +include_bsp_HEADERS += ../../../../../../bsps/arm/atsam/include/bsp/spi.h + +include_libchipdir = $(includedir)/libchip +include_libchip_HEADERS = +include_libchip_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/chip.h +include_libchip_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/compiler.h + +include_libchip_includedir = $(includedir)/libchip/include +include_libchip_include_HEADERS = +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/acc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/adc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/aes.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/afe_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/afec.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/chip.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/dac_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/efc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/exceptions.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/flashd.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/gmac.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/gmacd.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/hsmci.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/icm.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/isi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/iso7816_4.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mcan.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mcid.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mediaLB.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/mpu.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio_capture.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pio_it.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pmc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/pwmc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/qspi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/qspi_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rstc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rtc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/rtt.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sdramc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/smc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/spi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/spi_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/ssc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/supc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/tc.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/timetick.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/trace.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/trng.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/twi.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/twid.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/uart.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/uart_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usart.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usart_dma.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/usbhs.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/video.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/wdt.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdmac.h +include_libchip_include_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/xdmad.h + +include_libchip_include_same70dir = $(includedir)/libchip/include/same70 +include_libchip_include_same70_HEADERS = +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70j21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70n21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q19.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q20.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/same70q21.h +include_libchip_include_same70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/system_same70.h + +include_libchip_include_same70_componentdir = $(includedir)/libchip/include/same70/component +include_libchip_include_same70_component_HEADERS = +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h +include_libchip_include_same70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h + +include_libchip_include_same70_piodir = $(includedir)/libchip/include/same70/pio +include_libchip_include_same70_pio_HEADERS = +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h +include_libchip_include_same70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h + +include_libchip_include_sams70dir = $(includedir)/libchip/include/sams70 +include_libchip_include_sams70_HEADERS = +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h +include_libchip_include_sams70_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h + +include_libchip_include_sams70_componentdir = $(includedir)/libchip/include/sams70/component +include_libchip_include_sams70_component_HEADERS = +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h +include_libchip_include_sams70_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h + +include_libchip_include_sams70_piodir = $(includedir)/libchip/include/sams70/pio +include_libchip_include_sams70_pio_HEADERS = +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h +include_libchip_include_sams70_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h + +include_libchip_include_samv71dir = $(includedir)/libchip/include/samv71 +include_libchip_include_samv71_HEADERS = +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h +include_libchip_include_samv71_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h + +include_libchip_include_samv71_componentdir = $(includedir)/libchip/include/samv71/component +include_libchip_include_samv71_component_HEADERS = +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h +include_libchip_include_samv71_component_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h + +include_libchip_include_samv71_piodir = $(includedir)/libchip/include/samv71/pio +include_libchip_include_samv71_pio_HEADERS = +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h +include_libchip_include_samv71_pio_HEADERS += ../../../../../../bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h diff --git a/bsps/arm/atsam/include/bsp.h b/bsps/arm/atsam/include/bsp.h new file mode 100644 index 0000000000..cd0103ad70 --- /dev/null +++ b/bsps/arm/atsam/include/bsp.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_BSP_H +#define LIBBSP_ARM_ATSAM_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +uint32_t atsam_systick_frequency(void); + +#define BSP_ARMV7M_SYSTICK_FREQUENCY atsam_systick_frequency() + +struct rtems_bsdnet_ifconfig; + +int if_atsam_attach(struct rtems_bsdnet_ifconfig *config, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "atsam0" + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH if_atsam_attach + +/** + * @brief Interface driver configuration. + */ +typedef struct { + /** + * @brief Maximum retries for MDIO communication. + */ + uint32_t mdio_retries; + + /** + * @brief Address of PHY. + * + * Use 0xff to search for a PHY. + */ + uint8_t phy_addr; +} if_atsam_config; + +extern char atsam_memory_dtcm_begin[]; +extern char atsam_memory_dtcm_end[]; +extern char atsam_memory_dtcm_size[]; + +extern char atsam_memory_intflash_begin[]; +extern char atsam_memory_intflash_end[]; +extern char atsam_memory_intflash_size[]; + +extern char atsam_memory_intsram_begin[]; +extern char atsam_memory_intsram_end[]; +extern char atsam_memory_intsram_size[]; + +extern char atsam_memory_itcm_begin[]; +extern char atsam_memory_itcm_end[]; +extern char atsam_memory_itcm_size[]; + +extern char atsam_memory_nocache_begin[]; +extern char atsam_memory_nocache_end[]; +extern char atsam_memory_nocache_size[]; + +extern char atsam_memory_qspiflash_begin[]; +extern char atsam_memory_qspiflash_end[]; +extern char atsam_memory_qspiflash_size[]; + +extern char atsam_memory_sdram_begin[]; +extern char atsam_memory_sdram_end[]; +extern char atsam_memory_sdram_size[]; + +void atsam_rtc_get_time(rtems_time_of_day *tod); + + + +void bsp_restart( const void *const addr ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_BSP_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-clock-config.h b/bsps/arm/atsam/include/bsp/atsam-clock-config.h new file mode 100644 index 0000000000..396986894b --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-clock-config.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ATSAM_CLOCK_CONFIG_H +#define ATSAM_CLOCK_CONFIG_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if ATSAM_CHANGE_CLOCK_FROM_SRAM != 0 +/* Note: fast_text is the simplest section to put this code into. Other + * possibilities would include creating a new section. */ +#define ATSAM_START_SRAM_SECTION BSP_FAST_TEXT_SECTION +#else +#define ATSAM_START_SRAM_SECTION +#endif + +struct atsam_clock_config { + /* Initialization value for the PMC_PLLAR. */ + uint32_t pllar_init; + /* Initialization value for the PMC_MCKR. */ + uint32_t mckr_init; + /* Resulting frequency in Hz. */ + uint32_t mck_freq; +}; + +ATSAM_START_SRAM_SECTION +extern const struct atsam_clock_config atsam_clock_config; + +#define BOARD_MCK (atsam_clock_config.mck_freq) + +struct BOARD_Sdram_Config { + uint32_t sdramc_tr; + uint32_t sdramc_cr; + uint32_t sdramc_mdr; + uint32_t sdramc_cfr1; +}; + +ATSAM_START_SRAM_SECTION +extern const struct BOARD_Sdram_Config BOARD_Sdram_Config; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ATSAM_CLOCK_CONFIG_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-i2c.h b/bsps/arm/atsam/include/bsp/atsam-i2c.h new file mode 100644 index 0000000000..7425db9f7b --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-i2c.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ATSAM_I2C_H +#define LIBBSP_ARM_ATSAM_ATSAM_I2C_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TWI_AMOUNT_PINS 2 + +typedef enum { + TX_SEND_DATA, + TX_SEND_STOP, + TX_CONT_MESSAGE_NEEDED, + RX_SEND_DATA, + RX_SEND_STOP, + RX_CONT_MESSAGE_NEEDED, + TX_RX_STOP_SENT +}transfer_state; + +typedef struct { + uint8_t status; + uint8_t *data; + bool stop_request; + uint32_t data_size; + uint32_t already_transferred; + transfer_state trans_state; +} transfer_desc; + +typedef struct { + i2c_bus base; + i2c_msg *msgs; + Twihs *regs; + transfer_desc trans_desc; + uint32_t msg_todo; + uint32_t current_msg_todo; + uint8_t *current_msg_byte; + uint32_t input_clock; + bool read; + rtems_id task_id; + rtems_vector_number irq; +} atsam_i2c_bus; + +int i2c_bus_register_atsam( + const char *bus_path, + Twihs *register_base, + rtems_vector_number irq, + const Pin pins[TWI_AMOUNT_PINS] +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_ATSAM_I2C_H */ diff --git a/bsps/arm/atsam/include/bsp/atsam-spi.h b/bsps/arm/atsam/include/bsp/atsam-spi.h new file mode 100644 index 0000000000..548dd544f4 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/atsam-spi.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ATSAM_SPI_H +#define LIBBSP_ARM_ATSAM_ATSAM_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int spi_bus_register_atsam( + const char *bus_path, + uint8_t spi_peripheral_id, + Spi *spi_regs, + const Pin *pins, + size_t pin_count +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_ATSAM_SPI_H */ diff --git a/bsps/arm/atsam/include/bsp/i2c.h b/bsps/arm/atsam/include/bsp/i2c.h new file mode 100644 index 0000000000..1ea1204ff5 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/i2c.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_I2C_H +#define LIBBSP_ARM_ATSAM_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ATSAM_I2C_0_BUS_PATH "/dev/i2c-0" +#define ATSAM_I2C_1_BUS_PATH "/dev/i2c-1" +#define ATSAM_I2C_2_BUS_PATH "/dev/i2c-2" + +int atsam_register_i2c_0(void); + +int atsam_register_i2c_1(void); + +int atsam_register_i2c_2(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_I2C_H */ diff --git a/bsps/arm/atsam/include/bsp/irq.h b/bsps/arm/atsam/include/bsp/irq.h new file mode 100644 index 0000000000..19370e4852 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/irq.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_ESV_70_IRQ_H +#define LIBBSP_ARM_ATSAM_ESV_70_IRQ_H + +#include + +#ifndef ASM + #include + #include + #include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX 64 + +#endif /* LIBBSP_ARM_ATSAM_ESV_70_IRQ_H */ diff --git a/bsps/arm/atsam/include/bsp/pin-config.h b/bsps/arm/atsam/include/bsp/pin-config.h new file mode 100644 index 0000000000..8f4a61428f --- /dev/null +++ b/bsps/arm/atsam/include/bsp/pin-config.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_PIN_CONFIG_H +#define LIBBSP_ARM_ATSAM_PIN_CONFIG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const Pin atsam_pin_config[]; + +extern const size_t atsam_pin_config_count; + +extern const uint32_t atsam_matrix_ccfg_sysio; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_PIN_CONFIG_H */ diff --git a/bsps/arm/atsam/include/bsp/power.h b/bsps/arm/atsam/include/bsp/power.h new file mode 100644 index 0000000000..a352386a0e --- /dev/null +++ b/bsps/arm/atsam/include/bsp/power.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_POWER_H +#define LIBBSP_ARM_ATSAM_POWER_H + +#include + +#include + +#ifdef __cplusplus +extern "C"{ +#endif /* __cplusplus */ + +/** + * @brief Status of the Low Power Support + */ +typedef enum { + /** + * @brief Used for Initialization of Handlers + */ + ATSAM_POWER_INIT, + /** + * @brief Used for Switching On of Handlers + */ + ATSAM_POWER_ON, + /** + * @brief Used for Switching Off of Handlers + */ + ATSAM_POWER_OFF +} atsam_power_state; + +/** + * @brief Control structure for power control handling + */ +typedef struct atsam_power_control { + /** + * @brief Data pointer to the handler with its desired state + */ + void (*handler)( + const struct atsam_power_control *control, + atsam_power_state state + ); + /** + * @brief Data chunk that is used by the handler + */ + union { + void *arg; + struct { + uint8_t first; + uint8_t last; + } peripherals; + } data; +} atsam_power_control; + +/** + * @brief Performs a power state change according to the state parameter. + * + * The handlers of the control table are invoked in forward order (invocation + * starts with table index zero) for the ATSAM_POWER_INIT and ATSAM_POWER_OFF + * states, otherwise the handlers are invoked in reverse order (invocation + * starts with the last table index). + * + * @param controls Table with power controls. + * @param n Count of power control table entries. + * @param state The desired power state. + * + * @code + * #include + * #include + * + * #include + * + * static atsam_power_data_rtc_driver rtc_data = { .interval = 5 }; + * + * static const atsam_power_control power_controls[] = { + * ATSAM_POWER_CLOCK_DRIVER, + * ATSAM_POWER_RTC_DRIVER(&rtc_data), + * ATSAM_POWER_SLEEP_MODE + * }; + * + * static pthread_once_t once = PTHREAD_ONCE_INIT; + * + * static void init(void) + * { + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_INIT + * ); + * } + * + * void power_init(void) + * { + * pthread_once(&once, init); + * } + * + * void low_power(void) + * { + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_OFF + * ); + * atsam_power_change_state( + * &power_controls[0], + * RTEMS_ARRAY_SIZE(power_controls), + * ATSAM_POWER_ON + * ); + * } + * @end + */ +void atsam_power_change_state( + const atsam_power_control *controls, + size_t n, + atsam_power_state state +); + +/** + * @brief Power handler for a set of peripherals according to the specified + * peripheral indices. + * + * For the power off state, the peripherals are enabled in the PMC. + * + * For the power on state, the peripherals are disabled in the Power Management + * Controller (PMC). + * + * @see ATSAM_POWER_PERIPHERAL(). + */ +void atsam_power_handler_peripheral( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler for the clock driver. + * + * For the power off state, the system tick is disabled. + * + * For the power on state, the system tick is enabled. In case no clock driver + * is used by the application, then this may lead to a spurious interrupt + * resulting in a fatal error. + * + * @see ATSAM_POWER_CLOCK_DRIVER(). + */ +void atsam_power_handler_clock_driver( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler for the RTC driver. + * + * This handler installs an interrupt handler during power support initialization. + * + * For the power off state, the RTC alarm interrupt is set up according to the + * interval of the corresponding handler data. + * + * For the power on state, the RTC alarm interrupt is disabled. + * + * @see ATSAM_POWER_RTC_DRIVER(). + */ +void atsam_power_handler_rtc_driver( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Power handler to enter the processor sleep mode. + * + * For the power off state, the processor is set into the sleep mode and issues + * a wait for interrupt instruction. + * + * @see ATSAM_POWER_SLEEP_MODE(). + */ +void atsam_power_handler_sleep_mode( + const atsam_power_control *controls, + atsam_power_state state +); + +/** + * @brief Initializer for a peripheral power support. + * + * @param f The first peripheral index. + * @param l The last peripheral index. + */ +#define ATSAM_POWER_PERIPHERAL(f, l) \ + { \ + .handler = atsam_power_handler_peripheral, \ + .data = { .peripherals = { .first = f, .last = l } } \ + } + +#define ATSAM_POWER_HANDLER(h, a) \ + { \ + .handler = h, \ + .data = { .arg = a } \ + } + +#define ATSAM_POWER_CLOCK_DRIVER \ + { .handler = atsam_power_handler_clock_driver } + +#define ATSAM_POWER_SLEEP_MODE \ + { .handler = atsam_power_handler_sleep_mode } + +/** + * @brief Data for RTC driver power support. + * + * @see ATSAM_POWER_RTC_DRIVER(). + */ +typedef struct { + /** + * @brief Interval in seconds for which the power off mode should be active. + */ + uint8_t interval; +} atsam_power_data_rtc_driver; + +/** + * @brief Initializer for RTC driver power support. + * + * @param a Pointer to RTC driver power data. + * + * @see atsam_power_data_rtc_driver. + */ +#define ATSAM_POWER_RTC_DRIVER(a) \ + { \ + .handler = atsam_power_handler_rtc_driver, \ + .data = { .arg = a } \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_POWER_H */ diff --git a/bsps/arm/atsam/include/bsp/sc16is752.h b/bsps/arm/atsam/include/bsp/sc16is752.h new file mode 100644 index 0000000000..35d298a7ed --- /dev/null +++ b/bsps/arm/atsam/include/bsp/sc16is752.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_SC16IS752_H +#define LIBBSP_ARM_ATSAM_SC16IS752_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + sc16is752_spi_context base; + Pin irq_pin; +} atsam_sc16is752_spi_context; + +/** + * @brief Creates an SPI connected SC16IS752 device. + * + * This devices uses the interrupt server, see + * rtems_interrupt_server_initialize(). + * + * The device claims the interrupt of the PIO block. + * + * @param[in] ctx The device context. May have an arbitrary content. + * @param[in] device_path The device file path for the new device. + * @param[in] mode The SC16IS752 mode. + * @param[in] input_frequency The input frequency in Hertz of the SC16IS752 + * chip. See XTAL1 and XTAL2 pins. + * @param[in] spi_path The SPI bus device path. + * @param[in] spi_chip_select The SPI chip select (starts with 0, the SPI + * driver uses SPI_ChipSelect(1 << spi_chip_select)). + * @param[in] spi_speed_hz The SPI bus speed in Hertz. + * @param[in] irq_pin The interrupt pin, e.g. { PIO_PD28, PIOD, ID_PIOD, + * PIO_INPUT, PIO_IT_LOW_LEVEL }. + * + * @return See sc16is752_spi_create(). + */ +int atsam_sc16is752_spi_create( + atsam_sc16is752_spi_context *ctx, + const char *device_path, + sc16is752_mode mode, + uint32_t input_frequency, + const char *spi_path, + uint8_t spi_chip_select, + uint32_t spi_speed_hz, + const Pin *irq_pin +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */ diff --git a/bsps/arm/atsam/include/bsp/spi.h b/bsps/arm/atsam/include/bsp/spi.h new file mode 100644 index 0000000000..958e629ba3 --- /dev/null +++ b/bsps/arm/atsam/include/bsp/spi.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ATSAM_SPI_H +#define LIBBSP_ARM_ATSAM_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ATSAM_SPI_0_BUS_PATH "/dev/spi-0" +#define ATSAM_SPI_1_BUS_PATH "/dev/spi-1" +#define ATSAM_SPI_2_BUS_PATH "/dev/spi-2" + +int atsam_register_spi_0(void); + +int atsam_register_spi_1(void); + +int atsam_register_spi_2(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_ATSAM_SPI_H */ diff --git a/bsps/arm/atsam/include/libchip/chip.h b/bsps/arm/atsam/include/libchip/chip.h new file mode 100644 index 0000000000..56e8cffbd1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/chip.h @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SAMS7_CHIP_H +#define SAMS7_CHIP_H + +#include "compiler.h" + + +/************************************************* + * Memory type and its attribute + *************************************************/ +#define SHAREABLE 1 +#define NON_SHAREABLE 0 +/********************************************************************************************************************************************************************* +* Memory Type Definition Memory TEX attribute C attribute B attribute S attribute +**********************************************************************************************************************************************************************/ + +#define STRONGLY_ORDERED_SHAREABLE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // +#define SHAREABLE_DEVICE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos)) // DO not care // +#define INNER_OUTER_NORMAL_WT_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_WB_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_OUTER_NORMAL_WB_RWA_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define NON_SHAREABLE_DEVICE_TYPE ((0x02 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // + +/* Normal memory attributes with outer capability rules to Non_Cacable */ + +#define INNER_NORMAL_NOCACHE_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WB_RWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WT_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) +#define INNER_NORMAL_WB_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) + +/* SCB Interrupt Control State Register Definitions */ +#ifndef SCB_VTOR_TBLBASE_Pos + #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ + #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ +#endif + + +/* + * Peripherals + */ +#include "include/acc.h" +#include "include/aes.h" +#include "include/afec.h" +#include "include/efc.h" +#include "include/pio.h" +#include "include/pio_it.h" +#include "include/efc.h" +#include "include/rstc.h" +#include "include/mpu.h" +#include "include/gmac.h" +#include "include/gmacd.h" +#include "include/video.h" +#include "include/icm.h" +#include "include/isi.h" +#include "include/exceptions.h" +#include "include/pio_capture.h" +#include "include/rtc.h" +#include "include/rtt.h" +#include "include/tc.h" +#include "include/timetick.h" +#include "include/twi.h" +#include "include/flashd.h" +#include "include/pmc.h" +#include "include/pwmc.h" +#include "include/mcan.h" +#include "include/supc.h" +#include "include/usart.h" +#include "include/uart.h" +#include "include/isi.h" +#include "include/hsmci.h" +#include "include/ssc.h" +#include "include/twi.h" +#include "include/trng.h" +#include "include/wdt.h" +#include "include/spi.h" +#include "include/qspi.h" +#include "include/trace.h" +#include "include/xdmac.h" +#include "include/xdma_hardware_interface.h" +#include "include/xdmad.h" +#include "include/mcid.h" +#include "include/twid.h" +#include "include/spi_dma.h" +#include "include/qspi_dma.h" +#include "include/uart_dma.h" +#include "include/usart_dma.h" +#include "include/twid.h" +#include "include/afe_dma.h" +#include "include/dac_dma.h" +#include "include/usbhs.h" + +#define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral(dwId) +#define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral(dwId) + +#endif /* SAMS7_CHIP_H */ diff --git a/bsps/arm/atsam/include/libchip/compiler.h b/bsps/arm/atsam/include/libchip/compiler.h new file mode 100644 index 0000000000..f36013ac21 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/compiler.h @@ -0,0 +1,476 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +#ifdef __rtems__ +#include +#endif /* __rtems__ */ +/* + * Peripherals registers definitions + */ +#if defined __SAMV71J19__ \ + || defined __SAMV71J20__ \ + || defined __SAMV71J21__ \ + || defined __SAMV71N19__ \ + || defined __SAMV71N20__ \ + || defined __SAMV71N21__ \ + || defined __SAMV71Q19__ \ + || defined __SAMV71Q20__ \ + || defined __SAMV71Q21__ + #include "include/samv71/samv71.h" +#elif defined __SAMS70J19__ \ + || defined __SAMS70J20__ \ + || defined __SAMS70J21__ \ + || defined __SAMS70N19__ \ + || defined __SAMS70N20__ \ + || defined __SAMS70N21__ \ + || defined __SAMS70Q19__ \ + || defined __SAMS70Q20__ \ + || defined __SAMS70Q21__ + #include "include/sams70/sams70.h" +#elif defined __SAME70J19__ \ + || defined __SAME70J20__ \ + || defined __SAME70J21__ \ + || defined __SAME70N19__ \ + || defined __SAME70N20__ \ + || defined __SAME70N21__ \ + || defined __SAME70Q19__ \ + || defined __SAME70Q20__ \ + || defined __SAME70Q21__ + #include "include/same70/same70.h" +#else + #error "please define correct macro for the chip first!" +#endif + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +/* Define WEAK attribute */ +#if defined (__CC_ARM) + #define WEAK __attribute__ ((weak)) +#elif defined (__ICCARM__) + #define WEAK __weak +#elif defined (__GNUC__) + #define WEAK __attribute__ ((weak)) +#endif + +/* Define Compiler name of tool chains */ +#if defined (__CC_ARM) + #define COMPILER_NAME "KEIL" +#elif defined (__ICCARM__) + #define COMPILER_NAME "IAR" +#elif defined (__GNUC__) + #define COMPILER_NAME "GCC" +#endif + +/* Define NO_INIT attribute */ +#if defined (__CC_ARM) + #define NO_INIT +#elif defined (__ICCARM__) + #define NO_INIT __no_init +#elif defined (__GNUC__) + #define NO_INIT +#endif + + +/* Define memory sync for tool chains */ +#if defined (__CC_ARM) + #define memory_sync() __dsb(15);__isb(15); +#elif defined (__ICCARM__) + #define memory_sync() __DSB();__ISB(); +#elif defined (__GNUC__) + #define memory_sync() __DSB();__ISB(); +#endif + +/* Define memory barrier for tool chains */ +#if defined (__CC_ARM) + #define memory_barrier() __dmb(15); +#elif defined (__ICCARM__) + #define memory_barrier() __DMB(); +#elif defined (__GNUC__) + #define memory_barrier() __DMB(); +#endif + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2(a, b) a##b +#define TPASTE3(a, b, c) a##b##c +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2(a, b) TPASTE2(a, b) +#define ATPASTE3(a, b, c) TPASTE3(a, b, c) +//! @} + + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent structure and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent structure and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined (__CC_ARM) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined (__ICCARM__) + #define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined (__GNUC__) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Set aligned boundary. + */ +#if defined (__CC_ARM) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined (__ICCARM__) + #define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined (__GNUC__) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Set word-aligned boundary. + */ + +#if defined (__CC_ARM) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif defined (__ICCARM__) + #define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#elif defined (__GNUC__) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#endif + + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + +#define be32_to_cpu(x) __REV(x) +#define cpu_to_be32(x) __REV(x) +#define BE32_TO_CPU(x) __REV(x) +#define CPU_TO_BE32(x) __REV(x) + +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while (0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ((IRQn_Type)int_num); \ + NVIC_SetPriority((IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ((IRQn_Type)int_num); \ + + //@} + + +# define cpu_irq_enable() \ + do { \ + /*g_interrupt_enabled = true; */ \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + /*g_interrupt_enabled = false; */ \ + } while (0) + + typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) + extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + + static volatile uint32_t cpu_irq_critical_section_counter; + static volatile bool cpu_irq_prev_interrupt_state; + + static inline irqflags_t cpu_irq_save(void) + { + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; + } + + static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) + { + return (flags); + } + + static inline void cpu_irq_restore(irqflags_t flags) + { + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); + } + /* + void cpu_irq_enter_critical(void); + void cpu_irq_leave_critical(void);*/ + + /** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + + + //_____ M A C R O S ________________________________________________________ + + /*! \name Usual Constants + */ + //! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus + #if !defined(__bool_true_false_are_defined) + #define false FALSE + #define true TRUE + #endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 + //! @} + + /*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) + +#endif // __ASSEMBLY__ + +#endif // _COMPILER_H_ diff --git a/bsps/arm/atsam/include/libchip/include/acc.h b/bsps/arm/atsam/include/libchip/include/acc.h new file mode 100644 index 0000000000..4d10665bc6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/acc.h @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ACC + * -# Initialize the ACC with ACC_Initialize(). + * -# Select the active channel using ACC_EnableChannel() + * -# Start the conversion with ACC_StartConversion() + * -# Wait the end of the conversion by polling status with ACC_GetStatus() + * -# Finally, get the converted data using ACC_GetConvertedData() + * + */ +#ifndef _ACC_ +#define _ACC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define ACC_SELPLUS_AD12B0 0 +#define ACC_SELPLUS_AD12B1 1 +#define ACC_SELPLUS_AD12B2 2 +#define ACC_SELPLUS_AD12B3 3 +#define ACC_SELPLUS_AD12B4 4 +#define ACC_SELPLUS_AD12B5 5 +#define ACC_SELPLUS_AD12B6 6 +#define ACC_SELPLUS_AD12B7 7 +#define ACC_SELMINUS_TS 0 +#define ACC_SELMINUS_ADVREF 1 +#define ACC_SELMINUS_DAC0 2 +#define ACC_SELMINUS_DAC1 3 +#define ACC_SELMINUS_AD12B0 4 +#define ACC_SELMINUS_AD12B1 5 +#define ACC_SELMINUS_AD12B2 6 +#define ACC_SELMINUS_AD12B3 7 + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define ACC_CfgModeReg(pAcc, mode) { \ + (pAcc)->ACC_MR = (mode);\ + } + +#define ACC_GetModeReg(pAcc) ((pAcc)->ACC_MR) + +#define ACC_StartConversion(pAcc) ((pAcc)->ACC_CR = ACC_CR_START) + +#define ACC_SoftReset(pAcc) ((pAcc)->ACC_CR = ACC_CR_SWRST) + +#define ACC_EnableChannel(pAcc, dwChannel) {\ + assert(dwChannel < 16);\ + (pAcc)->ACC_CHER = (1 << (dwChannel));\ + } + +#define ACC_DisableChannel(pAcc, dwChannel) {\ + assert(dwChannel < 16);\ + (pAcc)->ACC_CHDR = (1 << (dwChannel));\ + } + +#define ACC_EnableIt(pAcc, dwMode) {\ + assert(((dwMode)&0xFFF00000)== 0);\ + (pAcc)->ACC_IER = (dwMode);\ + } + +#define ACC_DisableIt(pAcc, dwMode) {\ + assert(((dwMode)&0xFFF00000)== 0);\ + (pAcc)->ACC_IDR = (dwMode);\ + } + +#define ACC_EnableDataReadyIt(pAcc) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) + +#define ACC_GetStatus(pAcc) ((pAcc)->ACC_ISR) + +#define ACC_GetChannelStatus(pAcc) ((pAcc)->ACC_CHSR) + +#define ACC_GetInterruptMaskStatus(pAcc) ((pAcc)->ACC_IMR) + +#define ACC_GetLastConvertedData(pAcc) ((pAcc)->ACC_LCDR) + +#define ACC_CfgAnalogCtrlReg(pAcc, dwMode) {\ + assert(((dwMode) & 0xFFFCFF3C) == 0);\ + (pAcc)->ACC_ACR = (dwMode);\ + } + +#define ACC_CfgExtModeReg(pAcc, extmode) {\ + assert(((extmode) & 0xFF00FFFE) == 0);\ + (pAcc)->ACC_EMR = (extmode);\ + } + +#define ACC_GetAnalogCtrlReg(pAcc) ((pAcc)->ACC_ACR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ACC_Configure(Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, + uint8_t ucSelminus, uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert); + +extern void ACC_SetComparisonPair(Acc *pAcc, uint8_t ucSelplus, + uint8_t ucSelminus); + +extern uint32_t ACC_GetComparisonResult(Acc *pAcc, uint32_t dwStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ACC_ */ diff --git a/bsps/arm/atsam/include/libchip/include/adc.h b/bsps/arm/atsam/include/libchip/include/adc.h new file mode 100644 index 0000000000..a5585c9651 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/adc.h @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ADC. + * -# Initialize the ADC with ADC_Initialize(). + * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming(). + * -# Select the active channel using ADC_EnableChannel(). + * -# Start the conversion with ADC_StartConversion(). + * -# Wait the end of the conversion by polling status with ADC_GetStatus(). + * -# Finally, get the converted data using ADC_GetConvertedData() or + * ADC_GetLastConvertedData(). + * +*/ +#ifndef _ADC_ +#define _ADC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* Max. ADC Clock Frequency (Hz) */ +#define ADC_CLOCK_MAX 20000000 + +/* Max. normal ADC startup time (us) */ +#define ADC_STARTUP_NORMAL_MAX 40 +/* Max. fast ADC startup time (us) */ +#define ADC_STARTUP_FAST_MAX 12 + +/* Definitions for ADC channels */ +#define ADC_CHANNEL_0 0 +#define ADC_CHANNEL_1 1 +#define ADC_CHANNEL_2 2 +#define ADC_CHANNEL_3 3 +#define ADC_CHANNEL_4 4 +#define ADC_CHANNEL_5 5 +#define ADC_CHANNEL_6 6 +#define ADC_CHANNEL_7 7 +#define ADC_CHANNEL_8 8 +#define ADC_CHANNEL_9 9 +#define ADC_CHANNEL_10 10 +#define ADC_CHANNEL_11 11 +#define ADC_CHANNEL_12 12 +#define ADC_CHANNEL_13 13 +#define ADC_CHANNEL_14 14 +#define ADC_CHANNEL_15 15 + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define ADC_GetModeReg(pAdc) ((pAdc)->ADC_MR) + +#define ADC_StartConversion(pAdc) ((pAdc)->ADC_CR = ADC_CR_START) + +#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL) + +#define ADC_EnableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHER = (1 << (dwChannel));\ + } + +#define ADC_DisableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHDR = (1 << (dwChannel));\ + } + +#define ADC_EnableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IER = (dwMode);\ + } + +#define ADC_DisableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IDR = (dwMode);\ + } + +#define ADC_SetChannelGain(pAdc,dwMode) {\ + (pAdc)->ADC_CGR = dwMode;\ + } + +#define ADC_SetChannelOffset(pAdc,dwMode) {\ + (pAdc)->ADC_COR = dwMode;\ + } + +#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY) + +#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) + +#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk)) + +#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) + +#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) + +#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ADC_Initialize(Adc *pAdc, uint32_t dwId); +extern uint32_t ADC_SetClock(Adc *pAdc, uint32_t dwPres, uint32_t dwMck); +extern void ADC_SetTiming(Adc *pAdc, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling); +extern void ADC_SetTrigger(Adc *pAdc, uint32_t dwTrgSel); +extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetLowResolution(Adc *pAdc, uint32_t bEnDis); +extern void ADC_SetSleepMode(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetFastWakeup(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetSequenceMode(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetSequence(Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2); +extern void ADC_SetSequenceByList(Adc *pAdc, uint8_t ucChList[], + uint8_t ucNumCh); +extern void ADC_SetAnalogChange(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetTagEnable(Adc *pAdc, uint8_t bEnDis); +extern void ADC_SetCompareChannel(Adc *pAdc, uint32_t dwChannel); +extern void ADC_SetCompareMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetComparisonWindow(Adc *pAdc, uint32_t dwHi_Lo); +extern uint8_t ADC_CheckConfiguration(Adc *pAdc, uint32_t dwMcK); +extern uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t dwChannel); +extern void ADC_SetTsAverage(Adc *pADC, uint32_t dwAvg2Conv); +extern uint32_t ADC_GetTsXPosition(Adc *pADC); +extern uint32_t ADC_GetTsYPosition(Adc *pADC); +extern uint32_t ADC_GetTsPressure(Adc *pADC); +extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime); +extern void ADC_SetTsPenDetect(Adc *pADC, uint8_t bEnDis); +extern void ADC_SetStartupTime(Adc *pAdc, uint32_t dwUs); +extern void ADC_SetTrackingTime(Adc *pAdc, uint32_t dwNs); +extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod); +extern void ADC_SetTsMode(Adc *pADC, uint32_t dwMode); +extern void ADC_TsCalibration(Adc *pAdc); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ADC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/aes.h b/bsps/arm/atsam/include/libchip/include/aes.h new file mode 100644 index 0000000000..1fca47989d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/aes.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _AES_ +#define _AES_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*----------------------------------------------------------------------------*/ +/* Definition */ +/*----------------------------------------------------------------------------*/ +#define AES_MR_CIPHER_ENCRYPT 1 +#define AES_MR_CIPHER_DECRYPT 0 +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +extern void AES_Start(void); +extern void AES_SoftReset(void); +extern void AES_Recount(void); +extern void AES_Configure(uint32_t mode); +extern void AES_EnableIt(uint32_t sources); +extern void AES_DisableIt(uint32_t sources); +extern uint32_t AES_GetStatus(void); +extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength); +extern void AES_SetInput(uint32_t *data); +extern void AES_GetOutput(uint32_t *data); +extern void AES_SetVector(const uint32_t *pVector); +extern void AES_SetAadLen(uint32_t len); +extern void AES_SetDataLen(uint32_t len); +extern void AES_SetGcmHash(uint32_t *hash); +extern void AES_GetGcmTag(uint32_t *tag); +extern void AES_GetGcmCounter(uint32_t *counter); +extern void AES_GetGcmH(uint32_t *h); + + +#endif /* #ifndef _AES_ */ diff --git a/bsps/arm/atsam/include/libchip/include/afe_dma.h b/bsps/arm/atsam/include/libchip/include/afe_dma.h new file mode 100644 index 0000000000..6bcfbb3bcc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/afe_dma.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFE_DMA_ +#define _AFE_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** AFE transfer complete callback. */ +typedef void (*AfeCallback)(uint8_t, void *); + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the AFE_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Rx data. */ + uint32_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** Callback function invoked at the end of transfer. */ + AfeCallback callback; + /** Callback arguments. */ + void *pArgument; +} AfeCmd; + + +/** Constant structure associated with AFE port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** Pointer to AFE Hardware registers */ + Afec *pAfeHw; + /** Current SpiCommand being processed */ + AfeCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** AFEC Id as defined in the product datasheet */ + uint8_t afeId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} AfeDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +#define AFE_OK 0 +#define AFE_ERROR 1 +#define AFE_ERROR_LOCK 2 +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t Afe_ConfigureDma(AfeDma *pAfed , + Afec *pAfeHw , + uint8_t AfeId, + sXdmad *pXdmad); +extern uint32_t Afe_SendData(AfeDma *pAfed, AfeCmd *pCommand); + + +#endif /* #ifndef _AFE_DMA_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/afec.h b/bsps/arm/atsam/include/libchip/include/afec.h new file mode 100644 index 0000000000..75c74ff2b6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/afec.h @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFEC_ +#define _AFEC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_SETTLING_Pos 20 +#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) +/**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_SETTLING_AST3 (0x0u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST5 (0x1u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST9 (0x2u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/ +#define AFEC_MR_SETTLING_AST17 (0x3u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/ + +/***************************** Single Trigger Mode ****************************/ +#define AFEC_EMR_STM_Pos 25 +#define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) +/**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to + get an averaged result. */ +#define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required + to get an averaged value. */ + +/***************************** TAG of the AFEC_LDCR Register ******************/ +#define AFEC_EMR_TAG_Pos 24 +#define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */ +#define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero +in AFEC_LDCR. */ +#define AFEC_EMR_TAG_APPENDS (0x1u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel +number to the conversion result in AFEC_LDCR register. */ + +/***************************** Compare All Channels ******************/ +#define AFEC_EMR_CMPALL_Pos 9 +#define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in +CMPSEL field is compared. */ +#define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */ + +#define AFEC_ACR_PGA0_ON (0x1u << 2) +#define AFEC_ACR_PGA1_ON (0x1u << 3) + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define AFEC_GetModeReg(pAFEC) ((pAFEC)->AFEC_MR) +#define AFEC_SetModeReg(pAFEC, mode) ((pAFEC)->AFEC_MR = mode) + +#define AFEC_GetExtModeReg(pAFEC) ((pAFEC)->AFEC_EMR) +#define AFEC_SetExtModeReg(pAFEC, mode) ((pAFEC)->AFEC_EMR = mode) + +#define AFEC_StartConversion(pAFEC) ((pAFEC)->AFEC_CR = AFEC_CR_START) + +#define AFEC_EnableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHER = (1 << (dwChannel));\ + } + +#define AFEC_DisableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\ + } + +#define AFEC_EnableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IER = (dwMode);\ + } + +#define AFEC_DisableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IDR = (dwMode);\ + } + +#define AFEC_SetChannelGain(pAFEC,dwMode) {\ + (pAFEC)->AFEC_CGR = dwMode;\ + } + +#define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY) + +#define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR) + +#define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk)) + +#define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR) + +#define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR) + +#define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void AFEC_Initialize(Afec *pAFEC, uint32_t dwId); +extern uint32_t AFEC_SetClock(Afec *pAFEC, uint32_t dwPres, uint32_t dwMck); +extern void AFEC_SetTiming(Afec *pAFEC, uint32_t dwStartup, + uint32_t dwTracking, + uint32_t dwSettling); +extern void AFEC_SetTrigger(Afec *pAFEC, uint32_t dwTrgSel); +extern void AFEC_SetAnalogChange(Afec *pAFE, uint8_t bEnDis); +extern void AFEC_SetSleepMode(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetFastWakeup(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetSequenceMode(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetSequence(Afec *pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2); +extern void AFEC_SetSequenceByList(Afec *pAFEC, uint8_t ucChList[], + uint8_t ucNumCh); +extern void AFEC_SetTagEnable(Afec *pAFEC, uint8_t bEnDis); +extern void AFEC_SetCompareChannel(Afec *pAFEC, uint32_t dwChannel); +extern void AFEC_SetCompareMode(Afec *pAFEC, uint32_t dwMode); +extern void AFEC_SetComparisonWindow(Afec *pAFEC, uint32_t dwHi_Lo); +extern uint8_t AFEC_CheckConfiguration(Afec *pAFEC, uint32_t dwMcK); +extern uint32_t AFEC_GetConvertedData(Afec *pAFEC, uint32_t dwChannel); +extern void AFEC_SetStartupTime(Afec *pAFEC, uint32_t dwUs); +extern void AFEC_SetTrackingTime(Afec *pAFEC, uint32_t dwNs); +extern void AFEC_SetAnalogOffset(Afec *pAFE, uint32_t dwChannel, + uint32_t aoffset); +extern void AFEC_SetAnalogControl(Afec *pAFE, uint32_t control); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _AFEC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/chip.h b/bsps/arm/atsam/include/libchip/include/chip.h new file mode 100644 index 0000000000..a9f1f01bea --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/chip.h @@ -0,0 +1 @@ +#include "../chip.h" diff --git a/bsps/arm/atsam/include/libchip/include/dac_dma.h b/bsps/arm/atsam/include/libchip/include/dac_dma.h new file mode 100644 index 0000000000..11d100b76d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/dac_dma.h @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for DACC + * -# Initialize the DACC with DACC_Initialize(). + * -# Select the active channel using DACC_EnableChannel() + * -# Start the conversion with DACC_StartConversion() + * -# Wait the end of the conversion by polling status with DACC_GetStatus() + * -# Finally, get the converted data using DACC_GetConvertedData() + * +*/ +#ifndef _DAC_DMA_ +#define _DAC_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DAC transfer complete callback. */ +typedef void (*DacCallback)(uint8_t, void *); + +/** \brief Dac Transfer Request prepared by the application upper layer. + * + * This structure is sent to the DAC_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint16_t TxSize; + /** Tx loop back. */ + uint16_t loopback; + /** DACC channel*/ + uint8_t dacChannel; + /** Callback function invoked at the end of transfer. */ + DacCallback callback; + /** Callback arguments. */ + void *pArgument; +} DacCmd; + + +/** Constant structure associated with DAC port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** Pointer to DAC Hardware registers */ + Dacc *pDacHw; + /** Current SpiCommand being processed */ + DacCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** DACC Id as defined in the product datasheet */ + uint8_t dacId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} DacDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define DAC_OK 0 +#define DAC_ERROR 1 +#define DAC_ERROR_LOCK 2 + +#define DACC_CHANNEL_0 0 +#define DACC_CHANNEL_1 1 + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint32_t Dac_ConfigureDma(DacDma *pDacd , + Dacc *pDacHw , + uint8_t DacId, + sXdmad *pXdmad); +extern uint32_t Dac_SendData(DacDma *pDacd, DacCmd *pCommand); + + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) +#define DACC_CfgModeReg(pDACC, mode) { (pDACC)->DACC_MR = (mode); } +#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) +#define DACC_CfgTrigger(pDACC, mode) { (pDACC)->DACC_TRIGR = (mode); } + +#define DACC_EnableChannel(pDACC, channel) {(pDACC)->DACC_CHER = (1 << (channel));} +#define DACC_DisableChannel(pDACC, channel) {(pDACC)->DACC_CHDR = (1 << (channel));} + +#define DACC_EnableIt(pDACC, mode) {(pDACC)->DACC_IER = (mode);} +#define DACC_DisableIt(pDACC, mode) {(pDACC)->DACC_IDR = (mode);} +#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) +#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) +#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _DAC_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/efc.h b/bsps/arm/atsam/include/libchip/include/efc.h new file mode 100644 index 0000000000..c4ff7c49f6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/efc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) + * peripheral. + * + * \section Usage + * + * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() + * and EFC_DisableFrdyIt(). + * -# Translates the given address into which EEFC, page and offset values + * for difference density %flash memory using EFC_TranslateAddress(). + * -# Computes the address of a %flash access given the EFC, page and offset + * for difference density %flash memory using EFC_ComputeAddress(). + * -# Start the executing command with EFC_PerformCommand() + * -# Retrieve the current status of the EFC using EFC_GetStatus(). + * -# Retrieve the result of the last executed command with EFC_GetResult(). + */ + +#ifndef _EEFC_ +#define _EEFC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* TODO: Temporary definition for missing symbol in header file */ +#define IFLASH_SECTOR_SIZE 65536u + + +/* EFC command */ +#define EFC_FCMD_GETD 0x00 /* Get Flash Descriptor */ +#define EFC_FCMD_WP 0x01 /* Write page */ +#define EFC_FCMD_WPL 0x02 /* Write page and lock */ +#define EFC_FCMD_EWP 0x03 /* Erase page and write page */ +#define EFC_FCMD_EWPL 0x04 /* Erase page and write page then lock */ +#define EFC_FCMD_EA 0x05 /* Erase all */ +#define EFC_FCMD_EPA 0x07 /* Erase pages */ +#define EFC_FCMD_SLB 0x08 /* Set Lock Bit */ +#define EFC_FCMD_CLB 0x09 /* Clear Lock Bit */ +#define EFC_FCMD_GLB 0x0A /* Get Lock Bit */ +#define EFC_FCMD_SFB 0x0B /* Set GPNVM Bit */ +#define EFC_FCMD_CFB 0x0C /* Clear GPNVM Bit */ +#define EFC_FCMD_GFB 0x0D /* Get GPNVM Bit */ +#define EFC_FCMD_STUI 0x0E /* Start unique ID */ +#define EFC_FCMD_SPUI 0x0F /* Stop unique ID */ +#define EFC_FCMD_GCALB 0x10 /* Get CALIB Bit */ +#define EFC_FCMD_ES 0x11 /* Erase Sector */ +#define EFC_FCMD_WUS 0x12 /* Write User Signature */ +#define EFC_FCMD_EUS 0x13 /* Erase User Signature */ +#define EFC_FCMD_STUS 0x14 /* Start Read User Signature */ +#define EFC_FCMD_SPUS 0x15 /* Stop Read User Signature */ + +/* The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (0x00800008) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void EFC_EnableFrdyIt(Efc *efc); + +extern void EFC_DisableFrdyIt(Efc *efc); + +extern void EFC_SetWaitState(Efc *efc, uint8_t cycles); + +extern void EFC_TranslateAddress(Efc **pEfc, uint32_t dwAddress, + uint16_t *pwPage, uint16_t *pwOffset); + +extern void EFC_ComputeAddress(Efc *efc, uint16_t wPage, uint16_t wOffset, + uint32_t *pdwAddress); + +extern uint32_t EFC_PerformCommand(Efc *efc, uint32_t dwCommand, + uint32_t dwArgument, uint32_t dwUseIAP); + +extern uint32_t EFC_GetStatus(Efc *efc); + +extern uint32_t EFC_GetResult(Efc *efc); + +extern void EFC_SetFlashAccessMode(Efc *efc, uint32_t dwMode); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _EEFC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/exceptions.h b/bsps/arm/atsam/include/libchip/include/exceptions.h new file mode 100644 index 0000000000..2a18dae728 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/exceptions.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * Interface for default exception handlers. + */ + +#ifndef _EXCEPTIONS_ +#define _EXCEPTIONS_ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* Function prototype for exception table items (interrupt handler). */ +typedef void(*IntFunc)(void); + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* Default empty handler */ +extern void IrqHandlerNotUsed(void); + +#endif /* _EXCEPTIONS_ */ diff --git a/bsps/arm/atsam/include/libchip/include/flashd.h b/bsps/arm/atsam/include/libchip/include/flashd.h new file mode 100644 index 0000000000..c34325aa89 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/flashd.h @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * The flash driver provides the unified interface for flash program operations. + * + */ + +#ifndef _FLASHD_ +#define _FLASHD_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPNVBit_SecurityBit 0 +#define GPNVBit_BootMode 1 +#define GPNVBit_TCMBit1 6 +#define GPNVBit_TCMBit2 7 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FLASHD_Initialize(uint32_t dwMCk, uint32_t dwUseIAP); + +extern uint32_t FLASHD_Erase(uint32_t dwAddress); + +extern uint32_t FLASHD_EraseSector(uint32_t dwAddress); + +extern uint32_t FLASHD_ErasePages(uint32_t dwAddress, uint32_t dwPageNum); + +extern uint32_t FLASHD_Write(uint32_t dwAddress, const void *pvBuffer, + uint32_t dwSize); + +extern uint32_t FLASHD_Lock(uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd); + +extern uint32_t FLASHD_Unlock(uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd); + +extern uint32_t FLASHD_IsLocked(uint32_t dwStart, uint32_t dwEnd); + +extern uint32_t FLASHD_SetGPNVM(uint8_t gpnvm); + +extern uint32_t FLASHD_ClearGPNVM(uint8_t gpnvm); + +extern uint32_t FLASHD_IsGPNVMSet(uint8_t gpnvm); + +#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet(0) + +#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM(0) + +extern uint32_t FLASHD_ReadUniqueID(uint32_t *pdwUniqueID); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _FLASHD_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/gmac.h b/bsps/arm/atsam/include/libchip/include/gmac.h new file mode 100644 index 0000000000..64e0079c25 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/gmac.h @@ -0,0 +1,349 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup gmac_module + * @{ + * Provides the interface to configure and use the GMAC peripheral. + * + * \section gmac_usage Usage + * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls + * are also available, such as: + * - GMAC_SetSpeed(): Setup GMAC working clock. + * - GMAC_FullDuplexEnable(): Working in full duplex or not. + * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF). + * - ... + * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls + * can modify with: + * - GMAC_ReceiveEnable(): Enable/Disable Rx. + * - GMAC_TransmitEnable(): Enable/Disable Tx. + * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(), + * GMAC_GetItMask() and GMAC_GetItStatus(). + * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus() + * GMAC_ClearTxStatus() and GMAC_ClearRxStatus(). + * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(), + * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define + * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor. + * - Manage PHY through GMAC is performed by + * - GMAC_ManagementEnable(): Enable/Disable PHY management. + * - GMAC_PHYMaintain(): Execute PHY management commands. + * - GMAC_PHYData(): Return PHY management data. + * - GMAC_IsIdle(): Check if PHY is idle. + * - Setup GMAC parameters with following functions: + * - GMAC_SetHash(): Set Hash value. + * - GMAC_SetAddress(): Set MAC address. + * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable() + * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable() + * + * For more accurate information, please look at the GMAC section of the + * Datasheet. + * + * \sa \ref gmacd_module + * + * Related files:\n + * gmac.c\n + * gmac.h.\n + * + * \defgroup gmac_defines GMAC Defines + * \defgroup gmac_structs GMAC Data Structs + * \defgroup gmac_functions GMAC Functions + */ +/**@}*/ + +#ifndef _GMAC_H +#define _GMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_defines + @{*/ + +#define NUM_GMAC_QUEUES 3 +/// Board GMAC base address + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +// +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 +#define GMAC_SPEED_1000M 2 + +/*------------------------------------------------------------------------------ + Definitions +------------------------------------------------------------------------------ +*/ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the GMAC +/// peripheral and cannot be used as part of the address. +#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define GMAC_RX_OWNERSHIP_BIT (1u << 0) +#define GMAC_RX_WRAP_BIT (1u << 1) +#define GMAC_RX_SOF_BIT (1u << 14) +#define GMAC_RX_EOF_BIT (1u << 15) + +// Transmit buffer descriptor bits +#define GMAC_TX_LAST_BUFFER_BIT (1u << 15) +#define GMAC_TX_WRAP_BIT (1u << 30) +#define GMAC_TX_USED_BIT (1u << 31) +#define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded +#define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Under-run +#define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +// Interrupt bits +#define GMAC_INT_RX_BITS \ + (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR) +#define GMAC_INT_TX_ERR_BITS \ + (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP) +#define GMAC_INT_TX_BITS \ + (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP) +// Interrupt Status bits +#define GMAC_INT_RX_STATUS_BITS \ + (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR) +#define GMAC_INT_TX_STATUS_ERR_BITS \ + (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP) +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_structs + @{*/ + +/* This is the list of GMAC queue */ +typedef enum { + GMAC_QUE_0 = 0, + GMAC_QUE_1 = 1, + GMAC_QUE_2 = 2 +} gmacQueList_t; + +/** Receive buffer descriptor struct */ +typedef struct _GmacRxDescriptor { + union _GmacRxAddr { + uint32_t val; + struct _GmacRxAddrBM { + uint32_t bOwnership: 1, /**< User clear, GMAC set this to one once + it has successfully written a frame to + memory */ + bWrap: 1, /**< Marks last descriptor in receive buffer */ + addrDW: 30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _GmacRxStatus { + uint32_t val; + struct _GmacRxStatusBM { + uint32_t len: 12, /** Length of frame including FCS */ + offset: 2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof: 1, /** Start of frame */ + bEof: 1, /** End of frame */ + bCFI: 1, /** Concatenation Format Indicator */ + vlanPriority: 3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected: 1, /** Priority tag detected */ + bVlanDetected: 1, /**< VLAN tag detected */ + bTypeIDMatch: 1, /**< Type ID match */ + bAddr4Match: 1, /**< Address register 4 match */ + bAddr3Match: 1, /**< Address register 3 match */ + bAddr2Match: 1, /**< Address register 2 match */ + bAddr1Match: 1, /**< Address register 1 match */ + reserved: 1, + bExtAddrMatch: 1, /**< External address match */ + bUniHashMatch: 1, /**< Unicast hash match */ + bMultiHashMatch: 1, /**< Multicast hash match */ + bBroadcastDetected: 1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +} sGmacRxDescriptor; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _GmacTxDescriptor { + uint32_t addr; + union _GmacTxStatus { + uint32_t val; + struct _GmacTxStatusBM { + uint32_t len: 11, /**< Length of buffer */ + reserved: 4, + bLastBuffer: 1, /**< Last buffer (in the current frame) */ + bNoCRC: 1, /**< No CRC */ + reserved1: 10, + bExhausted: 1, /**< Buffer exhausted in mid frame */ + bUnderrun: 1, /**< Transmit under run */ + bError: 1, /**< Retry limit exceeded, error detected */ + bWrap: 1, /**< Marks last descriptor in TD list */ + bUsed: 1; /**< User clear, GMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} sGmacTxDescriptor; /* GCC */ + +/** @}*/ + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern uint8_t GMAC_IsIdle(Gmac *pGmac); +extern void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t GMAC_PHYData(Gmac *pGmac); +extern void GMAC_ClearStatistics(Gmac *pGmac); +extern void GMAC_IncreaseStatistics(Gmac *pGmac); +extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck); +extern void GMAC_EnableMdio(Gmac *pGmac); +extern void GMAC_DisableMdio(Gmac *pGmac); +extern void GMAC_EnableMII(Gmac *pGmac); +extern void GMAC_EnableRMII(Gmac *pGmac); +extern void GMAC_EnableGMII(Gmac *pGmac); +extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex); +extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, + gmacQueList_t queueIdx); +extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, + gmacQueList_t queueIdx); +extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxStatus(Gmac *pGmac); +extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus); +extern uint32_t GMAC_GetRxStatus(Gmac *pGmac); +extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus); +extern void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis); +extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac); +extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR); +extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac); +extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr); +extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, + uint32_t dwMacB); +extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac); +extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg); +extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, + gmacQueList_t queueIdx); +extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetConfigure(Gmac *pGmac); +extern void GMAC_TransmissionStart(Gmac *pGmac); +extern void GMAC_TransmissionHalt(Gmac *pGmac); +extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed); + +void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx, + uint32_t regVal); + +void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx, + uint32_t regVal); + +void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx, + uint16_t etherType); + +void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, + uint16_t c1Reg); + +void GMAC_EnableCbsQueA(Gmac *pGmac); + +void GMAC_DisableCbsQueA(Gmac *pGmac); + +void GMAC_EnableCbsQueB(Gmac *pGmac); + +void GMAC_DisableCbsQueB(Gmac *pGmac); + +void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA); + +void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB); + +void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec); + +uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac); + +uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac); + +uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac); + +void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, + uint32_t nanosec); + +void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec); + +void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31); + +void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47); + +uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac); + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef GMAC_H + diff --git a/bsps/arm/atsam/include/libchip/include/gmacd.h b/bsps/arm/atsam/include/libchip/include/gmacd.h new file mode 100644 index 0000000000..9cda2f8a6c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/gmacd.h @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup gmacd_module + * @{ + * Implement GMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler() + * to handle GMAC interrupt events. + * -# Implement sGmacd instance in application. + * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(), + * so that GMAC data can be transmitted/received. + * -# Some management callbacks can be set by GMACD_SetRxCallback() + * and GMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via GMACD_Poll(). + * + * \sa \ref gmacb_module, \ref gmac_module + * + * Related files:\n + * \ref gmacd.c\n + * \ref gmacd.h.\n + * + * \defgroup gmacd_defines GMAC Driver Defines + * \defgroup gmacd_types GMAC Driver Types + * \defgroup gmacd_functions GMAC Driver Functions + */ +/**@}*/ + +#ifndef _GMACD_H_ +#define _GMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_defines + @{*/ + + +/** \addtogroup gmacd_rc GMACD Return Codes + @{*/ +#define GMACD_OK 0 /**< Operation OK */ +#define GMACD_TX_BUSY 1 /**< TX in progress */ +#define GMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define GMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define GMACD_PARAM 3 +/** Transfer is not initialized */ +#define GMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ + +/* Should be a power of 2. + - Buffer Length to store the timestamps of 1588 event messages +*/ +#define EFRS_BUFFER_LEN (1u) + +/*--------------------------------------------------------------------------- +* Types +*---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_types + @{*/ + +typedef enum ptpMsgType_t { + SYNC_MSG_TYPE = 0, + DELAY_REQ_MSG_TYPE = 1, + PDELAY_REQ_TYPE = 2, + PDELAY_RESP_TYPE = 3, + FOLLOW_UP_MSG_TYPE = 8, + DELAY_RESP_MSG_TYPE = 9 +} ptpMsgType; + + + +/** RX callback */ +typedef void (*fGmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fGmacdWakeupCallback)(void); +/** Tx PTP message callback */ +typedef void (*fGmacdTxPtpEvtCallBack) (ptpMsgType msg, uint32_t sec, \ + uint32_t nanosec, uint16_t seqId); + +/** + * GMAC scatter-gather entry. + */ +typedef struct _GmacSG { + uint32_t size; + void *pBuffer; +} sGmacSG; + +/** + * GMAC scatter-gather list. + */ +typedef struct _GmacSGList { + uint32_t len; + sGmacSG *sg; +} sGmacSGList; + +/** + * GMAC Queue driver. + */ +typedef struct _GmacQueueDriver { + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sGmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sGmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fGmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fGmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fGmacdTransferCallback *fTxCbList; + + /** Optional callback to be invoked on transmit of PTP Event messages */ + fGmacdTxPtpEvtCallBack fTxPtpEvtCb; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + + /** RX buffer size */ + uint16_t wTxBufferSize; + uint16_t wRxBufferSize; + +} sGmacQd; + +/** + * GMAC driver struct. + */ +typedef struct _GmacDriver { + + /** Pointer to HW register base */ + Gmac *pHw; + /** HW ID */ + uint8_t bId; + /** Base Queue list params **/ + sGmacQd queueList[NUM_GMAC_QUEUES]; +} sGmacd; + +/** + * GMAC driver init struct. + */ +typedef struct _GmacInit { + uint32_t bIsGem: 1; + uint32_t reserved: 31; + + uint8_t bDmaBurstLength; + + /** RX descriptor and data buffers */ + uint8_t *pRxBuffer; + /** RX data buffers: should be wRxBufferSize * wRxSize byte long in a DMA + capable memory region */ + sGmacRxDescriptor *pRxD; + /** RX buffer descriptors: should have wRxSize entries in a DMA + capable memory region */ + uint16_t wRxBufferSize; /** size of a single RX data buffer */ + uint16_t wRxSize; /** number of RX descriptor and data buffers */ + + /** TX descriptor and data buffers */ + /** TX data buffers: should be wTxBufferSize * wTxSize byte long + in a DMA capable memory region */ + uint8_t *pTxBuffer; + /** TX buffer descriptors: should have wTxSize entries + in a DMA capable non-cached memory region */ + sGmacTxDescriptor *pTxD; + /** size of a single TX data buffer */ + uint16_t wTxBufferSize; + /** number of TX descriptor and data buffers */ + uint16_t wTxSize; + + fGmacdTransferCallback *pTxCb; /** should have wTxSize entries */ +} sGmacInit; +/** @}*/ + +/** \addtogroup gmacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * GMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void GMACD_Handler(sGmacd *pGmacd , gmacQueList_t queIdx); + +extern void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC); + +extern uint8_t GMACD_InitTransfer(sGmacd *pGmacd, + const sGmacInit *pInit, gmacQueList_t queIdx); + +extern void GMACD_Reset(sGmacd *pGmacd); + +extern uint8_t GMACD_SendSG(sGmacd *pGmacd, + const sGmacSGList *sgl, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx); + +extern uint8_t GMACD_Poll(sGmacd *pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize, + gmacQueList_t queIdx); + +extern void GMACD_SetRxCallback(sGmacd *pGmacd, fGmacdTransferCallback + fRxCb, gmacQueList_t queIdx); + +extern uint8_t GMACD_SetTxWakeupCallback(sGmacd *pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold, + gmacQueList_t queIdx); + +extern void GMACD_TxPtpEvtMsgCBRegister (sGmacd *pGmacd, + fGmacdTxPtpEvtCallBack pTxPtpEvtCb, + gmacQueList_t queIdx); + +/** @}*/ + +#endif // #ifndef _GMACD_H_ diff --git a/bsps/arm/atsam/include/libchip/include/hsmci.h b/bsps/arm/atsam/include/libchip/include/hsmci.h new file mode 100644 index 0000000000..f228a3e261 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/hsmci.h @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup hsmci_module Working with HSMCI + * \ingroup mcid_module + * + * \section Purpose + * + * The HSMCI driver provides the interface to configure and use the HSMCI + * peripheral. + * + * \section Usage + * + * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface. + * -# HSMCI_Reset(): Reset HSMCI interface. + * -# HSMCI_Select(): HSMCI slot and buswidth selection + * (\ref Hsmci::HSMCI_SDCR). + * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register + * (\ref Hsmci::HSMCI_MR). + * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus() + * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR, + * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR). + * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer + * (\ref Hsmci::HSMCI_BLKR). + * -# HSMCI_SendCmd(): Send SD/MMC command with argument + * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR). + * -# HSMCI_GetResponse(): Get SD/MMC response after command finished + * (\ref Hsmci::HSMCI_RSPR). + * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer + * (\ref Hsmci::HSMCI_DMA). + * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG). + * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control. + * + * For more accurate information, please look at the HSMCI section of the + * Datasheet. + * + * \sa \ref mcid_module + * + * Related files :\n + * \ref hsmci.h\n + * \ref hsmci.c.\n + */ + +#ifndef HSMCID_H +#define HSMCID_H +/** \addtogroup hsmci_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup hsmci_functions HSMCI Functions + * @{ + */ + +extern void HSMCI_Enable(Hsmci *pRMci); +extern void HSMCI_Disable(Hsmci *pRMci); +extern void HSMCI_Reset(Hsmci *pRMci, uint8_t bBackup); + +extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth); +extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot); +extern void HSMCI_SetBusWidth(Hsmci *pRMci, uint8_t bBusWidth); +extern uint8_t HSMCI_GetBusWidth(Hsmci *pRMci); + +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode); +extern uint32_t HSMCI_GetMode(Hsmci *pRMci); +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof); +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv); +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn); +extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci); +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv); + +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources); +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources); +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci); + +extern void HSMCI_ConfigureTransfer(Hsmci *pRMci, uint16_t wBlkLen, + uint16_t wCnt); +extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize); +extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt); + +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure); + +extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg); +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci); +extern uint32_t HSMCI_Read(Hsmci *pRMci); +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData); +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); + +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci); + +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable); + +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable); +extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci); + +extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth); +extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot); +extern uint8_t HSMCI_GetSlot(Hsmci *pRMci); + +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure); +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci); + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/bsps/arm/atsam/include/libchip/include/icm.h b/bsps/arm/atsam/include/libchip/include/icm.h new file mode 100644 index 0000000000..eee19260d5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/icm.h @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _ICM_ +#define _ICM_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define ICM_RCFG_CDWBN (0x1u << 0) +/**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */ +#define ICM_RCFG_WRAP (0x1u << 1) +/**< \brief (ICM_RCFG) Wrap Command */ +#define ICM_RCFG_EOM (0x1u << 2) +/**< \brief (ICM_RCFG) End Of Monitoring */ +#define ICM_RCFG_RHIEN (0x1u << 4) +/**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */ +#define ICM_RCFG_DMIEN (0x1u << 5) +/**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */ +#define ICM_RCFG_BEIEN (0x1u << 6) +/**< \brief (ICM_RCFG) Bus error interrupt enable */ +#define ICM_RCFG_WCIEN (0x1u << 7) +/**< \brief (ICM_RCFG) Warp condition interrupt enable */ +#define ICM_RCFG_ECIEN (0x1u << 8) +/**< \brief (ICM_RCFG) End bit condition interrupt enable */ +#define ICM_RCFG_SUIEN (0x1u << 9) +/**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */ +#define ICM_RCFG_PROCDLY (0x1u << 10) +/**< \brief (ICM_RCFG) Processing Delay*/ +#define ICM_RCFG_UALGO_Pos 12 +#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) +/**< \brief (ICM_RCFG) User SHA Algorithm */ +#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) +/**< \brief (ICM_RCFG) SHA1 algorithm processed */ +#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) +/**< \brief (ICM_RCFG) SHA256 algorithm processed */ +#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) +/**< \brief (ICM_RCFG) SHA224 algorithm processed */ +#define ICM_RCFG_MRPROT_Pos 24 +#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) +/**< \brief (ICM_RCFG) Memory Region AHB Protection */ +#define ICM_RCFG_MRPROT(value) \ + ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))) + +/*----------------------------------------------------------------------------*/ +/* Type */ +/*----------------------------------------------------------------------------*/ + +/** \brief Structure ICM region descriptor area. */ +typedef struct _LinkedListDescriporIcmRegion { + /** the first byte address of the Region. */ + uint32_t icm_raddr; + /** Configuration Structure Member. */ + uint32_t icm_rcfg; + /** Control Structure Member. */ + uint32_t icm_rctrl; + /** Next Address Structure Member. */ + uint32_t icm_rnext; +} LinkedListDescriporIcmRegion; + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ +extern void ICM_Enable(void); +extern void ICM_Disable(void); +extern void ICM_SoftReset(void); +extern void ICM_ReComputeHash(uint8_t region); +extern void ICM_EnableMonitor(uint8_t region); +extern void ICM_DisableMonitor(uint8_t region); +extern void ICM_Configure(uint32_t mode); +extern void ICM_EnableIt(uint32_t sources); +extern void ICM_DisableIt(uint32_t sources); +extern uint32_t ICM_GetIntStatus(void); +extern uint32_t ICM_GetStatus(void); +extern uint32_t ICM_GetUStatus(void); +extern void ICM_SetDescStartAddress(uint32_t addr); +extern void ICM_SetHashStartAddress(uint32_t addr); +extern void ICM_SetInitHashValue(uint32_t val); +#endif /* #ifndef _ICM_ */ diff --git a/bsps/arm/atsam/include/libchip/include/isi.h b/bsps/arm/atsam/include/libchip/include/isi.h new file mode 100644 index 0000000000..198dc98039 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/isi.h @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup isi_module + * @{ + * \section gmac_usage Usage + * - ISI_Init: initialize ISI with default parameters + * - ISI_EnableInterrupt: enable one or more interrupts + * - ISI_DisableInterrupt: disable one or more interrupts + * - ISI_Enable: enable isi module + * - ISI_Disable: disable isi module + * - ISI_CodecPathFull: enable codec path + * - ISI_SetFrame: set frame rate + * - ISI_BytesForOnePixel: return number of byte for one pixel + * - ISI_StatusRegister: return ISI status register + * - ISI_Reset: make a software reset + */ +/**@}*/ + +#ifndef ISI_H +#define ISI_H + + + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define YUV_INPUT 0 +#define RGB_INPUT 1 +#define GRAYSCALE_INPUT 2 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** ISI descriptors */ +typedef struct { + /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */ + uint32_t CurrentLcdIndex; + /** set if Fifo Codec Empty is present */ + volatile uint32_t DisplayCodec; + /** upgrade for each Fifo Codec Overflow (statistics use) */ + uint32_t nb_codec_ovf; + /** upgrade for each Fifo Preview Overflow (statistics use) */ + uint32_t nb_prev_ovf; +} ISI_Descriptors; + +/** Frame Buffer Descriptors */ +typedef struct { + /** Address of the Current FrameBuffer */ + uint32_t Current; + /** Address of the Control */ + uint32_t Control; + /** Address of the Next FrameBuffer */ + uint32_t Next; +} ISI_FrameBufferDescriptors; + + +/** ISI Matrix Color Space Conversion YCrCb to RGB */ +typedef struct { + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Matrix Coefficient C3 */ + uint8_t C3; + /** Color Space Conversion Red Chrominance Default Offset */ + uint8_t Croff; + /** Color Space Conversion Blue Chrominance Default Offset */ + uint8_t Cboff; + /** Color Space Conversion Luminance Default Offset */ + uint8_t Yoff; + /** Color Space Conversion Matrix Coefficient C4 */ + uint16_t C4; +} ISI_Y2R; + +/** ISI Matrix Color Space Conversion RGB to YCrCb */ +typedef struct { + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Red Component Offset */ + uint8_t Roff; + /** Color Space Conversion Matrix Coefficient C3*/ + uint8_t C3; + /** Color Space Conversion Matrix Coefficient C4 */ + uint8_t C4; + /** Color Space Conversion Matrix Coefficient C5 */ + uint8_t C5; + /** Color Space Conversion Green Component Offset */ + uint8_t Goff; + /** Color Space Conversion Matrix Coefficient C6*/ + uint8_t C6; + /** Color Space Conversion Matrix Coefficient C7 */ + uint8_t C7; + /** Color Space Conversion Matrix Coefficient C8 */ + uint8_t C8; + /** Color Space Conversion Blue Component Offset */ + uint8_t Boff; +} ISI_R2Y; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISI_Enable(void); + +extern void ISI_Disable(void); + +void ISI_DmaChannelEnable(uint32_t channel); + +void ISI_DmaChannelDisable(uint32_t channel); + +extern void ISI_EnableInterrupt(uint32_t flag); + +extern void ISI_DisableInterrupt(uint32_t flag); + +extern void ISI_CodecPathFull(void); + +extern void ISI_SetFrameRate(uint32_t frame); + +extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb); + +extern void ISI_Reset(void); + +extern void ISI_Init(pIsi_Video pVideo); + +extern uint32_t ISI_StatusRegister(void); + +extern void ISI_SetBlank( + uint8_t hBlank, + uint8_t vBlank); + +extern void ISI_SetSensorSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_RgbPixelMapping(uint32_t wRgbPixelMapping); + +extern void ISI_RgbSwapMode(uint32_t swapMode); + +extern void ISI_YCrCbFormat(uint32_t wYuvSwapMode); + +extern void ISI_setGrayScaleMode(uint32_t wPixelFormat); + +extern void ISI_setInputStream(uint32_t wStreamMode); + +extern void ISI_setPreviewSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_calcScalerFactor(void); + +extern void ISI_setDmaInPreviewPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_setDmaInCodecPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_SetMatrix4Yuv2Rgb (ISI_Y2R *yuv2rgb); +extern void ISI_SetMatrix4Rgb2Yuv (ISI_R2Y *rgb2yuv); + +#endif //#ifndef ISI_H + diff --git a/bsps/arm/atsam/include/libchip/include/iso7816_4.h b/bsps/arm/atsam/include/libchip/include/iso7816_4.h new file mode 100644 index 0000000000..3fa1ce97ea --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/iso7816_4.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +//------------------------------------------------------------------------------ +/** \page + * + * \section Purpose + * + * Definition of methods for ISO7816 driver. + * + * \section Usage + * + * -# ISO7816_Init + * -# ISO7816_IccPowerOff + * -# ISO7816_XfrBlockTPDU_T0 + * -# ISO7816_Escape + * -# ISO7816_RestartClock + * -# ISO7816_StopClock + * -# ISO7816_toAPDU + * -# ISO7816_Datablock_ATR + * -# ISO7816_SetDataRateandClockFrequency + * -# ISO7816_StatusReset + * -# ISO7816_cold_reset + * -# ISO7816_warm_reset + * -# ISO7816_Decode_ATR + *----------------------------------------------------------------------------*/ + +#ifndef ISO7816_4_H +#define ISO7816_4_H + +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Constants Definition + *----------------------------------------------------------------------------*/ + +/** Size max of Answer To Reset */ +#define ATR_SIZE_MAX 55 + +/** NULL byte to restart byte procedure */ +#define ISO_NULL_VAL 0x60 + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void ISO7816_Init( + Usart *pUsart, + uint32_t usartId , + const Pin pPinIso7816RstMC); + +extern void ISO7816_IccPowerOff(void); + +extern uint16_t ISO7816_XfrBlockTPDU_T0( + const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength); + +extern void ISO7816_Escape(void); + +extern void ISO7816_RestartClock(void); + +extern void ISO7816_StopClock(void); + +extern void ISO7816_toAPDU(void); + +extern void ISO7816_Datablock_ATR( + uint8_t *pAtr, + uint8_t *pLength); + +extern void ISO7816_SetDataRateandClockFrequency( + uint32_t dwClockFrequency, + uint32_t dwDataRate); + +extern uint8_t ISO7816_StatusReset(void); + +extern void ISO7816_cold_reset(void); + +extern void ISO7816_warm_reset(void); + +extern void ISO7816_Decode_ATR(uint8_t *pAtr); + +#endif /* ISO7816_4_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/mcan.h b/bsps/arm/atsam/include/libchip/include/mcan.h new file mode 100644 index 0000000000..216c3b07ae --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mcan.h @@ -0,0 +1,329 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_ +#define _MCAN_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + CAN_STD_ID = 0, + CAN_EXT_ID = 1 +} MCan_IdType; + +typedef enum { + CAN_DLC_0 = 0, + CAN_DLC_1 = 1, + CAN_DLC_2 = 2, + CAN_DLC_3 = 3, + CAN_DLC_4 = 4, + CAN_DLC_5 = 5, + CAN_DLC_6 = 6, + CAN_DLC_7 = 7, + CAN_DLC_8 = 8, + CAN_DLC_12 = 9, + CAN_DLC_16 = 10, + CAN_DLC_20 = 11, + CAN_DLC_24 = 12, + CAN_DLC_32 = 13, + CAN_DLC_48 = 14, + CAN_DLC_64 = 15 +} MCan_DlcType; + +typedef enum { + CAN_FIFO_0 = 0, + CAN_FIFO_1 = 1 +} MCan_FifoType; + +typedef enum { + CAN_INTR_LINE_0 = 0, + CAN_INTR_LINE_1 = 1 +} MCan_IntrLineType; + +typedef struct MailboxInfoTag { + uint32_t id; + uint32_t length; + uint32_t timestamp; +} MailboxInfoType; + + +typedef struct MailBox8Tag { + MailboxInfoType info; + uint8_t data[8]; +} Mailbox8Type; + +typedef struct MailBox12Tag { + MailboxInfoType info; + uint8_t data[12]; +} Mailbox12Type; + +typedef struct MailBox16Tag { + MailboxInfoType info; + uint8_t data[16]; +} Mailbox16Type; + +typedef struct MailBox20Tag { + MailboxInfoType info; + uint8_t data[20]; +} Mailbox20Type; + +typedef struct MailBox24Tag { + MailboxInfoType info; + uint8_t data[24]; +} Mailbox24Type; + +typedef struct MailBox32Tag { + MailboxInfoType info; + uint8_t data[32]; +} Mailbox32ype; + +typedef struct MailBox48Tag { + MailboxInfoType info; + uint8_t data[48]; +} Mailbox48Type; + +typedef struct MailBox64Tag { + MailboxInfoType info; + uint8_t data[64]; +} Mailbox64Type; + + + +typedef struct MCan_MsgRamPntrsTag { + uint32_t *pStdFilts; + uint32_t *pExtFilts; + uint32_t *pRxFifo0; + uint32_t *pRxFifo1; + uint32_t *pRxDedBuf; + uint32_t *pTxEvtFifo; + uint32_t *pTxDedBuf; + uint32_t *pTxFifoQ; +} MCan_MsgRamPntrs; + +typedef struct MCan_ConfigTag { + Mcan *pMCan; + uint32_t bitTiming; + uint32_t fastBitTiming; + uint32_t nmbrStdFilts; + uint32_t nmbrExtFilts; + uint32_t nmbrFifo0Elmts; + uint32_t nmbrFifo1Elmts; + uint32_t nmbrRxDedBufElmts; + uint32_t nmbrTxEvtFifoElmts; + uint32_t nmbrTxDedBufElmts; + uint32_t nmbrTxFifoQElmts; + uint32_t rxFifo0ElmtSize; + uint32_t rxFifo1ElmtSize; + uint32_t rxBufElmtSize; + // Element sizes and data sizes (encoded element size) + uint32_t txBufElmtSize; + // Element size and data size (encoded element size) + MCan_MsgRamPntrs msgRam; +} MCan_ConfigType; + +extern const MCan_ConfigType mcan0Config; +extern const MCan_ConfigType mcan1Config; + +__STATIC_INLINE uint32_t MCAN_IsTxComplete( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_TC); +} + +__STATIC_INLINE void MCAN_ClearTxComplete( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_TC; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxDedBuffer( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + + return (mcan->MCAN_IR & MCAN_IR_DRX); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxBuffer( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_DRX; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo0( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_RF0N); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo0( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF0N; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo1( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + return (mcan->MCAN_IR & MCAN_IR_RF1N); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo1( + const MCan_ConfigType *mcanConfig) +{ + Mcan *mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF1N; +} + +void MCAN_Init( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitFdEnable( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitFdBitRateSwitchEnable( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitTxQueue( + const MCan_ConfigType *mcanConfig); + +void MCAN_InitLoopback( + const MCan_ConfigType *mcanConfig); + +void MCAN_Enable( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestIso11898_1( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestFd( + const MCan_ConfigType *mcanConfig); + +void MCAN_RequestFdBitRateSwitch( + const MCan_ConfigType *mcanConfig); + +void MCAN_LoopbackOn( + const MCan_ConfigType *mcanConfig); + +void MCAN_LoopbackOff( + const MCan_ConfigType *mcanConfig); + +void MCAN_IEnableMessageStoredToRxDedBuffer( + const MCan_ConfigType *mcanConfig, + MCan_IntrLineType line); + +uint8_t *MCAN_ConfigTxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer, + uint32_t id, + MCan_IdType idType, + MCan_DlcType dlc); + +void MCAN_SendTxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +uint32_t MCAN_AddToTxFifoQ( + const MCan_ConfigType *mcanConfig, + uint32_t id, MCan_IdType idType, + MCan_DlcType dlc, uint8_t *data); + +uint8_t MCAN_IsBufferTxd( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +void MCAN_ConfigRxBufferFilter( + const MCan_ConfigType *mcanConfig, + uint32_t buffer, + uint32_t filter, + uint32_t id, + MCan_IdType idType); + +void MCAN_ConfigRxClassicFilter( + const MCan_ConfigType *mcanConfig, + MCan_FifoType fifo, + uint8_t filter, + uint32_t id, + MCan_IdType idType, + uint32_t mask); + +uint8_t MCAN_IsNewDataInRxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer); + +void MCAN_GetRxDedBuffer( + const MCan_ConfigType *mcanConfig, + uint8_t buffer, + Mailbox64Type *pRxMailbox); + +uint32_t MCAN_GetRxFifoBuffer( + const MCan_ConfigType *mcanConfig, + MCan_FifoType fifo, + Mailbox64Type *pRxMailbox); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/mcid.h b/bsps/arm/atsam/include/libchip/include/mcid.h new file mode 100644 index 0000000000..385f7ad29d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mcid.h @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** + * \ingroup sdmmc_hal + * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib) + * + * \section Purpose + * + * This driver implements SD(IO)/MMC command operations and MCI configuration + * routines to perform SD(IO)/MMC access. It's used for upper layer + * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations. + * + * \section Usage + * + * -# MCID_Init(): Initializes a MCI driver instance and the underlying + * peripheral. + * -# MCID_SendCmd(): Starts a MCI transfer which described by + * \ref sSdmmcCommand. + * -# MCID_CancelCmd(): Cancel a pending command. + * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished. + * -# MCID_Handler(): Interrupt handler which is called by ISR handler. + * -# MCID_IOCtrl(): IO control function to report HW attributes to upper + * layer driver and modify HW settings (such as clock + * frequency, High-speed support, etc. See + * \ref sdmmc_ioctrls). + * + * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI", + * \ref libsdmmc_module "SD/MMC Library" + * + * Related files:\n + * \ref mcid.h\n + * \ref mcid_dma.c.\n + */ + +#ifndef MCID_H +#define MCID_H +/** \addtogroup mcid_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/** \addtogroup mcid_defines MCI Driver Defines + * @{*/ + +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** MCI States */ +#define MCID_IDLE 0 /**< Idle */ +#define MCID_LOCKED 1 /**< Locked for specific slot */ +#define MCID_CMD 2 /**< Processing the command */ +#define MCID_ERROR 3 /**< Command error */ + +/** MCI Initialize clock 400K Hz */ +#define MCI_INITIAL_SPEED 400000 + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_structs MCI Driver Data Structs + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief MCI Driver + */ +typedef struct _Mcid { + /** Pointer to a MCI peripheral. */ + Hsmci *pMciHw; + /** Pointer to a DMA driver */ + sXdmad *pXdmad; + /** Pointer to currently executing command. */ + void *pCmd; + /** MCK source, Hz */ + uint32_t dwMck; + /** DMA transfer channel */ + uint32_t dwDmaCh; + /** DMA transferred data index (bytes) */ + uint32_t dwXfrNdx; + /** DMA transfer size (bytes) */ + uint32_t dwXSize; + /** MCI peripheral identifier. */ + uint8_t bID; + /** Polling mode */ + uint8_t bPolling; + /** Reserved */ + uint8_t reserved; + /** state. */ + volatile uint8_t bState; +} sMcid; + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_functions MCI Driver Functions + @{*/ +extern void MCID_Init(sMcid *pMcid, + Hsmci *pMci, uint8_t bID, uint32_t dwMck, + sXdmad *pXdmad, + uint8_t bPolling); + +extern void MCID_Reset(sMcid *pMcid); + +extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot); + +extern uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot); + +extern uint32_t MCID_Release(sMcid *pMcid); + +extern void MCID_Handler(sMcid *pMcid); + +extern uint32_t MCID_SendCmd(sMcid *pMcid, void *pCmd); + +extern uint32_t MCID_CancelCmd(sMcid *pMcid); + +extern uint32_t MCID_IsCmdCompleted(sMcid *pMcid); + +extern uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param); + +#ifdef __cplusplus +} +#endif +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/bsps/arm/atsam/include/libchip/include/mediaLB.h b/bsps/arm/atsam/include/libchip/include/mediaLB.h new file mode 100644 index 0000000000..566c444b01 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mediaLB.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _MEDILB_H_ +#define _MEDILB_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + + +#endif /* #ifndef _MEDILB_H_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/mpu.h b/bsps/arm/atsam/include/libchip/include/mpu.h new file mode 100644 index 0000000000..06f70d5d62 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/mpu.h @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _MPU_H_ +#define _MPU_H_ +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION (1) +#define MPU_DEFAULT_IFLASH_REGION (2) +#define MPU_DEFAULT_DTCM_REGION (3) +#define MPU_DEFAULT_SRAM_REGION_1 (4) +#define MPU_DEFAULT_SRAM_REGION_2 (5) +#define MPU_PERIPHERALS_REGION (6) +#define MPU_EXT_EBI_REGION (7) +#define MPU_DEFAULT_SDRAM_REGION (8) +#define MPU_QSPIMEM_REGION (9) +#define MPU_USBHSRAM_REGION (10) +#if defined MPU_HAS_NOCACHE_REGION + #define MPU_NOCACHE_SRAM_REGION (11) +#endif +#define MPU_SYSTEM_REGION (12) + +#define MPU_REGION_VALID (0x10) +#define MPU_REGION_ENABLE (0x01) +#define MPU_REGION_DISABLE (0x0) + +#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos) +#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos) + + +#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos) +#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos) +#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos) + +#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos) + +#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos) +#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos) +#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos) +#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos) +#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos) +#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos) +#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos) +#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos) + +#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos) +#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos) + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#ifdef __rtems__ +#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin) +#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1) +#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin) +#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1) +#else /* !__rtems__ */ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL +#endif /* __rtems__ */ + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#ifdef __rtems__ +#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin) +#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1) +#else /* !__rtems__ */ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL +#endif /* __rtems__ */ + + +/******* SRAM memory macros ***************************/ + +#ifdef __rtems__ +#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL +#endif /* __rtems__ */ + +#ifndef __rtems__ +#if defined MPU_HAS_NOCACHE_REGION + #define NOCACHE_SRAM_REGION_SIZE 0x1000 +#endif +#endif /* __rtems__ */ + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#ifdef __rtems__ +#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB +#endif /* __rtems__ */ + +#if defined MPU_HAS_NOCACHE_REGION +#ifdef __rtems__ + #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin) + #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1) + #define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS) +#else /* !__rtems__ */ + #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) + #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB + #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) + #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS) +#endif /* __rtems__ */ +#else +#ifndef __rtems__ + #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) + #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB +#endif /* __rtems__ */ +#endif +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL +#ifdef __rtems__ +#define SYSTEM_START_ADDRESS 0xE0000000UL +#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL +#endif /* __rtems__ */ + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#ifdef __rtems__ +#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin) +#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1) +#else /* !__rtems__ */ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL +#endif /* __rtems__ */ + +/******* QSPI macros ***************************/ +#ifdef __rtems__ +#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin) +#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1) +#else /* !__rtems__ */ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL +#endif /* __rtems__ */ + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void MPU_Enable(uint32_t dwMPUEnable); +void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr); +void MPU_SetRegionNum(uint32_t dwRegionNum); +void MPU_DisableRegion(void); +uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes); +void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, + uint32_t dwRegionAttr); + +#endif /* #ifndef _MMU_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio.h b/bsps/arm/atsam/include/libchip/include/pio.h new file mode 100644 index 0000000000..6cf463d1ec --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio.h @@ -0,0 +1,217 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * This file provides a basic API for PIO configuration and usage of + * user-controlled pins. Please refer to the board.h file for a list of + * available pin definitions. + * + * \section Usage + * + * -# Define a constant pin description array such as the following one, using + * the existing definitions provided by the board.h file if possible: + * \code + * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; + * \endcode + * Alternatively, it is possible to add new pins by provided the full Pin + * structure: + * \code + * // Pin instance to configure PA10 & PA11 as inputs with the internal + * // pull-up enabled. + * const Pin pPins = { + * (1 << 10) | (1 << 11), + * REG_PIOA, + * ID_PIOA, + * PIO_INPUT, + * PIO_PULLUP + * }; + * \endcode + * -# Configure a pin array by calling PIO_Configure() with a pointer to the + * array and its size (which is computed using the PIO_LISTSIZE macro). + * -# Change and get the value of a user-controlled pin using the PIO_Set, + * PIO_Clear and PIO_Get methods. + * -# Get the level being currently output by a user-controlled pin configured + * as an output using PIO_GetOutputDataStatus(). + */ + +#ifndef _PIO_ +#define _PIO_ + +/* + * Headers + */ + +#include "chip.h" + +#include + +/* + * Global Definitions + */ + +/** The pin is controlled by the associated signal of peripheral A. */ +#define PIO_PERIPH_A 0 +/** The pin is controlled by the associated signal of peripheral B. */ +#define PIO_PERIPH_B 1 +/** The pin is controlled by the associated signal of peripheral C. */ +#define PIO_PERIPH_C 2 +/** The pin is controlled by the associated signal of peripheral D. */ +#define PIO_PERIPH_D 3 +/** The pin is an input. */ +#define PIO_INPUT 4 +/** The pin is an output and has a default level of 0. */ +#define PIO_OUTPUT_0 5 +/** The pin is an output and has a default level of 1. */ +#define PIO_OUTPUT_1 6 + +/** Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0 << 0) +/** The internal pin pull-up is active. */ +#define PIO_PULLUP (1 << 0) +/** The internal glitch filter is active. */ +#define PIO_DEGLITCH (1 << 1) +/** The pin is open-drain. */ +#define PIO_OPENDRAIN (1 << 2) + +/** The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1 << 3) + +/** Enable additional interrupt modes. */ +#define PIO_IT_AIME (1 << 4) + +/** Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1 << 5) +/** Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1 << 6) + +/** Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/** High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/** Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/** Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) +/** The WP is enable */ +#define PIO_WPMR_WPEN_EN (0x01 << 0) +/** The WP is disable */ +#define PIO_WPMR_WPEN_DIS (0x00 << 0) +/** Valid WP key */ +#define PIO_WPMR_WPKEY_VALID (0x50494F << 8) +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Global Macros + */ + +/** + * Calculates the size of an array of Pin instances. The array must be defined + * locally (i.e. not a pointer), otherwise the computation will not be correct. + * \param pPins Local array of Pin instances. + * \return Number of elements in array. + */ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +/* + * Global Types + */ + + +/* + * Describes the type and attribute of one PIO pin or a group of similar pins. + * The #type# field can have the following values: + * - PIO_PERIPH_A + * - PIO_PERIPH_B + * - PIO_OUTPUT_0 + * - PIO_OUTPUT_1 + * - PIO_INPUT + * + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +typedef struct _Pin { + /* Bitmask indicating which pin(s) to configure. */ + uint32_t mask; + /* Pointer to the PIO controller which has the pin(s). */ + Pio *pio; + /* Peripheral ID of the PIO controller which has the pin(s). */ + uint8_t id; + /* Pin type. */ + uint8_t type; + /* Pin attribute. */ + uint8_t attribute; +} Pin; + +/* + * Global Access Macros + */ + +/* + * Global Functions + */ + +extern uint8_t PIO_Configure(const Pin *list, uint32_t size); + +extern void PIO_Set(const Pin *pin); + +extern void PIO_Clear(const Pin *pin); + +extern uint8_t PIO_Get(const Pin *pin); + +extern uint8_t PIO_GetOutputDataStatus(const Pin *pin); + +extern void PIO_SetDebounceFilter(const Pin *pin, uint32_t cuttoff); + +extern void PIO_EnableWriteProtect(const Pin *pin); + +extern void PIO_DisableWriteProtect(const Pin *pin); + +extern void PIO_SetPinType(Pin *pin, uint8_t pinType); + +extern uint32_t PIO_GetWriteProtectViolationInfo(const Pin *pin); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio_capture.h b/bsps/arm/atsam/include/libchip/include/pio_capture.h new file mode 100644 index 0000000000..087b19d0b4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio_capture.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef PIO_CAPTURE_H +#define PIO_CAPTURE_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief PIO Parallel Capture structure for initialize. + * + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpioCaptureInit { + + /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */ + uint8_t dsize; + /** PDC size, data to be received */ + uint16_t dPDCsize; + /** Data to be received */ + uint32_t *pData; + /** Parallel Capture Mode Always Sampling */ + uint8_t alwaysSampling; + /** Parallel Capture Mode Half Sampling */ + uint8_t halfSampling; + /** Parallel Capture Mode First Sample */ + uint8_t modeFirstSample; + /** Callback function invoked at Mode Data Ready */ + void (*CbkDataReady)(struct _SpioCaptureInit *); + /** Callback function invoked at Mode Overrun Error */ + void (*CbkOverrun)(struct _SpioCaptureInit *); + /** Callback function invoked at End of Reception Transfer */ + void (*CbkEndReception)(struct _SpioCaptureInit *); + /** Callback function invoked at Reception Buffer Full */ + void (*CbkBuffFull)(struct _SpioCaptureInit *); + /** Callback arguments.*/ + void *pParam; + +} SpioCaptureInit; + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +extern void PIO_CaptureDisableIt(uint32_t itToDisable); +extern void PIO_CaptureEnableIt(uint32_t itToEnable); +extern void PIO_CaptureEnable(void); +extern void PIO_CaptureDisable(void); +extern void PIO_CaptureInit(SpioCaptureInit *pInit); + +#endif /* #ifndef PIO_CAPTURE_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/pio_it.h b/bsps/arm/atsam/include/libchip/include/pio_it.h new file mode 100644 index 0000000000..b03973caa1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pio_it.h @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Configuration and handling of interrupts on PIO status changes. The API + * provided here have several advantages over the traditional PIO interrupt + * configuration approach: + * - It is highly portable + * - It automatically demultiplexes interrupts when multiples pins have been + * configured on a single PIO controller + * - It allows a group of pins to share the same interrupt + * + * However, it also has several minor drawbacks that may prevent from using it + * in particular applications: + * - It enables the clocks of all PIO controllers + * - PIO controllers all share the same interrupt handler, which does the + * demultiplexing and can be slower than direct configuration + * - It reserves space for a fixed number of interrupts, which can be + * increased by modifying the appropriate constant in pio_it.c. + * + * \par Usage + * + * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() + * with the desired priority (0 ... 7). + * -# Configure a status change interrupt on one or more pin(s) with + * PIO_ConfigureIt(). + * -# Enable & disable interrupts on pins using PIO_EnableIt() and + * PIO_DisableIt(). + */ + +#ifndef _PIO_IT_ +#define _PIO_IT_ + +/* + * Headers + */ + +#include "pio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Global functions + */ + +extern void PIO_InitializeInterrupts(uint32_t dwPriority); + +extern void PIO_ConfigureIt(const Pin *pPin, + void (*handler)(const Pin *, void *arg), void *arg); + + +/** + * Enables the given interrupt source if it has been configured. The status + * register of the corresponding PIO controller is cleared prior to enabling + * the interrupt. + * \param pPin Interrupt source to enable. + */ +static inline void PIO_EnableIt(const Pin *pPin) +{ + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask; +} + +/** + * Disables a given interrupt source, with no added side effects. + * + * \param pPin Interrupt source to disable. + */ +static inline void PIO_DisableIt(const Pin *pPin) +{ + pPin->pio->PIO_IDR = pPin->mask; +} + +extern void PIO_IT_InterruptHandler(void); + +extern void PioInterruptHandler(uint32_t id, Pio *pPio); + +extern void PIO_CaptureHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_IT_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/pmc.h b/bsps/arm/atsam/include/libchip/include/pmc.h new file mode 100644 index 0000000000..4494513fff --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pmc.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _PMC_ +#define _PMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* Definition for fast RC frequency */ +#define FAST_RC_4MHZ CKGR_MOR_MOSCRCF_4MHz +#define FAST_RC_8MHZ CKGR_MOR_MOSCRCF_8MHz +#define FAST_RC_12MHZ CKGR_MOR_MOSCRCF_12MHz + +/* Definitions for startup count. + * Note: 1 count unit stand for: 1 / 32768 * 8 = 244 us + */ +/* Default startup count for 4/8/12MHz fast RC (startup time: 10us) */ +#define DEFAUTL_FAST_RC_COUNT 1 +/* Default startup count for 3-20MHz main oscillator (startup time: 1.4ms) */ +#define DEFAUTL_MAIN_OSC_COUNT 8 +/* Default startup count for PLLA (startup time: 200us) */ +#define DEFAUTL_PLLA_COUNT 1 +/* Default startup count for UPLL */ +#define DEFAUTL_UPLL_COUNT 3 +/* No change for default startup count */ +#define DEFAUTL_COUNT_NO_CHANGE 0xFFFF + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void PMC_EnablePeripheral(uint32_t dwId); +extern void PMC_DisablePeripheral(uint32_t dwId); + +extern void PMC_EnableAllPeripherals(void); +extern void PMC_DisableAllPeripherals(void); + +extern uint32_t PMC_IsPeriphEnabled(uint32_t dwId); + +extern void PMC_SelectExtOsc(void); +extern void PMC_EnableExtOsc(void); +extern void PMC_DisableExtOsc(void); +extern void PMC_SelectExtBypassOsc(void); +extern void PMC_EnableIntRC4_8_12MHz(uint32_t fastRcFreq); +extern void PMC_DisableIntRC4_8_12MHz(void); +extern void PMC_SetPllaClock(uint32_t mul, uint32_t div); +extern void PMC_SetPllbClock(uint32_t mul, uint32_t div); +extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler); +extern void PMC_DisableAllClocks(void); +extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_ConfigureMckWithPllb(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_EnableXT32KFME(void); +extern void PMC_ConfigurePCK0(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK1(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ diff --git a/bsps/arm/atsam/include/libchip/include/pwmc.h b/bsps/arm/atsam/include/libchip/include/pwmc.h new file mode 100644 index 0000000000..fccfb15556 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/pwmc.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Interface for configuration the Pulse Width Modulation Controller (PWM) + * peripheral. + * + * \par Usage + * + * -# Configures PWM clocks A & B to run at the given frequencies using + * \ref PWMC_ConfigureClocks(). + * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), + * \ref PWMC_ConfigureChannelExt() + * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and + * \ref PWMC_SetDeadTime(). + * -# Enable & disable channel using \ref PWMC_EnableChannel() and + * \ref PWMC_DisableChannel(). + * -# Enable & disable the period interrupt for the given PWM channel using + * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). + * -# Enable & disable the selected interrupts sources on a PWMC peripheral + * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). + * -# Control synchronous channel using \ref PWMC_ConfigureSyncChannel(), + * \ref PWMC_SetSyncChannelUpdatePeriod() and + * \ref PWMC_SetSyncChannelUpdateUnlock(). + * -# Control PWM override output using \ref PWMC_SetOverrideValue(), + * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). + * -# Send data through the transmitter using \ref PWMC_WriteBuffer(). + * + */ + +#ifndef _PWMC_ +#define _PWMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void PWMC_ConfigureChannel( + Pwm *pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity); +extern void PWMC_ConfigureChannelExt( + Pwm *pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity, + uint32_t countEventSelect, + uint32_t DTEnable, + uint32_t DTHInverte, + uint32_t DTLInverte); +extern void PWMC_ConfigureClocks(Pwm *pPwm, uint32_t clka, uint32_t clkb, + uint32_t mck); +extern void PWMC_SetPeriod(Pwm *pPwm, uint8_t channel, uint16_t period); +extern void PWMC_SetDutyCycle(Pwm *pPwm, uint8_t channel, uint16_t duty); +extern void PWMC_SetDeadTime(Pwm *pPwm, uint8_t channel, uint16_t timeH, + uint16_t timeL); +extern void PWMC_ConfigureSyncChannel(Pwm *pPwm, + uint32_t channels, + uint32_t updateMode, + uint32_t requestMode, + uint32_t requestComparisonSelect); +extern void PWMC_SetSyncChannelUpdatePeriod(Pwm *pPwm, uint8_t period); +extern void PWMC_SetSyncChannelUpdateUnlock(Pwm *pPwm); +extern void PWMC_EnableChannel(Pwm *pPwm, uint8_t channel); +extern void PWMC_DisableChannel(Pwm *pPwm, uint8_t channel); +extern void PWMC_EnableChannelIt(Pwm *pPwm, uint8_t channel); +extern void PWMC_DisableChannelIt(Pwm *pPwm, uint8_t channel); +extern void PWMC_EnableIt(Pwm *pPwm, uint32_t sources1, uint32_t sources2); +extern void PWMC_DisableIt(Pwm *pPwm, uint32_t sources1, uint32_t sources2); +extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, + void *buffer, + uint32_t length); +extern void PWMC_SetOverrideValue(Pwm *pPwm, uint32_t value); +extern void PWMC_EnableOverrideOutput(Pwm *pPwm, uint32_t value, + uint32_t sync); +extern void PWMC_OutputOverrideSelection(Pwm *pPwm, uint32_t value); +extern void PWMC_DisableOverrideOutput(Pwm *pPwm, uint32_t value, + uint32_t sync); +extern void PWMC_SetFaultMode(Pwm *pPwm, uint32_t mode); +extern void PWMC_FaultClear(Pwm *pPwm, uint32_t fault); +extern void PWMC_SetFaultProtectionValue(Pwm *pPwm, uint32_t value); +extern void PWMC_EnableFaultProtection(Pwm *pPwm, uint32_t value); +extern void PWMC_ConfigureComparisonUnit(Pwm *pPwm, uint32_t x, + uint32_t value, uint32_t mode); +extern void PWMC_ConfigureEventLineMode(Pwm *pPwm, uint32_t x, uint32_t mode); +extern uint32_t PWMC_GetStatus2(Pwm *pPwm); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PWMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/qspi.h b/bsps/arm/atsam/include/libchip/include/qspi.h new file mode 100644 index 0000000000..c1f81f6ad6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/qspi.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _QSPI_ +#define _QSPI_ +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section qspi_configuration_macros SPI Configuration Macros + * - \ref QSPI_PCS + * - \ref QSPI_SCBR + * - \ref QSPI_DLYBS + * - \ref QSPI_DLYBCT + */ + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define QSPI_SCBR(baudrate, masterClock) \ + ((uint32_t) (masterClock / baudrate) << 8) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define QSPI_DLYBS(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define QSPI_DLYBCT(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) + +/*--------------------------------------------------------------------------- */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** \brief qspi access modes + */ +typedef enum { + CmdAccess = 0, + ReadAccess, + WriteAccess +} Access_t; + +/** \brief qspi modes SPI or QSPI + */ +typedef enum { + SpiMode = QSPI_MR_SMM_SPI, + QspiMemMode = QSPI_MR_SMM_MEMORY +} QspiMode_t; + + +/** \brief qspi clock modes , regarding clock phase and clock polarity + */ +typedef enum { + ClockMode_00 = 0, + ClockMode_10, + ClockMode_01, + ClockMode_11 +} QspiClockMode_t; + + +/** \brief qspi status codes + */ +typedef enum { + QSPI_SUCCESS = 0, + QSPI_BUSY, + QSPI_BUSY_SENDING, + QSPI_READ_ERROR, + QSPI_WRITE_ERROR, + QSPI_UNKNOWN_ERROR, + QSPI_INIT_ERROR, + QSPI_INPUT_ERROR, + QSPI_TOTAL_ERROR +} QspidStatus_t; + + +/** \brief qspi status regiter bits + */ +typedef enum { + IsReceived = QSPI_SR_RDRF, + IsTxSent = QSPI_SR_TDRE, + IsTxEmpty = QSPI_SR_TXEMPTY, + IsOverrun = QSPI_SR_OVRES, + IsCsRise = QSPI_SR_CSR, + IsCsAsserted = QSPI_SR_CSS, + IsEofInst = QSPI_SR_INSTRE, + IsEnabled = QSPI_SR_QSPIENS +} QspiStatus_t; + +/** \brief qspi command structure + */ +typedef struct { + uint8_t Instruction; + uint8_t Option; +} QspiMemCmd_t; + +/** \brief qspi buffer structure + */ +typedef struct { + uint32_t TxDataSize; /* Tx buffer size */ + uint32_t RxDataSize; /* Rx buffer size */ + const void *pDataTx; /* Tx buffer */ + void *pDataRx; /* Rx buffer */ +} QspiBuffer_t; + + +/** \brief qspi frame structure for QSPI mode + */ +typedef struct { + union _QspiInstFrame { + uint32_t val; + struct _QspiInstFrameBM { + uint32_t bwidth: 3, /** Width of QSPI Addr , inst data */ + reserved0: 1, /** Reserved*/ + bInstEn: 1, /** Enable Inst */ + bAddrEn: 1, /** Enable Address */ + bOptEn: 1, /** Enable Option */ + bDataEn: 1, /** Enable Data */ + bOptLen: 2, /** Option Length*/ + bAddrLen: 1, /** Addrs Length*/ + reserved1: 1, /** Option Length*/ + bXfrType: 2, /** Transfer type*/ + bContinuesRead: 1, /** Continoues read mode*/ + reserved2: 1, /** Reserved*/ + bDummyCycles: 5, /**< Unicast hash match */ + reserved3: 11; /** Reserved*/ + } bm; + } InstFrame; + uint32_t Addr; +} QspiInstFrame_t; + +/** \brief qspi driver structure + */ +typedef struct { + uint8_t qspiId; /* QSPI ID */ + Qspi *pQspiHw; /* QSPI Hw instance */ + QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */ + QspiMemCmd_t qspiCommand; /* Qspi command structure*/ + QspiBuffer_t qspiBuffer; /* Qspi buffer*/ + QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/ +} Qspid_t; + + +void QSPI_SwReset(Qspi *pQspi); + +void QSPI_Disable(Qspi *pQspi); + +void QSPI_Enable(Qspi *pQspi); + +QspidStatus_t QSPI_EndTransfer(Qspi *pQspi); + +uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus); + +void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, + uint32_t dwClockCfg); + +QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData); + +QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t * + const pData, uint32_t NumOfBytes); + +QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData); + +QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData , + uint32_t NumOfBytes); + +QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources); + +QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources); + +uint32_t QSPI_GetItMask(Qspi *pQspi); + +uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi); + +QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, + uint32_t dwConfiguration); + +QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg, + uint8_t ScrambleFlag); + +QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _QSPI_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/qspi_dma.h b/bsps/arm/atsam/include/libchip/include/qspi_dma.h new file mode 100644 index 0000000000..8ee274e15d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/qspi_dma.h @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef QSPI_DMA_H +#define QSPI_DMA_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#ifndef __rtems__ +#include "../../../../utils/utility.h" +#endif /* __rtems__ */ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define QSPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define QSPID_ERROR_LOCK 2 + +#define QSPID_CH_NOT_ENABLED 0xFF +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*QspidCallback)(uint8_t, void *); + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Qspid { + Qspid_t Qspid; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** Polling */ + uint8_t Polling; + /** Tx ch num */ + uint8_t TxChNum; + /** Rx ch num */ + uint8_t RxChNum; + /** QSPI Xfr state. */ + volatile uint8_t progress; +} QspiDma_t; + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t QSPID_Configure(QspiDma_t *pQspidma, QspiMode_t Mode, + uint32_t dwConfiguration, sXdmad *pXdmad); + +uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_ReadWriteQSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_IsBusy(volatile uint8_t *QspiSemaphore); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/rstc.h b/bsps/arm/atsam/include/libchip/include/rstc.h new file mode 100644 index 0000000000..7c33a465b0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rstc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _RSTC_H +#define _RSTC_H + +/*--------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +void RSTC_ConfigureMode(uint32_t rmr); + +void RSTC_SetUserResetEnable(uint8_t enable); + +void RSTC_SetUserResetInterruptEnable(uint8_t enable); + +void RSTC_SetExtResetLength(uint8_t powl); + +void RSTC_ProcessorReset(void); + +void RSTC_ExtReset(void); + +uint8_t RSTC_GetNrstLevel(void); + +uint8_t RSTC_IsUserResetDetected(void); + +uint8_t RSTC_IsBusy(void); + +uint32_t RSTC_GetStatus(void); + +#endif /* #ifndef _RSTC_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/rtc.h b/bsps/arm/atsam/include/libchip/include/rtc.h new file mode 100644 index 0000000000..9fd724824a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rtc.h @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Real Time Clock (RTC) controller. + * + */ + +#ifndef _RTC_ +#define _RTC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define RTC_HOUR_BIT_LEN_MASK 0x3F +#define RTC_MIN_BIT_LEN_MASK 0x7F +#define RTC_SEC_BIT_LEN_MASK 0x7F +#define RTC_CENT_BIT_LEN_MASK 0x7F +#define RTC_YEAR_BIT_LEN_MASK 0xFF +#define RTC_MONTH_BIT_LEN_MASK 0x1F +#define RTC_DATE_BIT_LEN_MASK 0x3F +#define RTC_WEEK_BIT_LEN_MASK 0x07 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void RTC_SetHourMode(Rtc *pRtc, uint32_t dwMode); + +extern uint32_t RTC_GetHourMode(Rtc *pRtc); + +extern void RTC_EnableIt(Rtc *pRtc, uint32_t dwSources); + +extern void RTC_DisableIt(Rtc *pRtc, uint32_t dwSources); + +extern int RTC_SetTime(Rtc *pRtc, uint8_t ucHour, uint8_t ucMinute, + uint8_t ucSecond); + +extern void RTC_GetTime(Rtc *pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond); + +extern int RTC_SetTimeAlarm(Rtc *pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond); + +extern void RTC_GetDate(Rtc *pRtc, uint16_t *pwYear, uint8_t *pucMonth, + uint8_t *pucDay, uint8_t *pucWeek); + +extern int RTC_SetDate(Rtc *pRtc, uint16_t wYear, uint8_t ucMonth, + uint8_t ucDay, uint8_t ucWeek); + +extern int RTC_SetDateAlarm(Rtc *pRtc, uint8_t *pucMonth, uint8_t *pucDay); + +extern void RTC_ClearSCCR(Rtc *pRtc, uint32_t dwMask); + +extern uint32_t RTC_GetSR(Rtc *pRtc, uint32_t dwMask); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _RTC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/rtt.h b/bsps/arm/atsam/include/libchip/include/rtt.h new file mode 100644 index 0000000000..2dd2ca5eb5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/rtt.h @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Interface for Real Time Timer (RTT) controller. + * + * \par Usage + * + * -# Changes the prescaler value of the given RTT and restarts it + * using \ref RTT_SetPrescaler(). + * -# Get current value of the RTT using \ref RTT_GetTime(). + * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). + * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). + * -# Configures the RTT to generate an alarm at the given time + * using \ref RTT_SetAlarm(). + */ + +#ifndef _RTT_ +#define _RTT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void RTT_SetPrescaler(Rtt *pRtt, uint16_t wPrescaler); + +extern uint32_t RTT_GetTime(Rtt *pRtt); + +extern void RTT_EnableIT(Rtt *pRtt, uint32_t dwSources); + +extern uint32_t RTT_GetStatus(Rtt *pRtt); + +extern void RTT_SetAlarm(Rtt *pRtt, uint32_t dwTime); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef RTT_H */ + diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h new file mode 100644 index 0000000000..9810e118f8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ACC_COMPONENT_ +#define _SAME70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAME70_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h new file mode 100644 index 0000000000..cd14abc0a1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_AES_COMPONENT_ +#define _SAME70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAME70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAME70_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h new file mode 100644 index 0000000000..8b009b4ba1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_AFEC_COMPONENT_ +#define _SAME70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h new file mode 100644 index 0000000000..0bf098d895 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_CHIPID_COMPONENT_ +#define _SAME70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAME70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAME70_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h new file mode 100644 index 0000000000..a57a1e1b32 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_DACC_COMPONENT_ +#define _SAME70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h new file mode 100644 index 0000000000..809db26a7a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_EFC_COMPONENT_ +#define _SAME70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[53]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h new file mode 100644 index 0000000000..6baf8fbd60 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h @@ -0,0 +1,1240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_GMAC_COMPONENT_ +#define _SAME70_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAME70_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[2]; + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[2]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[14]; + __IO uint32_t GMAC_TBQBAPQ[2]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[14]; + __IO uint32_t GMAC_RBQBAPQ[2]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[6]; + __IO uint32_t GMAC_RBSRPQ[2]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[5]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[2]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[6]; + __O uint32_t GMAC_IDRPQ[2]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[6]; + __IO uint32_t GMAC_IMRPQ[2]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[38]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAME70_GMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h new file mode 100644 index 0000000000..a88b2b63c4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_GPBR_COMPONENT_ +#define _SAME70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAME70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAME70_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h new file mode 100644 index 0000000000..47f3e1c57c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_HSMCI_COMPONENT_ +#define _SAME70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAME70_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h new file mode 100644 index 0000000000..62a077414f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ICM_COMPONENT_ +#define _SAME70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAME70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAME70_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h new file mode 100644 index 0000000000..78839a68a6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ISI_COMPONENT_ +#define _SAME70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h new file mode 100644 index 0000000000..f9325ce550 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h @@ -0,0 +1,301 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_MATRIX_COMPONENT_ +#define _SAME70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAME70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __IO uint32_t MATRIX_MCFG9; /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */ + __IO uint32_t MATRIX_MCFG10; /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */ + __IO uint32_t MATRIX_MCFG11; /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */ + __I uint32_t Reserved2[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved6[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */ +#define MATRIX_MCFG9_ULBT_Pos 0 +#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */ +#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos))) +#define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */ +#define MATRIX_MCFG10_ULBT_Pos 0 +#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos) /**< \brief (MATRIX_MCFG10) Undefined Length Burst Type */ +#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos))) +#define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG10) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG10) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG10) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG10) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG10) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG10) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG10) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG10) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */ +#define MATRIX_MCFG11_ULBT_Pos 0 +#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos) /**< \brief (MATRIX_MCFG11) Undefined Length Burst Type */ +#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos))) +#define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG11) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG11) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG11) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG11) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG11) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG11) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG11) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG11) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h new file mode 100644 index 0000000000..aa9784e723 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h @@ -0,0 +1,845 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_MCAN_COMPONENT_ +#define _SAME70_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAME70_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t Reserved1[2]; + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved2[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved4[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 4- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAME70_MCAN_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h new file mode 100644 index 0000000000..357ebaf4fd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h @@ -0,0 +1,1711 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PIO_COMPONENT_ +#define _SAME70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAME70_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h new file mode 100644 index 0000000000..63d9749f1f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h @@ -0,0 +1,723 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PMC_COMPONENT_ +#define _SAME70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAME70_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h new file mode 100644 index 0000000000..46ad816164 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_PWM_COMPONENT_ +#define _SAME70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAME70_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h new file mode 100644 index 0000000000..79711335d6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_QSPI_COMPONENT_ +#define _SAME70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h new file mode 100644 index 0000000000..984c621ac4 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RSTC_COMPONENT_ +#define _SAME70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h new file mode 100644 index 0000000000..959faa2875 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RSWDT_COMPONENT_ +#define _SAME70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAME70_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h new file mode 100644 index 0000000000..ef391274d5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RTC_COMPONENT_ +#define _SAME70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h new file mode 100644 index 0000000000..dd4dfd5b86 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_RTT_COMPONENT_ +#define _SAME70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h new file mode 100644 index 0000000000..758f78919a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SDRAMC_COMPONENT_ +#define _SAME70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAME70_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h new file mode 100644 index 0000000000..02489ddf9a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SMC_COMPONENT_ +#define _SAME70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h new file mode 100644 index 0000000000..69517090e6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SPI_COMPONENT_ +#define _SAME70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h new file mode 100644 index 0000000000..dd929003d7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SSC_COMPONENT_ +#define _SAME70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h new file mode 100644 index 0000000000..54ad2e048b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_SUPC_COMPONENT_ +#define _SAME70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAME70_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h new file mode 100644 index 0000000000..ce068e41c9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TC_COMPONENT_ +#define _SAME70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAME70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h new file mode 100644 index 0000000000..f1a18b7634 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TRNG_COMPONENT_ +#define _SAME70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAME70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAME70_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h new file mode 100644 index 0000000000..6a5f39da61 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_TWIHS_COMPONENT_ +#define _SAME70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAME70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h new file mode 100644 index 0000000000..451b72e618 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_UART_COMPONENT_ +#define _SAME70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h new file mode 100644 index 0000000000..c8e7a4abda --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h @@ -0,0 +1,478 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_USART_COMPONENT_ +#define _SAME70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAME70_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h new file mode 100644 index 0000000000..72ea8f5e34 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h @@ -0,0 +1,909 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_USBHS_COMPONENT_ +#define _SAME70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ + +/*@}*/ + + +#endif /* _SAME70_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h new file mode 100644 index 0000000000..26ca52180b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_UTMI_COMPONENT_ +#define _SAME70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAME70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAME70_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h new file mode 100644 index 0000000000..12ddb6da95 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_WDT_COMPONENT_ +#define _SAME70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h new file mode 100644 index 0000000000..28f3745e59 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_XDMAC_COMPONENT_ +#define _SAME70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAME70_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h new file mode 100644 index 0000000000..caae7f179b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h @@ -0,0 +1,431 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J19_PIO_ +#define _SAME70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h new file mode 100644 index 0000000000..b4c8725975 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j20.h @@ -0,0 +1,437 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J20_PIO_ +#define _SAME70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h new file mode 100644 index 0000000000..1c973f41f6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j21.h @@ -0,0 +1,437 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J21_PIO_ +#define _SAME70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h new file mode 100644 index 0000000000..ee761f9ce8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N19_PIO_ +#define _SAME70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h new file mode 100644 index 0000000000..8bec67ff00 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n20.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N20_PIO_ +#define _SAME70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h new file mode 100644 index 0000000000..a0b3757033 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n21.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N21_PIO_ +#define _SAME70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h new file mode 100644 index 0000000000..532ba6d4e6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q19_PIO_ +#define _SAME70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h new file mode 100644 index 0000000000..f9b35f5d23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q20_PIO_ +#define _SAME70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h new file mode 100644 index 0000000000..507b287f89 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h @@ -0,0 +1,668 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q21_PIO_ +#define _SAME70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70.h b/bsps/arm/atsam/include/libchip/include/same70/same70.h new file mode 100644 index 0000000000..f7e5a5c9ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70_ +#define _SAME70_ + +#if defined __SAME70J19__ + #include "same70j19.h" +#elif defined __SAME70J20__ + #include "same70j20.h" +#elif defined __SAME70J21__ + #include "same70j21.h" +#elif defined __SAME70N19__ + #include "same70n19.h" +#elif defined __SAME70N20__ + #include "same70n20.h" +#elif defined __SAME70N21__ + #include "same70n21.h" +#elif defined __SAME70Q19__ + #include "same70q19.h" +#elif defined __SAME70Q20__ + #include "same70q20.h" +#elif defined __SAME70Q21__ + #include "same70q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME70_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j19.h b/bsps/arm/atsam/include/libchip/include/same70/same70j19.h new file mode 100644 index 0000000000..a82d7c1ad8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j19.h @@ -0,0 +1,623 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J19_ +#define _SAME70J19_ + +/** \addtogroup SAME70J19_definitions SAME70J19 definitions + This file defines all structures and symbols for SAME70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J19 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j20.h b/bsps/arm/atsam/include/libchip/include/same70/same70j20.h new file mode 100644 index 0000000000..a877891ea7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j20.h @@ -0,0 +1,630 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J20_ +#define _SAME70J20_ + +/** \addtogroup SAME70J20_definitions SAME70J20 definitions + This file defines all structures and symbols for SAME70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70j21.h b/bsps/arm/atsam/include/libchip/include/same70/same70j21.h new file mode 100644 index 0000000000..812c28c3af --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70j21.h @@ -0,0 +1,630 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70J21_ +#define _SAME70J21_ + +/** \addtogroup SAME70J21_definitions SAME70J21 definitions + This file defines all structures and symbols for SAME70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70J21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70J21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAME70J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n19.h b/bsps/arm/atsam/include/libchip/include/same70/same70n19.h new file mode 100644 index 0000000000..ed565d4e31 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n19.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N19_ +#define _SAME70N19_ + +/** \addtogroup SAME70N19_definitions SAME70N19 definitions + This file defines all structures and symbols for SAME70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n20.h b/bsps/arm/atsam/include/libchip/include/same70/same70n20.h new file mode 100644 index 0000000000..84b12656c9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n20.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N20_ +#define _SAME70N20_ + +/** \addtogroup SAME70N20_definitions SAME70N20 definitions + This file defines all structures and symbols for SAME70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70n21.h b/bsps/arm/atsam/include/libchip/include/same70/same70n21.h new file mode 100644 index 0000000000..ceaeef3b3c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70n21.h @@ -0,0 +1,636 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70N21_ +#define _SAME70N21_ + +/** \addtogroup SAME70N21_definitions SAME70N21 definitions + This file defines all structures and symbols for SAME70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70N21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70N21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q19.h b/bsps/arm/atsam/include/libchip/include/same70/same70q19.h new file mode 100644 index 0000000000..136ac0e239 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q19.h @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q19_ +#define _SAME70Q19_ + +/** \addtogroup SAME70Q19_definitions SAME70Q19 definitions + This file defines all structures and symbols for SAME70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q20.h b/bsps/arm/atsam/include/libchip/include/same70/same70q20.h new file mode 100644 index 0000000000..dc5858cda6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q20.h @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q20_ +#define _SAME70Q20_ + +/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions + This file defines all structures and symbols for SAME70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/same70q21.h b/bsps/arm/atsam/include/libchip/include/same70/same70q21.h new file mode 100644 index 0000000000..3cd174e6cf --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/same70q21.h @@ -0,0 +1,689 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAME70Q21_ +#define _SAME70Q21_ + +/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions + This file defines all structures and symbols for SAME70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAME70Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAME70Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAME70Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAME70Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_same70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/same70/system_same70.h b/bsps/arm/atsam/include/libchip/include/same70/system_same70.h new file mode 100644 index 0000000000..fd0428426c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/same70/system_same70.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAME70_H_INCLUDED +#define SYSTEM_SAME70_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAME70_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h new file mode 100644 index 0000000000..84d991560e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ACC_COMPONENT_ +#define _SAMS70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAMS70_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h new file mode 100644 index 0000000000..86d6e95a18 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_AES_COMPONENT_ +#define _SAMS70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMS70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h new file mode 100644 index 0000000000..638bf0a4f1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_AFEC_COMPONENT_ +#define _SAMS70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h new file mode 100644 index 0000000000..b6ca561684 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_CHIPID_COMPONENT_ +#define _SAMS70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMS70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMS70_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h new file mode 100644 index 0000000000..d9f5fd020a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_DACC_COMPONENT_ +#define _SAMS70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h new file mode 100644 index 0000000000..7ac6dedf1d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_EFC_COMPONENT_ +#define _SAMS70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[53]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h new file mode 100644 index 0000000000..7a4139a128 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_GPBR_COMPONENT_ +#define _SAMS70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMS70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h new file mode 100644 index 0000000000..53fbd4a024 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_HSMCI_COMPONENT_ +#define _SAMS70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h new file mode 100644 index 0000000000..3c2c3eb854 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ICM_COMPONENT_ +#define _SAMS70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h new file mode 100644 index 0000000000..82dd0cbf91 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ISI_COMPONENT_ +#define _SAMS70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h new file mode 100644 index 0000000000..b539d4d1f9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h @@ -0,0 +1,461 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_MATRIX_COMPONENT_ +#define _SAMS70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMS70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Matrix hardware registers */ +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __I uint32_t Reserved2[7]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS0; /**< \brief (Matrix Offset: 0x0084) Priority Register B for Slave 0 */ + __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + __IO uint32_t MATRIX_PRBS1; /**< \brief (Matrix Offset: 0x008C) Priority Register B for Slave 1 */ + __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + __IO uint32_t MATRIX_PRBS2; /**< \brief (Matrix Offset: 0x0094) Priority Register B for Slave 2 */ + __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + __IO uint32_t MATRIX_PRBS3; /**< \brief (Matrix Offset: 0x009C) Priority Register B for Slave 3 */ + __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + __IO uint32_t MATRIX_PRBS4; /**< \brief (Matrix Offset: 0x00A4) Priority Register B for Slave 4 */ + __IO uint32_t MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ + __IO uint32_t MATRIX_PRBS5; /**< \brief (Matrix Offset: 0x00AC) Priority Register B for Slave 5 */ + __IO uint32_t MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ + __IO uint32_t MATRIX_PRBS6; /**< \brief (Matrix Offset: 0x00B4) Priority Register B for Slave 6 */ + __IO uint32_t MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ + __IO uint32_t MATRIX_PRBS7; /**< \brief (Matrix Offset: 0x00BC) Priority Register B for Slave 7 */ + __IO uint32_t MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ + __IO uint32_t MATRIX_PRBS8; /**< \brief (Matrix Offset: 0x00C4) Priority Register B for Slave 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */ + __I uint32_t Reserved6[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) +#define MATRIX_PRAS0_M5PR_Pos 20 +#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */ +#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos))) +#define MATRIX_PRAS0_M6PR_Pos 24 +#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */ +#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos))) +/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS0_M8PR_Pos 0 +#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) /**< \brief (MATRIX_PRBS0) Master 8 Priority */ +#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos))) +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) +#define MATRIX_PRAS1_M5PR_Pos 20 +#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */ +#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos))) +#define MATRIX_PRAS1_M6PR_Pos 24 +#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */ +#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos))) +/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */ +#define MATRIX_PRBS1_M8PR_Pos 0 +#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) /**< \brief (MATRIX_PRBS1) Master 8 Priority */ +#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos))) +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) +#define MATRIX_PRAS2_M5PR_Pos 20 +#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */ +#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos))) +#define MATRIX_PRAS2_M6PR_Pos 24 +#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */ +#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos))) +/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */ +#define MATRIX_PRBS2_M8PR_Pos 0 +#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) /**< \brief (MATRIX_PRBS2) Master 8 Priority */ +#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos))) +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) +#define MATRIX_PRAS3_M5PR_Pos 20 +#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */ +#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos))) +#define MATRIX_PRAS3_M6PR_Pos 24 +#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */ +#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos))) +/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */ +#define MATRIX_PRBS3_M8PR_Pos 0 +#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) /**< \brief (MATRIX_PRBS3) Master 8 Priority */ +#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos))) +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) +#define MATRIX_PRAS4_M5PR_Pos 20 +#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */ +#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos))) +#define MATRIX_PRAS4_M6PR_Pos 24 +#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */ +#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos))) +/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */ +#define MATRIX_PRBS4_M8PR_Pos 0 +#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) /**< \brief (MATRIX_PRBS4) Master 8 Priority */ +#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos))) +/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ +#define MATRIX_PRAS5_M0PR_Pos 0 +#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ +#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) +#define MATRIX_PRAS5_M1PR_Pos 4 +#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ +#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) +#define MATRIX_PRAS5_M2PR_Pos 8 +#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ +#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) +#define MATRIX_PRAS5_M3PR_Pos 12 +#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ +#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) +#define MATRIX_PRAS5_M4PR_Pos 16 +#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ +#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) +#define MATRIX_PRAS5_M5PR_Pos 20 +#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */ +#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos))) +#define MATRIX_PRAS5_M6PR_Pos 24 +#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */ +#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos))) +/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */ +#define MATRIX_PRBS5_M8PR_Pos 0 +#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) /**< \brief (MATRIX_PRBS5) Master 8 Priority */ +#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos))) +/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ +#define MATRIX_PRAS6_M0PR_Pos 0 +#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ +#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos))) +#define MATRIX_PRAS6_M1PR_Pos 4 +#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ +#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos))) +#define MATRIX_PRAS6_M2PR_Pos 8 +#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ +#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos))) +#define MATRIX_PRAS6_M3PR_Pos 12 +#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ +#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos))) +#define MATRIX_PRAS6_M4PR_Pos 16 +#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ +#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos))) +#define MATRIX_PRAS6_M5PR_Pos 20 +#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */ +#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos))) +#define MATRIX_PRAS6_M6PR_Pos 24 +#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) /**< \brief (MATRIX_PRAS6) Master 6 Priority */ +#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos))) +/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */ +#define MATRIX_PRBS6_M8PR_Pos 0 +#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) /**< \brief (MATRIX_PRBS6) Master 8 Priority */ +#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos))) +/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ +#define MATRIX_PRAS7_M0PR_Pos 0 +#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ +#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos))) +#define MATRIX_PRAS7_M1PR_Pos 4 +#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ +#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos))) +#define MATRIX_PRAS7_M2PR_Pos 8 +#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ +#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos))) +#define MATRIX_PRAS7_M3PR_Pos 12 +#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ +#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos))) +#define MATRIX_PRAS7_M4PR_Pos 16 +#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ +#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos))) +#define MATRIX_PRAS7_M5PR_Pos 20 +#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */ +#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos))) +#define MATRIX_PRAS7_M6PR_Pos 24 +#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) /**< \brief (MATRIX_PRAS7) Master 6 Priority */ +#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos))) +/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */ +#define MATRIX_PRBS7_M8PR_Pos 0 +#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) /**< \brief (MATRIX_PRBS7) Master 8 Priority */ +#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos))) +/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ +#define MATRIX_PRAS8_M0PR_Pos 0 +#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ +#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos))) +#define MATRIX_PRAS8_M1PR_Pos 4 +#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ +#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos))) +#define MATRIX_PRAS8_M2PR_Pos 8 +#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ +#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos))) +#define MATRIX_PRAS8_M3PR_Pos 12 +#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ +#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos))) +#define MATRIX_PRAS8_M4PR_Pos 16 +#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ +#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos))) +#define MATRIX_PRAS8_M5PR_Pos 20 +#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */ +#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos))) +#define MATRIX_PRAS8_M6PR_Pos 24 +#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) /**< \brief (MATRIX_PRAS8) Master 6 Priority */ +#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos))) +/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */ +#define MATRIX_PRBS8_M8PR_Pos 0 +#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) /**< \brief (MATRIX_PRBS8) Master 8 Priority */ +#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h new file mode 100644 index 0000000000..690fdfe227 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h @@ -0,0 +1,1711 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PIO_COMPONENT_ +#define _SAMS70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMS70_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h new file mode 100644 index 0000000000..37f413b90c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h @@ -0,0 +1,786 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PMC_COMPONENT_ +#define _SAMS70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK0; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __IO uint32_t PMC_PCK1; /**< \brief (Pmc Offset: 0x0044) Programmable Clock 1 Register */ + __IO uint32_t PMC_PCK2; /**< \brief (Pmc Offset: 0x0048) Programmable Clock 2 Register */ + __IO uint32_t PMC_PCK3; /**< \brief (Pmc Offset: 0x004C) Programmable Clock 3 Register */ + __IO uint32_t PMC_PCK4; /**< \brief (Pmc Offset: 0x0050) Programmable Clock 4 Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PMC_PCK6; /**< \brief (Pmc Offset: 0x0058) Programmable Clock 6 Register */ + __I uint32_t Reserved6[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved7[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved8[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved9[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK0 : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK0_CSS_Pos 0 +#define PMC_PCK0_CSS_Msk (0x7u << PMC_PCK0_CSS_Pos) /**< \brief (PMC_PCK0) Master Clock Source Selection */ +#define PMC_PCK0_CSS(value) ((PMC_PCK0_CSS_Msk & ((value) << PMC_PCK0_CSS_Pos))) +#define PMC_PCK0_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK0) Slow Clock is selected */ +#define PMC_PCK0_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK0) Main Clock is selected */ +#define PMC_PCK0_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK0) PLLA Clock is selected */ +#define PMC_PCK0_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK0) Divided UPLL Clock is selected */ +#define PMC_PCK0_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK0) Master Clock is selected */ +#define PMC_PCK0_PRES_Pos 4 +#define PMC_PCK0_PRES_Msk (0xffu << PMC_PCK0_PRES_Pos) /**< \brief (PMC_PCK0) Programmable Clock Prescaler */ +#define PMC_PCK0_PRES(value) ((PMC_PCK0_PRES_Msk & ((value) << PMC_PCK0_PRES_Pos))) +/* -------- PMC_PCK1 : (PMC Offset: 0x0044) Programmable Clock 1 Register -------- */ +#define PMC_PCK1_CSS_Pos 0 +#define PMC_PCK1_CSS_Msk (0x7u << PMC_PCK1_CSS_Pos) /**< \brief (PMC_PCK1) Master Clock Source Selection */ +#define PMC_PCK1_CSS(value) ((PMC_PCK1_CSS_Msk & ((value) << PMC_PCK1_CSS_Pos))) +#define PMC_PCK1_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK1) Slow Clock is selected */ +#define PMC_PCK1_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK1) Main Clock is selected */ +#define PMC_PCK1_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK1) PLLA Clock is selected */ +#define PMC_PCK1_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK1) Divided UPLL Clock is selected */ +#define PMC_PCK1_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK1) Master Clock is selected */ +#define PMC_PCK1_PRES_Pos 4 +#define PMC_PCK1_PRES_Msk (0xffu << PMC_PCK1_PRES_Pos) /**< \brief (PMC_PCK1) Programmable Clock Prescaler */ +#define PMC_PCK1_PRES(value) ((PMC_PCK1_PRES_Msk & ((value) << PMC_PCK1_PRES_Pos))) +/* -------- PMC_PCK2 : (PMC Offset: 0x0048) Programmable Clock 2 Register -------- */ +#define PMC_PCK2_CSS_Pos 0 +#define PMC_PCK2_CSS_Msk (0x7u << PMC_PCK2_CSS_Pos) /**< \brief (PMC_PCK2) Master Clock Source Selection */ +#define PMC_PCK2_CSS(value) ((PMC_PCK2_CSS_Msk & ((value) << PMC_PCK2_CSS_Pos))) +#define PMC_PCK2_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK2) Slow Clock is selected */ +#define PMC_PCK2_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK2) Main Clock is selected */ +#define PMC_PCK2_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK2) PLLA Clock is selected */ +#define PMC_PCK2_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK2) Divided UPLL Clock is selected */ +#define PMC_PCK2_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK2) Master Clock is selected */ +#define PMC_PCK2_PRES_Pos 4 +#define PMC_PCK2_PRES_Msk (0xffu << PMC_PCK2_PRES_Pos) /**< \brief (PMC_PCK2) Programmable Clock Prescaler */ +#define PMC_PCK2_PRES(value) ((PMC_PCK2_PRES_Msk & ((value) << PMC_PCK2_PRES_Pos))) +/* -------- PMC_PCK3 : (PMC Offset: 0x004C) Programmable Clock 3 Register -------- */ +#define PMC_PCK3_CSS_Pos 0 +#define PMC_PCK3_CSS_Msk (0x7u << PMC_PCK3_CSS_Pos) /**< \brief (PMC_PCK3) Master Clock Source Selection */ +#define PMC_PCK3_CSS(value) ((PMC_PCK3_CSS_Msk & ((value) << PMC_PCK3_CSS_Pos))) +#define PMC_PCK3_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK3) Slow Clock is selected */ +#define PMC_PCK3_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK3) Main Clock is selected */ +#define PMC_PCK3_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK3) PLLA Clock is selected */ +#define PMC_PCK3_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK3) Divided UPLL Clock is selected */ +#define PMC_PCK3_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK3) Master Clock is selected */ +#define PMC_PCK3_PRES_Pos 4 +#define PMC_PCK3_PRES_Msk (0xffu << PMC_PCK3_PRES_Pos) /**< \brief (PMC_PCK3) Programmable Clock Prescaler */ +#define PMC_PCK3_PRES(value) ((PMC_PCK3_PRES_Msk & ((value) << PMC_PCK3_PRES_Pos))) +/* -------- PMC_PCK4 : (PMC Offset: 0x0050) Programmable Clock 4 Register -------- */ +#define PMC_PCK4_CSS_Pos 0 +#define PMC_PCK4_CSS_Msk (0x7u << PMC_PCK4_CSS_Pos) /**< \brief (PMC_PCK4) Master Clock Source Selection */ +#define PMC_PCK4_CSS(value) ((PMC_PCK4_CSS_Msk & ((value) << PMC_PCK4_CSS_Pos))) +#define PMC_PCK4_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK4) Slow Clock is selected */ +#define PMC_PCK4_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK4) Main Clock is selected */ +#define PMC_PCK4_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK4) PLLA Clock is selected */ +#define PMC_PCK4_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK4) Divided UPLL Clock is selected */ +#define PMC_PCK4_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK4) Master Clock is selected */ +#define PMC_PCK4_PRES_Pos 4 +#define PMC_PCK4_PRES_Msk (0xffu << PMC_PCK4_PRES_Pos) /**< \brief (PMC_PCK4) Programmable Clock Prescaler */ +#define PMC_PCK4_PRES(value) ((PMC_PCK4_PRES_Msk & ((value) << PMC_PCK4_PRES_Pos))) +/* -------- PMC_PCK6 : (PMC Offset: 0x0058) Programmable Clock 6 Register -------- */ +#define PMC_PCK6_CSS_Pos 0 +#define PMC_PCK6_CSS_Msk (0x7u << PMC_PCK6_CSS_Pos) /**< \brief (PMC_PCK6) Master Clock Source Selection */ +#define PMC_PCK6_CSS(value) ((PMC_PCK6_CSS_Msk & ((value) << PMC_PCK6_CSS_Pos))) +#define PMC_PCK6_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK6) Slow Clock is selected */ +#define PMC_PCK6_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK6) Main Clock is selected */ +#define PMC_PCK6_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK6) PLLA Clock is selected */ +#define PMC_PCK6_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK6) Divided UPLL Clock is selected */ +#define PMC_PCK6_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK6) Master Clock is selected */ +#define PMC_PCK6_PRES_Pos 4 +#define PMC_PCK6_PRES_Msk (0xffu << PMC_PCK6_PRES_Pos) /**< \brief (PMC_PCK6) Programmable Clock Prescaler */ +#define PMC_PCK6_PRES(value) ((PMC_PCK6_PRES_Msk & ((value) << PMC_PCK6_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMS70_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h new file mode 100644 index 0000000000..3cfbfb6ec8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h @@ -0,0 +1,667 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_PWM_COMPONENT_ +#define _SAMS70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief Pwm hardware registers */ +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + __IO uint32_t PWM_CMPV0; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD0; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM0; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD0; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ + __IO uint32_t PWM_CMPV1; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ + __O uint32_t PWM_CMPVUPD1; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ + __IO uint32_t PWM_CMPM1; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ + __O uint32_t PWM_CMPMUPD1; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ + __IO uint32_t PWM_CMPV2; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ + __O uint32_t PWM_CMPVUPD2; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ + __IO uint32_t PWM_CMPM2; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ + __O uint32_t PWM_CMPMUPD2; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ + __IO uint32_t PWM_CMPV3; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ + __O uint32_t PWM_CMPVUPD3; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ + __IO uint32_t PWM_CMPM3; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ + __O uint32_t PWM_CMPMUPD3; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ + __IO uint32_t PWM_CMPV4; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ + __O uint32_t PWM_CMPVUPD4; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ + __IO uint32_t PWM_CMPM4; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ + __O uint32_t PWM_CMPMUPD4; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ + __IO uint32_t PWM_CMPV5; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ + __O uint32_t PWM_CMPVUPD5; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ + __IO uint32_t PWM_CMPM5; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ + __O uint32_t PWM_CMPMUPD5; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ + __IO uint32_t PWM_CMPV6; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ + __O uint32_t PWM_CMPVUPD6; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ + __IO uint32_t PWM_CMPM6; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ + __O uint32_t PWM_CMPMUPD6; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ + __IO uint32_t PWM_CMPV7; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ + __O uint32_t PWM_CMPVUPD7; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ + __IO uint32_t PWM_CMPM7; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ + __O uint32_t PWM_CMPMUPD7; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAMS70_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h new file mode 100644 index 0000000000..5cf18bc84f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_QSPI_COMPONENT_ +#define _SAMS70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h new file mode 100644 index 0000000000..75a8b6cb5e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RSTC_COMPONENT_ +#define _SAMS70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h new file mode 100644 index 0000000000..9f1247b865 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RSWDT_COMPONENT_ +#define _SAMS70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMS70_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h new file mode 100644 index 0000000000..c4829bf588 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RTC_COMPONENT_ +#define _SAMS70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h new file mode 100644 index 0000000000..ac0e7dfb15 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_RTT_COMPONENT_ +#define _SAMS70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMS70_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h new file mode 100644 index 0000000000..03b275a84e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SDRAMC_COMPONENT_ +#define _SAMS70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h new file mode 100644 index 0000000000..a616e3a7b1 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SMC_COMPONENT_ +#define _SAMS70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h new file mode 100644 index 0000000000..f7ac02f0e9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SPI_COMPONENT_ +#define _SAMS70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h new file mode 100644 index 0000000000..2aa87c0f46 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SSC_COMPONENT_ +#define _SAMS70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h new file mode 100644 index 0000000000..9f60ebe2fc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_SUPC_COMPONENT_ +#define _SAMS70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAMS70_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h new file mode 100644 index 0000000000..3a058c97c0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TC_COMPONENT_ +#define _SAMS70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h new file mode 100644 index 0000000000..928092bb36 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TRNG_COMPONENT_ +#define _SAMS70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAMS70_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h new file mode 100644 index 0000000000..a859622c92 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_TWIHS_COMPONENT_ +#define _SAMS70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h new file mode 100644 index 0000000000..d509699140 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_UART_COMPONENT_ +#define _SAMS70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMS70_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h new file mode 100644 index 0000000000..aa666b91d8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usart.h @@ -0,0 +1,478 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_USART_COMPONENT_ +#define _SAMS70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMS70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMS70_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h new file mode 100644 index 0000000000..a9b0a838db --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_usbhs.h @@ -0,0 +1,905 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_USBHS_COMPONENT_ +#define _SAMS70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMS70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ + +/*@}*/ + + +#endif /* _SAMS70_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h new file mode 100644 index 0000000000..b45b124527 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_UTMI_COMPONENT_ +#define _SAMS70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMS70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMS70_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h new file mode 100644 index 0000000000..28750e038e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_WDT_COMPONENT_ +#define _SAMS70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMS70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMS70_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h new file mode 100644 index 0000000000..8a8d5893ff --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/component/component_xdmac.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_XDMAC_COMPONENT_ +#define _SAMS70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMS70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAMS70_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h new file mode 100644 index 0000000000..c4d2927b7f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j19.h @@ -0,0 +1,406 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J19_PIO_ +#define _SAMS70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h new file mode 100644 index 0000000000..0724b32eae --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j20.h @@ -0,0 +1,407 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J20_PIO_ +#define _SAMS70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h new file mode 100644 index 0000000000..ded9233a47 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70j21.h @@ -0,0 +1,407 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J21_PIO_ +#define _SAMS70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h new file mode 100644 index 0000000000..ddb50ac46a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n19.h @@ -0,0 +1,464 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N19_PIO_ +#define _SAMS70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h new file mode 100644 index 0000000000..1f71c5270d --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n20.h @@ -0,0 +1,463 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N20_PIO_ +#define _SAMS70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h new file mode 100644 index 0000000000..9337105295 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70n21.h @@ -0,0 +1,463 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N21_PIO_ +#define _SAMS70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMS70N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h new file mode 100644 index 0000000000..a09aeb8038 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q19.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q19_PIO_ +#define _SAMS70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h new file mode 100644 index 0000000000..21085a77c8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q20.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q20_PIO_ +#define _SAMS70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h new file mode 100644 index 0000000000..f6a8772012 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/pio/pio_sams70q21.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q21_PIO_ +#define _SAMS70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMS70Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70.h new file mode 100644 index 0000000000..19360d766a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70_ +#define _SAMS70_ + +#if defined __SAMS70J19__ + #include "sams70j19.h" +#elif defined __SAMS70J20__ + #include "sams70j20.h" +#elif defined __SAMS70J21__ + #include "sams70j21.h" +#elif defined __SAMS70N19__ + #include "sams70n19.h" +#elif defined __SAMS70N20__ + #include "sams70n20.h" +#elif defined __SAMS70N21__ + #include "sams70n21.h" +#elif defined __SAMS70Q19__ + #include "sams70q19.h" +#elif defined __SAMS70Q20__ + #include "sams70q20.h" +#elif defined __SAMS70Q21__ + #include "sams70q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMS70_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h new file mode 100644 index 0000000000..82e2d7f8e0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J19_ +#define _SAMS70J19_ + +/** \addtogroup SAMS70J19_definitions SAMS70J19 definitions + This file defines all structures and symbols for SAMS70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h new file mode 100644 index 0000000000..e9f40dd5eb --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j20.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J20_ +#define _SAMS70J20_ + +/** \addtogroup SAMS70J20_definitions SAMS70J20 definitions + This file defines all structures and symbols for SAMS70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h new file mode 100644 index 0000000000..db2dbb90a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70j21.h @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70J21_ +#define _SAMS70J21_ + +/** \addtogroup SAMS70J21_definitions SAMS70J21 definitions + This file defines all structures and symbols for SAMS70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70J21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMS70J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h new file mode 100644 index 0000000000..8a810f1619 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N19_ +#define _SAMS70N19_ + +/** \addtogroup SAMS70N19_definitions SAMS70N19 definitions + This file defines all structures and symbols for SAMS70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h new file mode 100644 index 0000000000..f95b970e67 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n20.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N20_ +#define _SAMS70N20_ + +/** \addtogroup SAMS70N20_definitions SAMS70N20 definitions + This file defines all structures and symbols for SAMS70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h new file mode 100644 index 0000000000..61170b4d00 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70n21.h @@ -0,0 +1,616 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70N21_ +#define _SAMS70N21_ + +/** \addtogroup SAMS70N21_definitions SAMS70N21 definitions + This file defines all structures and symbols for SAMS70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMS70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMS70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMS70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70N21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMS70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMS70N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h new file mode 100644 index 0000000000..67d465f8ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q19.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q19_ +#define _SAMS70Q19_ + +/** \addtogroup SAMS70Q19_definitions SAMS70Q19 definitions + This file defines all structures and symbols for SAMS70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q19 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA11D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h new file mode 100644 index 0000000000..46c034cbab --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q20.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q20_ +#define _SAMS70Q20_ + +/** \addtogroup SAMS70Q20_definitions SAMS70Q20 definitions + This file defines all structures and symbols for SAMS70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q20 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h b/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h new file mode 100644 index 0000000000..1528f4139f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h @@ -0,0 +1,664 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMS70Q21_ +#define _SAMS70Q21_ + +/** \addtogroup SAMS70Q21_definitions SAMS70Q21 definitions + This file defines all structures and symbols for SAMS70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMS70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMS70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMS70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMS70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMS70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMS70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMS70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMS70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMS70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMS70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMS70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMS70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMS70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMS70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMS70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMS70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMS70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMS70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMS70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMS70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMS70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMS70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMS70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMS70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMS70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMS70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMS70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMS70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMS70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMS70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMS70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMS70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMS70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMS70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMS70Q21 USB Host / Device Controller (USBHS) */ + AFEC1_IRQn = 40, /**< 40 SAMS70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMS70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMS70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMS70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMS70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMS70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMS70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMS70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMS70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMS70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMS70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMS70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMS70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAMS70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMS70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMS70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMS70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMS70Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMS70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMS70Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pvReserved35; + void* pvReserved36; + void* pvReserved37; + void* pvReserved38; + void* pvReserved39; + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMS70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMS70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMS70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMS70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMS70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMS70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMS70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMS70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMS70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sams70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMS70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sams70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1120E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMS70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMS70Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h b/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h new file mode 100644 index 0000000000..3e74f5c900 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sams70/system_sams70.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMS70_H_INCLUDED +#define SYSTEM_SAMS70_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMS70_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h new file mode 100644 index 0000000000..593effacef --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_acc.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_COMPONENT_ +#define _SAMV71_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t ACC_VER; /**< \brief (Acc Offset: 0xFC) Version Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ +/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */ +#define ACC_VER_VERSION_Pos 0 +#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */ +#define ACC_VER_MFN_Pos 16 +#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h new file mode 100644 index 0000000000..10680b0258 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_aes.h @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_COMPONENT_ +#define _SAMV71_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ + __I uint32_t Reserved2[20]; + __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) +/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */ +#define AES_VERSION_VERSION_Pos 0 +#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */ +#define AES_VERSION_MFN_Pos 16 +#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_AES_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h new file mode 100644 index 0000000000..b514a28b05 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_afec.h @@ -0,0 +1,490 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC_COMPONENT_ +#define _SAMV71_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0x3ffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ +/* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */ +#define AFEC_VERSION_VERSION_Pos 0 +#define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */ +#define AFEC_VERSION_MFN_Pos 16 +#define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_AFEC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h new file mode 100644 index 0000000000..591fead101 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_COMPONENT_ +#define _SAMV71_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMV71_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMV71_CHIPID_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h new file mode 100644 index 0000000000..6f12ae2511 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_dacc.h @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_COMPONENT_ +#define _SAMV71_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t DACC_VERSION; /**< \brief (Dacc Offset: 0xFC) Version Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC Ready Flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC Ready Flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ +/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */ +#define DACC_VERSION_VERSION_Pos 0 +#define DACC_VERSION_VERSION_Msk (0xfffu << DACC_VERSION_VERSION_Pos) /**< \brief (DACC_VERSION) Version */ +#define DACC_VERSION_MFN_Pos 16 +#define DACC_VERSION_MFN_Msk (0x7u << DACC_VERSION_MFN_Pos) /**< \brief (DACC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_DACC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h new file mode 100644 index 0000000000..1b7161d8c8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_efc.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_COMPONENT_ +#define _SAMV71_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_EFC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h new file mode 100644 index 0000000000..fae8b33872 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gmac.h @@ -0,0 +1,1246 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_COMPONENT_ +#define _SAMV71_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[1]; + __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */ + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[2]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[14]; + __IO uint32_t GMAC_TBQBAPQ[2]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[14]; + __IO uint32_t GMAC_RBQBAPQ[2]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[6]; + __IO uint32_t GMAC_RBSRPQ[2]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[5]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[2]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[6]; + __O uint32_t GMAC_IDRPQ[2]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[6]; + __IO uint32_t GMAC_IMRPQ[2]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[38]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */ +#define GMAC_MID_MREV_Pos 0 +#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */ +#define GMAC_MID_MID_Pos 16 +#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAMV71_GMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h new file mode 100644 index 0000000000..8a1af5f2a9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_COMPONENT_ +#define _SAMV71_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GPBR_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h new file mode 100644 index 0000000000..f50b93deed --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_hsmci.h @@ -0,0 +1,342 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_COMPONENT_ +#define _SAMV71_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t HSMCI_VERSION; /**< \brief (Hsmci Offset: 0xFC) Version Register */ + __I uint32_t Reserved4[64]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */ +#define HSMCI_VERSION_VERSION_Pos 0 +#define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos) /**< \brief (HSMCI_VERSION) Hardware Module Version */ +#define HSMCI_VERSION_MFN_Pos 16 +#define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos) /**< \brief (HSMCI_VERSION) Metal Fix Number */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_HSMCI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h new file mode 100644 index 0000000000..b4d9653bb0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_icm.h @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_COMPONENT_ +#define _SAMV71_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ + __I uint32_t Reserved3[37]; + __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */ + __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */ + __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */ + __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) +/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */ +#define ICM_ADDRSIZE_ADDRSIZE_Pos 0 +#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */ +/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */ +#define ICM_IPNAME_IPNAME_Pos 0 +#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */ +/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */ +#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */ +#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */ +#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */ +#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */ +#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */ +#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */ +#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */ +#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */ +#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */ +#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */ +#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */ +#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */ +#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */ +#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */ +#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */ +/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */ +#define ICM_VERSION_VERSION_Pos 0 +#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */ +#define ICM_VERSION_MFN_Pos 16 +#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ICM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h new file mode 100644 index 0000000000..063bfb2c16 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_isi.h @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_COMPONENT_ +#define _SAMV71_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved2[4]; + __I uint32_t ISI_VERSION; /**< \brief (Isi Offset: 0xFC) Version Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ +/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */ +#define ISI_VERSION_VERSION_Pos 0 +#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos) /**< \brief (ISI_VERSION) Version of the Hardware Module */ +#define ISI_VERSION_MFN_Pos 16 +#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos) /**< \brief (ISI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_ISI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h new file mode 100644 index 0000000000..c8ec1289a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_matrix.h @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_COMPONENT_ +#define _SAMV71_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG[12]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved3[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved6[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[12] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[12]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG[12]) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG[12]) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG[12]) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG[12]) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG[12]) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG[12]) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG[12]) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG[12]) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +#define MATRIX_PRAS_M7PR_Pos 28 +#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */ +#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 7 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ +/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */ +#define MATRIX_VERSION_VERSION_Pos 0 +#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */ +#define MATRIX_VERSION_MFN_Pos 16 +#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_MATRIX_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h new file mode 100644 index 0000000000..cc11cd1929 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h @@ -0,0 +1,868 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN_COMPONENT_ +#define _SAMV71_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t MCAN_CREL; /**< \brief (Mcan Offset: 0x00) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< \brief (Mcan Offset: 0x04) Endian Register */ + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved1[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved3[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved5[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */ +#define MCAN_CREL_DAY_Pos 0 +#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */ +#define MCAN_CREL_MON_Pos 8 +#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */ +#define MCAN_CREL_YEAR_Pos 16 +#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */ +#define MCAN_CREL_SUBSTEP_Pos 20 +#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */ +#define MCAN_CREL_STEP_Pos 24 +#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */ +#define MCAN_CREL_REL_Pos 28 +#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */ +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */ +#define MCAN_ENDN_ETV_Pos 0 +#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_BEC (0x1u << 20) /**< \brief (MCAN_IR) Bit Error Corrected */ +#define MCAN_IR_BEU (0x1u << 21) /**< \brief (MCAN_IR) Bit Error Uncorrected */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_BECE (0x1u << 20) /**< \brief (MCAN_IE) Bit Error Corrected Interrupt Enable */ +#define MCAN_IE_BEUE (0x1u << 21) /**< \brief (MCAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_BECL (0x1u << 20) /**< \brief (MCAN_ILS) Bit Error Corrected Interrupt Line */ +#define MCAN_ILS_BEUL (0x1u << 21) /**< \brief (MCAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 4- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MCAN_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h new file mode 100644 index 0000000000..8dbaeab759 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_mlb.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_COMPONENT_ +#define _SAMV71_MLB_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Media LB */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MLB Media LB */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mlb hardware registers */ +typedef struct { + __IO uint32_t MLB_MLBC0; /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t MLB_MS0; /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t MLB_MS1; /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MLB_MSS; /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */ + __I uint32_t MLB_MSD; /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MLB_MIEN; /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t MLB_MLBC1; /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */ + __I uint32_t Reserved6[1]; + __I uint32_t Reserved7[15]; + __IO uint32_t MLB_HCTL; /**< \brief (Mlb Offset: 0x080) HBI Control Register */ + __I uint32_t Reserved8[1]; + __IO uint32_t MLB_HCMR[2]; /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */ + __I uint32_t MLB_HCER[2]; /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */ + __I uint32_t MLB_HCBR[2]; /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */ + __I uint32_t Reserved9[8]; + __IO uint32_t MLB_MDAT[4]; /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */ + __IO uint32_t MLB_MDWE[4]; /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */ + __IO uint32_t MLB_MCTL; /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */ + __IO uint32_t MLB_MADR; /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */ + __I uint32_t Reserved10[182]; + __IO uint32_t MLB_ACTL; /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */ + __I uint32_t Reserved11[3]; + __IO uint32_t MLB_ACSR[2]; /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */ + __IO uint32_t MLB_ACMR[2]; /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */ +} Mlb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */ +#define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */ +#define MLB_MLBC0_MLBCLK_Pos 2 +#define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLBCLK (MediaLB clock) speed select */ +#define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos))) +#define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */ +#define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */ +#define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */ +#define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */ +#define MLB_MLBC0_FCNT_Pos 15 +#define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */ +#define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos))) +#define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ +#define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */ +/* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */ +#define MLB_MS0_MCS_Pos 0 +#define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */ +#define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos))) +/* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */ +#define MLB_MS1_MCS_Pos 0 +#define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */ +#define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos))) +/* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */ +#define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */ +/* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */ +#define MLB_MSD_SD0_Pos 0 +#define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */ +#define MLB_MSD_SD1_Pos 8 +#define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */ +#define MLB_MSD_SD2_Pos 16 +#define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */ +#define MLB_MSD_SD3_Pos 24 +#define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */ +/* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */ +#define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */ +#define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */ +#define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */ +#define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */ +#define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */ +#define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */ +#define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */ +#define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */ +#define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */ +#define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */ +#define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */ +#define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */ +#define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */ +#define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */ +#define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */ +/* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */ +#define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */ +#define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */ +#define MLB_MLBC1_NDA_Pos 8 +#define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */ +#define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos))) +/* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */ +#define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */ +#define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */ +#define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */ +/* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */ +#define MLB_HCMR_CHM_Pos 0 +#define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */ +#define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos))) +/* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */ +#define MLB_HCER_CERR_Pos 0 +#define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */ +/* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */ +#define MLB_HCBR_CHB_Pos 0 +#define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */ +/* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */ +#define MLB_MDAT_DATA_Pos 0 +#define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */ +#define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos))) +/* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */ +#define MLB_MDWE_MASK_Pos 0 +#define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */ +#define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos))) +/* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */ +#define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */ +/* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */ +#define MLB_MADR_ADDR_Pos 0 +#define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */ +#define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos))) +#define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */ +#define MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */ +#define MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */ +#define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */ +/* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */ +#define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */ +#define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */ +#define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */ +#define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */ +#define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */ +#define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */ +/* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */ +#define MLB_ACSR_CHS_Pos 0 +#define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ +#define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos))) +/* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */ +#define MLB_ACMR_CHM_Pos 0 +#define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */ +#define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MLB_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h new file mode 100644 index 0000000000..835f663aa8 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pio.h @@ -0,0 +1,1717 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIO_COMPONENT_ +#define _SAMV71_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[4]; + __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */ + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */ +#define PIO_VERSION_VERSION_Pos 0 +#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */ +#define PIO_VERSION_MFN_Pos 16 +#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMV71_PIO_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h new file mode 100644 index 0000000000..145abd2e94 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pmc.h @@ -0,0 +1,729 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_COMPONENT_ +#define _SAMV71_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */ + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Source Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Clock Source Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */ +#define PMC_VERSION_VERSION_Pos 0 +#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */ +#define PMC_VERSION_MFN_Pos 16 +#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMV71_PMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h new file mode 100644 index 0000000000..a3b40e8020 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_pwm.h @@ -0,0 +1,651 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM_COMPONENT_ +#define _SAMV71_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */ + __I uint32_t Reserved7[12]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved9[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved10[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved12[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved13[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved14[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */ +#define PWM_VERSION_VERSION_Pos 0 +#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */ +#define PWM_VERSION_MFN_Pos 16 +#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAMV71_PWM_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h new file mode 100644 index 0000000000..46e0380e05 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_qspi.h @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_COMPONENT_ +#define _SAMV71_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ +/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */ +#define QSPI_VERSION_VERSION_Pos 0 +#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */ +#define QSPI_VERSION_MFN_Pos 16 +#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_QSPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h new file mode 100644 index 0000000000..0ff4473c32 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_COMPONENT_ +#define _SAMV71_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_RSTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h new file mode 100644 index 0000000000..4c9d146f36 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_COMPONENT_ +#define _SAMV71_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMV71_RSWDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h new file mode 100644 index 0000000000..533e0ed724 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtc.h @@ -0,0 +1,241 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_COMPONENT_ +#define _SAMV71_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */ +#define RTC_VERSION_VERSION_Pos 0 +#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */ +#define RTC_VERSION_MFN_Pos 16 +#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_RTC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h new file mode 100644 index 0000000000..aa49aa3fbd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_COMPONENT_ +#define _SAMV71_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_RTT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h new file mode 100644 index 0000000000..b524a1d438 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_sdramc.h @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_COMPONENT_ +#define _SAMV71_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ + __I uint32_t Reserved2[49]; + __I uint32_t SDRAMC_VERSION; /**< \brief (Sdramc Offset: 0xFC) SDRAMC Version Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) +/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */ +#define SDRAMC_VERSION_VERSION_Pos 0 +#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos) /**< \brief (SDRAMC_VERSION) Version of the Hardware Module */ +#define SDRAMC_VERSION_MFN_Pos 16 +#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos) /**< \brief (SDRAMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SDRAMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h new file mode 100644 index 0000000000..b345c982bc --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_smc.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_COMPONENT_ +#define _SAMV71_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ +/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */ +#define SMC_VERSION_VERSION_Pos 0 +#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */ +#define SMC_VERSION_MFN_Pos 16 +#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SMC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h new file mode 100644 index 0000000000..ed85ef1a60 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_spi.h @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI_COMPONENT_ +#define _SAMV71_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0xFC) Version Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */ +#define SPI_VERSION_VERSION_Pos 0 +#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */ +#define SPI_VERSION_MFN_Pos 16 +#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SPI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h new file mode 100644 index 0000000000..5705d61a8c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_ssc.h @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_COMPONENT_ +#define _SAMV71_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */ +#define SSC_VERSION_VERSION_Pos 0 +#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */ +#define SSC_VERSION_MFN_Pos 16 +#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SSC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h new file mode 100644 index 0000000000..1998c04dde --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_supc.h @@ -0,0 +1,302 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_COMPONENT_ +#define _SAMV71_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ + __I uint32_t Reserved1[57]; + __I uint32_t SYSC_VERSION; /**< \brief (Supc Offset: 0xFC) Version Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +/* -------- SYSC_VERSION : (SUPC Offset: 0xFC) Version Register -------- */ +#define SYSC_VERSION_VERSION_Pos 0 +#define SYSC_VERSION_VERSION_Msk (0xfffu << SYSC_VERSION_VERSION_Pos) /**< \brief (SYSC_VERSION) Version of the Hardware Module */ +#define SYSC_VERSION_MFN_Pos 16 +#define SYSC_VERSION_MFN_Msk (0x7u << SYSC_VERSION_MFN_Pos) /**< \brief (SYSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_SUPC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h new file mode 100644 index 0000000000..7457f031ce --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_tc.h @@ -0,0 +1,353 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC_COMPONENT_ +#define _SAMV71_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION_Pos 0 +#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ +#define TC_VER_MFN_Pos 16 +#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h new file mode 100644 index 0000000000..1892c83a23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_trng.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_COMPONENT_ +#define _SAMV71_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ + __I uint32_t Reserved3[42]; + __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ +/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */ +#define TRNG_VERSION_VERSION_Pos 0 +#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */ +#define TRNG_VERSION_MFN_Pos 16 +#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TRNG_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h new file mode 100644 index 0000000000..f8731a4ad3 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_twihs.h @@ -0,0 +1,264 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS_COMPONENT_ +#define _SAMV71_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[32]; + __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */ +#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */ +#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */ +#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */ +#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */ +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ +/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */ +#define TWIHS_VER_VERSION_Pos 0 +#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */ +#define TWIHS_VER_MFN_Pos 16 +#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_TWIHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h new file mode 100644 index 0000000000..9459816dfb --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_uart.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART_COMPONENT_ +#define _SAMV71_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t UART_VERSION; /**< \brief (Uart Offset: 0x00FC) Version Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */ +#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */ +#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */ +#define UART_VERSION_VERSION_Pos 0 +#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */ +#define UART_VERSION_MFN_Pos 16 +#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_UART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h new file mode 100644 index 0000000000..155c9ee2e0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usart.h @@ -0,0 +1,485 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART_COMPONENT_ +#define _SAMV71_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ +/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAMV71_USART_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h new file mode 100644 index 0000000000..95e34fd3b5 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_usbhs.h @@ -0,0 +1,961 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_COMPONENT_ +#define _SAMV71_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBUS Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBUS Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBUS Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAMV71_USBHS_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h new file mode 100644 index 0000000000..abdde2f148 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_COMPONENT_ +#define _SAMV71_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMV71_UTMI_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h new file mode 100644 index 0000000000..1c6d5b4321 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_COMPONENT_ +#define _SAMV71_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_WDT_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h b/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h new file mode 100644 index 0000000000..a36f4525f0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/component/component_xdmac.h @@ -0,0 +1,625 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_COMPONENT_ +#define _SAMV71_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ + __I uint32_t Reserved2[619]; + __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) +/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */ +#define XDMAC_VERSION_VERSION_Pos 0 +#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */ +#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) +#define XDMAC_VERSION_MFN_Pos 16 +#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */ +#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_XDMAC_COMPONENT_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h new file mode 100644 index 0000000000..c2adb67e71 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j19.h @@ -0,0 +1,441 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_PIO_ +#define _SAMV71J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h new file mode 100644 index 0000000000..311e7f1a48 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j20.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_PIO_ +#define _SAMV71J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h new file mode 100644 index 0000000000..f04d899e72 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71j21.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_PIO_ +#define _SAMV71J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h new file mode 100644 index 0000000000..d8060f8efd --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n19.h @@ -0,0 +1,499 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_PIO_ +#define _SAMV71N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h new file mode 100644 index 0000000000..b8670d4034 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n20.h @@ -0,0 +1,498 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_PIO_ +#define _SAMV71N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h new file mode 100644 index 0000000000..134f9f7e1a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71n21.h @@ -0,0 +1,498 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_PIO_ +#define _SAMV71N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h new file mode 100644 index 0000000000..37925fd3f9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q19.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_PIO_ +#define _SAMV71Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q19_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h new file mode 100644 index 0000000000..fcd68f266f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q20.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_PIO_ +#define _SAMV71Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q20_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h new file mode 100644 index 0000000000..aaa19aad5b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/pio/pio_samv71q21.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_PIO_ +#define _SAMV71Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q21_PIO_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71.h new file mode 100644 index 0000000000..4bdbce555e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ +#define _SAMV71_ + +#ifdef __rtems__ +#include +#endif /* __rtems__ */ +#if defined __SAMV71J19__ + #include "samv71j19.h" +#elif defined __SAMV71J20__ + #include "samv71j20.h" +#elif defined __SAMV71J21__ + #include "samv71j21.h" +#elif defined __SAMV71N19__ + #include "samv71n19.h" +#elif defined __SAMV71N20__ + #include "samv71n20.h" +#elif defined __SAMV71N21__ + #include "samv71n21.h" +#elif defined __SAMV71Q19__ + #include "samv71q19.h" +#elif defined __SAMV71Q20__ + #include "samv71q20.h" +#elif defined __SAMV71Q21__ + #include "samv71q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMV71_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h new file mode 100644 index 0000000000..ad3c38f6ab --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j19.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_ +#define _SAMV71J19_ + +/** \addtogroup SAMV71J19_definitions SAMV71J19 definitions + This file defines all structures and symbols for SAMV71J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h new file mode 100644 index 0000000000..9df556c9f0 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j20.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_ +#define _SAMV71J20_ + +/** \addtogroup SAMV71J20_definitions SAMV71J20 definitions + This file defines all structures and symbols for SAMV71J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h new file mode 100644 index 0000000000..4c306b8e23 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71j21.h @@ -0,0 +1,637 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_ +#define _SAMV71J21_ + +/** \addtogroup SAMV71J21_definitions SAMV71J21 definitions + This file defines all structures and symbols for SAMV71J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h new file mode 100644 index 0000000000..8f2c0b9731 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n19.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_ +#define _SAMV71N19_ + +/** \addtogroup SAMV71N19_definitions SAMV71N19 definitions + This file defines all structures and symbols for SAMV71N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h new file mode 100644 index 0000000000..e709e5f736 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_ +#define _SAMV71N20_ + +/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions + This file defines all structures and symbols for SAMV71N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h new file mode 100644 index 0000000000..dc1ef6e8a2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71n21.h @@ -0,0 +1,643 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_ +#define _SAMV71N21_ + +/** \addtogroup SAMV71N21_definitions SAMV71N21 definitions + This file defines all structures and symbols for SAMV71N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N21 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N21 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h new file mode 100644 index 0000000000..e42381c63c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q19.h @@ -0,0 +1,691 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_ +#define _SAMV71Q19_ + +/** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions + This file defines all structures and symbols for SAMV71Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q19 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q19 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q19_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h new file mode 100644 index 0000000000..cfc1780b56 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q20.h @@ -0,0 +1,691 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_ +#define _SAMV71Q20_ + +/** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions + This file defines all structures and symbols for SAMV71Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q20 MCAN Controller 0 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q20 MCAN Controller 1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pvReserved36; + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q20_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h b/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h new file mode 100644 index 0000000000..401ee9b8be --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/samv71q21.h @@ -0,0 +1,696 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_ +#define _SAMV71Q21_ + +/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions + This file defines all structures and symbols for SAMV71Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +#ifndef __rtems__ +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ +#endif /* __rtems__ */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (120000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q21_ */ diff --git a/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h b/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h new file mode 100644 index 0000000000..f38282d233 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/samv71/system_samv71.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMV71_H_INCLUDED +#define SYSTEM_SAMV71_H_INCLUDED +#ifdef __rtems__ +#include +#endif /* __rtems__ */ + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +#ifndef __rtems__ +void SystemInit(void); +#else /* __rtems__ */ +void ATSAM_START_SRAM_SECTION SystemInit(void); +#endif /* __rtems__ */ + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMV71_H_INCLUDED */ diff --git a/bsps/arm/atsam/include/libchip/include/sdramc.h b/bsps/arm/atsam/include/libchip/include/sdramc.h new file mode 100644 index 0000000000..078127fbe9 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/sdramc.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Definitions and function prototype for SDRAMC. + */ + +// --------------------------------------------------------------------------- +// SDRAM +// --------------------------------------------------------------------------- +/** SDRAMC Configuration */ +#define EBI_SDRAMC_ADDR (0x70000000u) + +/** SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + + +typedef struct _SSdramc_config { + uint32_t dwColumnBits; // Number of Column Bits + uint32_t dwRowBits; // Number of Row Bits + uint32_t dwBanks; // Number of Banks + uint32_t dwCAS; // CAS Latency + uint32_t dwDataBusWidth; // Data Bus Width + uint32_t dwWriteRecoveryDelay; // Write Recovery Delay + uint32_t dwRowCycleDelay_RowRefreshCycle; // Row Cycle Delay and Row Refresh Cycle + uint32_t dwRowPrechargeDelay; // Row Precharge Delay + uint32_t dwRowColumnDelay; // Row to Column Delay + uint32_t dwActivePrechargeDelay; // Active to Precharge Delay + uint32_t dwExitSelfRefreshActiveDelay; // Exit Self Refresh to Active Delay + uint32_t dwBK1; // bk1 addr + +} SSdramc_config; + +typedef struct _SSdramc_Memory { + SSdramc_config cfg; + +} SSdramc_Memory; + +extern void SDRAMC_Configure(SSdramc_Memory *pMemory, + uint32_t dwClockFrequency); diff --git a/bsps/arm/atsam/include/libchip/include/smc.h b/bsps/arm/atsam/include/libchip/include/smc.h new file mode 100644 index 0000000000..72253ab38a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/smc.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** +* \file +* +* Definitions and function prototype for SMC module +*/ + +#ifndef _SMC_ +#define _SMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef union _SmcStatus { + uint8_t BStatus; + struct _SmcStatusBits { + uint8_t smcSts: 1, /**< NAND Flash Controller Status */ + xfrDone: 1, /**< NFC Data Transfer Terminated */ + cmdDone: 1, /**< Command Done */ + rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/ + hammingReady: 1; /**< Hamming ecc ready */ + } bStatus; +} SmcStatus; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* + * NFC definitions + */ + +/** Base address of NFC SRAM */ +#define NFC_SRAM_BASE_ADDRESS 0x200000 +/** Base address for NFC Address Command */ +#define NFC_CMD_BASE_ADDR 0x70000000 + + +/* -------- NFCADDR_CMD : NFC Address Command -------- */ +#define NFCADDR_CMD_CMD1 (0xFFu << 2) +/* Command Register Value for Cycle 1 */ +#define NFCADDR_CMD_CMD2 (0xFFu << 10) +/* Command Register Value for Cycle 2 */ +#define NFCADDR_CMD_VCMD2 (0x1u << 18) +/* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7u << 19) +/* Number of Address required for the current command */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) +/* No address cycle */ +#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) +/* One address cycle */ +#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) +/* Two address cycles */ +#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) +/* Three address cycles */ +#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) +/* Four address cycles */ +#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) +/* Five address cycles */ +#define NFCADDR_CMD_CSID (0x7u << 22) +/* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0u << 22) +/* CS0 */ +#define NFCADDR_CMD_CSID_1 (0x1u << 22) +/* CS1 */ +#define NFCADDR_CMD_CSID_2 (0x2u << 22) +/* CS2 */ +#define NFCADDR_CMD_CSID_3 (0x3u << 22) +/* CS3 */ +#define NFCADDR_CMD_CSID_4 (0x4u << 22) +/* CS4 */ +#define NFCADDR_CMD_CSID_5 (0x5u << 22) +/* CS5 */ +#define NFCADDR_CMD_CSID_6 (0x6u << 22) +/* CS6 */ +#define NFCADDR_CMD_CSID_7 (0x7u << 22) +/* CS7 */ +#define NFCADDR_CMD_DATAEN (0x1u << 25) +/* NFC Data Enable */ +#define NFCADDR_CMD_DATADIS (0x0u << 25) +/* NFC Data disable */ +#define NFCADDR_CMD_NFCRD (0x0u << 26) +/* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1u << 26) +/* NFC Write Enable */ +#define NFCADDR_CMD_NFCCMD (0x1u << 27) +/* NFC Command Enable */ + +/* + * ECC definitions (Hsiao Code Errors) + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hsiao_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hsiao_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hsiao_ERROR_MULTIPLEBITS 3 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* + * NFC functions + */ + +extern void SMC_NFC_Configure(uint32_t mode); +extern void SMC_NFC_Reset(void); +extern void SMC_NFC_EnableNfc(void); +extern void SMC_NFC_EnableSpareRead(void); +extern void SMC_NFC_DisableSpareRead(void); +extern void SMC_NFC_EnableSpareWrite(void); +extern void SMC_NFC_DisableSpareWrite(void); +extern uint8_t SMC_NFC_isSpareRead(void); +extern uint8_t SMC_NFC_isSpareWrite(void); +extern uint8_t SMC_NFC_isTransferComplete(void); +extern uint8_t SMC_NFC_isReadyBusy(void); +extern uint8_t SMC_NFC_isNfcBusy(void); +extern uint32_t SMC_NFC_GetStatus(void); + +extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, + uint32_t cycle0); +extern void SMC_NFC_Wait_CommandDone(void); +extern void SMC_NFC_Wait_XfrDone(void); +extern void SMC_NFC_Wait_RBbusy(void); +extern void SMC_NFC_Wait_HammingReady(void); + +extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize); +extern uint32_t SMC_ECC_GetCorrectoinType(void); +extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber); + +extern void SMC_ECC_GetValue(uint32_t *ecc); +extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, + uint8_t busWidth); +extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, + const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth); + +#endif /* #ifndef _SMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/spi.h b/bsps/arm/atsam/include/libchip/include/spi.h new file mode 100644 index 0000000000..0d888fbdfa --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/spi.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _SPI_ +#define _SPI_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section spi_configuration_macros SPI Configuration Macros + * - \ref SPI_PCS + * - \ref SPI_SCBR + * - \ref SPI_DLYBS + * - \ref SPI_DLYBCT + */ + +/** Calculate the PCS field value given the chip select NPCS value */ +#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF)) + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define SPI_SCBR(baudrate, masterClock) \ + SPI_CSR_SCBR((uint32_t)(masterClock / baudrate)) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define SPI_DLYBS(delay, masterClock) \ + SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define SPI_DLYBCT(delay, masterClock) \ + SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1) + +/*------------------------------------------------------------------------------ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void SPI_Enable(Spi *spi); +extern void SPI_Disable(Spi *spi); + +extern void SPI_EnableIt(Spi *spi, uint32_t dwSources); +extern void SPI_DisableIt(Spi *spi, uint32_t dwSources); + +extern void SPI_Configure(Spi *spi, uint32_t dwId, uint32_t dwConfiguration); +extern void SPI_SetMode(Spi *spi, uint32_t dwConfiguration); + +extern void SPI_ChipSelect(Spi *spi, uint8_t cS); +extern void SPI_ReleaseCS(Spi *spi); + +extern void SPI_ConfigureNPCS(Spi *spi, uint32_t dwNpcs, + uint32_t dwConfiguration); +extern void SPI_ConfigureCSMode(Spi *spi, uint32_t dwNpcs, + uint32_t bReleaseOnLast); + +extern uint32_t SPI_Read(Spi *spi); +extern void SPI_Write(Spi *spi, uint32_t dwNpcs, uint16_t wData); +extern void SPI_WriteLast(Spi *spi, uint32_t dwNpcs, uint16_t wData); + +extern uint32_t SPI_GetStatus(Spi *spi); +extern uint32_t SPI_IsFinished(Spi *pSpi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/spi_dma.h b/bsps/arm/atsam/include/libchip/include/spi_dma.h new file mode 100644 index 0000000000..72a77d512c --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/spi_dma.h @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef _SPI_DMA_ +#define _SPI_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define SPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define SPID_ERROR_LOCK 2 + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** Calculates the value of the SCBR field of the Chip Select Register + given MCK and SPCK.*/ +#define SPID_CSR_SCBR(mck, spck) SPI_CSR_SCBR((mck) / (spck)) + +/** Calculates the value of the DLYBS field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBS(mck, delay) SPI_CSR_DLYBS((((delay) * \ + ((mck) / 1000000)) / 1000) + 1) + +/** Calculates the value of the DLYBCT field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBCT(mck, delay) SPI_CSR_DLYBCT((((delay) / 32 * \ + ((mck) / 1000000)) / 1000) + 1) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*SpidCallback)(uint8_t, void *); + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the SPI_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpidCmd { + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint8_t TxSize; + /** Pointer to the Rx data. */ + uint8_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** SPI chip select. */ + uint8_t spiCs; + /** Callback function invoked at the end of transfer. */ + SpidCallback callback; + /** Callback arguments. */ + void *pArgument; +} SpidCmd; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Spid { + /** Pointer to SPI Hardware registers */ + Spi *pSpiHw; + /** Current SpiCommand being processed */ + SpidCmd *pCurrentCommand; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore; +} Spid; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t SPID_Configure(Spid *pSpid, + Spi *pSpiHw, + uint8_t spiId, + uint32_t SpiMode, + sXdmad *pXdmad); + +extern void SPID_ConfigureCS(Spid *pSpid, uint32_t dwCS, uint32_t dwCsr); + +extern uint32_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand); + +extern void SPID_Handler(Spid *pSpid); + +extern void SPID_DmaHandler(Spid *pSpid); + +extern uint32_t SPID_IsBusy(const Spid *pSpid); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/ssc.h b/bsps/arm/atsam/include/libchip/include/ssc.h new file mode 100644 index 0000000000..bf76d6d2de --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/ssc.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _SSC_ +#define _SSC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); +extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); +extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); +extern void SSC_EnableTransmitter(Ssc *ssc); +extern void SSC_DisableTransmitter(Ssc *ssc); +extern void SSC_EnableReceiver(Ssc *ssc); +extern void SSC_DisableReceiver(Ssc *ssc); +extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_Write(Ssc *ssc, uint32_t frame); +extern uint32_t SSC_Read(Ssc *ssc); +extern uint8_t SSC_IsRxReady(Ssc *ssc); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SSC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/supc.h b/bsps/arm/atsam/include/libchip/include/supc.h new file mode 100644 index 0000000000..65d556372b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/supc.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SUPC_H_ +#define _SUPC_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + + + +void SUPC_SelectExtCrystal32K(void); +uint8_t SUPC_IsSlowClkExtCrystal32K(void); +uint8_t SUPC_Read_Status(uint32_t status); +void SUPC_DisableSupplyMonitor(void); +void SUPC_DisableVoltageReg(void); +void SUPC_ConfigSupplyMonitor(uint32_t Config); +void SUPC_BrownoutDetectEnable(uint8_t enable); +void SUPC_BrownoutResetEnable(void); +void SUPC_SramBackupMode(uint8_t enable); +void SUPC_BypassXtal32KOsc(void); +void SUPC_EnablesWakeupInput(uint32_t Input, uint8_t enable); +void SUPC_SetLowPowerDebounce(uint8_t period); +void SUPC_SetWakeupDebounce(uint8_t period); +void SUPC_EnablesWakeupMode(uint32_t Regs, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/tc.h b/bsps/arm/atsam/include/libchip/include/tc.h new file mode 100644 index 0000000000..2136634475 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/tc.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _TC_ +#define _TC_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void TC_Configure(Tc *pTc, uint32_t dwChannel, uint32_t dwMode); + +extern void TC_Start(Tc *pTc, uint32_t dwChannel); + +extern void TC_Stop(Tc *pTc, uint32_t dwChannel); + +extern uint32_t TC_FindMckDivisor(uint32_t dwFreq, uint32_t dwMCk, + uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TC_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/timetick.h b/bsps/arm/atsam/include/libchip/include/timetick.h new file mode 100644 index 0000000000..ac12a8b25a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/timetick.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Methods and definitions for Global time tick and wait functions. + * + * Defines a common and simplest use of Time Tick, to increase tickCount + * every 1ms, the application can get this value through GetTickCount(). + * + * \par Usage + * + * -# Configure the System Tick with TimeTick_Configure() when MCK changed + * \note + * Must be done before any invoke of GetTickCount(), Wait() or Sleep(). + * -# Uses GetTickCount to get current tick value. + * -# Uses Wait to wait several ms. + * -# Uses Sleep to enter wait for interrupt mode to wait several ms. + * + */ + +#ifndef _TIMETICK_ +#define _TIMETICK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +typedef struct { + volatile uint32_t *pTimer1; + volatile uint32_t *pTimer2; + volatile uint32_t *pTimer3; + volatile uint32_t *pTimer4; +} SyTickDelayCounter_t; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +typedef struct _TimeEvent { + uint32_t event; + uint32_t time_tick; + uint32_t time_start; + uint32_t occur; + struct _TimeEvent *pPreEvent; + struct _TimeEvent *pNextEvent; +} TimeEvent; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +uint32_t TimeTick_Configure(void); + +void TimeTick_Increment(uint32_t dwInc); + +uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick); + +uint32_t GetTicks(void); + +void Wait(volatile uint32_t dwMs); + +void Sleep(volatile uint32_t dwMs); + +extern void SetTimeEvent(TimeEvent *pEvent); + +#endif /* _TIMETICK_ */ diff --git a/bsps/arm/atsam/include/libchip/include/trace.h b/bsps/arm/atsam/include/libchip/include/trace.h new file mode 100644 index 0000000000..95a613f69a --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/trace.h @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +#include "pio.h" + +#include + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.5" + + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) + #define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) + #define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) + #error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE(uint32_t dwBaudRate, uint32_t dwMCk); + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE + #define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsUART0[] = {PINS_UART}; \ + PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \ + UART_Configure(baudrate, mck); \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + + /* Empty macro */ + #define TRACE_DEBUG(...) { } + #define TRACE_INFO(...) { } + #define TRACE_WARNING(...) { } + #define TRACE_ERROR(...) { } + #define TRACE_FATAL(...) { while (1); } + + #define TRACE_DEBUG_WP(...) { } + #define TRACE_INFO_WP(...) { } + #define TRACE_WARNING_WP(...) { } + #define TRACE_ERROR_WP(...) { } + #define TRACE_FATAL_WP(...) { while (1); } + +#elif (DYN_TRACES == 1) + + /* Trace output depends on dwTraceLevel value */ + #define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } + #define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } + #define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } + #define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } + #define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while (1); } } + + #define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } + #define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } + #define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } + #define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } + #define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while (1); } } + +#else + + /* Trace compilation depends on TRACE_LEVEL value */ + #if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) + #define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } + #define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_DEBUG(...) { } + #define TRACE_DEBUG_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_INFO) + #define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } + #define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_INFO(...) { } + #define TRACE_INFO_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) + #define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } + #define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_WARNING(...) { } + #define TRACE_WARNING_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) + #define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } + #define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } + #else + #define TRACE_ERROR(...) { } + #define TRACE_ERROR_WP(...) { } + #endif + + #if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) + #define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while (1); } + #define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while (1); } + #else + #define TRACE_FATAL(...) { while (1); } + #define TRACE_FATAL_WP(...) { while (1); } + #endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifiable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel; +#endif + +#endif //#ifndef TRACE_H + diff --git a/bsps/arm/atsam/include/libchip/include/trng.h b/bsps/arm/atsam/include/libchip/include/trng.h new file mode 100644 index 0000000000..29b28314c6 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TRNG_ +#define _TRNG_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +void TRNG_Enable(void); +void TRNG_Disable(void); +void TRNG_EnableIt(void); +void TRNG_DisableIt(void); +uint32_t TRNG_GetStatus(void); +uint32_t TRNG_GetRandData(void); + +#endif /* #ifndef _TRNG_ */ diff --git a/bsps/arm/atsam/include/libchip/include/twi.h b/bsps/arm/atsam/include/libchip/include/twi.h new file mode 100644 index 0000000000..6a5de366f2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/twi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Interface for configuration the Two Wire Interface (TWI) peripheral. + * + */ + +#ifndef _TWI_ +#define _TWI_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ +/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given + status register value.*/ +#define TWI_STATUS_TXRDY(status) ((status & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY) + +/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given + status register value.*/ +#define TWI_STATUS_RXRDY(status) ((status & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY) + +/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given + status register value.*/ +#define TWI_STATUS_TXCOMP(status) ((status & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP) + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * External function + *----------------------------------------------------------------------------*/ + +extern void TWI_ConfigureMaster(Twihs *pTwi, uint32_t twck, uint32_t mck); + +extern void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress); + +extern void TWI_Stop(Twihs *pTwi); + +extern void TWI_StartRead( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize); + +extern uint8_t TWI_ReadByte(Twihs *pTwi); + +extern void TWI_WriteByte(Twihs *pTwi, uint8_t byte); + +extern void TWI_StartWrite( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte); + +extern uint8_t TWI_ByteReceived(Twihs *pTwi); + +extern uint8_t TWI_ByteSent(Twihs *pTwi); + +extern uint8_t TWI_TransferComplete(Twihs *pTwi); + +extern void TWI_EnableIt(Twihs *pTwi, uint32_t sources); + +extern void TWI_DisableIt(Twihs *pTwi, uint32_t sources); + +extern uint32_t TWI_GetStatus(Twihs *pTwi); + +extern uint32_t TWI_GetMaskedStatus(Twihs *pTwi); + +extern void TWI_SendSTOPCondition(Twihs *pTwi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TWI_ */ diff --git a/bsps/arm/atsam/include/libchip/include/twid.h b/bsps/arm/atsam/include/libchip/include/twid.h new file mode 100644 index 0000000000..564a93339f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/twid.h @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _TWID_ +#define _TWID_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/** TWI driver is currently busy. */ +#define TWID_ERROR_BUSY 1 + +/** Transfer is still pending.*/ +#define ASYNC_STATUS_PENDING 0xFF +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- +* Type +*----------------------------------------------------------------------------*/ +/** \brief Asynchronous transfer descriptor. */ +typedef struct _Async { + /** Asynchronous transfer status.*/ + volatile uint32_t status; + /** Callback function to invoke when transfer completes or fails.*/ + void *callback; + /** Driver storage area; do not use.*/ + uint8_t pStorage[9]; +} Async; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct _Twid { + /** Pointer to the underlying TWI peripheral.*/ + Twihs *pTwi; + /** Current asynchronous transfer being processed.*/ + Async *pTransfer; +} Twid; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct { + uint8_t Twi_id; + /** Pointer to the underlying TWI driver.*/ + Twid *pTwid; + /** Pointer to the underlying DMA driver for TWI.*/ + sXdmad *pTwiDma; +} TwihsDma; + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +extern void TWID_Initialize(Twid *pTwid, Twihs *pTwi); +extern void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, + uint8_t bPolling); + +extern void TWID_Handler(Twid *pTwid); + +extern uint32_t ASYNC_IsFinished(Async *pAsync); + +extern uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaRead( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaWrite( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef TWID_H + diff --git a/bsps/arm/atsam/include/libchip/include/uart.h b/bsps/arm/atsam/include/libchip/include/uart.h new file mode 100644 index 0000000000..4380856285 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/uart.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef UART_H +#define UART_H + + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +void UART_Configure(Uart *uart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled); + +void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled); + +void UART_PutChar(Uart *uart, uint8_t c); + +uint32_t UART_IsRxReady(Uart *uart); + +uint8_t UART_GetChar(Uart *uart); + +uint32_t UART_GetStatus(Uart *uart); + +void UART_EnableIt(Uart *uart, uint32_t mode); + +void UART_DisableIt(Uart *uart, uint32_t mode); + +uint32_t UART_GetItMask(Uart *uart); + +void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2); + +uint32_t UART_IsTxReady(Uart *uart); + +#endif //#ifndef UART_H + diff --git a/bsps/arm/atsam/include/libchip/include/uart_dma.h b/bsps/arm/atsam/include/libchip/include/uart_dma.h new file mode 100644 index 0000000000..8329b6b930 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/uart_dma.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of UART driver, transfer data through DMA. + * + */ + +#ifndef _UART_DMA_ +#define _UART_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define UARTD_ERROR 1 + +/** UART driver is currently in use.*/ +#define UARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** UART transfer complete callback. */ +typedef void (*UartdCallback)(uint8_t, void *); + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the UART_Send or UART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint32_t ChNum; + /** Callback function invoked at the end of transfer. */ + UartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer. */ + volatile uint8_t sempaphore; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size */ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UartChannel; + +/** Constant structure associated with UART port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** USART Id as defined in the product datasheet */ + uint8_t uartId; + /** Pointer to DMA driver */ + sXdmad *pXdmad; + /** Pointer to UART Hardware registers */ + Uart *pUartHw; + /** Current Uart Rx channel */ + UartChannel *pRxChannel; + /** Current Uart Tx channel */ + UartChannel *pTxChannel; +} UartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t UARTD_Configure(UartDma *pUartd , + uint8_t uartId, + uint32_t uartMode, + uint32_t baud, + uint32_t clk); + +uint32_t UARTD_EnableTxChannels(UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_EnableRxChannels(UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_DisableTxChannels(UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_DisableRxChannels(UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_SendData(UartDma *pUartd); + +uint32_t UARTD_RcvData(UartDma *pUartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _UART_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/usart.h b/bsps/arm/atsam/include/libchip/include/usart.h new file mode 100644 index 0000000000..a1d1c378af --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usart.h @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \par Purpose + * + * This module provides several definitions and methods for using an USART + * peripheral. + * + * \par Usage + * + * -# Enable the USART peripheral clock in the PMC. + * -# Enable the required USART PIOs (see pio.h). + * -# Configure the UART by calling USART_Configure. + * -# Enable the transmitter and/or the receiver of the USART using + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + * -# Send data through the USART using the USART_Write methods. + * -# Receive data from the USART using the USART_Read functions; the + * availability of data can be polled + * with USART_IsDataAvailable. + * -# Disable the transmitter and/or the receiver of the USART with + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + */ + +#ifndef _USART_ +#define _USART_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \section USART_mode USART modes + * This section lists several common operating modes for an USART peripheral. + * + * \b Modes + * - USART_MODE_ASYNCHRONOUS + * - USART_MODE_IRDA + */ + +/** Basic asynchronous mode, i.e. 8 bits no parity.*/ +#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO) + +#define MAX_RX_TIMEOUT 131071 + +/** IRDA mode*/ +#define USART_MODE_IRDA \ + (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER) + +/** SPI mode*/ +#define AT91C_US_USMODE_SPIM 0xE +#define US_SPI_CPOL_0 (0x0<<16) +#define US_SPI_CPHA_0 (0x0<<8) +#define US_SPI_CPOL_1 (0x1<<16) +#define US_SPI_CPHA_1 (0x1<<8) +#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1) +#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0) +#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1) +#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0) + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + + +void USART_Configure(Usart *pUsart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void USART_SetBaudrate(Usart *pUsart, uint8_t OverSamp, uint32_t baudrate, + uint32_t masterClock); + +uint32_t USART_GetStatus(Usart *usart); + + +void USART_ResetRx(Usart *pUsart); + +void USART_ResetTx(Usart *pUsart); + +void USART_EnableTx(Usart *pUsart); + +void USART_EnableRx(Usart *pUsart); + +void USART_DisableRx(Usart *pUsart); + +void USART_DisableTx(Usart *pUsart); + +void USART_EnableIt(Usart *usart, uint32_t mode); + +void USART_DisableIt(Usart *usart, uint32_t mode); + +uint32_t USART_GetItMask(Usart *usart); + +void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled); + +void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled); + +void USART_SetRTSEnabled(Usart *usart, uint8_t enabled); + +void USART_Write(Usart *usart, uint16_t data, volatile uint32_t timeOut); + +uint16_t USART_Read(Usart *usart, volatile uint32_t timeOut); + +uint8_t USART_IsDataAvailable(Usart *usart); + +void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); + +void USART_PutChar(Usart *usart, uint8_t c); + +uint32_t USART_IsRxReady(Usart *usart); + +uint8_t USART_GetChar(Usart *usart); + +void USART_EnableRecvTimeOut(Usart *usart, uint32_t timeout); + +void USART_EnableTxTimeGaurd(Usart *pUsart, uint32_t TimeGaurd); + +void USART_AcknowledgeRxTimeOut(Usart *usart, uint8_t Periodic); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/usart_dma.h b/bsps/arm/atsam/include/libchip/include/usart_dma.h new file mode 100644 index 0000000000..0329cd1818 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usart_dma.h @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * Implementation of USART driver, transfer data through DMA. + * + */ + +#ifndef _USART_DMA_H_ +#define _USART_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define USARTD_ERROR 1 + +/** USART driver is currently in use.*/ +#define USARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** USART transfer complete callback. */ +typedef void (*UsartdCallback)(uint8_t, void *); + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the USART_Send or USART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct { + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint8_t ChNum; + /** Callback function invoked at the end of transfer. */ + UsartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer progress */ + volatile uint8_t dmaProgress; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size or num of micro block*/ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UsartChannel; + +/** Constant structure associated with USART port. This structure prevents + client applications to have access in the same time. */ +typedef struct { + /** USART Id as defined in the product datasheet */ + uint8_t usartId; + /** Pointer to USART Hardware registers */ + Usart *pUsartHw; + /** Current Usart Rx channel */ + UsartChannel *pRxChannel; + /** Current Usart Tx channel */ + UsartChannel *pTxChannel; + /** Pointer to DMA driver */ + sXdmad *pXdmad; +} UsartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t USARTD_Configure(UsartDma *pUsartd , + uint8_t USARTId, + uint32_t UsartMode, + uint32_t BaudRate, + uint32_t UsartClk); + +uint32_t USARTD_EnableTxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_EnableRxChannels(UsartDma *pUsartd, UsartChannel *pRxCh); + +uint32_t USARTD_DisableTxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_DisableRxChannels(UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_SendData(UsartDma *pUsartd); + +uint32_t USARTD_RcvData(UsartDma *pUsartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_DMA_ */ diff --git a/bsps/arm/atsam/include/libchip/include/usbhs.h b/bsps/arm/atsam/include/libchip/include/usbhs.h new file mode 100644 index 0000000000..e30e15b313 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/usbhs.h @@ -0,0 +1,1699 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +#ifndef USBHS_H +#define USBHS_H +/** addtogroup usbd_hal + *@{ + */ + +#define USB_DEVICE_HS_SUPPORT + +//! Control endpoint size +#define USB_DEVICE_EP_CTRL_SIZE 64 + +/** Indicates chip has an UDP High Speed. */ +#define CHIP_USB_UDP + +/** Indicates chip has an internal pull-up. */ +#define CHIP_USB_PULLUP_INTERNAL + +/** Number of USB endpoints */ +#define CHIP_USB_NUMENDPOINTS 10 + +/** Endpoints max packet size */ +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 8192 + + +//! @name USBHS Host IP properties +//! +//! @{ +//! Get maximal number of endpoints +#define uhd_get_pipe_max_nbr() (9) +#define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1) +//! Get maximal number of banks of endpoints +#define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : ((ep <= 2) ? 3 : 2)) +//! Get maximal size of endpoint (3X, 1024/64) +#define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024) +//! Get DMA support of endpoints +#define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 7)) ? true : false) +//! Get High Band Width support of endpoints +#define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false) +//! @} + +typedef enum { + HOST_MODE = 0, + DEVICE_MODE = 1 +} USB_Mode_t; + +//! Maximum transfer size on USB DMA +#define UHD_PIPE_MAX_TRANS 0x8000 + +/** +================================= + USBHS_CTRL +================================= +**/ + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK; +} + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK); +} +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable) +{ + + if (!Enable) + pUsbhs->USBHS_CTRL |= (1 << 8); + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)(1 << 8)); +} + +/** + * \brief Enables or disables USB + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ + +__STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE; + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE); +} + + +/** + * \brief Device or Host Mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Mode Device or Host Mode + */ + +__STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode) +{ + if (Mode) + pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE; + else + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE); +} + +/********************* USBHS_SR *****************/ + +/** + * \brief Check if clock is usable or not + * \param pUsbhs Pointer to an USBHS instance. + * \return 1 if USB clock is usable + */ + +__STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14); +} + + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \return USB status + */ + +__STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_SR); +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk)); +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? + true : false; +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? + true : false; +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? + true : false; +} +/********************* USBHS_SCR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param AckType Interrupt Acknowledge type + */ + +__STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType) +{ + pUsbhs->USBHS_SCR |= AckType; +} + +/********************* USBHS_SFR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus) +{ + pUsbhs->USBHS_SFR |= SetStatus; +} + + +/*-------------------------------------------------------- +* =========== USB Device functions ====================== +*---------------------------------------------------------*/ + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN); +} + +/** + * \brief Configure USB address and enable or disable it + * \param pUsbhs Pointer to an USBHS instance. + * \param Addr USB device status + */ + +__STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr); + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; +} + +/** + * \brief Get USB address + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk); +} + +/** + * \brief Attach or detach USB. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Attachs or detach USB device + */ + +__STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH); + +} + +/** + * \brief Force Low Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables the Full speed + */ + +__STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS; + else + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS); +} + +/** + * \brief Disable/Enables High Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + uint32_t cfg = pUsbhs->USBHS_DEVCTRL; + cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk); + + if (Enable) + pUsbhs->USBHS_DEVCTRL |= cfg; + else + pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS); + +} + +/** + * \brief Set Remote WakeUp mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP; +} + +/** + * \brief Disable/Enables Test mode + * \param pUsbhs Pointer to an USBHS instance. + * \param mode Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode) +{ + pUsbhs->USBHS_DEVCTRL |= mode; +} + + +/** + * \brief Disable/Enables HS Test mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED; +} + +/** + * \brief Read status for an interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt type + */ + +__STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVISR & IntType); +} + +/** + * \brief Read status for an Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint + */ + +__STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_PEP_0 << EpNum)); +} + +/** + * \brief Read status for a DMA Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum DMA Endpoint + */ +__STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_DMA_1 << DmaNum)); +} + +/** + * \brief Acknowledge interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVICR |= IntType; +} + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + + +__STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIFR |= IntType; +} + +/** + * \brief Raise DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma) +{ + assert(Dma < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIFR |= (USBHS_DEVIFR_DMA_1 << Dma); +} + +/** + * \brief check for interrupt of endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVIMR & IntType); +} + +/** + * \brief Check if endpoint's interrupt is enabled for a given endpoint number + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint number + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum)); +} + + +/** + * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint + * DMA number + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ + +__STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum)); +} + + +/** + * \brief Enables Interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIER |= IntType; +} + +/** + * \brief Enables interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum); +} + +/** + * \brief Enables DMA interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA interrupt number + */ + +__STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp) +{ + assert(DmaEp < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp); +} + +/** +* \brief Disables interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param IntType Int type +*/ + +__STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIDR |= IntType; +} + +/** +* \brief Disables interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint number +*/ + +__STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep); +} + +/** +* \brief Disables DMA interrupt for endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param DmaEp Endpoint's DMA number +*/ +__STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp) +{ + assert(DmaEp < USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp); +} + + +/** +* \brief Enables or disables endpoint. +* \param pUsbhs Pointer to an USBHS instance. +* \param Enable Enable/disable endpoint +*/ + +__STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep); + else + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep); + +} + + +/** +* \brief Rests Endpoint +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint Number +*/ + +__STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep); + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep); +} + +/** +* \brief Checks if Endpoint is enable +* \param pUsbhs Pointer to an USBHS instance. +* \param Ep Endpoint Number +*/ + +__STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep)); +} + +/** +* \brief Get MicrFrame number +* \param pUsbhs Pointer to an USBHS instance. +* \retruns Micro frame number +*/ +__STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk); +} + + +/** +* \brief Get Frame number +* \param pUsbhs Pointer to an USBHS instance. +* \retruns frame number +*/ +__STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) + >> USBHS_DEVFNUM_FNUM_Pos); +} + +/** +* \brief Get Frame number CRC error +* \param pUsbhs Pointer to an USBHS instance. +* \retruns Frame number error status +*/ +__STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs) +{ + return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15); +} + +/*----------------------------------------- +* =========== USB Device's Endpoint functions ======== +*------------------------------------------*/ + +/** + * Set Endpoints configuration + * Bank size, type and direction + */ +__STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep, + const uint8_t Type, const uint8_t Dir, + const uint8_t Size, const uint8_t Bank) +{ + + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Dir << 8) & USBHS_DEVEPTCFG_EPDIR); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (((Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (((Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk); +} + + +/** + * Enable or disable Auto switch of banks + */ +__STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, + uint8_t Enable) +{ + if (Enable) + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_AUTOSW; + else + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW); +} + + +/** + * Allocate Endpoint memory + */ +__STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_ALLOC; +} + + +/** + * Free allocated Endpoint memory + */ +__STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC); +} + + +/** + * Get Endpoint configuration + */ +__STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep, + uint32_t IntType) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep]) & IntType); +} + +/** + * Get Endpoint Type + */ +__STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk) + >> USBHS_DEVEPTCFG_EPTYPE_Pos); +} + +/** + * Get Endpoint Size + */ +__STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep) +{ + return (8 << ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk) + >> USBHS_DEVEPTCFG_EPSIZE_Pos)); +} + + +/** + * Sets ISO endpoint's Number of Transfer for High Speed + */ +__STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, + uint8_t nbTrans) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans); +} + +/** + * Check for interrupt types enabled for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpIntType) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType); +} + + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt; +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK); +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] = USBHS_DEVEPTIER_KILLBKS; +} +/** + * Disables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt; +} + +/** + * Clears register/acknowledge for a given endpoint + */ +__STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt; +} + +/** + * Sets/Raise register for a given endpoint + */ +__STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt; +} + +/** + * Gets interrupt status for a given EP + */ +__STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt); +} + +/** + * Check if given endpoint's bank is free + */ +__STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep) +{ + if ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) + return false; + else + return true; +} + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk) + >> USBHS_DEVEPTISR_NBUSYBK_Pos); +} + + +/** + * Read endpoint's byte count of the FIFO + */ +__STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep) +{ + return (uint16_t)((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk) + >> USBHS_DEVEPTISR_BYCT_Pos); +} + +/*-------------------------------------------------------- +* =========== USB Device's Ep's DMA functions ========= +*---------------------------------------------------------*/ + +/** +* \brief Sets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \param Desc NDA address +*/ +__STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_DEVDMANXTDSC = Desc; +} + +/** +* \brief Gets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \return Next DMA descriptor +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMANXTDSC); +} + +/** +* \brief Sets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \param Addr DMA's buffer Addrs +*/ +__STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_DEVDMAADDRESS = Addr; +} + + +/** +* \brief Gets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \return DMA addrs +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMAADDRESS); +} + +/** +* \brief Setup the USBHS DMA +* \param pUsbDma USBHS device DMA instance +* \param Cfg DMA's configuration +*/ +__STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_DEVDMACONTROL |= Cfg; +} + +/** +* \brief Get DMA configuration +* \param pUsbDma USBHS device DMA instance +* \return DMA control setup +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMACONTROL); +} + + +/** +* \brief Set DMA status +* \param pUsbDma USBHS device DMA instance +* \Status Set DMA status +*/ +__STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_DEVDMASTATUS = Status; +} + + +/** +* \brief Get Dma Status +* \param pUsbDma USBHS device DMA instance +* \return Dma status +*/ +__STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMASTATUS); +} + + +/** +* \brief Get DMA buffer's count +* \param pUsbDma USBHS device DMA instance +* \return Buffer count +*/ +__STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma) +{ + return ((pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos); +} + + +/*-------------------------------------------------------- +* =========== USB Host Functions ======================== +*---------------------------------------------------------*/ + +/** Number of USB endpoints */ +#define CHIP_USB_NUMPIPE 10 +/** Number of USB endpoints */ +#define CHIP_USB_DMA_NUMPIPE 7 + +/** Endpoints max paxcket size */ +#define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** +* \brief Sets USB host's speed to Normal , it sets to HS from FS +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL; +} + +/** +* \brief Sets USB host's speed to Low speed +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER; +} + +/** +* \brief Sets USB host's speed to forced Full speed +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS; +} + +/** +* \brief Sets USB host sends reste signal on USB Bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_Reset(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET; +} + +/** +* \brief Sets USB host sends reste signal on USB Bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_StopReset(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET; +} + +/** +* \brief Sets USB host send Resume on USB bus +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_Resume(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME; +} + +/** +* \brief Sets USB host Enable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE; +} + +/** +* \brief Sets USB host Enable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8; +} +/** +* \brief Sets USB host disable the Generation of Start of Frame +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_DisableSOF(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE; +} + +/** +* \brief Gets USB host interrupt status +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTISR & IntType); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_PEP_0 << PipeInt)); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_DMA_1 << PipeInt)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTICR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIFR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt); +} + +/*** Interrupt Mask ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTIMR & IntType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, + uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt)); +} + +/*** Interrupt Disable ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIDR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt); + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt); +} + +/*** Interrupt Enable ****/ + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIER = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIER = (USBHS_HSTIER_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert(PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSOF(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> + USBHS_HSTFNUM_FNUM_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetFramePos(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >> + USBHS_HSTFNUM_FLENHIGH_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetMSOF(void) +{ + return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> + USBHS_HSTFNUM_MFNUM_Pos); +} + +__STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Addr) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + + if (Pipe < 4) + pUsbhs->USBHS_HSTADDR1 |= (Addr << (8 * Pipe)); + else if ((Pipe < 8) && (Pipe >= 4)) + pUsbhs->USBHS_HSTADDR2 |= (Addr << (8 * (Pipe - 4))); + else + pUsbhs->USBHS_HSTADDR3 |= (Addr << (8 * (Pipe - 8))); + +} + +__STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + + if (Pipe < 4) + return (pUsbhs->USBHS_HSTADDR1 >> (8 * Pipe)); + else if ((Pipe < 8) && (Pipe >= 4)) + return (pUsbhs->USBHS_HSTADDR2 >> (8 * (Pipe - 4))); + else + return (pUsbhs->USBHS_HSTADDR3 >> (8 * (Pipe - 8))); + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTPIP & (USBHS_HSTPIP_PEN0 << Pipe)); +} +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, + uint8_t pipeEpNum, uint8_t PipeIntFreq) +{ + assert(Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= (pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE( + pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) | + USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> + USBHS_HSTPIPCFG_PSIZE_Pos)); + +} + +/** +* \brief Gets USB host interrupt status +* \param pUsbhs USBHS host instance +*/ +__STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t Token) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk); + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t PipeType) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk); + +} + +__STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + + if (USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN) + return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> + USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80); + else + return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> + USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00); +} + + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Freq) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> + USBHS_HSTPIPISR_DTSEQ_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> + USBHS_HSTPIPISR_NBUSYBK_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> + USBHS_HSTPIPISR_CURRBK_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> + USBHS_HSTPIPISR_PBYCT_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPICR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, + uint8_t Pipe, uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, + uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIER[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq - 1); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Err) +{ + return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, + uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] = Err; +} + + +__STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM)); +} + +static inline uint8_t USBHS_GetInterruptPipeDmaNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM - 1))) + 1); +} +/*-------------------------------------------------------- +* =========== USB Host's pipe DMA functions ========= +*---------------------------------------------------------*/ + +/** +* \brief Sets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \param Desc NDA addrs +*/ +__STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_HSTDMANXTDSC = Desc; +} + +/** +* \brief Gets DMA next descriptor address +* \param pUsbDma USBHS device DMA instance +* \return Next DMA descriptor +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMANXTDSC); +} + +/** +* \brief Sets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \param Addr DMA's buffer Addrs +*/ +__STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, + uint32_t Addr) +{ + pUsbDma->USBHS_HSTDMAADDRESS = Addr; +} + + +/** +* \brief Gets USBHS's DMA Buffer addresse +* \param pUsbDma USBHS device DMA instance +* \return DMA addrs +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMAADDRESS); +} + +/** +* \brief Setup the USBHS DMA +* \param pUsbDma USBHS device DMA instance +* \param Cfg DMA's configuration +*/ +__STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_HSTDMACONTROL |= Cfg; +} + +/** +* \brief Get DMA configuration +* \param pUsbDma USBHS device DMA instance +* \return DMA control setup +*/ +__STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMACONTROL); +} + + +/** +* \brief Set DMA status +* \param pUsbDma USBHS device DMA instance +* \Status Set DMA status +*/ +__STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, + uint32_t Status) +{ + pUsbDma->USBHS_HSTDMASTATUS = Status; +} + + +/** +* \brief Get Dma Status +* \param pUsbDma USBHS device DMA instance +* \return Dma status +*/ +__STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMASTATUS); +} + +/**@}*/ +#endif /* #ifndef USBHS_H */ diff --git a/bsps/arm/atsam/include/libchip/include/video.h b/bsps/arm/atsam/include/libchip/include/video.h new file mode 100644 index 0000000000..1ea18d214b --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/video.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _VIDEO_H +#define _VIDEO_H + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Type of video is YUV */ +#define YUV 0 +/** Type of video is RGB */ +#define RGB 1 + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct _isi_Video { + /** LCD Vertical Size */ + uint32_t lcd_vsize; + /** LCD Horizontal Size*/ + uint32_t lcd_hsize; + /** LCD Number of Bit Per Pixel*/ + uint32_t lcd_nbpp; + /** LCD Frame Buffer Address*/ + uint32_t lcd_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t Isi_fbd_base; + /** Start of Line Delay*/ + uint32_t Hblank; + /** Start of frame Delay */ + uint32_t Vblank; + /** Vertical size of the Image sensor [0..2047]*/ + uint32_t codec_vsize; + /** Horizontal size of the Image sensor [0..2047]*/ + uint32_t codec_hsize; + /** Base address for codec DMA*/ + uint32_t codec_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t codec_fbd_base; + /** Buffer index */ + uint32_t IsiPrevBuffIndex; + /** Type of video */ + uint8_t rgb_or_yuv; +} isi_Video, *pIsi_Video; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len); + +#endif + diff --git a/bsps/arm/atsam/include/libchip/include/wdt.h b/bsps/arm/atsam/include/libchip/include/wdt.h new file mode 100644 index 0000000000..9d87ffa55f --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/wdt.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** + * \file + * + * \section Purpose + * Interface for Watchdog Timer (WDT) controller. + * + * \section Usage + * -# Enable watchdog with given mode using \ref WDT_Enable(). + * -# Disable watchdog using \ref WDT_Disable() + * -# Restart the watchdog using \ref WDT_Restart(). + * -# Get watchdog status using \ref WDT_GetStatus(). + * -# Calculate watchdog period value using \ref WDT_GetPeriod(). + */ + +#ifndef _WDT_ +#define _WDT_ + +#include "chip.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void WDT_Enable(Wdt *pWDT, uint32_t dwMode); + +extern void WDT_Disable(Wdt *pWDT); + +extern void WDT_Restart(Wdt *pWDT); + +extern uint32_t WDT_GetStatus(Wdt *pWDT); + +extern uint32_t WDT_GetPeriod(uint32_t dwMs); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _WDT_ */ + diff --git a/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h b/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h new file mode 100644 index 0000000000..c115a4f8c7 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdma_hardware_interface.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _XDMAD_IF_H +#define _XDMAD_IF_H + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DMA hardware interface */ +typedef struct _XdmaHardwareInterface { + uint8_t bXdmac; /**< DMA Controller number */ + uint32_t bPeriphID; /**< Peripheral ID */ + uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/ + uint8_t bIfID; /**< DMA Interface ID */ +} XdmaHardwareInterface; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t XDMAIF_IsValidatedPeripherOnDma(uint8_t bPeriphID); +extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, uint8_t bTransfer); + +#endif //#ifndef _XDMAD_IF_H + diff --git a/bsps/arm/atsam/include/libchip/include/xdmac.h b/bsps/arm/atsam/include/libchip/include/xdmac.h new file mode 100644 index 0000000000..0b00dd505e --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdmac.h @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/** \file */ + +/** \addtogroup dmac_module Working with DMAC + * \ingroup peripherals_module + * + * \section Usage + *
    + *
  • Enable or disable the a DMAC controller with DMAC_Enable() and or + * DMAC_Disable().
    • + *
  • Enable or disable %Dma interrupt using DMAC_EnableIt()or + * DMAC_DisableIt().
    • + *
  • Get %Dma interrupt status by DMAC_GetStatus() and + * DMAC_GetInterruptMask().
    • + *
  • Enable or disable specified %Dma channel with DMAC_EnableChannel() or + * DMAC_DisableChannel().
    • + *
  • Get %Dma channel status by DMAC_GetChannelStatus().
    • + *
  • ControlA and ControlB register is set by DMAC_SetControlA() and + * DMAC_SetControlB().
    • + *
  • Configure source and/or destination start address with + * DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().
    • + *
  • Set %Dma descriptor address using DMAC_SetDescriptorAddr().
    • + *
  • Set source transfer buffer size with DMAC_SetBufferSize().
    • + *
  • Configure source and/or destination Picture-In-Picuture mode with + * DMAC_SetSourcePip() and/or DMAC_SetDestPip().
    • + *
+ * + * For more accurate information, please look at the DMAC section of the + * Datasheet. + * + * \sa \ref dmad_module + * + * Related files :\n + * \ref dmac.c\n + * \ref dmac.h.\n + * + */ + +#ifndef DMAC_H +#define DMAC_H +/**@{*/ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#ifndef __rtems__ +#include <../../../../utils/utility.h> +#endif /* __rtems__ */ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_defines DMAC Definitions + * @{ + */ +/** Number of DMA channels */ +#define XDMAC_CONTROLLER_NUM 1 +/** Number of DMA channels */ +#define XDMAC_CHANNEL_NUM 24 +/** Max DMA single transfer size */ +#define XDMAC_MAX_BT_SIZE 0xFFFF +/** @}*/ + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ + ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ + (XDMAC_CC_DWIDTH_WORD))) +#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ + ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ + ((s==2)? XDMAC_CC_SAM_UBS_AM : \ + XDMAC_CC_SAM_UBS_DS_AM))) +#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ + ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ + ((d==2)? XDMAC_CC_DAM_UBS_AM : \ + XDMAC_CC_DAM_UBS_DS_AM))) +#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ + XDMAC_CC_MEMSET_HW_MODE) + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmac_functions + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get XDMAC global type. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetType(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GTYPE; +} + +/** + * \brief Get XDMAC global configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetConfig(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GCFG; +} + +/** + * \brief Get XDMAC global weighted arbiter configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetArbiter(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GWAC; +} + +/** + * \brief Enables XDMAC global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled. + */ +static inline void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << dwInteruptMask); +} + +/** + * \brief Disables XDMAC global interrupt + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled + */ +static inline void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GID = (XDMAC_GID_ID0 << dwInteruptMask); +} + +/** + * \brief Get XDMAC global interrupt mask. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGItMask(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return (pXdmac->XDMAC_GIM); +} + +/** + * \brief Get XDMAC global interrupt status. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGIsr(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return (pXdmac->XDMAC_GIS); +} + +/** + * \brief Get XDMAC masked global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetMaskedGIsr(Xdmac *pXdmac) +{ + uint32_t _dwStatus; + _Assert(pXdmac); + _dwStatus = pXdmac->XDMAC_GIS; + _dwStatus &= pXdmac->XDMAC_GIM; + return _dwStatus; +} + +/** + * \brief enables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_EnableChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); +} + +/** + * \brief enables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +static inline void XDMAC_EnableChannels(Xdmac *pXdmac, uint32_t bmChannels) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GE = bmChannels; +} + +/** + * \brief Disables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_DisableChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GD = (XDMAC_GD_DI0 << channel); +} + +/** + * \brief Disables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +static inline void XDMAC_DisableChannels(Xdmac *pXdmac, uint32_t bmChannels) +{ + _Assert(pXdmac); + pXdmac->XDMAC_GD = bmChannels; +} + + +/** + * \brief Get Global channel status of given XDMAC. + * \note: When set to 1, this bit indicates that the channel x is enabled. + If a channel disable request is issued, this bit remains asserted + until pending transaction is completed. + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac) +{ + _Assert(pXdmac); + return pXdmac->XDMAC_GS; +} + +/** + * \brief Suspend the relevant channel's read. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendReadChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel; +} + +/** + * \brief Suspend the relevant channel's write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel; +} + +/** + * \brief Suspend the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SuspendReadWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel); +} + +/** + * \brief Resume the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_ResumeReadWriteChannel(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel); +} + +/** + * \brief Set software transfer request on the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel) +{ + + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel); +} + +/** + * \brief Get software transfer status of the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +static inline uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac) +{ + + _Assert(pXdmac); + return pXdmac->XDMAC_GSWS; +} + +/** + * \brief Get interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIS; +} + +/** + * \brief Set software flush request on the relevant channel. + * \note: This API is used as polling without enabling FIE interrupt. + * The user can use it in interrupt mode after deleting while sentense. + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel); + + while (!(XDMAC_GetChannelIsr(pXdmac, channel) & XDMAC_CIS_FIS)); +} + +/** + * \brief Disable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +static inline void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask; +} + +/** + * \brief Enable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +static inline void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask; +} + +/** + * \brief Get interrupt mask for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIM; +} + +/** + * \brief Get masked interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + uint32_t status; + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS; + status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM; + + return status; +} + +/** + * \brief Set source address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Source address. + */ +static inline void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr; +} + +/** + * \brief Set destination address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Destination address. + */ +static inline void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr; +} + +/** + * \brief Set next descriptor's address & interface for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Address of next descriptor. + * \param ndaif Interface of next descriptor. + */ +static inline void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr, uint8_t ndaif) +{ + _Assert(pXdmac); + _Assert(ndaif < 2); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = (addr & 0xFFFFFFFC) | ndaif; +} + +/** + * \brief Set next descriptor's configuration for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Configuration of next descriptor. + */ +static inline void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint8_t config) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config; +} + +/** + * \brief Set microblock length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param ublen Microblock length. + */ +static inline void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen); +} + +/** + * \brief Set block length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param blen Block length. + */ +static inline void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint16_t blen) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CBC = XDMAC_CBC_BLEN(blen); +} + +/** + * \brief Set configuration for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Channel configuration. + */ +static inline void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CC = config; +} + +/** + * \brief Get the relevant channel's configuration of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CC; +} + +/** + * \brief Set the relevant channel's data stride memory pattern of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dds_msp Data stride memory pattern. + */ +static inline void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, + uint32_t dds_msp) +{ + + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp; +} + +/** + * \brief Set the relevant channel's source microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param subs Source microblock stride. + */ +static inline void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t subs) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs); +} + +/** + * \brief Set the relevant channel's destination microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dubs Destination microblock stride. + */ +static inline void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t dubs) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs); +} + +/** + * \brief Get the relevant channel's destination address of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +static inline uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CDA; +} + +static inline void XDMAC_StartTransfer(Xdmac *pXdmac, uint8_t channel) +{ + _Assert(pXdmac); + _Assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); + pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << channel); +} + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef DMAC_H + diff --git a/bsps/arm/atsam/include/libchip/include/xdmad.h b/bsps/arm/atsam/include/libchip/include/xdmad.h new file mode 100644 index 0000000000..3b5e0838c2 --- /dev/null +++ b/bsps/arm/atsam/include/libchip/include/xdmad.h @@ -0,0 +1,253 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _XDMAD_H +#define _XDMAD_H + + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include + + +/** \addtogroup dmad_defines DMA Driver Defines + @{*/ +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ +#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */ +#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */ + +#define XDMAD_TRANSFER_TX 0 +#define XDMAD_TRANSFER_RX 1 + +/* XDMA_MBR_UBC */ +#define XDMA_UBC_NDE (0x1u << 24) +#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24) +#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24) +#define XDMA_UBC_NSEN (0x1u << 25) +#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25) +#define XDMA_UBC_NSEN_UPDATED (0x1u << 25) +#define XDMA_UBC_NDEN (0x1u << 26) +#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26) +#define XDMA_UBC_NDEN_UPDATED (0x1u << 26) +#define XDMA_UBC_NVIEW_Pos 27 +#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos) + +/*---------------------------------------------------------------------------- + * MACRO + *----------------------------------------------------------------------------*/ + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_structs DMA Driver Structs + @{*/ + +/** DMA status or return code */ +typedef enum _XdmadStatus { + XDMAD_OK = 0, /**< Operation is successful */ + XDMAD_PARTIAL_DONE, + XDMAD_DONE, + XDMAD_BUSY, /**< Channel occupied or transfer not finished */ + XDMAD_ERROR, /**< Operation failed */ + XDMAD_CANCELED /**< Operation cancelled */ +} eXdmadStatus, eXdmadRC; + +/** DMA state for channel */ +typedef enum _XdmadState { + XDMAD_STATE_FREE = 0, /**< Free channel */ + XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */ + XDMAD_STATE_START, /**< DMA started */ + XDMAD_STATE_IN_XFR, /**< DMA in transferring */ + XDMAD_STATE_DONE, /**< DMA transfer done */ + XDMAD_STATE_HALTED, /**< DMA transfer stopped */ +} eXdmadState; + +/** DMA Programming state for channel */ +typedef enum _XdmadProgState { + XDMAD_SINGLE = 0, + XDMAD_MULTI, + XDMAD_LLI, +} eXdmadProgState; + +/** DMA transfer callback */ +typedef void (*XdmadTransferCallback)(uint32_t Channel, void *pArg); + +/** DMA driver channel */ +typedef struct _XdmadChannel { + XdmadTransferCallback fCallback; /**< Callback */ + void *pArg; /**< Callback argument */ + uint8_t bIrqOwner; /**< Uses DMA handler or external one */ + uint8_t bSrcPeriphID; /**< HW ID for source */ + uint8_t bDstPeriphID; /**< HW ID for destination */ + uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */ + uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */ + uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */ + uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */ + volatile uint8_t state; /**< DMA channel state */ +} sXdmadChannel; + +/** DMA driver instance */ +typedef struct _Xdmad { + Xdmac *pXdmacs; + sXdmadChannel XdmaChannels[XDMACCHID_NUMBER]; + uint8_t numControllers; + uint8_t numChannels; + uint8_t xdmaMutex; +} sXdmad; + +typedef struct _XdmadCfg { + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} sXdmadCfg; + +/** \brief Structure for storing parameters for DMA view0 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView0 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Transfer Address Member. */ + uint32_t mbr_ta; +} LinkedListDescriporView0; + +/** \brief Structure for storing parameters for DMA view1 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView1 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; +} LinkedListDescriporView1; + +/** \brief Structure for storing parameters for DMA view2 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView2 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; +} LinkedListDescriporView2; + +/** \brief Structure for storing parameters for DMA view3 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView3 { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} LinkedListDescriporView3; + +/** @}*/ + +extern sXdmad XDMAD_Instance; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_functions DMA Driver Functions + @{*/ +extern uint32_t XDMAD_AllocateChannel(sXdmad *pXdmad, + uint8_t bSrcID, uint8_t bDstID); +extern eXdmadRC XDMAD_FreeChannel(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_ConfigureTransfer(sXdmad *pXdmad, + uint32_t dwChannel, + sXdmadCfg *pXdmaParam, + uint32_t dwXdmaDescCfg, + uint32_t dwXdmaDescAddr, + uint32_t dwXdmaIntEn); + +extern eXdmadRC XDMAD_PrepareChannel(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_IsTransferDone(sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_StartTransfer(sXdmad *pXdmad, uint32_t dwChannel); + +extern void XDMAD_DoNothingCallback(uint32_t Channel, void *pArg); + +extern eXdmadRC XDMAD_SetCallback(sXdmad *pXdmad, + uint32_t dwChannel, + XdmadTransferCallback fCallback, + void *pArg); + +extern eXdmadRC XDMAD_StopTransfer(sXdmad *pXdmad, uint32_t dwChannel); +/** @}*/ +/**@}*/ +#endif //#ifndef _XDMAD_H + diff --git a/bsps/arm/atsam/include/tm27.h b/bsps/arm/atsam/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/atsam/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/beagle/headers.am b/bsps/arm/beagle/headers.am new file mode 100644 index 0000000000..6692d0b69c --- /dev/null +++ b/bsps/arm/beagle/headers.am @@ -0,0 +1,14 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/beagle/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-pwm.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/beagleboneblack.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/irq.h diff --git a/bsps/arm/beagle/include/bsp.h b/bsps/arm/beagle/include/bsp.h new file mode 100644 index 0000000000..1a69b5e308 --- /dev/null +++ b/bsps/arm/beagle/include/bsp.h @@ -0,0 +1,364 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BSP_H +#define LIBBSP_ARM_BEAGLE_BSP_H + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +/* UART base clock frequency */ +#define UART_CLOCK 48000000 + +/* Access memory-mapped I/O devices */ +#define mmio_read(a) (*(volatile uint32_t *)(a)) +#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v)) +#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v)) +#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v)) + +#define REG16(x)(*((volatile uint16_t *)(x))) +#define REG(x)(*((volatile uint32_t *)(x))) +#define BIT(x)(0x1 << x) + +#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick())) + +/* Write a uint32_t value to a memory address. */ +static inline void +write32(uint32_t address, uint32_t value) +{ + REG(address) = value; +} + +/* Read an uint32_t from a memory address */ +static inline uint32_t +read32(uint32_t address) +{ + return REG(address); +} + +/* Set a 32 bits value depending on a mask */ +static inline void +set32(uint32_t address, uint32_t mask, uint32_t value) +{ + uint32_t val; + val = read32(address); + /* clear the bits */ + val &= ~(mask); + /* apply the value using the mask */ + val |= (value & mask); + write32(address, val); +} + +/* Write a uint16_t value to a memory address. */ +static inline void +write16(uint32_t address, uint16_t value) +{ + REG16(address) = value; +} + +/* Read an uint16_t from a memory address */ +static inline uint16_t +read16(uint32_t address) +{ + return REG16(address); +} + +/* Data synchronization barrier */ +static inline void dsb(void) +{ + asm volatile("dsb" : : : "memory"); +} + +/* Instruction synchronization barrier */ +static inline void isb(void) +{ + asm volatile("isb" : : : "memory"); +} + +/* flush data cache */ +static inline void flush_data_cache(void) +{ + asm volatile( + "mov r0, #0\n" + "mcr p15, #0, r0, c7, c10, #4\n" + : /* No outputs */ + : /* No inputs */ + : "r0","memory" + ); +} + +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; }) +#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; }) +#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; }) + +#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; }) +#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; }) +#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; }) + +#define SYSTEM_CLOCK_12 12000000 +#define SYSTEM_CLOCK_13 13000000 +#define SYSTEM_CLOCK_192 19200000 +#define SYSTEM_CLOCK_96 96000000 + +#if !defined(IS_DM3730) && !defined(IS_AM335X) +#error Unrecognized BSP configured. +#endif + +#if IS_DM3730 +#define BSP_DEVICEMEM_START 0x48000000 +#define BSP_DEVICEMEM_END 0x5F000000 +#endif + +#if IS_AM335X +#define BSP_DEVICEMEM_START 0x44000000 +#define BSP_DEVICEMEM_END 0x57000000 +#endif + +/* per-target uart config */ +#if IS_AM335X +#define BSP_CONSOLE_UART 1 +#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1 +#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ +#define BEAGLE_BASE_UART_1 0x44E09000 +#define BEAGLE_BASE_UART_2 0x48022000 +#define BEAGLE_BASE_UART_3 0x48024000 +#endif + +/* per-target uart config */ +#if IS_DM3730 +#define BSP_CONSOLE_UART 3 +#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3 +#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ +#define BEAGLE_BASE_UART_1 0x4806A000 +#define BEAGLE_BASE_UART_2 0x4806C000 +#define BEAGLE_BASE_UART_3 0x49020000 +#endif + +/* GPIO pin config */ +#if IS_AM335X +#define BSP_GPIO_PIN_COUNT 128 +#define BSP_GPIO_PINS_PER_BANK 32 +#endif + +#if IS_DM3730 +#define BSP_GPIO_PIN_COUNT 192 +#define BSP_GPIO_PINS_PER_BANK 32 +#endif + +#if BSP_START_COPY_FDT_FROM_U_BOOT +#define BSP_FDT_IS_SUPPORTED +#endif + +/* i2c stuff */ +typedef struct { + uint32_t rx_or_tx; + uint32_t stat; + uint32_t ctrl; + uint32_t clk_hi; + uint32_t clk_lo; + uint32_t adr; + uint32_t rxfl; + uint32_t txfl; + uint32_t rxb; + uint32_t txb; + uint32_t s_tx; + uint32_t s_txfl; +} beagle_i2c; + +/* sctlr */ +/* Read System Control Register */ +static inline uint32_t read_sctlr() +{ + uint32_t ctl; + + asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t" + : [ctl] "=r" (ctl)); + return ctl; +} + +/* Write System Control Register */ +static inline void write_sctlr(uint32_t ctl) +{ + asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t" + : : [ctl] "r" (ctl)); + isb(); +} + +/* Read Auxiliary Control Register */ +static inline uint32_t read_actlr() +{ + uint32_t ctl; + + asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t" + : [ctl] "=r" (ctl)); + return ctl; +} + +/* Write Auxiliary Control Register */ +static inline void write_actlr(uint32_t ctl) +{ + asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t" + : : [ctl] "r" (ctl)); + isb(); +} + +/* Write Translation Table Base Control Register */ +static inline void write_ttbcr(uint32_t bcr) +{ + asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t" + : : [bcr] "r" (bcr)); + + isb(); +} + +/* Read Domain Access Control Register */ +static inline uint32_t read_dacr() +{ + uint32_t dacr; + + asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t" + : [dacr] "=r" (dacr)); + + return dacr; +} + + +/* Write Domain Access Control Register */ +static inline void write_dacr(uint32_t dacr) +{ + asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t" + : : [dacr] "r" (dacr)); + + isb(); +} + +static inline void refresh_tlb(void) +{ + dsb(); + + /* Invalidate entire unified TLB */ + asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" + : : [zero] "r" (0)); + + /* Invalidate all instruction caches to PoU. + * Also flushes branch target cache. */ + asm volatile("mcr p15, 0, %[zero], c7, c5, 0" + : : [zero] "r" (0)); + + /* Invalidate entire branch predictor array */ + asm volatile("mcr p15, 0, %[zero], c7, c5, 6" + : : [zero] "r" (0)); /* flush BTB */ + + dsb(); + isb(); +} + +/* Read Translation Table Base Register 0 */ +static inline uint32_t read_ttbr0() +{ + uint32_t bar; + + asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" + : [bar] "=r" (bar)); + + return bar & ARM_TTBR_ADDR_MASK; +} + + +/* Read Translation Table Base Register 0 */ +static inline uint32_t read_ttbr0_unmasked() +{ + uint32_t bar; + + asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" + : [bar] "=r" (bar)); + + return bar; +} + +/* Write Translation Table Base Register 0 */ +static inline void write_ttbr0(uint32_t bar) +{ + dsb(); + isb(); + /* In our setup TTBR contains the base address *and* the flags + but other pieces of the kernel code expect ttbr to be the + base address of the l1 page table. We therefore add the + flags here and remove them in the read_ttbr0 */ + uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED; + asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t" + : : [bar] "r" (v)); + + refresh_tlb(); +} + +/* Behaviour on fatal error; default: test-friendly. + * set breakpoint to bsp_fatal_extension. + */ +/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */ +/*#define BSP_PRESS_KEY_FOR_RESET 1 */ +#define BSP_PRINT_EXCEPTION_CONTEXT 1 + /* human-readable exception info */ +#define BSP_RESET_BOARD_AT_EXIT 1 + /* causes qemu to exit, signaling end of test */ + + +/** + * @defgroup arm_beagle Beaglebone, Beagleboard Support + * + * @ingroup bsp_arm + * + * @brief Beaglebones and beagleboards support package + * + */ + +/** + * @brief Beagleboard specific set up of the MMU. + * + * Provide in the application to override. + */ +BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void); + +#endif /* LIBBSP_ARM_BEAGLE_BSP_H */ diff --git a/bsps/arm/beagle/include/bsp/bbb-gpio.h b/bsps/arm/beagle/include/bsp/bbb-gpio.h new file mode 100644 index 0000000000..ceb12a4dec --- /dev/null +++ b/bsps/arm/beagle/include/bsp/bbb-gpio.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black BSP definitions. + */ + +/** + * Copyright (c) 2015 Ketul Shah + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H +#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief BeagleBone Black GPIO functions. + */ +#define BBB_DIGITAL_IN 2 +#define BBB_DIGITAL_OUT 1 + +/** + * @brief BeagleBone Black GPIO pad configuration. + */ +#define BBB_PUDEN (1 << 3) +#define BBB_PUDDIS ~BBB_PUDEN +#define BBB_PU_EN (1 << 4) +#define BBB_PD_EN ~BBB_PU_EN +#define BBB_MUXMODE(X) (X & 0x7) +#define BBB_RXACTIVE (1 << 5) +#define BBB_SLEWCTRL (1 << 6) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */ diff --git a/bsps/arm/beagle/include/bsp/bbb-pwm.h b/bsps/arm/beagle/include/bsp/bbb-pwm.h new file mode 100644 index 0000000000..cf5d6fe552 --- /dev/null +++ b/bsps/arm/beagle/include/bsp/bbb-pwm.h @@ -0,0 +1,178 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black PWM support definitions. + */ + +/** + * Copyright (c) 2016 Punit Vara + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** Some constants are taken from + * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h + */ + +#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H +#define LIBBSP_ARM_BEAGLE_BBB_PWM_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief BeagleBone Black PWM Macros. + */ +#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4)) +#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4)) + +/** + * @brief The set of possible PWM subsystem module + * + * Enumerated type to define various instance of pwm module. + */ +typedef enum{ + BBB_PWMSS0 = 0, + BBB_PWMSS1, + BBB_PWMSS2, + BBB_PWMSS_COUNT +}BBB_PWMSS; + +typedef enum{ + BBB_P8_13_2B = 3, + BBB_P8_19_2A, + BBB_P8_45_2A, + BBB_P8_46_2B, + BBB_P8_34_1B, + BBB_P8_36_1A, + BBB_P9_14_1A, + BBB_P9_16_1B, + BBB_P9_21_0B, + BBB_P9_22_0A, + BBB_P9_29_0B, + BBB_P9_31_0A +}bbb_pwm_pin_t; + +#define BBB_P8_13_MUX_PWM 4 +#define BBB_P8_19_MUX_PWM 4 +#define BBB_P8_45_MUX_PWM 3 +#define BBB_P8_46_MUX_PWM 3 +#define BBB_P8_34_MUX_PWM 2 +#define BBB_P8_36_MUX_PWM 2 +#define BBB_P9_14_MUX_PWM 6 +#define BBB_P9_16_MUX_PWM 6 +#define BBB_P9_21_MUX_PWM 3 +#define BBB_P9_22_MUX_PWM 3 +#define BBB_P9_29_MUX_PWM 1 +#define BBB_P9_31_MUX_PWM 1 +#define BBB_PWM_FREQ_THRESHOLD 0.5f + +/** + * @brief BeagleBone Black PWM API. + */ + +/** + * @brief This function intilizes clock for pwm sub system. + * + * @param PWMSS_ID It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if not successful + * + **/ +bool beagle_pwm_init(BBB_PWMSS pwmss_id); + +/* PWMSS setting + * set pulse argument of epwm module + * + * @param pwm_id : EPWMSS number , 0~2 + * @param pwm_freq : frequency to be generated + * @param dutyA : Duty Cycle(in percentage) in PWM channel A + * @param dutyB : Duty Cycle(in percentage) in PWM channel B + * + * @return : 1 for success + * @return : 0 for failed + * + * @example : beagle_pwm_configure(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 , + * // duty cycle is 50% for ePWM0A , 25% for ePWM0B + * + * @Note : + * find an number nearst 65535 for TBPRD , to improve duty precision, + * + * Using big TBPRD can increase the range of CMPA and CMPB , + * and it means we can get better precision on duty cycle. + * + * EX : 20.25% duty cycle + * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500) + * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250) + * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500) + * + * Divisor = CLKDIV * HSPCLKDIV + * 1 TBPRD : 10 ns (default) + * 65535 TBPRD : 655350 ns + * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cycle + * + * accrooding to that , we must find a Divisor value , let X nearest 65535 . + * so , Divisor must Nearest Cycle/655350 + */ +int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b); + +/** + * @brief This API enables the particular PWM module. + * + * @param pwmid It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_enable(BBB_PWMSS pwmid); + +/** + * @brief This API disables the particular PWM module. + * + * @param pwmid It is the instance number of EPWM of pwm sub system. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_disable(BBB_PWMSS pwmid); + +/** + * @brief This function enables pinmuxing for PWM module. + * + * @param pin_no It is individual pin at which freuqency need to be generated. + * It should be according to pwm sub system. + * + * @param pwm_id It is the instance number of EPWM of pwmsubsystem. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id); + +/** + * @brief This function determines whether PWMSS-wide clocks enabled or not. + * + * @param pwmss_id It is the instance number of PWMSS which clocks need to be + * checked. + * + * @return true if successful + * @return false if fail + * + **/ +bool beagle_pwmss_is_running(unsigned int pwmss_id); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_BBB_PWM_H */ diff --git a/bsps/arm/beagle/include/bsp/beagleboneblack.h b/bsps/arm/beagle/include/bsp/beagleboneblack.h new file mode 100644 index 0000000000..c62f4aa92d --- /dev/null +++ b/bsps/arm/beagle/include/bsp/beagleboneblack.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief BeagleBone Black BSP definitions. + */ + +/** + * Copyright (c) 2015 Ketul Shah + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H +#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H + +/* In general GPIOs of BeagleBone Black/White can be addressed + * using two 46-pin dual-row expansion connectors P9 and P8, + * which are also known as Expansion A and Expansion B Connectors, + * respectively. + * + * Each Expansion Connector consists of 23 pins. So 2x23 pins would + * be available. It has 4 GPIO Banks each consists of 32 pins each. + * Toatal number of pins are 128 (32x4). + * + * So for mapping between generalized pin name and the unique pin + * numbers in this header file Macros are declared. + */ + +/* USER LEDs of BeagleBone Black */ +#define BBB_LED_USR0 53 /* USR LED0 */ +#define BBB_LED_USR1 54 /* USR LED1 */ +#define BBB_LED_USR2 55 /* USR LED2 */ +#define BBB_LED_USR3 56 /* USR LED3 */ + +/* Header P8 of BeagleBone Black */ +#define BBB_P8_7 66 /* GPIO2_2 */ +#define BBB_P8_8 67 /* GPIO2_3 */ +#define BBB_P8_9 69 /* GPIO2_5 */ +#define BBB_P8_10 68 /* GPIO2_4 */ +#define BBB_P8_11 45 /* GPIO1_13 */ +#define BBB_P8_12 44 /* GPIO1_12 */ +#define BBB_P8_13 23 /* GPIO0_23 */ +#define BBB_P8_14 26 /* GPIO0_26 */ +#define BBB_P8_15 47 /* GPIO1_15 */ +#define BBB_P8_16 46 /* GPIO1_14 */ +#define BBB_P8_17 27 /* GPIO0_27 */ +#define BBB_P8_18 65 /* GPIO2_1 */ +#define BBB_P8_19 22 /* GPIO0_22 */ +#define BBB_P8_26 61 /* GPIO1_29 */ + +/* Header P9 of BeagleBone Black */ +#define BBB_P9_11 30 /* GPIO0_30 */ +#define BBB_P9_12 60 /* GPIO1_28 */ +#define BBB_P9_13 31 /* GPIO0_31 */ +#define BBB_P9_14 50 /* GPIO1_18 */ +#define BBB_P9_15 48 /* GPIO1_16 */ +#define BBB_P9_16 51 /* GPIO1_19 */ +#define BBB_P9_17 5 /* GPIO0_5 */ +#define BBB_P9_18 4 /* GPIO0_4 */ +#define BBB_P9_23 49 /* GPIO1_17 */ +#define BBB_P9_24 15 /* GPIO0_15 */ +#define BBB_P9_26 14 /* GPIO1_14 */ +#define BBB_P9_27 115/* GPIO3_19 */ +#define BBB_P9_30 112/* GPIO3_16 */ +#define BBB_P9_41 20 /* GPIO0_20 */ +#define BBB_P9_42 7 /* GPIO0_7 */ + +#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */ \ No newline at end of file diff --git a/bsps/arm/beagle/include/bsp/i2c.h b/bsps/arm/beagle/include/bsp/i2c.h new file mode 100644 index 0000000000..3ada3c4b0d --- /dev/null +++ b/bsps/arm/beagle/include/bsp/i2c.h @@ -0,0 +1,211 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief I2C support API. + */ + +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_BEAGLE_I2C_H +#define LIBBSP_ARM_BEAGLE_I2C_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define BBB_I2C_CON_EN (1 << 15) /* I2C module enable */ +#define BBB_I2C_CON_BE (1 << 14) /* Big endian mode */ +#define BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define BBB_I2C_CON_XA (1 << 8) /* Expand address */ +#define BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ +#define BBB_I2C_CON_CLR 0x0 /* Clear configuration register */ +/* I2C Status Register (I2C_STAT): */ + +#define BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */ +#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define BBB_I2C_STAT_GC (1 << 5) +#define BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define BBB_I2C_IE_GC_IE (1 << 5) +#define BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C SYSC Register (I2C_SYSC): */ +#define BBB_I2C_SYSC_SRST (1 << 1) + +#define BBB_I2C_TIMEOUT 1000 + +#define BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ + +#define BBB_CONFIG_SYS_I2C_SPEED 100000 +#define BBB_CONFIG_SYS_I2C_SLAVE 1 +#define BBB_I2C_ALL_FLAGS 0x7FFF +#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF + +#define BBB_I2C_SYSCLK 48000000 +#define BBB_I2C_INTERNAL_CLK 12000000 +#define BBB_I2C_SPEED_CLK 100000 + +#define BBB_I2C_IRQ_ERROR \ + ( AM335X_I2C_IRQSTATUS_NACK \ + | AM335X_I2C_IRQSTATUS_ROVR \ + | AM335X_I2C_IRQSTATUS_AL \ + | AM335X_I2C_IRQSTATUS_ARDY \ + | AM335X_I2C_IRQSTATUS_RRDY \ + | AM335X_I2C_IRQSTATUS_XRDY \ + | AM335X_I2C_IRQSTATUS_XUDF ) + +#define BBB_I2C_IRQ_USED \ + ( AM335X_I2C_IRQSTATUS_ARDY \ + | AM335X_I2C_IRQSTATUS_XRDY ) + +#define BBB_I2C_0_BUS_PATH "/dev/i2c-0" +#define BBB_I2C_1_BUS_PATH "/dev/i2c-1" +#define BBB_I2C_2_BUS_PATH "/dev/i2c-2" + +#define BBB_I2C0_IRQ 70 +#define BBB_I2C1_IRQ 71 +#define BBB_I2C2_IRQ 30 + +#define BBB_MODE2 2 +#define BBB_MODE3 3 + +typedef enum { + I2C0, + I2C1, + I2C2, + I2C_COUNT +} bbb_i2c_id_t; + +typedef struct i2c_regs { + uint32_t BBB_I2C_REVNB_LO; + uint32_t BBB_I2C_REVNB_HI; + uint32_t dummy1[ 2 ]; + uint32_t BBB_I2C_SYSC; + uint32_t dummy2[ 4 ]; + uint32_t BBB_I2C_IRQSTATUS_RAW; + uint32_t BBB_I2C_IRQSTATUS; + uint32_t BBB_I2C_IRQENABLE_SET; + uint32_t BBB_I2C_IRQENABLE_CLR; + uint32_t BBB_I2C_WE; + uint32_t BBB_I2C_DMARXENABLE_SET; + uint32_t BBB_I2C_DMATXENABLE_SET; + uint32_t BBB_I2C_DMARXENABLE_CLR; + uint32_t BBB_I2C_DMATXENABLE_CLR; + uint32_t BBB_I2C_DMARXWAKE_EN; + uint32_t BBB_I2C_DMATXWAKE_EN; + uint32_t dummy3[ 16 ]; + uint32_t BBB_I2C_SYSS; + uint32_t BBB_I2C_BUF; + uint32_t BBB_I2C_CNT; + uint32_t BBB_I2C_DATA; + uint32_t dummy4; + uint32_t BBB_I2C_CON; + uint32_t BBB_I2C_OA; + uint32_t BBB_I2C_SA; + uint32_t BBB_I2C_PSC; + uint32_t BBB_I2C_SCLL; + uint32_t BBB_I2C_SCLH; + uint32_t BBB_I2C_SYSTEST; + uint32_t BBB_I2C_BUFSTAT; + uint32_t BBB_I2C_OA1; + uint32_t BBB_I2C_OA2; + uint32_t BBB_I2C_OA3; + uint32_t BBB_I2C_ACTOA; + uint32_t BBB_I2C_SBLOCK; +} bbb_i2c_regs; + +typedef struct bbb_i2c_bus { + i2c_bus base; + volatile bbb_i2c_regs *regs; + i2c_msg *msgs; + uint32_t msg_todo; + uint32_t current_msg_todo; + uint8_t *current_msg_byte; + uint32_t current_todo; + bool read; + bool hold; + rtems_id task_id; + rtems_vector_number irq; + uint32_t input_clock; + uint32_t already_transferred; +} bbb_i2c_bus; + +int am335x_i2c_bus_register( + const char *bus_path, + uintptr_t register_base, + uint32_t input_clock, + rtems_vector_number irq +); + +static inline int bbb_register_i2c_0( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_0_BUS_PATH, + AM335X_I2C0_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C0_IRQ + ); +} + +static inline int bbb_register_i2c_1( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_1_BUS_PATH, + AM335X_I2C1_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C1_IRQ + ); +} + +static inline int bbb_register_i2c_2( void ) +{ + return am335x_i2c_bus_register( + BBB_I2C_2_BUS_PATH, + AM335X_I2C2_BASE, + I2C_BUS_CLOCK_DEFAULT, + BBB_I2C2_IRQ + ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_BEAGLE_I2C_H */ diff --git a/bsps/arm/beagle/include/bsp/irq.h b/bsps/arm/beagle/include/bsp/irq.h new file mode 100644 index 0000000000..4cbf3a271f --- /dev/null +++ b/bsps/arm/beagle/include/bsp/irq.h @@ -0,0 +1,23 @@ +/** + * @file + * + * @ingroup arm_beagle + * + * @brief Basic BSP IRQ info. + */ + +#ifndef LIBBSP_ARM_BEAGLE_IRQ_H +#define LIBBSP_ARM_BEAGLE_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 127 + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */ diff --git a/bsps/arm/beagle/include/tm27.h b/bsps/arm/beagle/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/beagle/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/csb336/headers.am b/bsps/arm/csb336/headers.am new file mode 100644 index 0000000000..911de17b50 --- /dev/null +++ b/bsps/arm/csb336/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/csb336/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/csb336/include/mc9328mxl.h +include_HEADERS += ../../../../../../bsps/arm/csb336/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/csb336/include/bsp/irq.h diff --git a/bsps/arm/csb336/include/bsp.h b/bsps/arm/csb336/include/bsp.h new file mode 100644 index 0000000000..ed036d5454 --- /dev/null +++ b/bsps/arm/csb336/include/bsp.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup arm_csb336 + * + * @brief Global BSP definitions. + */ + +/* + * BSP CSB336 header file + * + * Copyright (c) 2004 Cogent Computer Systems + * Written by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_CSB336_BSP_H +#define LIBBSP_ARM_CSB336_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_csb336 CSB336 Support + * + * @ingroup bsp_arm + * + * @brief CSB336 support package. + * + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +/* What is the input clock freq in hertz? */ +#define BSP_OSC_FREQ 16000000 /* 16 MHz oscillator */ +#define BSP_XTAL_FREQ 32768 /* 32.768 KHz crystal */ + +int get_perclk1_freq(void); + +/** + * @brief Network driver configuration + */ +extern struct rtems_bsdnet_ifconfig *config; + +/* Change these to match your board */ +int rtems_mc9328mxl_enet_attach(struct rtems_bsdnet_ifconfig *config, + void *chip); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mc9328mxl_enet_attach + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/csb336/include/bsp/irq.h b/bsps/arm/csb336/include/bsp/irq.h new file mode 100644 index 0000000000..eb56fdd887 --- /dev/null +++ b/bsps/arm/csb336/include/bsp/irq.h @@ -0,0 +1,95 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the MC9328MXL */ +#define BSP_INT_UART3_PFERR 0 +#define BSP_INT_UART3_RTS 1 +#define BSP_INT_UART3_DTR 2 +#define BSP_INT_UART3_UARTC 3 +#define BSP_INT_UART3_TX 4 +#define BSP_INT_PEN_UP 5 +#define BSP_INT_CSI 6 +#define BSP_INT_MMA_MAC 7 +#define BSP_INT_MMA 8 +#define BSP_INT_COMP 9 +#define BSP_INT_MSIRQ 10 +#define BSP_INT_GPIO_PORTA 11 +#define BSP_INT_GPIO_PORTB 12 +#define BSP_INT_GPIO_PORTC 13 +#define BSP_INT_LCDC 14 +#define BSP_INT_SIM_IRQ 15 +#define BSP_INT_SIM_DATA 16 +#define BSP_INT_RTC 17 +#define BSP_INT_RTC_SAM 18 +#define BSP_INT_UART2_PFERR 19 +#define BSP_INT_UART2_RTS 20 +#define BSP_INT_UART2_DTR 21 +#define BSP_INT_UART2_UARTC 22 +#define BSP_INT_UART2_TX 23 +#define BSP_INT_UART2_RX 24 +#define BSP_INT_UART1_PFERR 25 +#define BSP_INT_UART1_RTS 26 +#define BSP_INT_UART1_DTR 27 +#define BSP_INT_UART1_UARTC 28 +#define BSP_INT_UART1_TX 29 +#define BSP_INT_UART1_RX 30 +#define BSP_INT_RES31 31 +#define BSP_INT_RES32 32 +#define BSP_INT_PEN_DATA 33 +#define BSP_INT_PWM 34 +#define BSP_INT_MMC_IRQ 35 +#define BSP_INT_SSI2_TX 36 +#define BSP_INT_SSI2_RX 37 +#define BSP_INT_SSI2_ERR 38 +#define BSP_INT_I2C 39 +#define BSP_INT_SPI2 40 +#define BSP_INT_SPI1 41 +#define BSP_INT_SSI_TX 42 +#define BSP_INT_SSI_TX_ERR 43 +#define BSP_INT_SSI_RX 44 +#define BSP_INT_SSI_RX_ERR 45 +#define BSP_INT_TOUCH 46 +#define BSP_INT_USBD0 47 +#define BSP_INT_USBD1 48 +#define BSP_INT_USBD2 49 +#define BSP_INT_USBD3 50 +#define BSP_INT_USBD4 51 +#define BSP_INT_USBD5 52 +#define BSP_INT_USBD6 53 +#define BSP_INT_UART3_RX 54 +#define BSP_INT_BTSYS 55 +#define BSP_INT_BTTIM 56 +#define BSP_INT_BTWUI 57 +#define BSP_INT_TIMER2 58 +#define BSP_INT_TIMER1 59 +#define BSP_INT_DMA_ERR 60 +#define BSP_INT_DMA 61 +#define BSP_INT_GPIO_PORTD 62 +#define BSP_INT_WDT 63 +#define BSP_MAX_INT 64 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/csb336/include/mc9328mxl.h b/bsps/arm/csb336/include/mc9328mxl.h new file mode 100644 index 0000000000..dd0516283a --- /dev/null +++ b/bsps/arm/csb336/include/mc9328mxl.h @@ -0,0 +1,486 @@ +/* + * Motorola MC9328MXL Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __MC9328MXL_H__ +#define __MC9328MXL_H__ + +#include + +#define bit(_x_) (1 << (_x_)) + +/* Define some constants relating to the CPU */ +#define MC9328MXL_NUM_INTS 64 /* CPU supports 64 interrupts */ + +/* Define the base addresses of the internal registers */ +#define MC9328MXL_AIPI1_BASE 0x00200000 +#define MC9328MXL_AIPI2_BASE 0x00210000 +#define MC9328MXL_WDOG_BASE 0x00201000 +#define MC9328MXL_TMR1_BASE 0x00202000 +#define MC9328MXL_TMR2_BASE 0x00203000 +#define MC9328MXL_RTC_BASE 0x00204000 +#define MC9328MXL_LCDC_BASE 0x00205000 +#define MC9328MXL_UART1_BASE 0x00206000 +#define MC9328MXL_UART2_BASE 0x00207000 +#define MC9328MXL_PWM_BASE 0x00208000 +#define MC9328MXL_DMAC_BASE 0x00209000 +#define MC9328MXL_USBD_BASE 0x00212000 +#define MC9328MXL_SPI1_BASE 0x00213000 +#define MC9328MXL_SPI2_BASE 0x00219000 +#define MC9328MXL_MMC_BASE 0x00214000 +#define MC9328MXL_I2C_BASE 0x00217000 +#define MC9328MXL_SSI_BASE 0x00218000 +#define MC9328MXL_MSHC_BASE 0x0021a000 +#define MC9328MXL_PLL_BASE 0x0021b000 +#define MC9328MXL_RESET_BASE 0x0021b800 +#define MC9328MXL_SYSCTRL_BASE 0x0021b804 +#define MC9328MXL_GPIOA_BASE 0x0021c000 +#define MC9328MXL_GPIOB_BASE 0x0021c100 +#define MC9328MXL_GPIOC_BASE 0x0021c200 +#define MC9328MXL_GPIOD_BASE 0x0021c300 +#define MC9328MXL_EIM_BASE 0x00220000 +#define MC9328MXL_SDRAM_BASE 0x00221000 +#define MC9328MXL_MMA_BASE 0x00222000 +#define MC9328MXL_AITC_BASE 0x00223000 +#define MC9328MXL_CSI_BASE 0x00224000 + + +#define MC9328MXL_TMR1_TCTL (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x00))) +#define MC9328MXL_TMR1_TPRER (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x04))) +#define MC9328MXL_TMR1_TCMP (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x08))) +#define MC9328MXL_TMR1_TCR (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x0c))) +#define MC9328MXL_TMR1_TCN (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x10))) +#define MC9328MXL_TMR1_TSTAT (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x14))) + +#define MC9328MXL_TMR2_TCTL (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x00))) +#define MC9328MXL_TMR2_TPRER (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x04))) +#define MC9328MXL_TMR2_TCMP (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x08))) +#define MC9328MXL_TMR2_TCR (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x0c))) +#define MC9328MXL_TMR2_TCN (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x10))) +#define MC9328MXL_TMR2_TSTAT (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x14))) + +#define MC9328MXL_TMR_TCTL_SWR (bit(15)) +#define MC9328MXL_TMR_TCTL_FRR (bit(8)) +#define MC9328MXL_TMR_TCTL_CAP_DIS (0 << 6) +#define MC9328MXL_TMR_TCTL_CAP_RISE (1 << 6) +#define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6) +#define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6) +#define MC9328MXL_TMR_TCTL_OM (bit(5)) +#define MC9328MXL_TMR_TCTL_IRQEN (bit(4)) +#define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1) +#define MC9328MXL_TMR_TCTL_TEN (bit(0)) + +#define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00))) +#define MC9328MXL_UART1_TXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x40))) +#define MC9328MXL_UART1_CR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x80))) +#define MC9328MXL_UART1_CR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x84))) +#define MC9328MXL_UART1_CR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x88))) +#define MC9328MXL_UART1_CR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x8c))) +#define MC9328MXL_UART1_FCR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x90))) +#define MC9328MXL_UART1_SR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x94))) +#define MC9328MXL_UART1_SR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x98))) +#define MC9328MXL_UART1_ESC (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x9c))) +#define MC9328MXL_UART1_TIM (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa0))) +#define MC9328MXL_UART1_BIR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa4))) +#define MC9328MXL_UART1_BMR (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa8))) +#define MC9328MXL_UART1_BRC (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xac))) +#define MC9328MXL_UART1_IPR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb0))) +#define MC9328MXL_UART1_IPR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb4))) +#define MC9328MXL_UART1_IPR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb8))) +#define MC9328MXL_UART1_IPR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xbc))) +#define MC9328MXL_UART1_MPR1 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc0))) +#define MC9328MXL_UART1_MPR2 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc4))) +#define MC9328MXL_UART1_MPR3 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc8))) +#define MC9328MXL_UART1_MPR4 (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xcc))) +#define MC9328MXL_UART1_TS (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xd0))) + +#define MC9328MXL_UART2_RXD (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x00))) +#define MC9328MXL_UART2_TXD (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x40))) +#define MC9328MXL_UART2_CR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x80))) +#define MC9328MXL_UART2_CR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x84))) +#define MC9328MXL_UART2_CR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x88))) +#define MC9328MXL_UART2_CR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x8c))) +#define MC9328MXL_UART2_FCR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x90))) +#define MC9328MXL_UART2_SR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x94))) +#define MC9328MXL_UART2_SR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x98))) +#define MC9328MXL_UART2_ESC (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x9c))) +#define MC9328MXL_UART2_TIM (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa0))) +#define MC9328MXL_UART2_BIR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa4))) +#define MC9328MXL_UART2_BMR (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa8))) +#define MC9328MXL_UART2_BRC (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xac))) +#define MC9328MXL_UART2_IPR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb0))) +#define MC9328MXL_UART2_IPR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb4))) +#define MC9328MXL_UART2_IPR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb8))) +#define MC9328MXL_UART2_IPR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xbc))) +#define MC9328MXL_UART2_MPR1 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc0))) +#define MC9328MXL_UART2_MPR2 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc4))) +#define MC9328MXL_UART2_MPR3 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc8))) +#define MC9328MXL_UART2_MPR4 (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xcc))) +#define MC9328MXL_UART2_TS (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xd0))) + +typedef struct { + volatile uint32_t rxd; + volatile uint32_t _res0[15]; + volatile uint32_t txd; + volatile uint32_t _res1[15]; + volatile uint32_t cr1; + volatile uint32_t cr2; + volatile uint32_t cr3; + volatile uint32_t cr4; + volatile uint32_t fcr; + volatile uint32_t sr1; + volatile uint32_t sr2; + volatile uint32_t esc; + volatile uint32_t tim; + volatile uint32_t bir; + volatile uint32_t bmr; + volatile uint32_t brc; + volatile uint32_t ipr1; + volatile uint32_t ipr2; + volatile uint32_t ipr3; + volatile uint32_t ipr4; + volatile uint32_t mpr1; + volatile uint32_t mpr2; + volatile uint32_t mpr3; + volatile uint32_t mpr4; + volatile uint32_t ts; +} mc9328mxl_uart_regs_t; + +#define MC9328MXL_UART_RXD_CHARRDY (bit(15)) +#define MC9328MXL_UART_RXD_ERR (bit(14)) +#define MC9328MXL_UART_RXD_OVRRUN (bit(13)) +#define MC9328MXL_UART_RXD_FRMERR (bit(12)) +#define MC9328MXL_UART_RXD_BRK (bit(11)) +#define MC9328MXL_UART_RXD_PRERR (bit(10)) +#define MC9328MXL_UART_RXD_CHARMASK (0xff) + +#define MC9328MXL_UART_CR1_ADEN (bit(15)) +#define MC9328MXL_UART_CR1_ADBR (bit(14)) +#define MC9328MXL_UART_CR1_TRDYEN (bit(13)) +#define MC9328MXL_UART_CR1_IDEN (bit(12)) +#define MC9328MXL_UART_CR1_ICD4 (0x0 << 10) +#define MC9328MXL_UART_CR1_ICD8 (0x1 << 10) +#define MC9328MXL_UART_CR1_ICD16 (0x2 << 10) +#define MC9328MXL_UART_CR1_ICD32 (0x3 << 10) +#define MC9328MXL_UART_CR1_RRDYEN (bit(9)) +#define MC9328MXL_UART_CR1_RDMAEN (bit(8)) +#define MC9328MXL_UART_CR1_IREN (bit(7)) +#define MC9328MXL_UART_CR1_TXMPTYEN (bit(6)) +#define MC9328MXL_UART_CR1_RTSDEN (bit(5)) +#define MC9328MXL_UART_CR1_SNDBRK (bit(4)) +#define MC9328MXL_UART_CR1_TDMAEN (bit(3)) +#define MC9328MXL_UART_CR1_UARTCLKEN (bit(2)) +#define MC9328MXL_UART_CR1_DOZE (bit(1)) +#define MC9328MXL_UART_CR1_UARTEN (bit(0)) + + +#define MC9328MXL_UART_CR2_ESCI (bit(15)) +#define MC9328MXL_UART_CR2_IRTS (bit(14)) +#define MC9328MXL_UART_CR2_CTSC (bit(13)) +#define MC9328MXL_UART_CR2_CTS (bit(12)) +#define MC9328MXL_UART_CR2_ESCEN (bit(11)) +#define MC9328MXL_UART_CR2_RTEC_RE (0 << 9) +#define MC9328MXL_UART_CR2_RTEC_FE (1 << 9) +#define MC9328MXL_UART_CR2_RTEC_ANY (2 << 9) +#define MC9328MXL_UART_CR2_PREN (bit(8)) +#define MC9328MXL_UART_CR2_PROE (bit(7)) +#define MC9328MXL_UART_CR2_STPB (bit(6)) +#define MC9328MXL_UART_CR2_WS (bit(5)) +#define MC9328MXL_UART_CR2_RTSEN (bit(4)) +#define MC9328MXL_UART_CR2_TXEN (bit(2)) +#define MC9328MXL_UART_CR2_RXEN (bit(1)) +#define MC9328MXL_UART_CR2_SRST (bit(0)) + +#define MC9328MXL_UART_CR3_DPEC_RE (0 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DPEC_FE (1 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DPEC_ANY (2 << 14) /* UART2 only */ +#define MC9328MXL_UART_CR3_DTREN (bit(13)) /* UART2 only */ +#define MC9328MXL_UART_CR3_PARERREN (bit(12)) +#define MC9328MXL_UART_CR3_FRAERREN (bit(11)) +#define MC9328MXL_UART_CR3_DSR (bit(10)) /* UART2 only */ +#define MC9328MXL_UART_CR3_DCD (bit(9)) /* UART2 only */ +#define MC9328MXL_UART_CR3_RI (bit(8)) /* UART2 only */ +#define MC9328MXL_UART_CR3_RXDSEN (bit(6)) +#define MC9328MXL_UART_CR3_AIRINTEN (bit(5)) +#define MC9328MXL_UART_CR3_AWAKEN (bit(4)) +#define MC9328MXL_UART_CR3_REF25 (bit(3)) +#define MC9328MXL_UART_CR3_REF30 (bit(2)) +#define MC9328MXL_UART_CR3_INVT (bit(1)) +#define MC9328MXL_UART_CR3_BPEN (bit(0)) + +#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10) +#define MC9328MXL_UART_CR4_INVR (bit(9)) +#define MC9328MXL_UART_CR4_ENIRI (bit(8)) +#define MC9328MXL_UART_CR4_WKEN (bit(7)) +#define MC9328MXL_UART_CR4_REF16 (bit(6)) +#define MC9328MXL_UART_CR4_IRSC (bit(5)) +#define MC9328MXL_UART_CR4_TCEN (bit(3)) +#define MC9328MXL_UART_CR4_BKEN (bit(2)) +#define MC9328MXL_UART_CR4_OREN (bit(1)) +#define MC9328MXL_UART_CR4_DREN (bit(0)) + +#define MC9328MXL_UART_FCR_TXTL(x) (((x) & 0x3f) << 10) +#define MC9328MXL_UART_FCR_RFDIV_1 (5 << 7) +#define MC9328MXL_UART_FCR_RFDIV_2 (4 << 7) +#define MC9328MXL_UART_FCR_RFDIV_3 (3 << 7) +#define MC9328MXL_UART_FCR_RFDIV_4 (2 << 7) +#define MC9328MXL_UART_FCR_RFDIV_5 (1 << 7) +#define MC9328MXL_UART_FCR_RFDIV_6 (0 << 7) +#define MC9328MXL_UART_FCR_RFDIV_7 (6 << 7) +#define MC9328MXL_UART_FCR_RFDIV_MASK (7 << 7) +#define MC9328MXL_UART_FCR_RXTL(x) (((x) & 0x3f) << 0) + +#define MC9328MXL_UART_SR1_PARERR (bit(15)) +#define MC9328MXL_UART_SR1_RTSS (bit(14)) +#define MC9328MXL_UART_SR1_TRDY (bit(13)) +#define MC9328MXL_UART_SR1_RTSD (bit(12)) +#define MC9328MXL_UART_SR1_ESCF (bit(11)) +#define MC9328MXL_UART_SR1_FRMERR (bit(10)) +#define MC9328MXL_UART_SR1_RRDY (bit(9)) +#define MC9328MXL_UART_SR1_RXDS (bit(6)) +#define MC9328MXL_UART_SR1_AIRINT (bit(5)) +#define MC9328MXL_UART_SR1_AWAKE (bit(4)) + +#define MC9328MXL_UART_SR2_ADET (bit(15)) +#define MC9328MXL_UART_SR2_TXFE (bit(14)) +#define MC9328MXL_UART_SR2_DTRF (bit(13)) +#define MC9328MXL_UART_SR2_IDLE (bit(12)) +#define MC9328MXL_UART_SR2_IRINT (bit(8)) +#define MC9328MXL_UART_SR2_WAKE (bit(7)) +#define MC9328MXL_UART_SR2_RTSF (bit(4)) +#define MC9328MXL_UART_SR2_TXDC (bit(3)) +#define MC9328MXL_UART_SR2_BRCD (bit(2)) +#define MC9328MXL_UART_SR2_ORE (bit(1)) +#define MC9328MXL_UART_SR2_RDR (bit(0)) + + +#define MC9328MXL_PLL_CSCR (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x00))) +#define MC9328MXL_PLL_MPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x04))) +#define MC9328MXL_PLL_MPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x08))) +#define MC9328MXL_PLL_SPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x0c))) +#define MC9328MXL_PLL_SPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x10))) +#define MC9328MXL_PLL_PCDR (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x20))) + +#define MC9328MXL_PLL_CSCR_CLKOSEL_PERCLK1 (0 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_HCLK (1 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK48M (2 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK16M (3 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_PREMCLK (4 << 29) +#define MC9328MXL_PLL_CSCR_CLKOSEL_FCLK (5 << 29) + +#define MC9328MXL_PLL_CSCR_USBDIV(_x_) (((_x_) & 0x7) << 26) +#define MC9328MXL_PLL_CSCR_SDCNT_1 (0 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_2 (1 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_3 (2 << 24) +#define MC9328MXL_PLL_CSCR_SDCNT_4 (3 << 24) + +#define MC9328MXL_PLL_CSCR_SPLLRSTRT (bit(22)) +#define MC9328MXL_PLL_CSCR_MPLLRSTRT (bit(21)) +#define MC9328MXL_PLL_CSCR_CLK16SEL (bit(18)) +#define MC9328MXL_PLL_CSCR_OSCEN (bit(17)) +#define MC9328MXL_PLL_CSCR_SYSSEL (bit(16)) +#define MC9328MXL_PLL_CSCR_PRESC (bit(15)) +#define MC9328MXL_PLL_CSCR_BLKDIV(_x_) (((_x_) & 0xf) << 10) +#define MC9328MXL_PLL_CSCR_SPEN (bit(1)) +#define MC9328MXL_PLL_CSCR_MPEN (bit(0)) + +#define MC9328MXL_PLL_PCDR_PCLK1_MASK (0x0000000f) +#define MC9328MXL_PLL_PCDR_PCLK1_SHIFT (0) +#define MC9328MXL_PLL_PCDR_PCLK2_MASK (0x000000f0) +#define MC9328MXL_PLL_PCDR_PCLK2_SHIFT (4) +#define MC9328MXL_PLL_PCDR_PCLK3_MASK (0x007f0000) +#define MC9328MXL_PLL_PCDR_PCLK3_SHIFT (16) + + +#define MC9328MXL_PLL_SPCTL_PD_MASK (0x3c000000) +#define MC9328MXL_PLL_SPCTL_PD_SHIFT (26) +#define MC9328MXL_PLL_SPCTL_MFD_MASK (0x03ff0000) +#define MC9328MXL_PLL_SPCTL_MFD_SHIFT (16) +#define MC9328MXL_PLL_SPCTL_MFI_MASK (0x00003c00) +#define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10) +#define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff) +#define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0) + + +#define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00))) +#define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04))) +#define MC9328MXL_GPIOA_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x08))) +#define MC9328MXL_GPIOA_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x0c))) +#define MC9328MXL_GPIOA_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x10))) +#define MC9328MXL_GPIOA_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x14))) +#define MC9328MXL_GPIOA_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x18))) +#define MC9328MXL_GPIOA_DR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x1c))) +#define MC9328MXL_GPIOA_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x20))) +#define MC9328MXL_GPIOA_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x24))) +#define MC9328MXL_GPIOA_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x28))) +#define MC9328MXL_GPIOA_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x2c))) +#define MC9328MXL_GPIOA_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x30))) +#define MC9328MXL_GPIOA_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x34))) +#define MC9328MXL_GPIOA_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x38))) +#define MC9328MXL_GPIOA_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x3c))) +#define MC9328MXL_GPIOA_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x40))) + +#define MC9328MXL_GPIOB_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x00))) +#define MC9328MXL_GPIOB_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x04))) +#define MC9328MXL_GPIOB_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x08))) +#define MC9328MXL_GPIOB_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x0c))) +#define MC9328MXL_GPIOB_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x10))) +#define MC9328MXL_GPIOB_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x14))) +#define MC9328MXL_GPIOB_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x18))) +#define MC9328MXL_GPIOB_DR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x1c))) +#define MC9328MXL_GPIOB_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x20))) +#define MC9328MXL_GPIOB_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x24))) +#define MC9328MXL_GPIOB_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x28))) +#define MC9328MXL_GPIOB_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x2c))) +#define MC9328MXL_GPIOB_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x30))) +#define MC9328MXL_GPIOB_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x34))) +#define MC9328MXL_GPIOB_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x38))) +#define MC9328MXL_GPIOB_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x3c))) +#define MC9328MXL_GPIOB_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x40))) + +#define MC9328MXL_GPIOC_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x00))) +#define MC9328MXL_GPIOC_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x04))) +#define MC9328MXL_GPIOC_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x08))) +#define MC9328MXL_GPIOC_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x0c))) +#define MC9328MXL_GPIOC_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x10))) +#define MC9328MXL_GPIOC_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x14))) +#define MC9328MXL_GPIOC_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x18))) +#define MC9328MXL_GPIOC_DR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x1c))) +#define MC9328MXL_GPIOC_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x20))) +#define MC9328MXL_GPIOC_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x24))) +#define MC9328MXL_GPIOC_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x28))) +#define MC9328MXL_GPIOC_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x2c))) +#define MC9328MXL_GPIOC_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x30))) +#define MC9328MXL_GPIOC_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x34))) +#define MC9328MXL_GPIOC_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x38))) +#define MC9328MXL_GPIOC_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x3c))) +#define MC9328MXL_GPIOC_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x40))) + +#define MC9328MXL_GPIOD_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x00))) +#define MC9328MXL_GPIOD_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x04))) +#define MC9328MXL_GPIOD_OCR2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x08))) +#define MC9328MXL_GPIOD_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x0c))) +#define MC9328MXL_GPIOD_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x10))) +#define MC9328MXL_GPIOD_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x14))) +#define MC9328MXL_GPIOD_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x18))) +#define MC9328MXL_GPIOD_DR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x1c))) +#define MC9328MXL_GPIOD_GIUS (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x20))) +#define MC9328MXL_GPIOD_SSR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x24))) +#define MC9328MXL_GPIOD_ICR1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x28))) +#define MC9328MXL_GPIOD_ICR2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x2c))) +#define MC9328MXL_GPIOD_IMR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x30))) +#define MC9328MXL_GPIOD_ISR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x34))) +#define MC9328MXL_GPIOD_GPR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x38))) +#define MC9328MXL_GPIOD_SWR (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x3c))) +#define MC9328MXL_GPIOD_PUEN (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x40))) + +#define MC9328MXL_AITC_INTCNTL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x00))) +#define MC9328MXL_AITC_NIMASK (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x04))) +#define MC9328MXL_AITC_INTENNUM (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x08))) +#define MC9328MXL_AITC_INTDISNUM (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x0c))) +#define MC9328MXL_AITC_INTENABLEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x10))) +#define MC9328MXL_AITC_INTENABLEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x14))) +#define MC9328MXL_AITC_INTTYPEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x18))) +#define MC9328MXL_AITC_INTTYPEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x1c))) +#define MC9328MXL_AITC_NIPIR7 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x20))) +#define MC9328MXL_AITC_NIPRI6 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x24))) +#define MC9328MXL_AITC_NIPRI5 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x28))) +#define MC9328MXL_AITC_NIPRI4 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x2c))) +#define MC9328MXL_AITC_NIPRI3 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x30))) +#define MC9328MXL_AITC_NIPRI2 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x34))) +#define MC9328MXL_AITC_NIPRI1 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x38))) +#define MC9328MXL_AITC_NIPRI0 (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x3c))) +#define MC9328MXL_AITC_NIVECSR (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x40))) +#define MC9328MXL_AITC_FIVECSR (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x44))) +#define MC9328MXL_AITC_INTSRCH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x48))) +#define MC9328MXL_AITC_INTSRCL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x4c))) +#define MC9328MXL_AITC_INTFRCH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x50))) +#define MC9328MXL_AITC_INTFRCL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x54))) +#define MC9328MXL_AITC_NIPNDH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x58))) +#define MC9328MXL_AITC_NIPNDL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x5c))) +#define MC9328MXL_AITC_FIPNDH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x60))) +#define MC9328MXL_AITC_FIPNDL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x64))) + +#define MC9328MXL_INT_UART3_PFERR (0) +#define MC9328MXL_INT_UART3_RTS (1) +#define MC9328MXL_INT_UART3_DTR (2) +#define MC9328MXL_INT_UART3_UARTC (3) +#define MC9328MXL_INT_UART3_TX (4) +#define MC9328MXL_INT_PEN_UP (5) +#define MC9328MXL_INT_CSI (6) +#define MC9328MXL_INT_MMA_MAC (7) +#define MC9328MXL_INT_MMA (8) +#define MC9328MXL_INT_COMP (9) +#define MC9328MXL_INT_MSIRQ (10) +#define MC9328MXL_INT_GPIO_PORTA (11) +#define MC9328MXL_INT_GPIO_PORTB (12) +#define MC9328MXL_INT_GPIO_PORTC (13) +#define MC9328MXL_INT_LCDC (14) +#define MC9328MXL_INT_SIM_IRQ (15) +#define MC9328MXL_INT_SIM_DATA (16) +#define MC9328MXL_INT_RTC (17) +#define MC9328MXL_INT_RTC_SAM (18) +#define MC9328MXL_INT_UART2_PFERR (19) +#define MC9328MXL_INT_UART2_RTS (20) +#define MC9328MXL_INT_UART2_DTR (21) +#define MC9328MXL_INT_UART2_UARTC (22) +#define MC9328MXL_INT_UART2_TX (23) +#define MC9328MXL_INT_UART2_RX (24) +#define MC9328MXL_INT_UART1_PFERR (25) +#define MC9328MXL_INT_UART1_RTS (26) +#define MC9328MXL_INT_UART1_DTR (27) +#define MC9328MXL_INT_UART1_UARTC (28) +#define MC9328MXL_INT_UART1_TX (29) +#define MC9328MXL_INT_UART1_RX (30) +#define MC9328MXL_INT_PEN_DATA (33) +#define MC9328MXL_INT_PWM (34) +#define MC9328MXL_INT_MMC_IRQ (35) +#define MC9328MXL_INT_SSI2_TX (36) +#define MC9328MXL_INT_SSI2_RX (37) +#define MC9328MXL_INT_SSI2_ERR (38) +#define MC9328MXL_INT_I2C (39) +#define MC9328MXL_INT_SPI2 (40) +#define MC9328MXL_INT_SPI1 (41) +#define MC9328MXL_INT_SSI_TX (42) +#define MC9328MXL_INT_SSI_TX_ERR (43) +#define MC9328MXL_INT_SSI_RX (44) +#define MC9328MXL_INT_SSI_RX_ERR (45) +#define MC9328MXL_INT_TOUCH (46) +#define MC9328MXL_INT_USBD0 (47) +#define MC9328MXL_INT_USBD1 (48) +#define MC9328MXL_INT_USBD2 (49) +#define MC9328MXL_INT_USBD3 (50) +#define MC9328MXL_INT_USBD4 (51) +#define MC9328MXL_INT_USBD5 (52) +#define MC9328MXL_INT_USBD6 (53) +#define MC9328MXL_INT_UART3_RX (54) +#define MC9328MXL_INT_BTSYS (55) +#define MC9328MXL_INT_BTTIM (56) +#define MC9328MXL_INT_BTWUI (57) +#define MC9328MXL_INT_TIMER2 (58) +#define MC9328MXL_INT_TIMER1 (59) +#define MC9328MXL_INT_DMA_ERR (60) +#define MC9328MXL_INT_DMA (61) +#define MC9328MXL_INT_GPIO_PORTD (62) +#define MC9328MXL_INT_WDT (63) + +#define MC9328MXL_AITC_INTCTL_NIAD BIT(20) +#define MC9328MXL_AITC_INTCTL_FIAD BIT(19) +#define MC9328MXL_AITC_NIMASK_MASK (0X1F) +#define MC9328MXL_AITC_INTENNUM_MASK (0X3F) +#define MC9328MXL_AITC_INTDISNUM_MASK (0X3F) +#define MC9328MXL_AITC_NIPRIORITY(_int_, _pri_) \ + (((_pri_) & 0xf) << ((_int_) & 0x7) * 4) + + +#endif /* __MC9328MXL_H__ */ diff --git a/bsps/arm/csb336/include/tm27.h b/bsps/arm/csb336/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/csb336/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/csb337/headers.am b/bsps/arm/csb337/headers.am new file mode 100644 index 0000000000..4fff8adeac --- /dev/null +++ b/bsps/arm/csb337/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_dbgu.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_emac.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_gpio.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_mem.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_pmc.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/at91rm9200_usart.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/bits.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/font8x16.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/sed1356.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/sed1356_16bit.h +include_HEADERS += ../../../../../../bsps/arm/csb337/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/csb337/include/bsp/irq.h diff --git a/bsps/arm/csb337/include/at91rm9200.h b/bsps/arm/csb337/include/at91rm9200.h new file mode 100644 index 0000000000..3ed64c7073 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200.h @@ -0,0 +1,344 @@ +/* + * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637) + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + + +#ifndef __AT91RM9200_H__ +#define __AT91RM9200_H__ + +#include "bits.h" + +typedef volatile unsigned long vulong; + +/* Source Mode Register - 32 of them */ +#define AIC_SMR_BASE 0xFFFFF000 +#define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c)) + +/* Source Vector Register - 32 of them */ +#define AIC_SVR_BASE 0xFFFFF080 +#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) + +/* Control Register - 32 of them */ +#define AIC_CTL_BASE 0xFFFFF100 +#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) + +/* Register Offsets */ +/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */ +#define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */ +#define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */ +#define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */ +#define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */ +#define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */ +#define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */ +#define AIC_SMR_US0 0x18 /* USART 0 */ +#define AIC_SMR_US1 0x1c /* USART 1 */ +#define AIC_SMR_US2 0x20 /* USART 2 */ +#define AIC_SMR_US3 0x24 /* USART 3 */ +#define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */ +#define AIC_SMR_UDP 0x2c /* USB Device Port */ +#define AIC_SMR_TWI 0x30 /* Two-wire Interface */ +#define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */ +#define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */ +#define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */ +#define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */ +#define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */ +#define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */ +#define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */ +#define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */ +#define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */ +#define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */ +#define AIC_SMR_UHP 0x5c /* USB Host Port */ +#define AIC_SMR_EMAC 0x60 /* Ethernet MAC */ +#define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */ +#define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */ +#define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */ +#define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */ +#define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */ +#define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */ +#define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */ + +/* from AIC_CTL_BASE */ +#define AIC_IVR 0x00 /* IRQ Vector Register */ +#define AIC_FVR 0x04 /* FIQ Vector Register */ +#define AIC_ISR 0x08 /* Interrupt Status Register */ +#define AIC_IPR 0x0C /* Interrupt Pending Register */ +#define AIC_IMR 0x10 /* Interrupt Mask Register */ +#define AIC_CISR 0x14 /* Core Interrupt Status Register */ +#define AIC_IECR 0x20 /* Interrupt Enable Command Register */ +#define AIC_IDCR 0x24 /* Interrupt Disable Command Register */ +#define AIC_ICCR 0x28 /* Interrupt Clear Command Register */ +#define AIC_ISCR 0x2C /* Interrupt Set Command Register */ +#define AIC_EOICR 0x30 /* End of Interrupt Command Register */ +#define AIC_SPU 0x34 /* Spurious Vector Register */ +#define AIC_DCR 0x38 /* Debug Control Register (Protect) */ +#define AIC_FFER 0x40 /* Fast Forcing Enable Register */ +#define AIC_FFDR 0x44 /* Fast Forcing Disable Register */ +#define AIC_FFSR 0x48 /* Fast Forcing Status Register */ + +/* Bit Defines */ +/* AIC_ISR - Interrupt Status Register */ +#define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */ + +/* AIC_CISR - Core Interrupt Status Register */ +#define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */ +#define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */ + +/* AIC_DCR - Debug Control Register (Protect) */ +#define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */ +#define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */ + +/* AIC_SMR */ +#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) +#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ +#define AIC_SMR_SRC_EDGE_LOW (1 << 5) +#define AIC_SMR_SRC_LVL_HI (2 << 5) +#define AIC_SMR_SRC_EDGE_HI (3 << 5) + +/**************************************************************************/ +/* Debug Unit */ +/**************************************************************************/ +#define DBGU_BASE 0xFFFFF200 +#define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_) + +/* Register Offsets */ +#define DBGU_CR 0x00 /* Control Register */ +#define DBGU_MR 0x04 /* Mode Register */ +#define DBGU_IER 0x08 /* Interrupt Enable Register */ +#define DBGU_IDR 0x0C /* Interrupt Disable Register */ +#define DBGU_IMR 0x10 /* Interrupt Mask Register */ +#define DBGU_CSR 0x14 /* Channel Status Register */ +#define DBGU_RHR 0x18 /* Receiver Holding Register */ +#define DBGU_THR 0x1C /* Transmitter Holding Register */ +#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ +#define DBGU_C1R 0x40 /* Chip ID1 Register */ +#define DBGU_C2R 0x44 /* Chip ID2 Register */ +#define DBGU_FNTR 0x48 /* Force NTRST Register */ + +/**************************************************************************/ +/* USART 0-3 */ +/**************************************************************************/ +#define USART0_BASE 0xFFFC0000 +#define USART1_BASE 0xFFFC4000 +#define USART2_BASE 0xFFFC8000 +#define USART3_BASE 0xFFFCC000 +/* + * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!! + * Manual revision: Rev. 1768H-ATARM–16-Jun-09 + * USART3_BASE is NOT 0xFFECC000 + */ + +/****************/ +/* System Timer */ +/****************/ +#define ST_BASE 0xFFFFFD00 +#define ST_REG(_x_) *(vulong *)(ST_BASE + _x_) + +/* Register Offsets */ +#define ST_CR 0x00 /* Control Register */ +#define ST_PIMR 0x04 /* Period Interval Mode Register */ +#define ST_WDMR 0x08 /* Watchdog Mode Register */ +#define ST_RTMR 0x0C /* Real-time Mode Register */ +#define ST_SR 0x10 /* Status Register */ +#define ST_IER 0x14 /* Interrupt Enable Register */ +#define ST_IDR 0x18 /* Interrupt Disable Register */ +#define ST_IMR 0x1C /* Interrupt Mask Register */ +#define ST_RTAR 0x20 /* Real-time Alarm Register */ +#define ST_CRTR 0x24 /* Current Real-time Register */ + +/* Bit Defines */ +/* ST_CR - Control Register */ +#define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */ + +/* ST_PIMR - Period Interval Mode Register */ +#define ST_PIMR_PIV_MASK 0x0000ffff + +/* ST_WDMR - Watchdog Mode Register */ +#define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */ +#define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */ +#define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */ + +/* ST_RTMR - Real-time Mode Register */ +#define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */ + +/* ST_SR - Status Register - Read Only */ +/* ST_IER - Interrupt Enable Register - Write Only */ +/* ST_IDR - Interrupt Disable Register - Write Only */ +/* ST_IMR - Interrupt Mask Register - Read Only */ +#define ST_SR_ALMS BIT3 +#define ST_SR_RTTINC BIT2 +#define ST_SR_WDOVF BIT1 +#define ST_SR_PITS BIT0 + +/* ST_RTAR - Real-time Alarm Register */ +#define ST_RTAR_ALMV_MASK 0x000fffff + +/* ST_CRTR - Current Real-time Register */ +#define ST_CRTR_CRTV_MASK 0x000fffff + + +/************************************************************************** + * Peripheral Data Control (DMA) + * Note that each of the following peripherals has it's own + * set of these registers starting at offset 0x100 from it's + * base address: DBGU, SPI, USART and SSC + * To access the DMA for a peripheral, use the macro for that + * peripheral but with these register offsets + **************************************************************************/ +/* Register Offsets */ +#define PDC_RPR 0x100 /* Receive Pointer Register */ +#define PDC_RCR 0x104 /* Receive Counter Register */ +#define PDC_TPR 0x108 /* Transmit Pointer Register */ +#define PDC_TCR 0x10c /* Transmit Counter Register */ +#define PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define PDC_TNCR 0x11c /* Transmit Next Counter Register */ +#define PDC_PTCR 0x120 /* PDC Transfer Control Register */ +#define PDC_PTSR 0x124 /* PDC Transfer Status Register */ + +/************************************************************************** + * Parallel I/O Unit + * There are four PIO blocks - A, B, C and D. They all have the + * same register set, but different base addresses + **************************************************************************/ +/* Port A */ +#define PIOA_BASE 0xFFFFF400 +#define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_) + +/* Port B */ +#define PIOB_BASE 0xFFFFF600 +#define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_) + +/* Port C */ +#define PIOC_BASE 0xFFFFF800 +#define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_) + +/* Port D */ +#define PIOD_BASE 0xFFFFFA00 +#define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_) + +/************************************************************************** + * Power Management and Clock Control + *************************************************************************/ +#define PMC_BASE 0xFFFFFC00 +#define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_) + +/************************************************************************** + * MAC Unit + *************************************************************************/ +#define EMAC_BASE 0xFFFBC000 +#define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_) + +/************************************************************************** + * Timer/Counter Unit + **************************************************************************/ +#define TC_BASE 0xFFFA0000 +#define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) +#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) +#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_) +#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_) + +/* Offsets from TC_TC?_REG */ +#define TC_CCR 0x00 /* Channel Control Register */ +#define TC_CMR 0x04 /* Channel Mode Register */ +#define TC_CV 0x10 /* Counter Value */ +#define TC_RA 0x14 /* Register A */ +#define TC_RB 0x18 /* Register B */ +#define TC_RC 0x1C /* Register C */ +#define TC_SR 0x20 /* Status Register */ +#define TC_IER 0x24 /* Interrupt Enable Register */ +#define TC_IDR 0x28 /* Interrupt Disable Register */ +#define TC_IMR 0x2C /* Interrupt Mask Register */ + +/* Offsets from TC_BASE */ +#define TC_BCR 0xc0 /* Channel Control Register */ +#define TC_BMR 0xc4 /* Channel Control Register */ + +/* Block control register */ +#define TC_BCR_SYNC BIT1 /* Set to syncronize channels */ + +/* Block mode register */ +#define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */ +#define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */ +#define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */ + +/* Channel Control register */ +#define TC_CCR_CLKEN BIT0 /* Enable clock */ +#define TC_CCR_CLKDIS BIT1 /* Disable clock */ +#define TC_CCR_SWTRG BIT2 /* Software trigger command */ + +/* Channel mode register */ +#define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */ +#define TC_CMR_CLKI BIT3 /* Clock invert */ +#define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */ +#define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */ + +/* Channel mode register - capture mode (TC_WAVE = 0) */ +#define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */ +#define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */ +#define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */ +#define TC_CMR_ABETRG BIT10 /* Select ext trigger source */ +#define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */ +#define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */ +#define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */ + +/* Channel mode register - wave mode (TC_WAVE = 1) */ +#define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */ +#define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */ +#define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */ +#define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */ +#define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */ +#define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */ +#define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */ +#define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */ +#define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */ +#define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */ +#define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */ +#define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */ +#define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */ +#define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */ + +/* Counter value */ +#define TC_CV_MASK 0xffff /* Timer counter mask */ + +/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */ +#define TC_SR_COVFS BIT0 /* Counter overflow status */ +#define TC_SR_LOVRS BIT1 /* Load overrun status */ +#define TC_SR_CPAS BIT2 /* RA compare status */ +#define TC_SR_CPBS BIT3 /* RB compare status */ +#define TC_SR_CPCS BIT4 /* RC compare status */ +#define TC_SR_LDRAS BIT5 /* RA loading status */ +#define TC_SR_LDRBS BIT6 /* RB loading status */ +#define TC_SR_ETRGS BIT7 /* External trigger status */ +#define TC_SR_CLKSTA BIT16 /* Clock enabling status */ +#define TC_SR_MTIOA BIT17 /* TIOA Mirror */ +#define TC_SR_MTIOB BIT18 /* TIOB Mirror */ + +/*************************************************************************** + * External Bus Interface Unit + **************************************************************************/ +#define EBI_BASE 0xFFFFFF60 +#define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_) + +/*************************************************************************** + * Static Memory Interface Unit + ***************************************************************************/ +#define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_) + +/************************************************************************** + * SDRAM Memory Interface Unit + **************************************************************************/ +#define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_) + +#endif /* __AT91RM9200_H__ */ + diff --git a/bsps/arm/csb337/include/at91rm9200_dbgu.h b/bsps/arm/csb337/include/at91rm9200_dbgu.h new file mode 100644 index 0000000000..9a65483db0 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_dbgu.h @@ -0,0 +1,89 @@ +/* + * Atmel AT91RM9200_DBGU Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_DBGU_H__ +#define __AT91RM9200_DBGU_H__ + +#include "bits.h" + +/* Register Offsets */ +#define DBGU_CR 0x00 /* Control Register */ +#define DBGU_MR 0x04 /* Mode Register */ +#define DBGU_IER 0x08 /* Interrupt Enable Register */ +#define DBGU_IDR 0x0C /* Interrupt Disable Register */ +#define DBGU_IMR 0x10 /* Interrupt Mask Register */ +#define DBGU_SR 0x14 /* Channel Status Register */ +#define DBGU_RHR 0x18 /* Receiver Holding Register */ +#define DBGU_THR 0x1C /* Transmitter Holding Register */ +#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ +#define DBGU_C1R 0x40 /* Chip ID1 Register */ +#define DBGU_C2R 0x44 /* Chip ID2 Register */ +#define DBGU_FNTR 0x48 /* Force NTRST Register */ + +/* Bit Defines */ +/* Control Register, DBGU_CR, Offset 0x00 */ +#define DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ +#define DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ +#define DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */ +#define DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */ +#define DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */ +#define DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */ +#define DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ + +/* Mode Register. DBGU_MR. Offset 0x04 */ +#define DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */ +#define DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */ +#define DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */ +#define DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */ +#define DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */ +#define DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */ +#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */ +#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */ +#define DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */ +#define DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ + +/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */ +/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */ +/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */ +/* Channel Status Register, DBGU_SR, Offset 0x14 */ +#define DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */ +#define DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */ +#define DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */ +/*efine DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */ +#define DBGU_INT_OVRE BIT5 /* Overrun Interrupt */ +#define DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */ +#define DBGU_INT_PARE BIT7 /* Parity Error Interrupt */ +#define DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */ +#define DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */ +#define DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */ +#define DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */ +#define DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */ +#define DBGU_INT_ALL 0xC0001AFB /* all assigned bits */ + +/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */ +#define DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ + +typedef struct { + volatile uint32_t cr; + volatile uint32_t mr; + volatile uint32_t ier; + volatile uint32_t idr; + volatile uint32_t imr; + volatile uint32_t sr; + volatile uint32_t rhr; + volatile uint32_t thr; + volatile uint32_t brgr; + volatile uint32_t _res0[7]; + volatile uint32_t cidr; + volatile uint32_t exid; + volatile uint32_t fnr; +} at91rm9200_dbgu_regs_t; + +#endif /* __AT91RM9200_DBGU_H__ */ diff --git a/bsps/arm/csb337/include/at91rm9200_emac.h b/bsps/arm/csb337/include/at91rm9200_emac.h new file mode 100644 index 0000000000..77c42d1526 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_emac.h @@ -0,0 +1,160 @@ +/* + * Atmel AT91RM9200 EMAC Register definitions + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_EMAC_H__ +#define __AT91RM9200_EMAC_H__ + +#include + +/*Register offsets */ +#define EMAC_CTL 0x00 /* Network Control Register */ +#define EMAC_CFG 0x04 /* Network Configuration Register */ +#define EMAC_SR 0x08 /* Network Status Register */ +#define EMAC_TAR 0x0C /* Transmit Address Register */ +#define EMAC_TCR 0x10 /* Transmit Control Register */ +#define EMAC_TSR 0x14 /* Transmit Status Register */ +#define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ +#define EMAC_RSR 0x20 /* Receive Status Register */ +#define EMAC_ISR 0x24 /* Interrupt Enable Register */ +#define EMAC_IER 0x28 /* Interrupt Enable Register */ +#define EMAC_IDR 0x2C /* Interrupt Disable Register */ +#define EMAC_IMR 0x30 /* Interrupt Mask Register */ +#define EMAC_MAN 0x34 /* PHY Maintenance Register */ +#define EMAC_FRA 0x40 /* Frames Transmitted OK Register */ +#define EMAC_SCOL 0x44 /* Single Collision Frame Register */ +#define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */ +#define EMAC_OK 0x4C /* Frames Received OK Register */ +#define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */ +#define EMAC_ALE 0x54 /* Alignment Error Register */ +#define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */ +#define EMAC_LCOL 0x5C /* Late Collision Register */ +#define EMAC_ECOL 0x60 /* Excessive Collision Register */ +#define EMAC_CSE 0x64 /* Carrier Sense Error Register */ +#define EMAC_TUE 0x68 /* Transmit Underrun Error Register */ +#define EMAC_CDE 0x6C /* Code Error Register */ +#define EMAC_ELR 0x70 /* Excessive Length Error Register */ +#define EMAC_RJB 0x74 /* Receive Jabber Register */ +#define EMAC_USF 0x78 /* Undersize Frame Register */ +#define EMAC_SQEE 0x7C /* SQE Test Error Register */ +#define EMAC_DRFC 0x80 /* Discarded RX Frame Register */ +#define EMAC_HSH 0x90 /* Hash Address High[63:32] */ +#define EMAC_HSL 0x94 /* Hash Address Low[31:0] */ +#define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */ +#define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */ +#define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */ +#define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */ +#define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */ +#define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */ +#define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */ +#define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */ + +/* Control Register, EMAC_CTL, Offset 0x0 */ +#define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */ +#define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */ +#define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */ +#define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */ +#define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */ +#define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */ +#define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */ +#define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */ +#define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */ + +/* Configuration Register, EMAC_CFG, Offset 0x4 */ +#define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */ +#define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */ +#define EMAC_CFG_BR BIT2 /* write 0 */ +#define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */ +#define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */ +#define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */ +#define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */ +#define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */ +#define EMAC_CFG_EAE BIT9 /* write 0 */ +#define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */ +#define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */ +#define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */ +#define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */ +#define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */ +#define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */ +#define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */ + +/* Status Register, EMAC_SR, Offset 0x8 */ +#define EMAC_LINK BIT0 /* Link pin */ +#define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */ +#define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */ + +/* Transmit Control Register, EMAC_TCR, Offset 0x10 */ +#define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */ +#define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */ + +/* Transmit Status Register, EMAC_TSR, Offset 0x14 */ +#define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */ +#define EMAC_TSR_COL BIT1 /* 1 = Collision occured */ +#define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */ +#define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */ +#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ +#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ +#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ + +/* Receive Status Register, EMAC_RSR, Offset 0x20 */ +#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ +#define EMAC_RSR_REC BIT1 /* 1 = Frame received */ +#define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */ + +/* + * Interrupt Status Register, EMAC_ISR, Offsen 0x24 + * Interrupt Enable Register, EMAC_IER, Offset 0x28 + * Interrupt Disable Register, EMAC_IDR, Offset 0x2c + * Interrupt Mask Register, EMAC_IMR, Offset 0x30 + */ +#define EMAC_INT_DONE BIT0 /* Phy management done */ +#define EMAC_INT_RCOM BIT1 /* Receive complete */ +#define EMAC_INT_RBNA BIT2 /* Receive buffer not available */ +#define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */ +#define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */ +#define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */ +#define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */ +#define EMAC_INT_TCOM BIT7 /* Transmit complete */ +#define EMAC_INT_TIDLE BIT8 /* Transmit idle */ +#define EMAC_INT_LINK BIT9 /* Link pin changed value */ +#define EMAC_INT_ROVR BIT10 /* Receive overrun */ +#define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */ + +/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */ +#define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */ +#define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */ +#define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */ +#define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */ +#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ +#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ +#define EMAC_MAN_HIGH BIT30 /* Must be set */ +#define EMAC_MAN_LOW BIT31 + +/* + * Bit assignments for Receive Buffer Descriptor + * Address - Word 0 + */ +#define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */ +#define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */ +#define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */ + +/* Status - Word 1 */ +#define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */ +#define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */ +#define RXBUF_STAT_UNI BIT29 /* Unicast hash match */ +#define RXBUF_STAT_EXT BIT28 /* External address (optional) */ +#define RXBUF_STAT_UNK BIT27 /* Unknown source address */ +#define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */ +#define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */ +#define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */ +#define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */ +#define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */ + +#endif /* __AT91RM9200_EMAC_H__ */ + diff --git a/bsps/arm/csb337/include/at91rm9200_gpio.h b/bsps/arm/csb337/include/at91rm9200_gpio.h new file mode 100644 index 0000000000..9fa18ad476 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_gpio.h @@ -0,0 +1,401 @@ +/* + * AT91RM9200 GPIO definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef AT91RM9200_GPIO_H +#define AT91RM9200_GPIO_H + +#include + +/* Register Offsets */ +#define PIO_PER 0x00 /* PIO Enable Register */ +#define PIO_PDR 0x04 /* PIO Disable Register */ +#define PIO_PSR 0x08 /* PIO Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Registerr */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Input Filter Enable Register */ +#define PIO_IFDR 0x24 /* Input Filter Disable Register */ +#define PIO_IFSR 0x28 /* Input Filter Status Register */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pad Pull-up Status Register */ +#define PIO_ASR 0x70 /* Select A Register */ +#define PIO_BSR 0x74 /* Select B Register */ +#define PIO_ABSR 0x78 /* AB Select Status Register */ +#define PIO_OWER 0xA0 /* Output Write Enable Register */ +#define PIO_OWDR 0xA4 /* Output Write Disable Register */ +#define PIO_OWSR 0xA8 /* Output Write Status Register */ + + +/* + * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D. + * To make it easier to interface with them and to eliminate the need + * to track which GPIO is in which port, we convert the Port x, Bit y + * into a single GPIO number 0 - 127. + * + * Board specific defines will assign the board level signal to a + * virutal GPIO. + * + * PORT A + */ +#define GPIO_0 BIT0 +#define GPIO_1 BIT1 +#define GPIO_2 BIT2 +#define GPIO_3 BIT3 +#define GPIO_4 BIT4 +#define GPIO_5 BIT5 +#define GPIO_6 BIT6 +#define GPIO_7 BIT7 +#define GPIO_8 BIT8 +#define GPIO_9 BIT9 +#define GPIO_10 BIT10 +#define GPIO_11 BIT11 +#define GPIO_12 BIT12 +#define GPIO_13 BIT13 +#define GPIO_14 BIT14 +#define GPIO_15 BIT15 +#define GPIO_16 BIT16 +#define GPIO_17 BIT17 +#define GPIO_18 BIT18 +#define GPIO_19 BIT19 +#define GPIO_20 BIT20 +#define GPIO_21 BIT21 +#define GPIO_22 BIT22 +#define GPIO_23 BIT23 +#define GPIO_24 BIT24 +#define GPIO_25 BIT25 +#define GPIO_26 BIT26 +#define GPIO_27 BIT27 +#define GPIO_28 BIT28 +#define GPIO_29 BIT29 +#define GPIO_30 BIT30 +#define GPIO_31 BIT31 +/* PORT B */ +#define GPIO_32 BIT0 +#define GPIO_33 BIT1 +#define GPIO_34 BIT2 +#define GPIO_35 BIT3 +#define GPIO_36 BIT4 +#define GPIO_37 BIT5 +#define GPIO_38 BIT6 +#define GPIO_39 BIT7 +#define GPIO_40 BIT8 +#define GPIO_41 BIT9 +#define GPIO_42 BIT10 +#define GPIO_43 BIT11 +#define GPIO_44 BIT12 +#define GPIO_45 BIT13 +#define GPIO_46 BIT14 +#define GPIO_47 BIT15 +#define GPIO_48 BIT16 +#define GPIO_49 BIT17 +#define GPIO_50 BIT18 +#define GPIO_51 BIT19 +#define GPIO_52 BIT20 +#define GPIO_53 BIT21 +#define GPIO_54 BIT22 +#define GPIO_55 BIT23 +#define GPIO_56 BIT24 +#define GPIO_57 BIT25 +#define GPIO_58 BIT26 +#define GPIO_59 BIT27 +#define GPIO_60 BIT28 +#define GPIO_61 BIT29 +#define GPIO_62 BIT30 +#define GPIO_63 BIT31 +/* PORT C */ +#define GPIO_64 BIT0 +#define GPIO_65 BIT1 +#define GPIO_66 BIT2 +#define GPIO_67 BIT3 +#define GPIO_68 BIT4 +#define GPIO_69 BIT5 +#define GPIO_70 BIT6 +#define GPIO_71 BIT7 +#define GPIO_72 BIT8 +#define GPIO_73 BIT9 +#define GPIO_74 BIT10 +#define GPIO_75 BIT11 +#define GPIO_76 BIT12 +#define GPIO_77 BIT13 +#define GPIO_78 BIT14 +#define GPIO_79 BIT15 +#define GPIO_80 BIT16 +#define GPIO_81 BIT17 +#define GPIO_82 BIT18 +#define GPIO_83 BIT19 +#define GPIO_84 BIT20 +#define GPIO_85 BIT21 +#define GPIO_86 BIT22 +#define GPIO_87 BIT23 +#define GPIO_88 BIT24 +#define GPIO_89 BIT25 +#define GPIO_90 BIT26 +#define GPIO_91 BIT27 +#define GPIO_92 BIT28 +#define GPIO_93 BIT29 +#define GPIO_94 BIT30 +#define GPIO_95 BIT31 +/* PORT D */ +#define GPIO_96 BIT0 +#define GPIO_97 BIT1 +#define GPIO_98 BIT2 +#define GPIO_99 BIT3 +#define GPIO_100 BIT4 +#define GPIO_101 BIT5 +#define GPIO_102 BIT6 +#define GPIO_103 BIT7 +#define GPIO_104 BIT8 +#define GPIO_105 BIT9 +#define GPIO_106 BIT10 +#define GPIO_107 BIT11 +#define GPIO_108 BIT12 +#define GPIO_109 BIT13 +#define GPIO_110 BIT14 +#define GPIO_111 BIT15 +#define GPIO_112 BIT16 +#define GPIO_113 BIT17 +#define GPIO_114 BIT18 +#define GPIO_115 BIT19 +#define GPIO_116 BIT20 +#define GPIO_117 BIT21 +#define GPIO_118 BIT22 +#define GPIO_119 BIT23 +#define GPIO_120 BIT24 +#define GPIO_121 BIT25 +#define GPIO_122 BIT26 +#define GPIO_123 BIT27 +#define GPIO_124 BIT28 +#define GPIO_125 BIT29 +#define GPIO_126 BIT30 +#define GPIO_127 BIT31 + +/* + * Most of the GPIO pins can have one of two alternate functions + * in addition to being GPIO + * + * Port A, Alternate Function A + */ +#define PIOA_ASR_MISO BIT0 /* SPI Master In (RX), Slave out */ +#define PIOA_ASR_MOSI BIT1 /* SPI Master Out (TX), Slave In */ +#define PIOA_ASR_SPCK BIT2 /* SPI Clock */ +#define PIOA_ASR_NPCS0 BIT3 /* SPI Chip Select 0 */ +#define PIOA_ASR_NPCS1 BIT4 /* SPI Chip Select 1 */ +#define PIOA_ASR_NPCS2 BIT5 /* SPI Chip Select 2 */ +#define PIOA_ASR_NPCS3 BIT6 /* SPI Chip Select 3 */ +#define PIOA_ASR_ETXCK BIT7 /* EMAC TX Clock */ +#define PIOA_ASR_ETXEN BIT8 /* EMAC TXEN */ +#define PIOA_ASR_ETX0 BIT9 /* EMAC TXD0 */ +#define PIOA_ASR_ETX1 BIT10 /* EMAC TXD1 */ +#define PIOA_ASR_ECRS BIT11 /* EMAC CRS */ +#define PIOA_ASR_ERX0 BIT12 /* EMAC RXD0 */ +#define PIOA_ASR_ERX1 BIT13 /* EMAC RXD1 */ +#define PIOA_ASR_ERXER BIT14 /* EMAC RXER */ +#define PIOA_ASR_EMDC BIT15 /* EMAC MDC */ +#define PIOA_ASR_EMDIO BIT16 /* EMAC MDIO */ +#define PIOA_ASR_TXD0 BIT17 /* USART 0 Receive */ +#define PIOA_ASR_RXD0 BIT18 /* USART 0 Transmit */ +#define PIOA_ASR_SCK0 BIT19 /* USART 0 Clock */ +#define PIOA_ASR_CTS0 BIT20 /* USART 0 CTS */ +#define PIOA_ASR_RTS0 BIT21 /* USART 0 RTS */ +#define PIOA_ASR_RXD2 BIT22 /* USART 2 Receive */ +#define PIOA_ASR_TXD2 BIT23 /* USART 2 Transmit */ +#define PIOA_ASR_SCK2 BIT24 /* USART 2 Clock */ +#define PIOA_ASR_TWD BIT25 /* Two-Wire (I2C) Data */ +#define PIOA_ASR_TWCK BIT26 /* Two-Wire (I2C) Clock */ +#define PIOA_ASR_MCCK BIT27 /* MMC/SD Card Clock */ +#define PIOA_ASR_MCCDA BIT28 /* MMC/SD Card A Command */ +#define PIOA_ASR_MCDA0 BIT29 /* MMC/SD Card A Data 0 */ +#define PIOA_ASR_DRXD BIT30 /* Debug Uart Receive */ +#define PIOA_ASR_DTXD BIT31 /* Debug Uart Transmit */ + +/* Port A, Alternate Function B */ +#define PIOA_BSR_PCK3 BIT0 /* Peripheral Clock 3 */ +#define PIOA_BSR_PCK0 BIT1 /* Peripheral Clock 0 */ +#define PIOA_BSR_IRQ4 BIT2 /* IRQ4 */ +#define PIOA_BSR_IRQ5 BIT3 /* IRQ5 */ +/*#define PIOA_BSR_PCK1 BIT4 Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */ +#define PIOA_BSR_TXD3 BIT5 /* USART 3 Transmit */ +#define PIOA_BSR_RXD3 BIT6 /* USART 3 Receive */ +#define PIOA_BSR_PCK2 BIT7 /* Peripheral Clock 2 */ +#define PIOA_BSR_MCCDB BIT8 /* MMC/SD Card B Command */ +#define PIOA_BSR_MCDB0 BIT9 /* MMC/SD Card B Data 0 */ +#define PIOA_BSR_MCDB1 BIT10 /* MMC/SD Card B Data 1 */ +#define PIOA_BSR_MCDB2 BIT11 /* MMC/SD Card B Data 2 */ +#define PIOA_BSR_MCDB3 BIT12 /* MMC/SD C ard B Data 3 */ +#define PIOA_BSR_TCLK0 BIT13 /* Timer 0 Clock */ +#define PIOA_BSR_TCLK1 BIT14 /* Timer 1 Clck */ +#define PIOA_BSR_TCLK2 BIT15 /* Timer 2 Clock */ +#define PIOA_BSR_IRQ6 BIT16 /* IRQ6 */ +#define PIOA_BSR_TIOA0 BIT17 /* Timer 0 I/O A */ +#define PIOA_BSR_TIOB0 BIT18 /* Timer 0 I/O B */ +#define PIOA_BSR_TIOA1 BIT19 /* Timer 1 I/O A */ +#define PIOA_BSR_TIOB1 BIT20 /* Timer 1 I/O B */ +#define PIOA_BSR_TIOA2 BIT21 /* Timer 2 I/O A */ +#define PIOA_BSR_TIOB2 BIT22 /* Timer 2 I/O B */ +#define PIOA_BSR_IRQ3 BIT23 /* IRQ3 */ +#define PIOA_BSR_PCK1 BIT24 /* Peripheral Clock 1 */ +#define PIOA_BSR_IRQ2 BIT25 /* IRQ2 */ +#define PIOA_BSR_IRQ1 BIT26 /* IRQ1 */ +#define PIOA_BSR_TCLK3 BIT27 /* Timer Block Clock 3 (docs only show 0-2?) */ +#define PIOA_BSR_TCLK4 BIT28 /* Timer Block Clock 4 */ +#define PIOA_BSR_TCLK5 BIT29 /* Timer Block Clock 5 */ +#define PIOA_BSR_CTS2 BIT30 /* USART 2 CTS */ +#define PIOA_BSR_RTS2 BIT31 /* USART 2 RTS */ + +/* Port B, Function A */ +#define PIOB_ASR_TF0 BIT0 /* AC'97/I2S 0 Transmit Frame */ +#define PIOB_ASR_TK0 BIT1 /* AC'97/I2S 0 Transmit Clock */ +#define PIOB_ASR_TD0 BIT2 /* AC'97/I2S 0 Transmit Data */ +#define PIOB_ASR_RD0 BIT3 /* AC'97/I2S 0 Receive Data */ +#define PIOB_ASR_RK0 BIT4 /* AC'97/I2S 0 Receive Clock */ +#define PIOB_ASR_RF0 BIT5 /* AC'97/I2S 0 Receive Frame */ +#define PIOB_ASR_TF1 BIT6 /* AC'97/I2S 1 Transmit Frame */ +#define PIOB_ASR_TK1 BIT7 /* AC'97/I2S 1 Transmit Clock */ +#define PIOB_ASR_TD1 BIT8 /* AC'97/I2S 1 Transmit Data */ +#define PIOB_ASR_RD1 BIT9 /* AC'97/I2S 1 Receive Data */ +#define PIOB_ASR_RK1 BIT10 /* AC'97/I2S 1 Receive Clock */ +#define PIOB_ASR_RF1 BIT11 /* AC'97/I2S 1 Receive Frame */ +#define PIOB_ASR_TF2 BIT12 /* AC'97/I2S 1 Transmit Frame */ +#define PIOB_ASR_TK2 BIT13 /* AC'97/I2S 1 Transmit Clock */ +#define PIOB_ASR_TD2 BIT14 /* AC'97/I2S 1 Transmit Data */ +#define PIOB_ASR_RD2 BIT15 /* AC'97/I2S 1 Receive Data */ +#define PIOB_ASR_RK2 BIT16 /* AC'97/I2S 1 Receive Clock */ +#define PIOB_ASR_RF2 BIT17 /* AC'97/I2S 1 Receive Frame */ +#define PIOB_ASR_RI1 BIT18 /* USART 1 RI */ +#define PIOB_ASR_DTR1 BIT19 /* USART 1 DTR */ +#define PIOB_ASR_TXD1 BIT20 /* USART 1 TXD */ +#define PIOB_ASR_RXD1 BIT21 /* USART 1 RXD */ +#define PIOB_ASR_SCK1 BIT22 /* USART 1 SCK */ +#define PIOB_ASR_DCD1 BIT23 /* USART 1 DCD */ +#define PIOB_ASR_CTS1 BIT24 /* USART 1 CTS */ +#define PIOB_ASR_DSR1 BIT25 /* USART 1 DSR */ +#define PIOB_ASR_RTS1 BIT26 /* USART 1 RTS */ +#define PIOB_ASR_PCK0 BIT27 /* Peripheral Clock 0 */ +#define PIOB_ASR_FIQ BIT28 /* FIQ */ +#define PIOB_ASR_IRQ0 BIT29 /* IRQ0 */ + +/* Port B, Function B */ +#define PIOB_BSR_RTS3 BIT0 /* USART 3 */ +#define PIOB_BSR_CTS3 BIT1 /* USART 3 */ +#define PIOB_BSR_SCK3 BIT2 /* USART 3 */ +#define PIOB_BSR_MCDA1 BIT3 /* MMC/SD Card A, Data 1 */ +#define PIOB_BSR_MCDA2 BIT4 /* MMC/SD Card A, Data 2 */ +#define PIOB_BSR_MCDA3 BIT5 /* MMC/SD Card A, Data 3 */ +#define PIOB_BSR_TIOA3 BIT6 /* Timer 3 IO A */ +#define PIOB_BSR_TIOB3 BIT7 /* Timer 3 IO B */ +#define PIOB_BSR_TIOA4 BIT8 /* Timer 4 IO A */ +#define PIOB_BSR_TIOB4 BIT9 /* Timer 4 IO B */ +#define PIOB_BSR_TIOA5 BIT10 /* Timer 5 IO A */ +#define PIOB_BSR_TIOB5 BIT11 /* Timer 5 IO B */ +#define PIOB_BSR_ETX2 BIT12 /* EMAC TXD2 */ +#define PIOB_BSR_ETX3 BIT13 /* EMAC TXD3 */ +#define PIOB_BSR_ETXER BIT14 /* EMAC TXER */ +#define PIOB_BSR_ERX2 BIT15 /* EMAC RXD2 */ +#define PIOB_BSR_ERX3 BIT16 /* EMAC RXD3 */ +#define PIOB_BSR_ERXDV BIT17 /* EMAC RXDV */ +#define PIOB_BSR_ECOL BIT18 /* EMAC COL */ +#define PIOB_BSR_ERXCK BIT19 /* EMAC RX Clock */ +#define PIOB_BSR_EF100 BIT25 /* EMAC Speed 100 (RMII Only) */ + +/* Port C, Alternate Function A */ +#define PIOC_ASR_BFCK BIT0 /* Burst Flash Clock */ +#define PIOC_ASR_BFRDY BIT1 /* Burst Flash Ready or SMC Card OE */ +#define PIOC_ASR_BFAVD BIT2 /* Burst Flash Address Valid */ +#define PIOC_ASR_BFBAA BIT3 /* Burst Flash Address Advance or SMC Card WE */ +#define PIOC_ASR_BFOE BIT4 /* Burst Flash OE */ +#define PIOC_ASR_BFWE BIT5 /* Burst Flash WE */ +#define PIOC_ASR_NWAIT BIT6 /* WAIT Input */ +#define PIOC_ASR_A23 BIT7 /* A23 */ +#define PIOC_ASR_A24 BIT8 /* A24 */ +#define PIOC_ASR_A25 BIT9 /* A25 or Compact Flash R/W */ +#define PIOC_ASR_NCS4 BIT10 /* CS4 or Compact Flash CS */ +#define PIOC_ASR_NCS5 BIT11 /* CS5 or Compact Flash CE1 */ +#define PIOC_ASR_NCS6 BIT12 /* CS6 or Compact Flash CE2 */ +#define PIOC_ASR_NCS7 BIT13 /* CS7 */ +#define PIOC_ASR_D16 BIT16 /* Databus Bit 16 */ +#define PIOC_ASR_D17 BIT17 /* Databus Bit 17 */ +#define PIOC_ASR_D18 BIT18 /* Databus Bit 18 */ +#define PIOC_ASR_D19 BIT19 /* Databus Bit 19 */ +#define PIOC_ASR_D20 BIT20 /* Databus Bit 20 */ +#define PIOC_ASR_D21 BIT21 /* Databus Bit 21 */ +#define PIOC_ASR_D22 BIT22 /* Databus Bit 22 */ +#define PIOC_ASR_D23 BIT23 /* Databus Bit 23 */ +#define PIOC_ASR_D24 BIT24 /* Databus Bit 24 */ +#define PIOC_ASR_D25 BIT25 /* Databus Bit 25 */ +#define PIOC_ASR_D26 BIT26 /* Databus Bit 26 */ +#define PIOC_ASR_D27 BIT27 /* Databus Bit 27 */ +#define PIOC_ASR_D28 BIT28 /* Databus Bit 28 */ +#define PIOC_ASR_D29 BIT29 /* Databus Bit 29 */ +#define PIOC_ASR_D30 BIT30 /* Databus Bit 30 */ +#define PIOC_ASR_D31 BIT31 /* Databus Bit 31 */ + +/* Port C, Alternate Function B - None */ + +/* Port D, Alternate Function A */ +#define PIOD_ASR_ETX0 BIT0 /* EMAC TXD0 */ +#define PIOD_ASR_ETX1 BIT1 /* EMAC TXD1 */ +#define PIOD_ASR_ETX2 BIT2 /* EMAC TXD2 */ +#define PIOD_ASR_ETX3 BIT3 /* EMAC TXD3 */ +#define PIOD_ASR_ETXEN BIT4 /* EMAC TXEN */ +#define PIOD_ASR_ETXER BIT5 /* EMAC TXER */ +#define PIOD_ASR_DTXD BIT6 /* Debug UART Transmit */ +#define PIOD_ASR_PCK0 BIT7 /* Peripheral Clock 0 */ +#define PIOD_ASR_PCK1 BIT8 /* Peripheral Clock 1 */ +#define PIOD_ASR_PCK2 BIT9 /* Peripheral Clock 2 */ +#define PIOD_ASR_PCK3 BIT10 /* Peripheral Clock 3 */ +#define PIOD_ASR_TD0 BIT15 /* AC'97/I2S 0 Transmit Data */ +#define PIOD_ASR_TD1 BIT16 /* AC'97/I2S 1 Transmit Data */ +#define PIOD_ASR_TD2 BIT17 /* AC'97/I2S 2 Transmit Data */ +#define PIOD_ASR_NPCS1 BIT18 /* SPI Chip Select 1 */ +#define PIOD_ASR_NPCS2 BIT19 /* SPI Chip Select 2 */ +#define PIOD_ASR_NPCS3 BIT20 /* SPI Chip Select 3 */ +#define PIOD_ASR_RTS0 BIT21 /* USART 0 RTS */ +#define PIOD_ASR_RTS1 BIT22 /* USART 1 RTS */ +#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ +#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ +#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ + +/* Port D, Alternate Function B */ + +#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ +#define PIOC_ASR_TCLK BIT8 /* ETM Clock */ +#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ +#define PIOC_ASR_TPS1 BIT10 /* ETM Processor Status 1 */ +#define PIOC_ASR_TPS2 BIT11 /* ETM Processor Status 2 */ +#define PIOC_ASR_TPK0 BIT12 /* ETM Packet Data 0 */ +#define PIOC_ASR_TPK1 BIT13 /* ETM Packet Data 1 */ +#define PIOC_ASR_TPK2 BIT14 /* ETM Packet Data 2 */ +#define PIOC_ASR_TPK3 BIT15 /* ETM Packet Data 3 */ +#define PIOC_ASR_TPK4 BIT16 /* ETM Packet Data 4 */ +#define PIOC_ASR_TPK5 BIT17 /* ETM Packet Data 5 */ +#define PIOC_ASR_TPK6 BIT18 /* ETM Packet Data 6 */ +#define PIOC_ASR_TPK7 BIT19 /* ETM Packet Data 7 */ +#define PIOC_ASR_TPK8 BIT20 /* ETM Packet Data 8 */ +#define PIOC_ASR_TPK9 BIT21 /* ETM Packet Data 9 */ +#define PIOC_ASR_TPK10 BIT22 /* ETM Packet Data 10 */ +#define PIOC_ASR_TPK11 BIT23 /* ETM Packet Data 11 */ +#define PIOC_ASR_TPK12 BIT24 /* ETM Packet Data 12 */ +#define PIOC_ASR_TPK13 BIT25 /* ETM Packet Data 13 */ +#define PIOC_ASR_TPK14 BIT26 /* ETM Packet Data 14 */ +#define PIOC_ASR_TPK15 BIT27 /* ETM Packet Data 15 */ + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_mem.h b/bsps/arm/csb337/include/at91rm9200_mem.h new file mode 100644 index 0000000000..fafb18f6e8 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_mem.h @@ -0,0 +1,115 @@ +/* + * AT91RM9200 Memory Controller definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef AT91RM9200_MEM_H +#define AT91RM9200_MEM_H + +/********************************************************************** + * External Bus Interface Unit + **********************************************************************/ +#define EBI_CSA 0x00 /* Chip Select Assignment Register */ +#define EBI_CFGR 0x04 /* Configuration Register */ + +/* Bit Defines */ +/* EBI_CSA - Chip Select Assignment Register */ +#define EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */ +#define EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */ +#define EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */ +#define EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */ + +/* EBI_CFGR - Configuration Register */ +#define EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */ + +/*************************************************************************** + * Static Memory Interface Unit + ***************************************************************************/ +#define SMC_CSR0 0x00 /* Chip Select Register 0 */ +#define SMC_CSR1 0x04 /* Chip Select Register 1 */ +#define SMC_CSR2 0x08 /* Chip Select Register 2 */ +#define SMC_CSR3 0x0C /* Chip Select Register 3 */ +#define SMC_CSR4 0x10 /* Chip Select Register 4 */ +#define SMC_CSR5 0x14 /* Chip Select Register 5 */ +#define SMC_CSR6 0x18 /* Chip Select Register 6 */ +#define SMC_CSR7 0x1C /* Chip Select Register 7 */ + +/* Bit Defines */ +/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */ +#define SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) /* Hold CS after R/W strobes */ +#define SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) /* Setup CS before R/W strobes */ +#define SMC_CSR_ACSS_0 (0 << 16) /* Setup/Hold Address 0 clocks before/after CS */ +#define SMC_CSR_ACSS_1 (1 << 16) /* Setup/Hold Address 1 clock before/after CS */ +#define SMC_CSR_ACSS_2 (2 << 16) /* Setup/Hold Address 2 clocks before/after CS */ +#define SMC_CSR_ACSS_3 (3 << 16) /* Setup/Hold Address 3 clocks before/after CS */ +#define SMC_CSR_DRP_NORMAL 0 /* 0 = normal read protocol */ +#define SMC_CSR_DRP_EARLY BIT15 /* 1 = early read protocol */ +#define SMC_CSR_DBW_16 (1 << 13) /* CS DataBus Width = 16-Bits */ +#define SMC_CSR_DBW_8 (2 << 13) /* CS DataBus Width = 8 Bits */ +#define SMC_CSR_BAT_16_1 0 /* Single 16-Bit device (when DBW is 16) */ +#define SMC_CSR_BAT_16_2 BIT12 /* Dual 8-Bit devices (when DBW is 16) */ +#define SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) /* Intercycle Data Float Time */ +#define SMC_CSR_WSEN BIT7 /* 1 = wait states are enabled */ +#define SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) /* Wait States + 1 */ + +/* ***************************************************************************** */ +/* SDRAM Memory Interface Unit */ +/* ***************************************************************************** */ +#define SDRC_MR 0x00 /* Mode Register */ +#define SDRC_TR 0x04 /* Refresh Timer Register */ +#define SDRC_CR 0x08 /* Configuration Register */ +#define SDRC_SRR 0x0C /* Self Refresh Register */ +#define SDRC_LPR 0x10 /* Low Power Register */ +#define SDRC_IER 0x14 /* Interrupt Enable Register */ +#define SDRC_IDR 0x18 /* Interrupt Disable Register */ +#define SDRC_IMR 0x1C /* Interrupt Mask Register */ +#define SDRC_ISR 0x20 /* Interrupt Status Register */ + +/* Bit Defines */ +/* SDRC_MR - Mode Register */ +#define SDRC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */ +#define SDRC_MR_NORM (0 << 0) /* Normal Mode - All accesses to SDRAM are decoded normally */ +#define SDRC_MR_NOP (1 << 0) /* NOP Command is sent to SDRAM */ +#define SDRC_MR_PRE (2 << 0) /* Precharge All Command is sent to SDRAM */ +#define SDRC_MR_MRS (3 << 0) /* Mode Register Set Command is sent to SDRAM */ +#define SDRC_MR_REF (4 << 0) /* Refresh Command is sent to SDRAM */ + +/* SDRC_TR - Refresh Timer Register */ +#define SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0) + +/* SDRC_CR - Configuration Register */ +#define SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) /* CKE to ACT Time */ +#define SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) /* ACT to PRE Time */ +#define SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) /* RAS to CAS Time */ +#define SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) /* PRE to ACT Time */ +#define SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) /* REF to ACT Time */ +#define SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) /* Write Recovery Time */ +#define SDRC_CR_CAS_2 (2 << 5) /* Cas Delay = 2, this is the only supported value */ +#define SDRC_CR_NB_2 0 /* 2 Banks per device */ +#define SDRC_CR_NB_4 BIT4 /* 4 Banks per device */ +#define SDRC_CR_NR_11 (0 << 2) /* Number of rows = 11 */ +#define SDRC_CR_NR_12 (1 << 2) /* Number of rows = 12 */ +#define SDRC_CR_NR_13 (2 << 2) /* Number of rows = 13 */ +#define SDRC_CR_NC_8 (0 << 0) /* Number of columns = 8 */ +#define SDRC_CR_NC_9 (1 << 0) /* Number of columns = 9 */ +#define SDRC_CR_NC_10 (2 << 0) /* Number of columns = 10 */ +#define SDRC_CR_NC_11 (3 << 0) /* Number of columns = 11 */ + +/* SDRC_SRR - Self Refresh Register */ +#define SDRC_SRR_SRCB BIT0 /* 1 = Enter Self Refresh */ + +/* SDRC_LPR - Low Power Register */ +#define SDRC_LPR_LPCB BIT0 /* 1 = De-assert CKE between accesses */ + +/* SDRC_IER - Interrupt Enable Register */ +/* SDRC_IDR - Interrupt Disable Register */ +/* SDRC_ISR - Interrupt Mask Register */ +/* SDRC_IMR - Interrupt Mask Register */ +#define SDRC_INT_RES BIT0 /* Refresh Error Status */ + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_pmc.h b/bsps/arm/csb337/include/at91rm9200_pmc.h new file mode 100644 index 0000000000..70cf77fc5a --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_pmc.h @@ -0,0 +1,169 @@ +/* + * AT91RM9200 Power Management and Clock definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __AT91RM9200_PMC_H__ +#define __AT91RM9200_PMC_H__ + +#include + +/*********************************************************************** + * Power Management and Clock Control Register Offsets + ***********************************************************************/ +int at91rm9200_get_mainclk(void); +int at91rm9200_get_slck(void); +int at91rm9200_get_mck(void); + + +#define PMC_SCER 0x00 /* System Clock Enable Register */ +#define PMC_SCDR 0x04 /* System Clock Disable Register */ +#define PMC_SCSR 0x08 /* System Clock Status Register */ +#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ +#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ +#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ +#define PMC_MOR 0x20 /* Main Oscillator Register */ +#define PMC_MCFR 0x24 /* Main Clock Frequency Register */ +#define PMC_PLLAR 0x28 /* PLL A Register */ +#define PMC_PLLBR 0x2C /* PLL B Register */ +#define PMC_MCKR 0x30 /* Master Clock Register */ +#define PMC_PCKR0 0x40 /* Programmable Clock Register 0 */ +#define PMC_PCKR1 0x44 /* Programmable Clock Register 1 */ +#define PMC_PCKR2 0x48 /* Programmable Clock Register 2 */ +#define PMC_PCKR3 0x4C /* Programmable Clock Register 3 */ +#define PMC_PCKR4 0x50 /* Programmable Clock Register 4 */ +#define PMC_PCKR5 0x54 /* Programmable Clock Register 5 */ +#define PMC_PCKR6 0x58 /* Programmable Clock Register 6 */ +#define PMC_PCKR7 0x5C /* Programmable Clock Register 7 */ +#define PMC_IER 0x60 /* Interrupt Enable Register */ +#define PMC_IDR 0x64 /* Interrupt Disable Register */ +#define PMC_SR 0x68 /* Status Register */ +#define PMC_IMR 0x6C /* Interrupt Mask Register */ + +/* Bit Defines */ + +/* PMC_SCDR - System Clock Disable Register */ +/* PMC_SCSR - System Clock Status Register */ +/* PMC_SCER - System Clock Enable Register */ +#define PMC_SCR_PCK7 BIT15 +#define PMC_SCR_PCK6 BIT14 +#define PMC_SCR_PCK5 BIT13 +#define PMC_SCR_PCK4 BIT12 +#define PMC_SCR_PCK3 BIT11 +#define PMC_SCR_PCK2 BIT10 +#define PMC_SCR_PCK1 BIT9 +#define PMC_SCR_PCK0 BIT8 +#define PMC_SCR_UHP BIT4 +#define PMC_SCR_MCKUDP BIT2 +#define PMC_SCR_UDP BIT1 +#define PMC_SCR_PCK BIT0 + +/* PMC_PCER - Peripheral Clock Enable Register */ +/* PMC_PCDR - Peripheral Clock Disable Register */ +/* PMC_PCSR - Peripheral Clock Status Register */ +#define PMC_PCR_PID_EMAC BIT24 /* Ethernet Peripheral Clock */ +#define PMC_PCR_PID_UHP BIT23 /* USB Host Ports Peripheral Clock */ +#define PMC_PCR_PID_TC5 BIT22 /* Timer/Counter 5 Peripheral Clock */ +#define PMC_PCR_PID_TC4 BIT21 /* Timer/Counter 4 Peripheral Clock */ +#define PMC_PCR_PID_TC3 BIT20 /* Timer/Counter 3 Peripheral Clock */ +#define PMC_PCR_PID_TC2 BIT19 /* Timer/Counter 2 Peripheral Clock */ +#define PMC_PCR_PID_TC1 BIT18 /* Timer/Counter 1 Peripheral Clock */ +#define PMC_PCR_PID_TC0 BIT17 /* Timer/Counter 0 Peripheral Clock */ +#define PMC_PCR_PID_SSC2 BIT16 /* Synchronous Serial 2 Peripheral Clock */ +#define PMC_PCR_PID_SSC1 BIT15 /* Synchronous Serial 1 Peripheral Clock */ +#define PMC_PCR_PID_SSC0 BIT14 /* Synchronous Serial 0 Peripheral Clock */ +#define PMC_PCR_PID_SPI BIT13 /* Serial Peripheral Interface Peripheral Clock */ +#define PMC_PCR_PID_TWI BIT12 /* Two-Wire Interface Peripheral Clock */ +#define PMC_PCR_PID_UDP BIT11 /* USB Device Port Peripheral Clock */ +#define PMC_PCR_PID_MCI BIT10 /* MMC/SD Card Peripheral Clock */ +#define PMC_PCR_PID_US3 BIT9 /* USART 3 Peripheral Clock */ +#define PMC_PCR_PID_US2 BIT8 /* USART 2 Peripheral Clock */ +#define PMC_PCR_PID_US1 BIT7 /* USART 1 Peripheral Clock */ +#define PMC_PCR_PID_US0 BIT6 /* USART 0 Peripheral Clock */ +#define PMC_PCR_PID_PIOD BIT5 /* Parallel I/O D Peripheral Clock */ +#define PMC_PCR_PID_PIOC BIT4 /* Parallel I/O C Peripheral Clock */ +#define PMC_PCR_PID_PIOB BIT3 /* Parallel I/O B Peripheral Clock */ +#define PMC_PCR_PID_PIOA BIT2 /* Parallel I/O A Peripheral Clock */ + +/* PMC_MOR - Main Oscillator Register */ +#define PMC_MOR_MOSCEN BIT0 + +/* PMC_MCFR - Main Clock Frequency Register */ +#define PMC_MCFR_MAINRDY BIT16 + +/* PMC_PLLAR - PLL A Register */ +#define PMC_PLLAR_MUST_SET BIT29 /* This bit must be set according to the docs */ +#define PMC_PLLAR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ +#define PMC_PLLAR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ + +#define PMC_PLLAR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ +#define PMC_PLLAR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ +#define PMC_PLLAR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ +#define PMC_PLLAR_DIV_MASK (0xff) /* Divider mask */ + +/* PMC_PLLBR - PLL B Register */ +#define PMC_PLLBR_USB_96M BIT28 /* Set when PLL is 96Mhz to divide it by 2 for USB */ +#define PMC_PLLBR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ +#define PMC_PLLBR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ +#define PMC_PLLBR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ +#define PMC_PLLBR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ +#define PMC_PLLBR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ +#define PMC_PLLBR_DIV_MASK (0xff) /* Divider mask */ + +/* PMC_MCKR - Master Clock Register */ +#define PMC_MCKR_MDIV_MASK (3 << 8) /* for masking out the MDIV field */ +#define PMC_MCKR_MDIV_1 (0 << 8) /* MCK = Core/1 */ +#define PMC_MCKR_MDIV_2 (1 << 8) /* MCK = Core/2 */ +#define PMC_MCKR_MDIV_3 (2 << 8) /* MCK = Core/3 */ +#define PMC_MCKR_MDIV_4 (3 << 8) /* MCK = Core/4 */ +#define PMC_MCKR_PRES_MASK (7 << 2) /* for masking out the PRES field */ +#define PMC_MCKR_PRES_1 (0 << 2) /* Core = CSS/1 */ +#define PMC_MCKR_PRES_2 (1 << 2) /* Core = CSS/2 */ +#define PMC_MCKR_PRES_4 (2 << 2) /* Core = CSS/4 */ +#define PMC_MCKR_PRES_8 (3 << 2) /* Core = CSS/8 */ +#define PMC_MCKR_PRES_16 (4 << 2) /* Core = CSS/16 */ +#define PMC_MCKR_PRES_32 (5 << 2) /* Core = CSS/32 */ +#define PMC_MCKR_PRES_64 (6 << 2) /* Core = CSS/64 */ +#define PMC_MCKR_CSS_MASK (3 << 0) /* for masking out the CSS field */ +#define PMC_MCKR_CSS_SLOW (0 << 0) /* Core Source = Slow Clock */ +#define PMC_MCKR_CSS_MAIN (1 << 0) /* Core Source = Main Oscillator */ +#define PMC_MCKR_CSS_PLLA (2 << 0) /* Core Source = PLL A */ +#define PMC_MCKR_CSS_PLLB (3 << 0) /* Core Source = PLL B */ + +/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */ +#define PMC_PCKR_PRES_1 (0 << 2) /* Peripheral Clock = CSS/1 */ +#define PMC_PCKR_PRES_2 (1 << 2) /* Peripheral Clock = CSS/2 */ +#define PMC_PCKR_PRES_4 (2 << 2) /* Peripheral Clock = CSS/4 */ +#define PMC_PCKR_PRES_8 (3 << 2) /* Peripheral Clock = CSS/8 */ +#define PMC_PCKR_PRES_16 (4 << 2) /* Peripheral Clock = CSS/16 */ +#define PMC_PCKR_PRES_32 (5 << 2) /* Peripheral Clock = CSS/32 */ +#define PMC_PCKR_PRES_64 (6 << 2) /* Peripheral Clock = CSS/64 */ +#define PMC_PCKR_CSS_SLOW (0 << 0) /* Peripheral Clock Source = Slow Clock */ +#define PMC_PCKR_CSS_MAIN (1 << 0) /* Peripheral Clock Source = Main Oscillator */ +#define PMC_PCKR_CSS_PLLA (2 << 0) /* Peripheral Clock Source = PLL A */ +#define PMC_PCKR_CSS_PLLB (3 << 0) /* Peripheral Clock Source = PLL B */ + +/* PMC_IER - Interrupt Enable Register */ +/* PMC_IDR - Interrupt Disable Register */ +/* PMC_SR - Status Register */ +/* PMC_IMR - Interrupt Mask Register */ +#define PMC_INT_PCK7_RDY BIT15 +#define PMC_INT_PCK6_RDY BIT14 +#define PMC_INT_PCK5_RDY BIT13 +#define PMC_INT_PCK4_RDY BIT12 +#define PMC_INT_PCK3_RDY BIT11 +#define PMC_INT_PCK2_RDY BIT10 +#define PMC_INT_PCK1_RDY BIT9 +#define PMC_INT_PCK0_RDY BIT8 +#define PMC_INT_MCK_RDY BIT3 +#define PMC_INT_LOCKB BIT2 +#define PMC_INT_LCKA BIT1 +#define PMC_INT_MOSCS BIT0 + + +#endif diff --git a/bsps/arm/csb337/include/at91rm9200_usart.h b/bsps/arm/csb337/include/at91rm9200_usart.h new file mode 100644 index 0000000000..387f353992 --- /dev/null +++ b/bsps/arm/csb337/include/at91rm9200_usart.h @@ -0,0 +1,146 @@ +/* + * Atmel AT91RM9200_USART Register definitions, used in KIT637_V6 (CSB637) + * + * Copyright (c) 2003 by Cogent Computer Systems + * Written by Mike Kelly + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __AT91RM9200_USART_H__ +#define __AT91RM9200_USART_H__ + +#include + +/* Register Offsets */ +#define US_CR 0x00 /* Control Register */ +#define US_MR 0x04 /* Mode Register */ +#define US_IER 0x08 /* Interrupt Enable Register */ +#define US_IDR 0x0C /* Interrupt Disable Register */ +#define US_IMR 0x10 /* Interrupt Mask Register */ +#define US_SR 0x14 /* Channel Status Register */ +#define US_RHR 0x18 /* Receiver Holding Register */ +#define US_THR 0x1C /* Transmitter Holding Register */ +#define US_BRGR 0x20 /* Baud Rate Generator Register */ +#define US_RTOR 0x24 /* Receiver Time-out Register */ +#define US_TTGR 0x28 /* Transmitter Timeguard Register */ +#define US_C1R 0x40 /* Chip ID1 Register - FI DI Ratio Register */ +#define US_C2R 0x44 /* Chip ID2 Register - Number of Erros Register */ +#define US_FNTR 0x48 /* Force NTRST Register */ +#define US_IF 0x4C /* IrDA Filter Register */ + +/* Bit Defines */ +/* Control Register, US_CR, Offset 0x00 */ +#define US_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ +#define US_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ +#define US_CR_RXEN BIT4 /* 1 = Receiver enable */ +#define US_CR_RXDIS BIT5 /* 1 = Receiver disable */ +#define US_CR_TXEN BIT6 /* 1 = Transmitter enable */ +#define US_CR_TXDIS BIT7 /* 1 = Transmitter disable */ +#define US_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ +#define US_CR_STTBRK BIT9 /* 1 = Start transmission of a Break */ +#define US_CR_STPBRK BIT10 /* 1 = Stop transmission of a Break */ +#define US_CR_STTTO BIT11 /* 1 = Start Time-out */ +#define US_CR_SENDA BIT12 /* 1 = Send Address - MDROP mode only */ +#define US_CR_RSTIT BIT13 /* 1 = Reset Iteration */ +#define US_CR_RSTNACK BIT14 /* 1 = Reset Non Acknowledge */ +#define US_CR_RETTO BIT15 /* 1 = Restart Time-out */ +#define US_CR_DTREN BIT16 /* 1 = Data Terminal Ready Enable - AT91RM9200 only */ +#define US_CR_DTRDIS BIT17 /* 1 = Data Terminal Ready Disable - AT91RM9200 only */ +#define US_CR_RTSEN BIT18 /* 1 = Request To Send Enable */ +#define US_CR_RTSDIS BIT19 /* 1 = Request To Send Disable */ + + +/* Mode Register. US_MR. Offset 0x04 */ +#define US_MR_USMODE (0xF << 0) /* Mode of the USART */ +#define US_MR_USMODE_NORMAL 0 +#define US_MR_USMODE_RS485 1 +#define US_MR_USMODE_HWHS 2 +#define US_MR_USMODE_MODEM 3 +#define US_MR_USMODE_ISO7816_T0 4 +#define US_MR_USMODE_ISO7816_T1 6 +#define US_MR_USMODE_IRDA 8 +#define US_MR_USCLKS (3 << 4) /* Clock Selection */ +#define US_MR_USCLKS_MCK (0 << 4) +#define US_MR_USCLKS_MCK_DIV8 (1 << 4) +#define US_MR_USCLKS_SCK (3 << 4) +#define US_MR_CHRL (3 << 6) /* Character Length */ +#define US_MR_CHRL_5 (0 << 6) +#define US_MR_CHRL_6 (1 << 6) +#define US_MR_CHRL_7 (2 << 6) +#define US_MR_CHRL_8 (3 << 6) +#define US_MR_SYNC (1 << 8) /* Synchronous Mode Select */ +#define US_MR_PAR (7 << 9) /* Parity Type */ +#define US_MR_PAR_EVEN (0 << 9) /* Even Parity */ +#define US_MR_PAR_ODD (1 << 9) /* Odd Parity */ +#define US_MR_PAR_SPACE (2 << 9) /* Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (3 << 9) /* Parity forced to 1 (Mark) */ +#define US_MR_PAR_NONE (4 << 9) /* No Parity */ +#define US_MR_PAR_MDROP (6 << 9) /* Multi-drop mode */ +#define US_MR_NBSTOP (3 << 12) /* Number of Stop Bits */ +#define US_MR_NBSTOP_1 (0 << 12) +#define US_MR_NBSTOP_1_5 (1 << 12) +#define US_MR_NBSTOP_2 (2 << 12) +#define US_MR_CHMODE (3 << 14) /* Channel Mode */ +#define US_MR_CHMODE_NORM (0 << 14) /* Normal Mode */ +#define US_MR_CHMODE_AUTO (1 << 14) /* Auto Echo: RXD drives TXD */ +#define US_MR_CHMODE_LOC (2 << 14) /* Local Loopback: TXD drives RXD */ +#define US_MR_CHMODE_REM (3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ +#define US_MR_MSBF (1 << 16) /* Bit Order */ +#define US_MR_MODE9 (1 << 17) /* 9-bit Character Length */ +#define US_MR_CLKO (1 << 18) /* Clock Output Select */ +#define US_MR_OVER (1 << 19) /* Oversampling Mode */ +#define US_MR_INACK (1 << 20) /* Inhibit Non Acknowledge */ +#define US_MR_DSNACK (1 << 21) /* Disable Successive NACK */ +#define US_MR_MAX_ITER (7 << 24) /* Max Iterations */ +#define US_MR_FILTER (1 << 28) /* Infrared Receive Line Filter */ + +/* Interrupt Enable Register, US_IER, Offset 0x08 */ +/* Interrupt Disable Register, US_IDR, Offset 0x0C */ +/* Interrupt Mask Register, US_IMR, Offset 0x10 */ +/* Channel Status Register, US_SR, Offset 0x14 */ +#define US_IER_RXRDY BIT0 /* RXRDY Interrupt */ +#define US_IER_TXRDY BIT1 /* TXRDY Interrupt */ +#define US_IER_RXBRK BIT2 /* End of Receive Transfer Interrupt */ +#define US_IER_ENDRX BIT3 /* End of Receiver Transfer */ +//#define US_IER_ENDTX BIT4 /* End of Transmit Interrupt */ +#define US_IER_OVRE BIT5 /* Overrun Interrupt */ +#define US_IER_FRAME BIT6 /* Framing Error Interrupt */ +#define US_IER_PARE BIT7 /* Parity Error */ +#define US_IER_TIMEOUT BIT8 /* Receiver Time-out */ +#define US_IER_TXEMPTY BIT9 /* Transmitter Empty */ +#define US_IER_ITERATION BIT10 /* Max number of Repetitions Reached */ +#define US_IER_TXBUFE BIT11 /* Transmission Buffer Empty */ +#define US_IER_RXBUFF BIT12 /* Reception Buffer Full */ +#define US_IER_NACK BIT13 /* Non Acknowledge */ +#define US_IER_RIIC BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */ +#define US_IER_DSRIC BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */ +#define US_IER_DCDIC BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */ +#define US_IER_CTSIC BIT19 /* Clear to Send Input Change */ +#define US_IER_ALL 0xC0001AFB /* all assigned bits */ + +/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */ +#define US_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ + +typedef struct { + volatile uint32_t cr; + volatile uint32_t mr; + volatile uint32_t ier; + volatile uint32_t idr; + volatile uint32_t imr; + volatile uint32_t sr; + volatile uint32_t rhr; + volatile uint32_t thr; + volatile uint32_t brgr; + volatile uint32_t _res0[7]; + volatile uint32_t cidr; + volatile uint32_t exid; + volatile uint32_t fnr; +} at91rm9200_usart_regs_t; + +#endif /* __AT91RM9200_USART_H__ */ diff --git a/bsps/arm/csb337/include/bits.h b/bsps/arm/csb337/include/bits.h new file mode 100644 index 0000000000..6f2c4036b6 --- /dev/null +++ b/bsps/arm/csb337/include/bits.h @@ -0,0 +1,48 @@ +/* + * Bit position definitions + * + * Copyright (c) 2002 by Cogent Computer Systems + * Written by Mike Kelly + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __BITS_H__ +#define __BITS_H__ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* __BITS_H__ */ + diff --git a/bsps/arm/csb337/include/bsp.h b/bsps/arm/csb337/include/bsp.h new file mode 100644 index 0000000000..c99de2fd0a --- /dev/null +++ b/bsps/arm/csb337/include/bsp.h @@ -0,0 +1,78 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Global BSP definitions. + */ + +/* + * CSB337 BSP header file + * + * Copyright (c) 2004 by Cogent Computer Systems + * Writtent by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_CSB337_BSP_H +#define LIBBSP_ARM_CSB337_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_csb337 CSB337 Support + * + * @ingroup bsp_arm + * + * @brief CSB337 support package. + * + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +/* What is the input clock freq in hertz? */ +#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ +#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ + +/* What is the last interrupt? */ +#define BSP_MAX_INT AT91RM9200_MAX_INT + +/* + * forward reference the type to avoid conflicts between libchip serial + * and libchip rtc get and set register types. + */ +typedef struct _console_tbl console_tbl; +console_tbl *BSP_get_uart_from_minor(int minor); + +static inline int32_t BSP_get_baud(void) {return 38400;} + +#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ + +/** + * @brief Network driver configuration + */ +extern struct rtems_bsdnet_ifconfig *config; + +/* Change these to match your board */ +int rtems_at91rm9200_emac_attach(struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_at91rm9200_emac_attach + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/csb337/include/bsp/irq.h b/bsps/arm/csb337/include/bsp/irq.h new file mode 100644 index 0000000000..771059a3e4 --- /dev/null +++ b/bsps/arm/csb337/include/bsp/irq.h @@ -0,0 +1,63 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the AT91RM9200 */ +#define AT91RM9200_INT_FIQ 0 +#define AT91RM9200_INT_SYSIRQ 1 +#define AT91RM9200_INT_PIOA 2 +#define AT91RM9200_INT_PIOB 3 +#define AT91RM9200_INT_PIOC 4 +#define AT91RM9200_INT_PIOD 5 +#define AT91RM9200_INT_US0 6 +#define AT91RM9200_INT_US1 7 +#define AT91RM9200_INT_US2 8 +#define AT91RM9200_INT_US3 9 +#define AT91RM9200_INT_MCI 10 +#define AT91RM9200_INT_UDP 11 +#define AT91RM9200_INT_TWI 12 +#define AT91RM9200_INT_SPI 13 +#define AT91RM9200_INT_SSC0 14 +#define AT91RM9200_INT_SSC1 15 +#define AT91RM9200_INT_SSC2 16 +#define AT91RM9200_INT_TC0 17 +#define AT91RM9200_INT_TC1 18 +#define AT91RM9200_INT_TC2 19 +#define AT91RM9200_INT_TC3 20 +#define AT91RM9200_INT_TC4 21 +#define AT91RM9200_INT_TC5 22 +#define AT91RM9200_INT_UHP 23 +#define AT91RM9200_INT_EMAC 24 +#define AT91RM9200_INT_IRQ0 25 +#define AT91RM9200_INT_IRQ1 26 +#define AT91RM9200_INT_IRQ2 27 +#define AT91RM9200_INT_IRQ3 28 +#define AT91RM9200_INT_IRQ4 28 +#define AT91RM9200_INT_IRQ5 30 +#define AT91RM9200_INT_IRQ6 31 +#define AT91RM9200_MAX_INT 32 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (AT91RM9200_MAX_INT - 1) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/csb337/include/font8x16.h b/bsps/arm/csb337/include/font8x16.h new file mode 100644 index 0000000000..0445b67668 --- /dev/null +++ b/bsps/arm/csb337/include/font8x16.h @@ -0,0 +1,3615 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Simple 8 x 16 font, printable characters only. + */ + +/** + * @defgroup csb337_font Simple 8 x 16 font + * + * @ingroup arm_csb337 + * + * @brief Simple 8 x 16 font, printable characters only. + */ + +/* + * font8x16.h + * + * Simple 8 x 16 font printable Characters only. To lookup, subtract + * FIRST_CHAR from the Character, multiply x FONT_HEIGHT and get the next + * FONT_WIDTH bytes. + * + * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#define FONT_WIDTH 8 +#define FONT_HEIGHT 16 +#define FIRST_CHAR 0x20 +#define LAST_CHAR 0x7F +#define CURSOR_ON 0x7F +#define CURSOR_OFF 0x20 + +const uint8_t font8x16[] = { + + +/* Character (0x20): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ! (0x21): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | **** | + | **** | + | **** | + | **** | + | ** | + | ** | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x3C, +0x3C, +0x3C, +0x3C, +0x18, +0x18, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character " (0x22): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x36, +0x36, +0x36, +0x36, +0x14, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character # (0x23): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + |******* | + | ** ** | + | ** ** | + |******* | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x6C, +0x6C, +0x6C, +0xFE, +0x6C, +0x6C, +0xFE, +0x6C, +0x6C, +0x6C, +0x00, +0x00, +0x00, +0x00, + +/* Character $ (0x24): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ***** | + |** ** | + |** * | + | **** | + | **** | + | * ** | + |** ** | + | ***** | + | ** | + | ** | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x7C, +0xC6, +0xC0, +0x78, +0x3C, +0x06, +0xC6, +0x7C, +0x18, +0x18, +0x00, +0x00, + +/* Character % (0x25): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** * | + | ** ** | + | ** | + | ** | + | ** | + | ** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x62, +0x66, +0x0C, +0x18, +0x30, +0x66, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character & (0x26): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + | *** | + | ** | + | *** ** | + | ****** | + |** ** | + |** ** | + |** ** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x38, +0x6C, +0x38, +0x30, +0x76, +0x7E, +0xCC, +0xCC, +0xCC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character ' (0x27): + ht=16, width=8 + +--------+ + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ( (0x28): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x18, +0x30, +0x30, +0x30, +0x30, +0x30, +0x30, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, + +/* Character ) (0x29): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x30, +0x18, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x18, +0x30, +0x00, +0x00, +0x00, +0x00, + +/* Character * (0x2A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** ** | + | *** | + |******* | + | *** | + | ** ** | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x6C, +0x38, +0xFE, +0x38, +0x6C, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character (0x2B): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | ****** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x18, +0x18, +0x7E, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character , (0x2C): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, + +/* Character - (0x2D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | ****** | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character . (0x2E): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character / (0x2F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | * | + | ** | + | ** | + | ** | + | ** | + | ** | + | * | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x02, +0x06, +0x0C, +0x18, +0x30, +0x60, +0xC0, +0x80, +0x00, +0x00, +0x00, +0x00, + +/* Character 0 (0x30): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** *** | + |** **** | + |**** ** | + |*** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xCE, +0xDE, +0xF6, +0xE6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 1 (0x31): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x78, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character 2 (0x32): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0x06, +0x0C, +0x18, +0x30, +0x60, +0xC6, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character 3 (0x33): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + | ** | + | ** | + | **** | + | ** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0x06, +0x06, +0x3C, +0x06, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 4 (0x34): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | *** | + | **** | + | ** ** | + |** ** | + |** ** | + |******* | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x1C, +0x3C, +0x6C, +0xCC, +0xCC, +0xFE, +0x0C, +0x0C, +0x1E, +0x00, +0x00, +0x00, +0x00, + +/* Character 5 (0x35): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** | + |** | + |** | + |****** | + | ** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC0, +0xC0, +0xC0, +0xFC, +0x06, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 6 (0x36): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** | + |** | + |****** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0xFC, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 7 (0x37): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC6, +0x06, +0x0C, +0x18, +0x30, +0x30, +0x30, +0x30, +0x30, +0x00, +0x00, +0x00, +0x00, + +/* Character 8 (0x38): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character 9 (0x39): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + | ****** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0x7E, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character : (0x3A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | ** | + | ** | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character ; (0x3B): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** | + | ** | + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x00, +0x0C, +0x0C, +0x0C, +0x18, +0x00, +0x00, +0x00, + +/* Character < (0x3C): + ht=16, width=8 + +--------+ + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + |** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x0C, +0x18, +0x30, +0x60, +0xC0, +0x60, +0x30, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, + +/* Character = (0x3D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + |******* | + | | + |******* | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x00, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character > (0x3E): + ht=16, width=8 + +--------+ + | | + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x60, +0x30, +0x18, +0x0C, +0x06, +0x0C, +0x18, +0x30, +0x60, +0x00, +0x00, +0x00, +0x00, + +/* Character ? (0x3F): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + | ** | + | ** | + | ** | + | ** | + | | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0x0C, +0x18, +0x18, +0x18, +0x00, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character @ (0x40): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** **** | + |** **** | + |** **** | + |** *** | + |** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xDE, +0xDE, +0xDE, +0xDC, +0xC0, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character A (0x41): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + |** ** | + |** ** | + |** ** | + |******* | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x38, +0x6C, +0xC6, +0xC6, +0xC6, +0xFE, +0xC6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character B (0x42): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x7C, +0x66, +0x66, +0x66, +0x66, +0xFC, +0x00, +0x00, +0x00, +0x00, + +/* Character C (0x43): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** ** | + |** * | + |** | + |** | + |** | + |** | + |** * | + | ** ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x66, +0xC2, +0xC0, +0xC0, +0xC0, +0xC0, +0xC2, +0x66, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character D (0x44): + ht=16, width=8 + +--------+ + | | + | | + |***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xF8, +0x6C, +0x66, +0x66, +0x66, +0x66, +0x66, +0x66, +0x6C, +0xF8, +0x00, +0x00, +0x00, +0x00, + +/* Character E (0x45): + ht=16, width=8 + +--------+ + | | + | | + |******* | + | ** ** | + | ** | + | ** * | + | ***** | + | ** * | + | ** | + | ** | + | ** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0x66, +0x60, +0x64, +0x7C, +0x64, +0x60, +0x60, +0x66, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character F (0x46): + ht=16, width=8 + +--------+ + | | + | | + |******* | + | ** ** | + | ** | + | ** * | + | ***** | + | ** * | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0x66, +0x60, +0x64, +0x7C, +0x64, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character G (0x47): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** | + |** | + |** | + |** *** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC0, +0xC0, +0xC0, +0xCE, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character H (0x48): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |******* | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xFE, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character I (0x49): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character J (0x4A): + ht=16, width=8 + +--------+ + | | + | | + | **** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |** ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x3C, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0xD8, +0xD8, +0x70, +0x00, +0x00, +0x00, +0x00, + +/* Character K (0x4B): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |**** | + |**** | + |** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xCC, +0xD8, +0xF0, +0xF0, +0xD8, +0xCC, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character L (0x4C): + ht=16, width=8 + +--------+ + | | + | | + |**** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** * | + | ** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xF0, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x62, +0x66, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character M (0x4D): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |*** *** | + |*** *** | + |******* | + |** * ** | + |** * ** | + |** * ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xEE, +0xEE, +0xFE, +0xD6, +0xD6, +0xD6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character N (0x4E): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |*** ** | + |*** ** | + |**** ** | + |** **** | + |** *** | + |** *** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xE6, +0xE6, +0xF6, +0xDE, +0xCE, +0xCE, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character O (0x4F): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character P (0x50): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x66, +0x7C, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character Q (0x51): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** * ** | + |** * ** | + | ***** | + | ** | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xD6, +0xD6, +0x7C, +0x06, +0x00, +0x00, +0x00, + +/* Character R (0x52): + ht=16, width=8 + +--------+ + | | + | | + |****** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | **** | + | ** ** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFC, +0x66, +0x66, +0x66, +0x7C, +0x78, +0x6C, +0x66, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character S (0x53): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + |** ** | + |** | + |** | + | *** | + | *** | + | ** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0x70, +0x1C, +0x06, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character T (0x54): + ht=16, width=8 + +--------+ + | | + | | + | ****** | + | * ** * | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7E, +0x5A, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character U (0x55): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character V (0x56): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x10, +0x00, +0x00, +0x00, +0x00, + +/* Character W (0x57): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + |** * ** | + |** * ** | + |** * ** | + |******* | + |*** *** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xD6, +0xD6, +0xD6, +0xFE, +0xEE, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character X (0x58): + ht=16, width=8 + +--------+ + | | + | | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | *** | + | ** ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x38, +0x6C, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character Y (0x59): + ht=16, width=8 + +--------+ + | | + | | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | **** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x66, +0x66, +0x66, +0x66, +0x66, +0x3C, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character Z (0x5A): + ht=16, width=8 + +--------+ + | | + | | + |******* | + |** ** | + |* ** | + | ** | + | ** | + | ** | + | ** | + |** * | + |** ** | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xFE, +0xC6, +0x86, +0x0C, +0x18, +0x30, +0x60, +0xC2, +0xC6, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character [ (0x5B): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x60, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character \ (0x5C): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + |* | + |** | + | ** | + | ** | + | ** | + | ** | + | ** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x80, +0xC0, +0x60, +0x30, +0x18, +0x0C, +0x06, +0x02, +0x00, +0x00, +0x00, +0x00, + +/* Character ] (0x5D): + ht=16, width=8 + +--------+ + | | + | | + | ***** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x7C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character ^ (0x5E): + ht=16, width=8 + +--------+ + | | + | * | + | *** | + | ** ** | + |** ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x10, +0x38, +0x6C, +0xC6, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character _ (0x5F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + |********| + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0xFF, +0x00, +0x00, + +/* Character ` (0x60): + ht=16, width=8 + +--------+ + | | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x18, +0x18, +0x18, +0x0C, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character A (0x61): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | **** | + | ** | + | ***** | + |** ** | + |** ** | + |** *** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x78, +0x0C, +0x7C, +0xCC, +0xCC, +0xDC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character B (0x62): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x7C, +0x66, +0x66, +0x66, +0x66, +0x66, +0xFC, +0x00, +0x00, +0x00, +0x00, + +/* Character C (0x63): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** | + |** | + |** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0xC0, +0xC0, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character D (0x64): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ****** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x1C, +0x0C, +0x0C, +0x7C, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0x7E, +0x00, +0x00, +0x00, +0x00, + +/* Character E (0x65): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** ** | + |******* | + |** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xFE, +0xC0, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character F (0x66): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** ** | + | ** | + | ** | + |****** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x1C, +0x36, +0x30, +0x30, +0xFC, +0x30, +0x30, +0x30, +0x30, +0x78, +0x00, +0x00, +0x00, +0x00, + +/* Character g (0x67): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | *** ** | + |** *** | + |** ** | + |** ** | + |** *** | + | *** ** | + | ** | + |** ** | + | ***** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x76, +0xCE, +0xC6, +0xC6, +0xCE, +0x76, +0x06, +0xC6, +0x7C, +0x00, +0x00, + +/* Character h (0x68): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ***** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x7C, +0x66, +0x66, +0x66, +0x66, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character i (0x69): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | | + | *** | + | ** | + | ** | + | ** | + | ** | + | ** | + | **** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x00, +0x38, +0x18, +0x18, +0x18, +0x18, +0x18, +0x3C, +0x00, +0x00, +0x00, +0x00, + +/* Character j (0x6A): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | | + | *** | + | ** | + | ** | + | ** | + | ** | + | ** | + |** ** | + |** ** | + | **** | + | | + | | + +--------+ */ +0x00, +0x00, +0x0C, +0x0C, +0x00, +0x1C, +0x0C, +0x0C, +0x0C, +0x0C, +0x0C, +0xCC, +0xCC, +0x78, +0x00, +0x00, + +/* Character k (0x6B): + ht=16, width=8 + +--------+ + | | + | | + |*** | + | ** | + | ** | + | ** ** | + | ** ** | + | ** ** | + | **** | + | ** ** | + | ** ** | + |*** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0xE0, +0x60, +0x60, +0x66, +0x66, +0x6C, +0x78, +0x6C, +0x66, +0xE6, +0x00, +0x00, +0x00, +0x00, + +/* Character l (0x6C): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x18, +0x1C, +0x00, +0x00, +0x00, +0x00, + +/* Character m (0x6D): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ** ** | + |******* | + |** * ** | + |** * ** | + |** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x6C, +0xFE, +0xD6, +0xD6, +0xC6, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character n (0x6E): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x66, +0x66, +0x66, +0x66, +0x66, +0x00, +0x00, +0x00, +0x00, + +/* Character o (0x6F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC6, +0xC6, +0xC6, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character p (0x70): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** ** | + | ** ** | + | ** ** | + | ***** | + | ** | + | ** | + |**** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x66, +0x66, +0x66, +0x7C, +0x60, +0x60, +0xF0, +0x00, +0x00, + +/* Character q (0x71): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | *** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | ***** | + | ** | + | ** | + | **** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x76, +0xCC, +0xCC, +0xCC, +0xCC, +0x7C, +0x0C, +0x0C, +0x1E, +0x00, +0x00, + +/* Character r (0x72): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** *** | + | ** ** | + | ** | + | ** | + | ** | + | ** | + |**** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xDC, +0x66, +0x60, +0x60, +0x60, +0x60, +0xF0, +0x00, +0x00, +0x00, +0x00, + +/* Character s (0x73): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | ***** | + |** ** | + |** | + | ***** | + | ** | + |** ** | + | ***** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x7C, +0xC6, +0xC0, +0x7C, +0x06, +0xC6, +0x7C, +0x00, +0x00, +0x00, +0x00, + +/* Character t (0x74): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + |****** | + | ** | + | ** | + | ** | + | ** | + | ** ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x30, +0x30, +0x30, +0xFC, +0x30, +0x30, +0x30, +0x30, +0x36, +0x1C, +0x00, +0x00, +0x00, +0x00, + +/* Character u (0x75): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + |** ** | + | *** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0xCC, +0x76, +0x00, +0x00, +0x00, +0x00, + +/* Character v (0x76): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + | ** ** | + | *** | + | * | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0x6C, +0x38, +0x10, +0x00, +0x00, +0x00, +0x00, + +/* Character w (0x77): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** * ** | + |** * ** | + |** * ** | + |******* | + | ** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xD6, +0xD6, +0xD6, +0xFE, +0x6C, +0x00, +0x00, +0x00, +0x00, + +/* Character x (0x78): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + | ** ** | + | *** | + | ** ** | + |** ** | + |** ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0x6C, +0x38, +0x6C, +0xC6, +0xC6, +0x00, +0x00, +0x00, +0x00, + +/* Character y (0x79): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |** ** | + |** ** | + |** ** | + |** ** | + |** *** | + | *** ** | + | ** | + |** ** | + | ***** | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xC6, +0xC6, +0xC6, +0xC6, +0xCE, +0x76, +0x06, +0xC6, +0x7C, +0x00, +0x00, + +/* Character z (0x7A): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + |******* | + |* ** | + | ** | + | ** | + | ** | + | ** * | + |******* | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0xFE, +0x86, +0x0C, +0x18, +0x30, +0x62, +0xFE, +0x00, +0x00, +0x00, +0x00, + +/* Character { (0x7B): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ** | + | *** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x0E, +0x18, +0x18, +0x18, +0x70, +0x18, +0x18, +0x18, +0x18, +0x0E, +0x00, +0x00, +0x00, +0x00, + +/* Character | (0x7C): + ht=16, width=8 + +--------+ + | | + | | + | ** | + | ** | + | ** | + | ** | + | | + | ** | + | ** | + | ** | + | ** | + | ** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x18, +0x18, +0x18, +0x18, +0x00, +0x18, +0x18, +0x18, +0x18, +0x18, +0x00, +0x00, +0x00, +0x00, + +/* Character } (0x7D): + ht=16, width=8 + +--------+ + | | + | | + | *** | + | ** | + | ** | + | ** | + | *** | + | ** | + | ** | + | ** | + | ** | + | *** | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x70, +0x18, +0x18, +0x18, +0x0E, +0x18, +0x18, +0x18, +0x18, +0x70, +0x00, +0x00, +0x00, +0x00, + +/* Character ~ (0x7E): + ht=16, width=8 + +--------+ + | | + | | + | *** ** | + |** *** | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x76, +0xDC, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +/* Character DELTA (0x7F): + ht=16, width=8 + +--------+ + | | + | | + | | + | | + | | + | * | + | *** | + | *** | + | ** ** | + | ** ** | + |******* | + | | + | | + | | + | | + | | + +--------+ */ +0x00, +0x00, +0x00, +0x00, +0x00, +0x10, +0x38, +0x38, +0x6C, +0x6C, +0xFE, +0x00, +0x00, +0x00, +0x00, +0x00, +}; diff --git a/bsps/arm/csb337/include/sed1356.h b/bsps/arm/csb337/include/sed1356.h new file mode 100644 index 0000000000..d4451ab7e1 --- /dev/null +++ b/bsps/arm/csb337/include/sed1356.h @@ -0,0 +1,52 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief Public Interface for SED Video Controller Operations. + */ + +/** + * @defgroup csb337_sed1356 SED Video Controller + * + * @ingroup arm_csb337 + * + * @brief Public Interface for SED Video Controller Operations. + */ + +/* + * Public Interface for SED Video Controller Operations + * + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * Modified by Fernando Nicodemos + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SED1356_h +#define __SED1356_h + +void sed_init(void); + +int sed_frame_buffer_size(void); + +void sed_clr_row(int char_row); + +void sed_putchar(char c); + +void sed_putstring(char *s); + +void sed_clearscreen(void); + +void sed_write_frame_buffer( + uint32_t i, + uint16_t wr16 +); + +#endif +/* end of file */ diff --git a/bsps/arm/csb337/include/sed1356_16bit.h b/bsps/arm/csb337/include/sed1356_16bit.h new file mode 100644 index 0000000000..5ccf85d01c --- /dev/null +++ b/bsps/arm/csb337/include/sed1356_16bit.h @@ -0,0 +1,566 @@ +/** + * @file + * + * @ingroup arm_csb337 + * + * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + */ + +/** + * @defgroup csb337_sed1356 SED Video Controller. + * + * @ingroup arm_csb337 + * + * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + */ + +/* + * sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) + * 16-Bit access mode + * + * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * The code has been reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards + * and to eliminate C++ style comments. + */ + +#ifndef __sed1356_16bit_h +#define __sed1356_16bit_h + +#include "bits.h" +/*------------------------------------------------------------------------ + * cpu specific code must define the following board specific macros. + * in cpuio.h. These examples assume the SED135x has been placed in + * the correct endian mode via hardware. + * #define SED_MEM_BASE 0xf0600000 <-- just example addresses, + * #define SED_REG_BASE 0xf0400000 <-- define for each board + * #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry + * #define SED_REG16(_x_) *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers + * #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP))))) + * #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_)) + * Big endian processors + * #define H2SED(_x_) ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8)) + * Little endian + * #define H2SED(_x_) (_x_) + * + */ + +/* + * SED1356 registers - 16-Bit Access Mode. The first register + * referenced is the even addressed register. The byte offsets + * of the odd registers are shown in the comments + */ +#define SED1356_REG_REV_and_MISC SED_REG16(0x00) +#define SED1356_REG_GPIO_CFG SED_REG16(0x04) +#define SED1356_REG_GPIO_CTL SED_REG16(0x08) +#define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c) +#define SED1356_REG_MCLK_CFG SED_REG16(0x10) +#define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14) +#define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18) +#define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c) +#define SED1356_REG_WAIT_STATE SED_REG16(0x1e) +#define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20) +#define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a) +#define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30) +/* LCD Control registers */ +#define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32) +#define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34) +#define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36) +#define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38) +#define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a) +#define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c) +#define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40) +#define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42) +#define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44) +#define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46) +#define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48) +#define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a) +/* CRT/TV Control registers */ +#define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50) +#define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52) +#define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54) +#define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56) +#define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58) +#define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a) +#define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60) +#define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62) +#define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64) +#define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66) +#define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68) +#define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a) +/* LCD Cursor Control Registers */ +#define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70) +#define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72) +#define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74) +#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76) +#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78) +#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a) +#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c) +#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e) +/* CRT Cursor Control Registers */ +#define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80) +#define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82) +#define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84) +#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86) +#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88) +#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a) +#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c) +#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e) +/* BitBlt Control Registers */ +#define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100) +#define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102) +#define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104) +#define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106) +#define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108) +#define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a) +#define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c) +#define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110) +#define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112) +#define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114) +#define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118) +/* Look-Up Table Control Registers */ +#define SED1356_REG_LUT_MODE SED_REG16(0x1e0) +#define SED1356_REG_LUT_ADD SED_REG16(0x1e2) +#define SED1356_REG_LUT_DATA SED_REG16(0x1e4) +/* Power and Miscellaneous Control Registers */ +#define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0) +#define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4) +#define SED1356_REG_DISP_MODE SED_REG16(0x1fc) + +/* + * Bit Assignments - Little Endian, Use H2SED() macro to access + * + * SED1356_REG_REV_and_MISC - even + */ +#define SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */ +#define SED1356_REV_ID_1356 BIT4 +#define SED1356_REV_ID_1355 BIT3 + +/* SED1356_REG_REV_and_MISC - odd */ +#define SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */ + +/* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */ +#define SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */ +#define SED1356_GPIO_GPIO2 BIT2 +#define SED1356_GPIO_GPIO1 BIT1 + +/* SED1356_REG_MCLK_CFG */ +#define SED1356_MCLK_DIV2 BIT4 +#define SED1356_MCLK_SRC_BCLK BIT0 +#define SED1356_MCLK_SRC_CLKI 0x00 + +/* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG + * and SED1356_REG_MEDIA_PCLK_CFG + */ +#define SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */ +#define SED1356_PCLK_DIV1 0x00 << 4 +#define SED1356_PCLK_DIV2 0x01 << 4 +#define SED1356_PCLK_DIV3 0x02 << 4 +#define SED1356_PCLK_DIV4 0x03 << 4 +#define SED1356_PCLK_SRC_CLKI 0x00 +#define SED1356_PCLK_SRC_BCLK 0x01 +#define SED1356_PCLK_SRC_CLKI2 0x02 +#define SED1356_PCLK_SRC_MCLK 0x03 + +/* SED1356_REG_MEM_CFG_and_REF_RATE - even */ +#define SED1356_MEM_CFG_2CAS_EDO 0x00 +#define SED1356_MEM_CFG_2CAS_FPM 0x01 +#define SED1356_MEM_CFG_2WE_EDO 0x02 +#define SED1356_MEM_CFG_2WE_FPM 0x03 +#define SED1356_MEM_CFG_MASK 0x03 + +/* SED1356_REG_MEM_CFG_and_REF_RATE - odd */ +#define SED1356_REF_TYPE_CBR 0x00 << 6 << 8 +#define SED1356_REF_TYPE_SELF 0x01 << 6 << 8 +#define SED1356_REF_TYPE_NONE 0x02 << 6 << 8 +#define SED1356_REF_TYPE_MASK 0x03 << 6 << 8 +#define SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */ +#define SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */ +#define SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */ +#define SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */ +#define SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */ +#define SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */ +#define SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */ +#define SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */ +#define SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */ + +/* SED1356_REG_MEM_TMG0_and_1 - even */ +#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01 +#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01 +#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01 +#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01 +#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00 +#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12 +#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01 +#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00 +#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12 +#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01 +#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12 +#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01 +#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12 +#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12 +#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11 +#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01 + +/* SED1356_REG_MEM_TMG0_and_1 - odd */ +#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8 +#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8 +#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8 +#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8 +#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8 + + +/* Bit definitions + * + * SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even + */ +#define SED1356_PANEL_TYPE_EL BIT7 +#define SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */ +#define SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */ +#define SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */ +#define SED1356_PANEL_TYPE_MASK (0x03 << 4) +#define SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */ +#define SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */ +#define SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */ +#define SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */ + +/* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE, + * SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE + */ +#define SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ +#define SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ +#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */ + +/* SED1356_LCD_DISP_MODE_and_MISC - even */ +#define SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */ +#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */ +#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4) +#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4) +#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4) +#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4) +#define SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ +#define SED1356_LCD_DISP_15BPP 0x04 +#define SED1356_LCD_DISP_8BPP 0x03 +#define SED1356_LCD_DISP_4BPP 0x02 +#define SED1356_LCD_DISP_BPP_MASK 0x07 + +/* SED1356_LCD_DISP_MODE_and_MISC - odd */ +#define SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */ +#define SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */ + +/* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */ +#define SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */ +#define SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */ +#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */ +#define SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */ +#define SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */ + +/* SED1356_REG_CRT_DISP_MODE */ +#define SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */ +#define SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ +#define SED1356_CRT_DISP_15BPP 0x04 +#define SED1356_CRT_DISP_8BPP 0x03 +#define SED1356_CRT_DISP_4BPP 0x02 +#define SED1356_CRT_DISP_BPP_MASK 0x07 + +/* SED1356_DISP_MODE */ +#define SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */ +#define SED1356_DISP_SWIV_90 (0x01 << 6) +#define SED1356_DISP_SWIV_180 (0x00 << 6) +#define SED1356_DISP_SWIV_270 (0x01 << 6) +#define SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */ +#define SED1356_DISP_MODE_LCD 0x01 /* LCD Only */ +#define SED1356_DISP_MODE_CRT 0x02 /* CRT Only */ +#define SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */ +#define SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */ +#define SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */ +#define SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */ +#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */ + +/* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */ +#define SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */ +#define SED1356_PWR_MCLK BIT0 + +/* SED1356_REG_VER_NONDISP */ +#define SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */ + +/* Display size defines */ +extern long PIXELS_PER_ROW; +extern long PIXELS_PER_COL; +#define BYTES_PER_PIXEL 2 +extern long COLS_PER_SCREEN; +extern long ROWS_PER_SCREEN; + +/* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */ +/* LCD Interface, while the LSB of GREEN is loaded as 0 */ +#define RED_SUBPIXEL(n) ((n & 0x1f) << 11) +#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5) +#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0) + +/* define a simple VGA style 16-color pallette */ +#if 0 +#define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) +#define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) +#define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) +#define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) +#define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) +#define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) +#define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17)) +#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) +#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) +#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) +/* RED, GREEN, BLUE Entry */ + { 0x00, 0x00, 0x00, }, /* LU_BLACK */ + { 0x00, 0x00, 0xA0, }, /* LU_BLUE */ + { 0x00, 0xA0, 0x00, }, /* LU_GREEN */ + { 0x00, 0xA0, 0xA0, }, /* LU_CYAN */ + { 0xA0, 0x00, 0x00, }, /* LU_RED */ + { 0xA0, 0x00, 0xA0, }, /* LU_VIOLET */ + { 0xA0, 0xA0, 0x00, }, /* LU_YELLOW */ + { 0xA0, 0xA0, 0xA0, }, /* LU_WHITE */ + { 0x50, 0x50, 0x50, }, /* LU_GREY */ + { 0x50, 0x50, 0xF0, }, /* LU_BRT_BLUE */ + { 0x50, 0xF0, 0x50, }, /* LU_BRT_GREEN */ + { 0x50, 0xF0, 0xF0, }, /* LU_BRT_CYAN */ + { 0xF0, 0x50, 0x50, }, /* LU_BRT_RED */ + { 0xF0, 0x50, 0xF0, }, /* LU_BRT_VIOLET */ + { 0xF0, 0xF0, 0x50, }, /* LU_BRT_YELLOW */ + { 0xF0, 0xF0, 0xF0, }, /* LU_BRT_WHITE */ +#endif + +#define BLUE (0x14 << 0) +#define GREEN (0x14 << 6) +#define RED (0x14 << 11) + +#define HALF_BLUE (0x0a << 0) +#define HALF_GREEN (0x0a << 6) +#define HALF_RED (0x0a << 11) + + +#define BRT_BLUE (0x1e << 0) +#define BRT_GREEN (0x1e << 6) +#define BRT_RED (0x1e << 11) + +#define LU_BLACK 0 +#define LU_BLUE (BLUE) +#define LU_GREEN (GREEN) +#define LU_CYAN (GREEN | BLUE) +#define LU_RED (RED) +#define LU_VIOLET (RED | BLUE) +#define LU_YELLOW (RED | GREEN) +#define LU_WHITE (RED | GREEN | BLUE) +#define LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE) +#define LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE) +#define LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE) +#define LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE) +#define LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE) +#define LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE) +#define LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE) +#define LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE) + +const ushort vga_lookup[] = { +LU_BLACK, /* 0 */ +LU_BLUE, /* 1 */ +LU_GREEN, /* 2 */ +LU_CYAN, /* 3 */ +LU_RED, /* 4 */ +LU_VIOLET, /* 5 */ +LU_YELLOW, /* 6 */ +LU_WHITE, /* 7 */ +LU_GREY, /* 8 */ +LU_BRT_BLUE, /* 9 */ +LU_BRT_GREEN, /* 10 */ +LU_BRT_CYAN, /* 11 */ +LU_BRT_RED, /* 12 */ +LU_BRT_VIOLET, /* 13 */ +LU_BRT_YELLOW, /* 14 */ +LU_BRT_WHITE /* 15 */ +}; + +/* default foreground and background colors */ +#define SED_BG_DEF 1 +#define SED_FG_DEF 14 + +/* Draw defines */ +#define TOP 0 +#define BOTTOM (PIXELS_PER_COL-1) +#define LEFT 0 +#define RIGHT (PIXELS_PER_ROW-1) +#define CENTER_X (PIXELS_PER_ROW/2) +#define CENTER_Y (PIXELS_PER_COL/2) + + +/* Vertical and Horizontal Pulse, Start and Non-Display values vary depending + * upon the mode. The following section gives some insight into how the + * values are arrived at. + * ms = milliseconds, us = microseconds, ns = nanoseconds + * Mhz = Megaherz, Khz = Kiloherz, Hz = Herz + * + * *************************************************************************************************** + * CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns) + * *************************************************************************************************** + * + * CRT MODE HORIZONTAL TIMING PARAMETERS + * + * |<-------Tha------->| + * |___________________| ______ + * Display Enable _____________________| |____________________| + * | | + * Horizontal Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Thp ->| | | | + * | |<-Thbp->| | | + * | |<-Thfp->| + * |<----------------------Tht-------------------->| + * + * Tha - Active Display Time = 640 pixels + * Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels + * Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels + * Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels + * Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz + * + * Correlation between horizontal timing parameters and SED registers + */ +#define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */ +#define SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */ +#define SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */ +/* + * CRT MODE VERTICAL TIMING PARAMTERS + * + * |<-------Tva------->| + * |___________________| ______ + * Display Enable _____________________| |_____________________| + * | | + * Vertical Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Tvp ->| | | | + * | |<-Tvbp->| | | + * | |<-Tvfp->| + * |<----------------------Tvt-------------------->| + * + * Tva - Active Display Time = 480 lines + * Tvp - Vertical Pulse = 3 lines + * Tvfp - Vertical Front Porch = 9 lines + * Tvbp - Vertical Back Porch = 28 lines + * Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz + * + * Correlation between vertical timing parameters and SED registers + */ +#define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 +#define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1 +#define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 +/* + ***************************************************************************************************** + * DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns) + ***************************************************************************************************** + * + * LCD MODE HORIZONTAL TIMING PARAMTERS + * + * |<-------Tha------->| + * |___________________| ______ + * Display Enable _____________________| |____________________| + * | | + * Horizontal Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Thp ->| | | | + * | |<-Thbp->| | | + * | |<-Thfp->| + * |<----------------------Tht-------------------->| + * + * Tha - Active Display Time = 640 pixels + * Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels + * Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels + * Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels + * Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz + * + * Correlation between horizontal timing parameters and SED registers + *#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1 + *#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2 + *#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 + */ +extern long SED_HOR_PULSE_WIDTH_LCD; +extern long SED_HOR_PULSE_START_LCD; +extern long SED_HOR_NONDISP_LCD; + +/* + * + * LCD MODE VERTICAL TIMING PARAMTERS + * + * |<-------Tva------->| + * |___________________| ______ + * Display Enable _____________________| |_____________________| + * | | + * Vertical Pulse __ ________|___________________|________ __________ + * |_________| | | |________| + * |<- Tvp ->| | | | + * | |<-Tvbp->| | | + * | |<-Tvfp->| + * |<----------------------Tvt-------------------->| + * + * Tva - Active Display Time = 480 lines + * Tvp - Vertical Pulse = 2 lines + * Tvfp - Vertical Front Porch = 10 lines + * Tvbp - Vertical Backporch = 33 lines + * Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz + * + * Correlation between vertical timing parameters and SED registers + *#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 + *#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1 + *#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 + */ +extern long SED_VER_PULSE_WIDTH_LCD; +extern long SED_VER_PULSE_START_LCD; +extern long SED_VER_NONDISP_LCD; + +#endif diff --git a/bsps/arm/csb337/include/tm27.h b/bsps/arm/csb337/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/csb337/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/edb7312/headers.am b/bsps/arm/edb7312/headers.am new file mode 100644 index 0000000000..706c1e138e --- /dev/null +++ b/bsps/arm/edb7312/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/ep7312.h +include_HEADERS += ../../../../../../bsps/arm/edb7312/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/edb7312/include/bsp/irq.h diff --git a/bsps/arm/edb7312/include/bsp.h b/bsps/arm/edb7312/include/bsp.h new file mode 100644 index 0000000000..fa7a480970 --- /dev/null +++ b/bsps/arm/edb7312/include/bsp.h @@ -0,0 +1,72 @@ +/** + * @file + * @ingroup arm_edb7312 + * @brief Global BSP definitions. + */ + +/* + * Cirrus EP7312 BSP header file + * + * Copyright (c) 2002 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_EDB7312_BSP_H +#define LIBBSP_ARM_EDB7312_BSP_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +/** + * @defgroup arm_edb7312 EDB7312 Support + * @ingroup bsp_arm + * @brief EDB7312 Support Package + * @{ + */ + +/** + * @brief Define the interrupt mechanism for Time Test 27 + * + * NOTE: Following are not defined and are board independent + * + */ +struct rtems_bsdnet_ifconfig; +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * @name Network driver configuration + * @{ + */ + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach + +/** @} */ + +/* + * Prototypes for methods called from .S but implemented in C + */ +void edb7312_interrupt_dispatch(rtems_vector_number vector); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif /* _BSP_H */ diff --git a/bsps/arm/edb7312/include/bsp/irq.h b/bsps/arm/edb7312/include/bsp/irq.h new file mode 100644 index 0000000000..04579a7c6f --- /dev/null +++ b/bsps/arm/edb7312/include/bsp/irq.h @@ -0,0 +1,92 @@ +/** + * @file + * @ingroup edb7312_interrupt + * @brief Interrupt definitions. + */ + +/* + * Cirrus EP7312 Intererrupt handler + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2002 by Jay Monkman + * + * Copyright (c) 2002 by Charlie Steader + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/** + * @defgroup edb7312_interrupt Interrupt Support + * @ingroup arm_edb7312 + * @brief Interrupt Support + * @{ + */ + +/** + * @name int interrupt status/mask register 1 + * @{ + */ + +#define BSP_EXTFIQ 0 +#define BSP_BLINT 1 +#define BSP_WEINT 2 +#define BSP_MCINT 3 +#define BSP_CSINT 4 +#define BSP_EINT1 5 +#define BSP_EINT2 6 +#define BSP_EINT3 7 +#define BSP_TC1OI 8 +#define BSP_TC2OI 9 +#define BSP_RTCMI 10 +#define BSP_TINT 11 +#define BSP_UTXINT1 12 +#define BSP_URXINT1 13 +#define BSP_UMSINT 14 +#define BSP_SSEOTI 15 + +/** @} */ + +/** + * @name int interrupt status/mask register 2 + * @{ + */ + +#define BSP_KBDINT 16 +#define BSP_SS2RX 17 +#define BSP_SS2TX 18 +#define BSP_UTXINT2 19 +#define BSP_URXINT2 20 + +/** @} */ + +/** + * @name int interrupt status/mask register 3 + * @{ + */ + +#define BSP_DAIINT 21 +#define BSP_MAX_INT 22 + +/** @} */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +/** @} */ + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/edb7312/include/ep7312.h b/bsps/arm/edb7312/include/ep7312.h new file mode 100644 index 0000000000..ba9d430bc6 --- /dev/null +++ b/bsps/arm/edb7312/include/ep7312.h @@ -0,0 +1,218 @@ +/** + * @file + * @ingroup edb7312_registers + * @brief Register declarations. + */ + +/* + * Cirrus EP7312 register declarations + * + * Copyright (c) 2002 by Charlie Steader + * + * Copyright (c) 2002 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Notes: The PLL registers (pll_ro and pll_wo) are either read only + * or write only. The data sheet says not to write the read + * only one or read the write only one. I'm not sure what will + * happen if you do. +*/ +#ifndef __EP7312_H__ +#define __EP7312_H__ + +#define EP7312_REG_BASE 0x80000000 + +/** + * @defgroup edb7312_registers Register Definitions + * @ingroup arm_edb7312 + * @brief Cirrus EP7312 Register Definitions + * @{ + */ + +#define EP7312_PADR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000)) +#define EP7312_PBDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001)) +#define EP7312_PDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003)) +#define EP7312_PADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040)) +#define EP7312_PBDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041)) +#define EP7312_PDDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043)) +#define EP7312_PEDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080)) +#define EP7312_PEDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0)) +#define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100)) +#define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140)) +#define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180)) +#define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0)) +#define EP7312_INTSR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240)) +#define EP7312_INTMR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280)) +#define EP7312_LCDCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0)) +#define EP7312_TC1D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300)) +#define EP7312_TC2D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340)) +#define EP7312_RTCDR ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380)) +#define EP7312_RTCMR ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0)) +#define EP7312_PMPCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400)) +#define EP7312_CODR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440)) +#define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480)) +#define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0)) +#define EP7312_SYNCIO ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500)) +#define EP7312_PALLSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540)) +#define EP7312_PALMSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580)) +#define EP7312_STFCLR ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0)) +#define EP7312_BLEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600)) +#define EP7312_MCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640)) +#define EP7312_TEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680)) +#define EP7312_TC1EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0)) +#define EP7312_TC2EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700)) +#define EP7312_RTCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740)) +#define EP7312_UMSEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780)) +#define EP7312_COEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0)) +#define EP7312_HALT ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800)) +#define EP7312_STDBY ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840)) +#define EP7312_FBADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000)) +#define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100)) +#define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140)) +#define EP7312_INTSR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240)) +#define EP7312_INTMR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280)) +#define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480)) +#define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0)) +#define EP7312_SS2DR ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500)) +#define EP7312_SRXEOF ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600)) +#define EP7312_SS2POP ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0)) +#define EP7312_KBDEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700)) +#define EP7312_DAIR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000)) +#define EP7312_DAIDR0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040)) +#define EP7312_DAIDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080)) +#define EP7312_DAIDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0)) +#define EP7312_DAISR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100)) +#define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200)) +#define EP7312_INTSR3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240)) +#define EP7312_INTMR3 ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280)) +#define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0)) +#define EP7312_SDCONF ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300)) +#define EP7312_SDRFPR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340)) +#define EP7312_UNIQID ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440)) +#define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600)) +#define EP7312_PLLW ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610)) +#define EP7312_PLLR ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8)) +#define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700)) +#define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704)) +#define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708)) +#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C)) + +/* serial port bits */ + +/** + * @name BITS in UBRLCR1 + * @{ + */ + +#define EP7312_UART_WRDLEN5 0x00000000 +#define EP7312_UART_WRDLEN6 0x00020000 +#define EP7312_UART_WRDLEN7 0x00040000 +#define EP7312_UART_WRDLEN8 0x00060000 +#define EP7312_UART_FIFOEN 0x00010000 +#define EP7312_UART_XSTOP 0x00008000 +#define EP7312_UART_EVENPRT 0x00004000 +#define EP7312_UART_PRTEN 0x00002000 +#define EP7312_UART_BREAK 0x00001000 + +/** @} */ + +/** + * @name BITS in INTSR1 + * @{ + */ + +#define EP7312_UART_UTXINT1 0x00002000 +#define EP7312_UART_URXINT1 0x00001000 + +/** @} */ + +/** + * @name BITS in UARTTDR1 + * @{ + */ + +#define EP7312_UART_FRMERR 0x00000100 +#define EP7312_UART_PARERR 0x00000200 +#define EP7312_UART_OVERR 0x00000400 + +/** @} */ + +/** + * @name BITS in system status flag register 1 + * @{ + */ + +#define EP7312_UART_UBUSY1 0x00000800 +#define EP7312_UART_URXFE1 0x00400000 +#define EP7312_UART_UTXFF1 0x00800000 + +/** @} */ + +/* system configuration bits */ + +/** + * @name BITS in SYSCON1 + * @{ + */ + +#define EP7312_SYSCON1_UART1EN 0x00000100 +#define EP7312_SYSCON1_TC1_PRESCALE 0x00000010 +#define EP7312_SYSCON1_TC1_512KHZ 0x00000020 +#define EP7312_SYSCON1_TC2_PRESCALE 0x00000040 +#define EP7312_SYSCON1_TC2_512KHZ 0x00000080 + +/** @} */ + +/** + * @name INTR1 (Interrupt 1) mask/status register bits + * @{ + */ + +#define EP7312_INTR1_EXTFIQ 0x00000001 +#define EP7312_INTR1_BLINT 0x00000002 +#define EP7312_INTR1_WEINT 0x00000004 +#define EP7312_INTR1_MCINT 0x00000008 +#define EP7312_INTR1_CSINT 0x00000010 +#define EP7312_INTR1_EINT1 0x00000020 +#define EP7312_INTR1_EINT2 0x00000040 +#define EP7312_INTR1_EINT3 0x00000080 +#define EP7312_INTR1_TC1OI 0x00000100 +#define EP7312_INTR1_TC2OI 0x00000200 +#define EP7312_INTR1_RTCMI 0x00000400 +#define EP7312_INTR1_TINT 0x00000800 +#define EP7312_INTR1_URXINT1 0x00001000 +#define EP7312_INTR1_UTXINT1 0x00002000 +#define EP7312_INTR1_UMSINT 0x00004000 +#define EP7312_INTR1_SSEOTI 0x00008000 + +/** @} */ + +/** + * @name INTR2 (Interrupt 2) mask/status register bits + * @{ + */ + +#define EP7312_INTR2_KBDINT 0x00000001 +#define EP7312_INTR2_SS2RX 0x00000002 +#define EP7312_INTR2_SS2TX 0x00000004 +#define EP7312_INTR2_URXINT2 0x00001000 +#define EP7312_INTR2_UTXINT2 0x00002000 + +/** @} */ + +/** + * @name INTR3 (Interrupt 3) mask/status register bits + * @{ + */ + +#define EP7312_INTR2_DAIINT 0x00000001 + +/** @} */ + +/** @} */ + +#endif /* __EP7312_H__ */ diff --git a/bsps/arm/edb7312/include/tm27.h b/bsps/arm/edb7312/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/edb7312/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/gdbarmsim/headers.am b/bsps/arm/gdbarmsim/headers.am new file mode 100644 index 0000000000..25e9fcafc7 --- /dev/null +++ b/bsps/arm/gdbarmsim/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/gdbarmsim/include/bsp/swi.h diff --git a/bsps/arm/gdbarmsim/include/bsp.h b/bsps/arm/gdbarmsim/include/bsp.h new file mode 100644 index 0000000000..798fa95cb4 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp.h @@ -0,0 +1,82 @@ +/** + * @file + * + * @ingroup arm_gdbarmsim + * + * @brief Global BSP definitions. + */ + +/* + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_GDBARMSIM_BSP_H +#define LIBBSP_ARM_GDBARMSIM_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_gdbarmsim GDBARMSIM Support + * + * @ingroup bsp_arm + * + * @brief GDBARMSIM support package. + * + * @{ + */ + +//#define BSP_GET_WORK_AREA_DEBUG 1 + +/** + * @brief Support for simulated clock tick + */ +void *clock_driver_sim_idle_body(uintptr_t); +#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body + +/* + * Access to the GDB simulator. + */ +int gdbarmsim_system(const char *); +int gdbarmsim_rename(const char *, const char *); +int gdbarmsim__isatty(int); +clock_t gdbarmsim_times(struct tms *); +int gdbarmsim_gettimeofday(struct timeval *, void *); +int gdbarmsim_unlink(const char *); +int gdbarmsim_link(void); +int gdbarmsim_stat(const char *, struct stat *); +int gdbarmsim_fstat(int, struct stat *); +int gdbarmsim_swistat(int fd, struct stat * st); +int gdbarmsim_close(int); +clock_t gdbarmsim_clock(void); +int gdbarmsim_swiclose(int); +int gdbarmsim_open(const char *, int, ...); +int gdbarmsim_swiopen(const char *, int); +int gdbarmsim_writec(const char c); +int gdbarmsim_write(int, char *, int); +int gdbarmsim_swiwrite(int, char *, int); +int gdbarmsim_lseek(int, int, int); +int gdbarmsim_swilseek(int, int, int); +int gdbarmsim_read(int, char *, int); +int gdbarmsim_swiread(int, char *, int); +void initialise_monitor_handles(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/gdbarmsim/include/bsp/irq.h b/bsps/arm/gdbarmsim/include/bsp/irq.h new file mode 100644 index 0000000000..3c86d22797 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp/irq.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Dummy interrupt definitions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_DUMMY_IRQ_H +#define LIBBSP_ARM_DUMMY_IRQ_H + +#ifndef ASM + +#include +#include +#include + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define DUMMY_IRQ_WDT 0 +#define DUMMY_IRQ_SOFTWARE 1 +#define DUMMY_IRQ_ARM_CORE_0 2 +#define DUMMY_IRQ_ARM_CORE_1 3 +#define DUMMY_IRQ_TIMER_0 4 +#define DUMMY_IRQ_TIMER_1 5 +#define DUMMY_IRQ_UART_0 6 +#define DUMMY_IRQ_UART_1 7 +#define DUMMY_IRQ_PWM 8 +#define DUMMY_IRQ_I2C_0 9 +#define DUMMY_IRQ_SPI_SSP_0 10 +#define DUMMY_IRQ_SSP_1 11 +#define DUMMY_IRQ_PLL 12 +#define DUMMY_IRQ_RTC 13 +#define DUMMY_IRQ_EINT_0 14 +#define DUMMY_IRQ_EINT_1 15 +#define DUMMY_IRQ_EINT_2 16 +#define DUMMY_IRQ_EINT_3 17 +#define DUMMY_IRQ_ADC_0 18 +#define DUMMY_IRQ_I2C_1 19 +#define DUMMY_IRQ_BOD 20 +#define DUMMY_IRQ_ETHERNET 21 +#define DUMMY_IRQ_USB 22 +#define DUMMY_IRQ_CAN 23 +#define DUMMY_IRQ_SD_MMC 24 +#define DUMMY_IRQ_DMA 25 +#define DUMMY_IRQ_TIMER_2 26 +#define DUMMY_IRQ_TIMER_3 27 +#define DUMMY_IRQ_UART_2 28 +#define DUMMY_IRQ_UART_3 29 +#define DUMMY_IRQ_I2C_2 30 +#define DUMMY_IRQ_I2S 31 + +#define DUMMY_IRQ_PRIORITY_VALUE_MIN 0U +#define DUMMY_IRQ_PRIORITY_VALUE_MAX 15U + +/** + * @brief Minimum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MIN DUMMY_IRQ_WDT + +/** + * @brief Maximum vector number. + */ +#define BSP_INTERRUPT_VECTOR_MAX DUMMY_IRQ_I2S + +void bsp_interrupt_dispatch(void); + +#if 0 +void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority); + +unsigned lpc24xx_irq_priority( rtems_vector_number vector); +#endif + +/** @} */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_DUMMY_IRQ_H */ diff --git a/bsps/arm/gdbarmsim/include/bsp/swi.h b/bsps/arm/gdbarmsim/include/bsp/swi.h new file mode 100644 index 0000000000..e9eb434a58 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/bsp/swi.h @@ -0,0 +1,110 @@ +/** + * @file + * + * @ingroup arm_gdbarmsim + * + * @brief Software interrupt definitions. + */ + +/** + * @defgroup gdbarmsim_swi SWI Definitions + * + * @ingroup arm_gdbarmsim + * + * @brief Software interrupt definitions. + */ + +/* + * Copied from libgloss 1 Oct 2009. + * Minor modifications to work with RTEMS. + */ + +/* SWI numbers for RDP (Demon) monitor. */ +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + + +/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */ +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +/* For Thumb-2 code use the BKPT instruction instead of SWI. */ +#ifdef __thumb2__ +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +/* The reason codes: */ +#define AngelSWI_Reason_Open 0x01 +#define AngelSWI_Reason_Close 0x02 +#define AngelSWI_Reason_WriteC 0x03 +#define AngelSWI_Reason_Write0 0x04 +#define AngelSWI_Reason_Write 0x05 +#define AngelSWI_Reason_Read 0x06 +#define AngelSWI_Reason_ReadC 0x07 +#define AngelSWI_Reason_IsTTY 0x09 +#define AngelSWI_Reason_Seek 0x0A +#define AngelSWI_Reason_FLen 0x0C +#define AngelSWI_Reason_TmpNam 0x0D +#define AngelSWI_Reason_Remove 0x0E +#define AngelSWI_Reason_Rename 0x0F +#define AngelSWI_Reason_Clock 0x10 +#define AngelSWI_Reason_Time 0x11 +#define AngelSWI_Reason_System 0x12 +#define AngelSWI_Reason_Errno 0x13 +#define AngelSWI_Reason_GetCmdLine 0x15 +#define AngelSWI_Reason_HeapInfo 0x16 +#define AngelSWI_Reason_EnterSVC 0x17 +#define AngelSWI_Reason_ReportException 0x18 +#define ADP_Stopped_ApplicationExit ((2 << 16) + 38) +#define ADP_Stopped_RunTimeError ((2 << 16) + 35) + +#if defined(ARM_RDI_MONITOR) && !defined(__ASSEMBLER__) + +static inline int +do_AngelSWI (int reason, void * arg) +{ + int value; + __asm__ volatile ("mov r0, %1; mov r1, %2; " AngelSWIInsn " %a3; mov %0, r0" + : "=r" (value) /* Outputs */ + : "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + /* Clobbers r0 and r1, and lr if in supervisor mode */); + /* Accordingly to page 13-77 of ARM DUI 0040D other registers + can also be clobbered. Some memory positions may also be + changed by a system call, so they should not be kept in + registers. Note: we are assuming the manual is right and + Angel is respecting the APCS. */ + return value; +} + +#endif diff --git a/bsps/arm/gdbarmsim/include/tm27.h b/bsps/arm/gdbarmsim/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/gdbarmsim/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/gumstix/headers.am b/bsps/arm/gumstix/headers.am new file mode 100644 index 0000000000..410ad6cf75 --- /dev/null +++ b/bsps/arm/gumstix/headers.am @@ -0,0 +1,12 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/ffuart.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/pxa255.h +include_HEADERS += ../../../../../../bsps/arm/gumstix/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/gumstix/include/bsp/irq.h diff --git a/bsps/arm/gumstix/include/bsp.h b/bsps/arm/gumstix/include/bsp.h new file mode 100644 index 0000000000..caee8f9e19 --- /dev/null +++ b/bsps/arm/gumstix/include/bsp.h @@ -0,0 +1,84 @@ +/** + * @file + * @ingroup arm_gumstix + * @brief Global BSP definitions. + */ + +/* + * By Yang Xi . + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_GUMSTIX_BSP_H +#define LIBBSP_ARM_GUMSTIX_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup arm_gumstix Gumstix Support + * @ingroup bsp_arm + * @brief Gumstix support package + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_HAS_FRAME_BUFFER 1 + +/** @brief What is the input clock freq in hertz */ +#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ +#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ + +/** @brief What is the last interrupt */ +#define BSP_MAX_INT AT91RM9200_MAX_INT + +/* + * forward reference the type to avoid conflicts between libchip serial + * and libchip rtc get and set register types. + */ +typedef struct _console_tbl console_tbl; +console_tbl *BSP_get_uart_from_minor(int minor); + +static inline int32_t BSP_get_baud(void) {return 115200;} + +/** @brief How big should the interrupt stack be? */ +#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) + +#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ + +#define outport_byte(port,val) *((unsigned char volatile*)(port)) = (val) +#define inport_byte(port,val) (val) = *((unsigned char volatile*)(port)) +#define outport_word(port,val) *((unsigned short volatile*)(port)) = (val) +#define inport_word(port,val) (val) = *((unsigned short volatile*)(port)) + +struct rtems_bsdnet_ifconfig; +extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int); +#define BSP_NE2000_NETWORK_DRIVER_NAME "ne1" +#define BSP_NE2000_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach + +#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_NE2000_NETWORK_DRIVER_NAME +#endif + +#ifndef RTEMS_BSP_NETWORK_DRIVER_ATTACH +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_NE2000_NETWORK_DRIVER_ATTACH +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/gumstix/include/bsp/irq.h b/bsps/arm/gumstix/include/bsp/irq.h new file mode 100644 index 0000000000..a8b5d24da1 --- /dev/null +++ b/bsps/arm/gumstix/include/bsp/irq.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. + * + * Interrupt handler Header file for PXA By Yang Xi + * Copyright (c) 2004 by Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (PRIMARY_IRQS - 1) + +#endif /* __asm__ */ + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/gumstix/include/ffuart.h b/bsps/arm/gumstix/include/ffuart.h new file mode 100644 index 0000000000..68df822183 --- /dev/null +++ b/bsps/arm/gumstix/include/ffuart.h @@ -0,0 +1,48 @@ +/* + * FFUART for PXA250 CPU by Yang Xi + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __FFUART_H__ +#define __FFUART_H__ + +typedef struct { + /* + *Receive buffer(DLAB=0).Transmit buffer(DLAB=0). + *Divisor Latch Low(DLAB=1) + */ + volatile unsigned int rbr; + /*Interrupt enable(DLAB=0). Divisor Latch High(DLAB=1)*/ + volatile unsigned int ier; + /*Interrupt identification.FIFO control*/ + volatile unsigned int iir; + /*Line Control*/ + volatile unsigned int lcr; + /*Modem control*/ + volatile unsigned int mcr; + /*Line Status*/ + volatile unsigned int lsr; + /*Modem status*/ + volatile unsigned int msr; + /*Scratch Pad*/ + volatile unsigned int spr; + /*Infrared Selection*/ + volatile unsigned int isr; +} ffuart_reg_t; + + +#define EIGHT_BITS_NOPARITY_1STOPBIT 0x3 +#define DLAB 0x80 + + +/*Divisor = frequency_uart/(16 * BaudRate*)*/ +#define FREQUENCY_UART (14745600) + +#define SEND_EMPTY 0x20 +#define FULL_RECEIVE 0x01 + +#endif + diff --git a/bsps/arm/gumstix/include/pxa255.h b/bsps/arm/gumstix/include/pxa255.h new file mode 100644 index 0000000000..d5f2830c53 --- /dev/null +++ b/bsps/arm/gumstix/include/pxa255.h @@ -0,0 +1,128 @@ +/* + * By Yang Xi . + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __PXA_255_H__ +#define __PXA_255_H__ + +typedef unsigned int word_t; + +/*Interrupt*/ + +#define PRIMARY_IRQS 32 +#define GPIO_IRQS (85 - 2) /* The first two IRQs have level + one interrupts */ +#define GPIO_IRQ 10 + +#define IRQS (PRIMARY_IRQS + GPIO_IRQS) + +/* Interrupt Controller */ +#define INTERRUPT_OFFSET 0xd00000 +#define XSCALE_IRQ_OS_TIMER 26 +#define XSCALE_IRQ_PMU 12 +#define XSCALE_IRQ_STUART 20 +#define XSCALE_IRQ_NETWORK 16 + +#define PMU_IRQ 12 +#define CCNT_IRQ_ENABLE 1UL << 6 +#define PMN1_IRQ_ENABLE 1UL << 5 +#define PMN0_IRQ_ENABLE 1UL << 4 + +#define IODEVICE_VADDR 0x40000000 +#define XSCALE_INT (IODEVICE_VADDR + INTERRUPT_OFFSET) + +#define XSCALE_INT_ICMR (*(volatile word_t *)(XSCALE_INT + 0x04)) /* Mask register */ +#define XSCALE_INT_ICLR (*(volatile word_t *)(XSCALE_INT + 0x08)) /* FIQ / IRQ selection */ +#define XSCALE_INT_ICCR (*(volatile word_t *)(XSCALE_INT + 0x14)) /* Control register */ +#define XSCALE_INT_ICIP (*(volatile word_t *)(XSCALE_INT + 0x00)) /* IRQ pending */ +#define XSCALE_INT_ICFP (*(volatile word_t *)(XSCALE_INT + 0x0c)) /* FIQ pending */ +#define XSCALE_INT_ICPR (*(volatile word_t *)(XSCALE_INT + 0x10)) /* Pending (unmasked) */ + +/* GPIO */ +#define GPIO_OFFSET 0xe00000 +#define PXA_GPIO (IODEVICE_VADDR + GPIO_OFFSET) + +#define PXA_GEDR0 (*(volatile word_t *)(PXA_GPIO + 0x48)) /* GPIO edge detect 0 */ +#define PXA_GEDR1 (*(volatile word_t *)(PXA_GPIO + 0x4C)) /* GPIO edge detect 1 */ +#define PXA_GEDR2 (*(volatile word_t *)(PXA_GPIO + 0x50)) /* GPIO edge detect 2 */ + + +/* PXA2XX Timer */ + +#define TIMER_OFFSET 0x0a00000 +#define CLOCKS_OFFSET 0x1300000 +/*I change the TIMER_RATE to 36864,because when I use 3686400, the period will be calculate + to 30000*/ +#define TIMER_RATE 36864 + +#define XSCALE_TIMERS (IODEVICE_VADDR + TIMER_OFFSET) + +/* Match registers */ +#define XSCALE_OS_TIMER_MR0 (*(volatile word_t *)(XSCALE_TIMERS + 0x00)) +#define XSCALE_OS_TIMER_MR1 (*(volatile word_t *)(XSCALE_TIMERS + 0x04)) +#define XSCALE_OS_TIMER_MR2 (*(volatile word_t *)(XSCALE_TIMERS + 0x08)) +#define XSCALE_OS_TIMER_MR3 (*(volatile word_t *)(XSCALE_TIMERS + 0x0c)) + +/* Interrupt enable register */ +#define XSCALE_OS_TIMER_IER (*(volatile word_t *)(XSCALE_TIMERS + 0x1c)) +/* Watchdog match enable register */ +#define XSCALE_OS_TIMER_WMER (*(volatile word_t *)(XSCALE_TIMERS + 0x18)) +/* Timer count register */ +#define XSCALE_OS_TIMER_TCR (*(volatile word_t *)(XSCALE_TIMERS + 0x10)) +/* Timer status register */ +#define XSCALE_OS_TIMER_TSR (*(volatile word_t *)(XSCALE_TIMERS + 0x14)) + +#define XSCALE_CLOCKS (IODEVICE_VADDR + CLOCKS_VOFFSET) + +#define XSCALE_CLOCKS_CCCR (*(volatile word_t *)(XSCALE_CLOCKS + 0x00)) + +/*Use ffuart port as the console*/ +#define FFUART_BASE 0x40100000 + +/*Write to SKYEYE_MAGIC_ADDRESS to make SKYEYE exit*/ + +#define SKYEYE_MAGIC_ADDRESS (*(volatile word_t *)(0xb0000000)) +#define SKYEYE_MAGIC_NUMBER (0xf0f0f0f0) + +/*PMC*/ +#define PMC_PMNC 0 +#define PMC_CCNT 1 +#define PMC_INTEN 2 +#define PMC_FLAG 3 +#define PMC_EVTSEL 4 +#define PMC_PMN0 5 +#define PMC_PMN1 6 +#define PMC_PMN2 7 +#define PMC_PMN3 8 + +#define PMC_PMNC_E (0x01) +#define PMC_PMNC_PCR (0x01 << 1) +#define PMC_PMNC_CCR (0x01 << 2) +#define PMC_PMNC_CCD (0x01 << 3) +#define PMC_PMNC_PCD (0x01 << 4) + +/*LCD*/ +#define LCCR0 (*(volatile word_t *)(0x44000000)) +#define LCCR1 (*(volatile word_t *)(0x44000004)) +#define LCCR2 (*(volatile word_t *)(0x44000008)) +#define LCCR3 (*(volatile word_t *)(0x4400000C)) + +#define FDADR0 (*(volatile word_t *)(0x44000200)) +#define FSADR0 (*(volatile word_t *)(0x44000204)) +#define FIDR0 (*(volatile word_t *)(0x44000208)) +#define LDCMD0 (*(volatile word_t *)(0x4400020C)) + +#define FDADR1 (*(volatile word_t *)(0x44000210)) +#define FSADR1 (*(volatile word_t *)(0x44000214)) +#define FIDR1 (*(volatile word_t *)(0x44000218)) +#define LDCMD1 (*(volatile word_t *)(0x4400021C)) + +#define LCCR0_ENB 0x00000001 +#define LCCR1_PPL 0x000003FF +#define LCCR2_LPP 0x000003FF +#define LCCR3_BPP 0x07000000 +#endif diff --git a/bsps/arm/gumstix/include/tm27.h b/bsps/arm/gumstix/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/gumstix/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am new file mode 100644 index 0000000000..764a085442 --- /dev/null +++ b/bsps/arm/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/arm/include/cmsis_gcc.h +include_HEADERS += ../../../../../bsps/arm/include/core_cm7.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmFunc.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmInstr.h +include_HEADERS += ../../../../../bsps/arm/include/core_cmSimd.h +include_HEADERS += ../../../../../bsps/arm/include/uart.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a8core-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-clock.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-regs.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-i2s.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-lcd.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-timer.h +include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/start.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/am335x.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/mmu.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/omap3.h +include_libcpu_HEADERS += ../../../../../bsps/arm/include/libcpu/omap_timer.h diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am new file mode 100644 index 0000000000..dd18164254 --- /dev/null +++ b/bsps/arm/imx/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/imx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/imx/include/tm27.h + +include_arm_freescale_imxdir = $(includedir)/arm/freescale/imx +include_arm_freescale_imx_HEADERS = +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h new file mode 100644 index 0000000000..5633de6f50 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 2014 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_ccmvar.h 292565 2015-12-21 20:17:24Z gonzo $ + */ + +#ifndef IMX_CCMVAR_H +#define IMX_CCMVAR_H + +/* + * We need a clock management system that works across unrelated SoCs and + * devices. For now, to keep imx development moving, define some barebones + * functionality that can be shared within the imx family by having each SoC + * implement functions with a common name. + * + * The usb enable functions are best-effort. They turn on the usb otg, host, + * and phy clocks in a SoC-specific manner, but it may take a lot more than that + * to make usb work on a given board. In particular, it can require specific + * pinmux setup of gpio pins connected to external phy parts, voltage regulators + * and overcurrent detectors, and so on. On such boards, u-boot or other early + * board setup code has to handle those things. + */ + +uint32_t imx_ccm_ipg_hz(void); +uint32_t imx_ccm_perclk_hz(void); +uint32_t imx_ccm_sdhci_hz(void); +uint32_t imx_ccm_uart_hz(void); +uint32_t imx_ccm_ahb_hz(void); + +#ifndef __rtems__ +void imx_ccm_usb_enable(device_t _usbdev); +void imx_ccm_usbphy_enable(device_t _phydev); +void imx_ccm_ssi_configure(device_t _ssidev); +void imx_ccm_hdmi_enable(void); +void imx_ccm_ipu_enable(int ipu); + +/* Routines to get and set the arm clock root divisor register. */ +uint32_t imx_ccm_get_cacrr(void); +void imx_ccm_set_cacrr(uint32_t _divisor); +#endif /* __rtems__ */ + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h new file mode 100644 index 0000000000..299ed2bd7a --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_ECSPIREG_H +#define IMX_ECSPIREG_H + +#include + +typedef struct { + uint32_t rxdata; + uint32_t txdata; + uint32_t conreg; +#define IMX_ECSPI_CONREG_BURST_LENGTH(val) BSP_FLD32(val, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_GET(reg) BSP_FLD32GET(reg, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 20, 31) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT(val) BSP_FLD32(val, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define IMX_ECSPI_CONREG_DRCTL(val) BSP_FLD32(val, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define IMX_ECSPI_CONREG_PRE_DIVIDER(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONREG_POST_DIVIDER(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONREG_CHANNEL_MODE(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONREG_SMC BSP_BIT32(3) +#define IMX_ECSPI_CONREG_XCH BSP_BIT32(2) +#define IMX_ECSPI_CONREG_HT BSP_BIT32(1) +#define IMX_ECSPI_CONREG_EN BSP_BIT32(0) + uint32_t configreg; +#define IMX_ECSPI_CONFIGREG_HT_LENGTH(val) BSP_FLD32(val, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL(val) BSP_FLD32(val, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) +#define IMX_ECSPI_CONFIGREG_DATA_CTL(val) BSP_FLD32(val, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_ECSPI_CONFIGREG_SS_POL(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_CTL(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SCLK_POL(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA(val) BSP_FLD32(val, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define IMX_ECSPI_TC BSP_BIT32(7) +#define IMX_ECSPI_RO BSP_BIT32(6) +#define IMX_ECSPI_RF BSP_BIT32(5) +#define IMX_ECSPI_RDR BSP_BIT32(4) +#define IMX_ECSPI_RR BSP_BIT32(3) +#define IMX_ECSPI_TF BSP_BIT32(2) +#define IMX_ECSPI_TDR BSP_BIT32(1) +#define IMX_ECSPI_TE BSP_BIT32(0) + uint32_t intreg; + uint32_t dmareg; +#define IMX_ECSPI_DMAREG_RXTDEN BSP_BIT32(31) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH(val) BSP_FLD32(val, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_ECSPI_DMAREG_RXDEN BSP_BIT32(23) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_DMAREG_TEDEN BSP_BIT32(7) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD(val) BSP_FLD32(val, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t statreg; + uint32_t periodreg; +#define IMX_ECSPI_PERIODREG_CSD_CTL(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSRC BSP_BIT32(15) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD(val) BSP_FLD32(val, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_GET(reg) BSP_FLD32GET(reg, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 14) + uint32_t testreg; +#define IMX_ECSPI_TESTREG_LBC BSP_BIT32(31) +#define IMX_ECSPI_TESTREG_RXCNT(val) BSP_FLD32(val, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_GET(reg) BSP_FLD32GET(reg, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 14) +#define IMX_ECSPI_TESTREG_TXCNT(val) BSP_FLD32(val, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) + uint32_t reserved_24[7]; + uint32_t msgdata; +} imx_ecspi; + +#endif /* IMX_ECSPIREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h new file mode 100644 index 0000000000..924166c70d --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_GPCREG_H +#define IMX_GPCREG_H + +#include + +typedef struct { + uint32_t lpcr_a7_bsc; + uint32_t lpcr_a7_ad; + uint32_t lpcr_m4; + uint32_t reserved_0c[2]; + uint32_t slpcr; + uint32_t reserved_18[2]; + uint32_t mlpcr; + uint32_t pgc_ack_sel_a7; + uint32_t pgc_ack_sel_m4; + uint32_t misc; + uint32_t imr1_core0_a7; + uint32_t imr2_core0_a7; + uint32_t imr3_core0_a7; + uint32_t imr4_core0_a7; + uint32_t imr1_core1_a7; + uint32_t imr2_core1_a7; + uint32_t imr3_core1_a7; + uint32_t imr4_core1_a7; + uint32_t imr1_m4; + uint32_t imr2_m4; + uint32_t imr3_m4; + uint32_t imr4_m4; + uint32_t reserved_60[4]; + uint32_t isr1_a7; + uint32_t isr2_a7; + uint32_t isr3_a7; + uint32_t isr4_a7; + uint32_t isr1_m4; + uint32_t isr2_m4; + uint32_t isr3_m4; + uint32_t isr4_m4; + uint32_t reserved_90[8]; + uint32_t slt0_cfg; + uint32_t slt1_cfg; + uint32_t slt2_cfg; + uint32_t slt3_cfg; + uint32_t slt4_cfg; + uint32_t slt5_cfg; + uint32_t slt6_cfg; + uint32_t slt7_cfg; + uint32_t slt8_cfg; + uint32_t slt9_cfg; + uint32_t reserved_d8[5]; + uint32_t pgc_cpu_mapping; +#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2) +#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1) +#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0) +#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4) +#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3) +#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2) +#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1) +#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0) + uint32_t cpu_pgc_sw_pup_req; + uint32_t reserved_f4; + uint32_t pu_pgc_sw_pup_req; + uint32_t cpu_pgc_sw_pdn_req; + uint32_t reserved_100; + uint32_t pu_pgc_sw_pdn_req; + uint32_t reserved_108[10]; + uint32_t cpu_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status0; + uint32_t a7_mix_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status2; + uint32_t m4_mix_pgc_pup_status0; + uint32_t m4_mix_pgc_pup_status1; + uint32_t m4_mix_pgc_pup_status2; + uint32_t a7_pu_pgc_pup_status0; + uint32_t a7_pu_pgc_pup_status1; + uint32_t a7_pu_pgc_pup_status2; + uint32_t m4_pu_pgc_pup_status0; + uint32_t m4_pu_pgc_pup_status1; + uint32_t m4_pu_pgc_pup_status2; + uint32_t reserved_164[3]; + uint32_t cpu_pgc_pdn_status1; + uint32_t reserved_174[6]; + uint32_t a7_pu_pgc_pdn_status0; + uint32_t a7_pu_pgc_pdn_status1; + uint32_t a7_pu_pgc_pdn_status2; + uint32_t m4_pu_pgc_pdn_status0; + uint32_t m4_pu_pgc_pdn_status1; + uint32_t m4_pu_pgc_pdn_status2; + uint32_t reserved_1a4[3]; + uint32_t a7_mix_pdn_flg; + uint32_t a7_pu_pdn_flg; + uint32_t m4_mix_pdn_flg; + uint32_t m4_pu_pdn_flg; +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6) +#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0) + uint32_t reserved_1c0[400]; + uint32_t pgc_a7core0_ctrl; + uint32_t pgc_a7core0_pupscr; + uint32_t pgc_a7core0_pdnscr; + uint32_t pgc_a7core0_sr; + uint32_t reserved_810[12]; + uint32_t pgc_a7core1_ctrl; + uint32_t pgc_a7core1_pupscr; + uint32_t pgc_a7core1_pdnscr; + uint32_t pgc_a7core1_sr; + uint32_t reserved_850[12]; + uint32_t pgc_a7scu_ctrl; + uint32_t pgc_a7scu_pupscr; + uint32_t pgc_a7scu_pdnscr; + uint32_t pgc_a7scu_sr; + uint32_t pgc_scu_auxsw; + uint32_t reserved_894[11]; + uint32_t pgc_mix_ctrl; + uint32_t pgc_mix_pupscr; + uint32_t pgc_mix_pdnscr; + uint32_t pgc_mix_sr; + uint32_t reserved_8d0[12]; + uint32_t pgc_mipi_ctrl; + uint32_t pgc_mipi_pupscr; + uint32_t pgc_mipi_pdnscr; + uint32_t pgc_mipi_sr; + uint32_t reserved_910[12]; + uint32_t pgc_pcie_ctrl; + uint32_t pgc_pcie_pupscr; + uint32_t pgc_pcie_pdnscr; + uint32_t pgc_pcie_sr; + uint32_t reserved_950[176]; + uint32_t pgc_mipi_auxsw; + uint32_t reserved_c14[15]; + uint32_t pgc_pcie_auxsw; + uint32_t reserved_c54[43]; + uint32_t pgc_hsic_ctrl; + uint32_t pgc_hsic_pupscr; + uint32_t pgc_hsic_pdnscr; + uint32_t pgc_hsic_sr; +} imx_gpc; + +#endif /* IMX_GPCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h new file mode 100644 index 0000000000..0f1b7f13c5 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_I2CREG_H +#define IMX_I2CREG_H + +#include + +typedef struct { + uint16_t iadr; +#define IMX_I2C_IADR_ADR(val) BSP_FLD16(val, 1, 7) +#define IMX_I2C_IADR_ADR_GET(reg) BSP_FLD16GET(reg, 1, 7) +#define IMX_I2C_IADR_ADR_SET(reg, val) BSP_FLD16SET(reg, val, 1, 7) + uint16_t reserved_02; + uint16_t ifdr; +#define IMX_I2C_IFDR_IC(val) BSP_FLD16(val, 0, 5) +#define IMX_I2C_IFDR_IC_GET(reg) BSP_FLD16GET(reg, 0, 5) +#define IMX_I2C_IFDR_IC_SET(reg, val) BSP_FLD16SET(reg, val, 0, 5) + uint16_t reserved_06; + uint16_t i2cr; +#define IMX_I2C_I2CR_IEN BSP_BIT16(7) +#define IMX_I2C_I2CR_IIEN BSP_BIT16(6) +#define IMX_I2C_I2CR_MSTA BSP_BIT16(5) +#define IMX_I2C_I2CR_MTX BSP_BIT16(4) +#define IMX_I2C_I2CR_TXAK BSP_BIT16(3) +#define IMX_I2C_I2CR_RSTA BSP_BIT16(2) + uint16_t reserved_0a; + uint16_t i2sr; +#define IMX_I2C_I2SR_ICF BSP_BIT16(7) +#define IMX_I2C_I2SR_IAAS BSP_BIT16(6) +#define IMX_I2C_I2SR_IBB BSP_BIT16(5) +#define IMX_I2C_I2SR_IAL BSP_BIT16(4) +#define IMX_I2C_I2SR_SRW BSP_BIT16(2) +#define IMX_I2C_I2SR_IIF BSP_BIT16(1) +#define IMX_I2C_I2SR_RXAK BSP_BIT16(0) + uint16_t reserved_0e; + uint16_t i2dr; +#define IMX_I2C_I2DR_DATA(val) BSP_FLD16(val, 0, 7) +#define IMX_I2C_I2DR_DATA_GET(reg) BSP_FLD16GET(reg, 0, 7) +#define IMX_I2C_I2DR_DATA_SET(reg, val) BSP_FLD16SET(reg, val, 0, 7) +} imx_i2c; + +#endif /* IMX_I2CREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h new file mode 100644 index 0000000000..b84fde26de --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2015 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxreg.h 322015 2017-08-03 14:43:41Z ian $ + */ + +#ifndef IMX_IOMUXREG_H +#define IMX_IOMUXREG_H + +#define IMX_IOMUXREG_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) +#define IMX_IOMUXREG_SHIFTIN(__x, __mask) ((__x) * IMX_IOMUXREG_LOWEST_SET_BIT(__mask)) + +#define IMX_IOMUXREG_BIT(n) (1 << (n)) +#define IMX_IOMUXREG_BITS(__m, __n) \ + ((IMX_IOMUXREG_BIT(MAX((__m), (__n)) + 1) - 1) ^ (IMX_IOMUXREG_BIT(MIN((__m), (__n))) - 1)) + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0C +#define IOMUXC_GPR3_HDMI_MASK (3 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2) + +#define IOMUX_GPR13 0x34 +#define IOMUX_GPR13_SATA_PHY_8(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(26, 24)) +#define IOMUX_GPR13_SATA_PHY_7(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(23, 19)) +#define IOMUX_GPR13_SATA_PHY_6(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(18, 16)) +#define IOMUX_GPR13_SATA_SPEED(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 15)) +#define IOMUX_GPR13_SATA_PHY_5(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 14)) +#define IOMUX_GPR13_SATA_PHY_4(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(13, 11)) +#define IOMUX_GPR13_SATA_PHY_3(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(10, 7)) +#define IOMUX_GPR13_SATA_PHY_2(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(6, 2)) +#define IOMUX_GPR13_SATA_PHY_1(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 1)) +#define IOMUX_GPR13_SATA_PHY_0(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 0)) + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h new file mode 100644 index 0000000000..8050b56a84 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h @@ -0,0 +1,49 @@ +/*- + * Copyright (c) 2014 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxvar.h 321938 2017-08-02 18:28:06Z ian $ + */ + +#ifndef IMX_IOMUXVAR_H +#define IMX_IOMUXVAR_H + +/* + * IOMUX interface functions + */ +void iomux_set_function(u_int pin, u_int fn); +void iomux_set_pad(u_int pin, u_int cfg); +u_int iomux_get_pad_config(u_int pin); + +/* + * The IOMUX Controller device has a small set of "general purpose registers" + * which control various aspects of SoC operation that really have nothing to do + * with IO pin assignments or pad control. These functions let other soc level + * code manipulate these values. + */ +uint32_t imx_iomux_gpr_get(u_int regaddr); +void imx_iomux_gpr_set(u_int regaddr, uint32_t val); +void imx_iomux_gpr_set_masked(u_int regaddr, uint32_t clrbits, uint32_t setbits); + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h new file mode 100644 index 0000000000..b5f3490b79 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_SRCREG_H +#define IMX_SRCREG_H + +#include + +typedef struct { + uint32_t scr; +#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_SCR_LOCK BSP_BIT32(30) +#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) + uint32_t a7rcr0; +#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21) +#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13) +#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12) +#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9) +#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8) +#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5) +#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0) + uint32_t a7rcr1; +#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1) + uint32_t m4rcr; +#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30) +#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3) +#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2) +#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1) +#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0) + uint32_t reserved_10; + uint32_t ercr; + uint32_t reserved_18; + uint32_t hsicphy_rcr; + uint32_t usbophy1_rcr; + uint32_t usbophy2_rcr; + uint32_t mipiphy_rcr; + uint32_t pciephy_rcr; + uint32_t reserved_30[10]; + uint32_t sbmr1; + uint32_t srsr; + uint32_t reserved_60[2]; + uint32_t sisr; + uint32_t simr; + uint32_t sbmr2; + uint32_t gpr1; + uint32_t gpr2; + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t reserved_9c[985]; + uint32_t ddrc_rcr; +} imx_src; + +#endif /* IMX_SRCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h new file mode 100644 index 0000000000..35862601e2 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_UARTREG_H +#define IMX_UARTREG_H + +#include + +typedef struct { + uint32_t urxd; +#define IMX_UART_URXD_CHARRDY BSP_BIT32(15) +#define IMX_UART_URXD_ERR BSP_BIT32(14) +#define IMX_UART_URXD_OVRRUN BSP_BIT32(13) +#define IMX_UART_URXD_FRMERR BSP_BIT32(12) +#define IMX_UART_URXD_BRK BSP_BIT32(11) +#define IMX_UART_URXD_PRERR BSP_BIT32(10) +#define IMX_UART_URXD_RX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_URXD_RX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_URXD_RX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_04[15]; + uint32_t utxd; +#define IMX_UART_UTXD_TX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_UTXD_TX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_UTXD_TX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_44[15]; + uint32_t ucr1; +#define IMX_UART_UCR1_ADEN BSP_BIT32(15) +#define IMX_UART_UCR1_ADBR BSP_BIT32(14) +#define IMX_UART_UCR1_TRDYEN BSP_BIT32(13) +#define IMX_UART_UCR1_IDEN BSP_BIT32(12) +#define IMX_UART_UCR1_ICD(val) BSP_FLD32(val, 10, 11) +#define IMX_UART_UCR1_ICD_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define IMX_UART_UCR1_ICD_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define IMX_UART_UCR1_RRDYEN BSP_BIT32(9) +#define IMX_UART_UCR1_RXDMAEN BSP_BIT32(8) +#define IMX_UART_UCR1_IREN BSP_BIT32(7) +#define IMX_UART_UCR1_TXMPTYEN BSP_BIT32(6) +#define IMX_UART_UCR1_RTSDEN BSP_BIT32(5) +#define IMX_UART_UCR1_SNDBRK BSP_BIT32(4) +#define IMX_UART_UCR1_TXDMAEN BSP_BIT32(3) +#define IMX_UART_UCR1_ATDMAEN BSP_BIT32(2) +#define IMX_UART_UCR1_DOZE BSP_BIT32(1) +#define IMX_UART_UCR1_UARTEN BSP_BIT32(0) + uint32_t ucr2; +#define IMX_UART_UCR2_ESCI BSP_BIT32(15) +#define IMX_UART_UCR2_IRTS BSP_BIT32(14) +#define IMX_UART_UCR2_CTSC BSP_BIT32(13) +#define IMX_UART_UCR2_CTS BSP_BIT32(12) +#define IMX_UART_UCR2_ESCEN BSP_BIT32(11) +#define IMX_UART_UCR2_RTEC(val) BSP_FLD32(val, 9, 10) +#define IMX_UART_UCR2_RTEC_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define IMX_UART_UCR2_RTEC_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10) +#define IMX_UART_UCR2_PREN BSP_BIT32(8) +#define IMX_UART_UCR2_PROE BSP_BIT32(7) +#define IMX_UART_UCR2_STPB BSP_BIT32(6) +#define IMX_UART_UCR2_WS BSP_BIT32(5) +#define IMX_UART_UCR2_RTSEN BSP_BIT32(4) +#define IMX_UART_UCR2_ATEN BSP_BIT32(3) +#define IMX_UART_UCR2_TXEN BSP_BIT32(2) +#define IMX_UART_UCR2_RXEN BSP_BIT32(1) +#define IMX_UART_UCR2_SRST BSP_BIT32(0) + uint32_t ucr3; +#define IMX_UART_UCR3_DPEC(val) BSP_FLD32(val, 14, 15) +#define IMX_UART_UCR3_DPEC_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define IMX_UART_UCR3_DPEC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define IMX_UART_UCR3_DTREN BSP_BIT32(13) +#define IMX_UART_UCR3_PARERREN BSP_BIT32(12) +#define IMX_UART_UCR3_FRAERREN BSP_BIT32(11) +#define IMX_UART_UCR3_DSR BSP_BIT32(10) +#define IMX_UART_UCR3_DCD BSP_BIT32(9) +#define IMX_UART_UCR3_RI BSP_BIT32(8) +#define IMX_UART_UCR3_ADNIMP BSP_BIT32(7) +#define IMX_UART_UCR3_RXDSEN BSP_BIT32(6) +#define IMX_UART_UCR3_AIRINTEN BSP_BIT32(5) +#define IMX_UART_UCR3_AWAKEN BSP_BIT32(4) +#define IMX_UART_UCR3_DTRDEN BSP_BIT32(3) +#define IMX_UART_UCR3_RXDMUXSEL BSP_BIT32(2) +#define IMX_UART_UCR3_INVT BSP_BIT32(1) +#define IMX_UART_UCR3_ACIEN BSP_BIT32(0) + uint32_t ucr4; +#define IMX_UART_UCR4_CTSTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UCR4_CTSTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UCR4_CTSTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UCR4_INVR BSP_BIT32(9) +#define IMX_UART_UCR4_ENIRI BSP_BIT32(8) +#define IMX_UART_UCR4_WKEN BSP_BIT32(7) +#define IMX_UART_UCR4_IDDMAEN BSP_BIT32(6) +#define IMX_UART_UCR4_IRSC BSP_BIT32(5) +#define IMX_UART_UCR4_LPBYP BSP_BIT32(4) +#define IMX_UART_UCR4_TCEN BSP_BIT32(3) +#define IMX_UART_UCR4_BKEN BSP_BIT32(2) +#define IMX_UART_UCR4_OREN BSP_BIT32(1) +#define IMX_UART_UCR4_DREN BSP_BIT32(0) + uint32_t ufcr; +#define IMX_UART_UFCR_TXTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UFCR_TXTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UFCR_TXTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UFCR_RFDIV(val) BSP_FLD32(val, 7, 9) +#define IMX_UART_UFCR_RFDIV_GET(reg) BSP_FLD32GET(reg, 7, 9) +#define IMX_UART_UFCR_RFDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 9) +#define IMX_UART_UFCR_DCEDTE BSP_BIT32(6) +#define IMX_UART_UFCR_RXTL(val) BSP_FLD32(val, 0, 5) +#define IMX_UART_UFCR_RXTL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_UART_UFCR_RXTL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t usr1; +#define IMX_UART_USR1_PARITYERR BSP_BIT32(15) +#define IMX_UART_USR1_RTSS BSP_BIT32(14) +#define IMX_UART_USR1_TRDY BSP_BIT32(13) +#define IMX_UART_USR1_RTSD BSP_BIT32(12) +#define IMX_UART_USR1_ESCF BSP_BIT32(11) +#define IMX_UART_USR1_FRAMERR BSP_BIT32(10) +#define IMX_UART_USR1_RRDY BSP_BIT32(9) +#define IMX_UART_USR1_AGTIM BSP_BIT32(8) +#define IMX_UART_USR1_DTRD BSP_BIT32(7) +#define IMX_UART_USR1_RXDS BSP_BIT32(6) +#define IMX_UART_USR1_AIRINT BSP_BIT32(5) +#define IMX_UART_USR1_AWAKE BSP_BIT32(4) +#define IMX_UART_USR1_SAD BSP_BIT32(3) + uint32_t usr2; +#define IMX_UART_USR2_ADET BSP_BIT32(15) +#define IMX_UART_USR2_TXFE BSP_BIT32(14) +#define IMX_UART_USR2_DTRF BSP_BIT32(13) +#define IMX_UART_USR2_IDLE BSP_BIT32(12) +#define IMX_UART_USR2_ACST BSP_BIT32(11) +#define IMX_UART_USR2_RIDELT BSP_BIT32(10) +#define IMX_UART_USR2_RIIN BSP_BIT32(9) +#define IMX_UART_USR2_IRINT BSP_BIT32(8) +#define IMX_UART_USR2_WAKE BSP_BIT32(7) +#define IMX_UART_USR2_DCDDELT BSP_BIT32(6) +#define IMX_UART_USR2_DCDIN BSP_BIT32(5) +#define IMX_UART_USR2_RTSF BSP_BIT32(4) +#define IMX_UART_USR2_TXDC BSP_BIT32(3) +#define IMX_UART_USR2_BRCD BSP_BIT32(2) +#define IMX_UART_USR2_ORE BSP_BIT32(1) +#define IMX_UART_USR2_RDR BSP_BIT32(0) + uint32_t uesc; + uint32_t utim; + uint32_t ubir; + uint32_t ubmr; + uint32_t ubrc; + uint32_t onems; + uint32_t uts; +#define IMX_UART_UTS_FRCPERR BSP_BIT32(13) +#define IMX_UART_UTS_LOOP BSP_BIT32(12) +#define IMX_UART_UTS_DBGEN BSP_BIT32(11) +#define IMX_UART_UTS_LOOPIR BSP_BIT32(10) +#define IMX_UART_UTS_RXDBG BSP_BIT32(9) +#define IMX_UART_UTS_TXEMPTY BSP_BIT32(6) +#define IMX_UART_UTS_RXEMPTY BSP_BIT32(5) +#define IMX_UART_UTS_TXFULL BSP_BIT32(4) +#define IMX_UART_UTS_RXFULL BSP_BIT32(3) +#define IMX_UART_UTS_SOFTRST BSP_BIT32(0) + uint32_t umcr; +#define IMX_UART_UMCR_SLADDR(val) BSP_FLD32(val, 8, 15) +#define IMX_UART_UMCR_SLADDR_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define IMX_UART_UMCR_SLADDR_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define IMX_UART_UMCR_SADEN BSP_BIT32(3) +#define IMX_UART_UMCR_TXB8 BSP_BIT32(2) +#define IMX_UART_UMCR_SLAM BSP_BIT32(1) +#define IMX_UART_UMCR_MDEN BSP_BIT32(0) +} imx_uart; + +#endif /* IMX_UARTREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h new file mode 100644 index 0000000000..e26dfb2cc3 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2012, 2013 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Oleksandr Rybalko under sponsorship + * from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_wdogreg.h 291367 2015-11-26 17:26:52Z ian $ + */ + +#define WDOG_CLK_FREQ 32768 + +#define WDOG_CR_REG 0x00 /* Control Register */ +#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */ +#define WDOG_CR_WT_SHIFT 8 +#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */ +#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */ +#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */ +#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */ +#define WDOG_CR_WDE (1 << 2) /* WDog Enable */ +#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */ +#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */ + +#define WDOG_SR_REG 0x02 /* Service Register */ +#define WDOG_SR_STEP1 0x5555 +#define WDOG_SR_STEP2 0xaaaa + +#define WDOG_RSR_REG 0x04 /* Reset Status Register */ +#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */ +#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */ +#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */ + +#define WDOG_ICR_REG 0x06 /* Interrupt Control Register */ +#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */ +#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */ +#define WDOG_ICR_WTCT_MASK 0x00ff +#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */ + +#define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */ +#define WDOG_MCR_PDE (1 << 0) + diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h new file mode 100644 index 0000000000..b5fb7127df --- /dev/null +++ b/bsps/arm/imx/include/bsp.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_BSP_H +#define LIBBSP_ARM_IMX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_GIC_DIST_BASE 0x31001000 + +#define BSP_ARM_GIC_CPUIF_BASE 0x31002000 + +#define BSP_ARM_A9MPCORE_GT_BASE 0 + +#define BSP_ARM_A9MPCORE_SCU_BASE 0 + +void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq); + +void *imx_get_reg_of_node(const void *fdt, int node); + +int imx_iomux_configure_pins(const void *fdt, uint32_t phandle); + +rtems_vector_number imx_get_irq_of_node( + const void *fdt, + int node, + size_t index +); + +void imx_uart_console_drain(void); + +/** + * @brief Registers an IMX I2C bus driver. + * + * @param[in] bus_path The I2C bus driver device path, e.g. "/dev/i2c-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "i2c0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int i2c_bus_register_imx(const char *bus_path, const char *alias_or_path); + +/** + * @brief Registers an IMX ECSPI bus driver. + * + * @param[in] bus_path The ECSPI bus driver device path, e.g. "/dev/spi-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "spi0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int spi_bus_register_imx(const char *bus_path, const char *alias_or_path); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_BSP_H */ diff --git a/bsps/arm/imx/include/bsp/irq.h b/bsps/arm/imx/include/bsp/irq.h new file mode 100644 index 0000000000..73d2e69b30 --- /dev/null +++ b/bsps/arm/imx/include/bsp/irq.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_IRQ_H +#define LIBBSP_ARM_IMX_IRQ_H + +#ifndef ASM + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 159 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_IRQ_H */ diff --git a/bsps/arm/imx/include/tm27.h b/bsps/arm/imx/include/tm27.h new file mode 100644 index 0000000000..c17c0107b4 --- /dev/null +++ b/bsps/arm/imx/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/include/bsp/arm-a8core-start.h b/bsps/arm/include/bsp/arm-a8core-start.h new file mode 100644 index 0000000000..416f282028 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a8core-start.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A8CORE_START Support + */ + +/* + * Copyright (c) 2014 Chris Johns . All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A8CORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A8CORE_START_H + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline arm_a8core_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline arm_a8core_start_hook_1(void) +{ + arm_a8core_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A8CORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-clock.h b/bsps/arm/include/bsp/arm-a9mpcore-clock.h new file mode 100644 index 0000000000..9a8c653801 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-clock.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013 Chris Johns . All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Return the peripheral clock. For systems such as the zynq this + * is controlled by the PL logic generation and can vary. Provide this + * function in your application to override the BSP default. + */ +uint32_t a9mpcore_clock_periphclk(void); + +/** + * @brief Do early clock initialization so that the CPU counter conversion + * works. + */ +static inline void a9mpcore_clock_initialize_early(void) +{ + rtems_counter_initialize_converter(a9mpcore_clock_periphclk()); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-irq.h b/bsps/arm/include/bsp/arm-a9mpcore-irq.h new file mode 100644 index 0000000000..f0d3c1b983 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-irq.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_IRQ Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define A9MPCORE_IRQ_GT 27 +#define A9MPCORE_IRQ_NFIQ 28 +#define A9MPCORE_IRQ_PT 29 +#define A9MPCORE_IRQ_PW 30 +#define A9MPCORE_IRQ_NIRQ 31 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-regs.h b/bsps/arm/include/bsp/arm-a9mpcore-regs.h new file mode 100644 index 0000000000..d1538357d8 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-regs.h @@ -0,0 +1,133 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_REGS Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H + +#include + +typedef struct { + uint32_t ctrl; +#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0) +#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1) +#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2) +#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3) +#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4) +#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5) +#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6) + uint32_t cfg; +#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) + uint32_t pwrst; + uint32_t invss; +#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) +#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved_09[8]; + uint32_t diagn_ctrl; +#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) + uint32_t reserved_10[3]; + uint32_t fltstart; + uint32_t fltend; + uint32_t reserved_48[2]; + uint32_t sac; + uint32_t snsac; +} a9mpcore_scu; + +typedef struct { +} a9mpcore_gic; + +typedef struct { + uint32_t cntrlower; + uint32_t cntrupper; +#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3) +#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1) +#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t ctrl; +#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0) + uint32_t irqst; + uint32_t cmpvallower; + uint32_t cmpvalupper; + uint32_t autoinc; +} a9mpcore_gt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; +#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1) +#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t irqst; +#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0) +} a9mpcore_pt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; + uint32_t irqst; + uint32_t rstst; + uint32_t dis; +} a9mpcore_pw; + +typedef struct { +} a9mpcore_idist; + +typedef struct { + a9mpcore_scu scu; + uint32_t reserved_58[42]; + a9mpcore_gic gic; + uint32_t reserved_100[64]; + a9mpcore_gt gt; + uint32_t reserved_21c[249]; + a9mpcore_pt pt; + uint32_t reserved_610[4]; + a9mpcore_pw pw; + uint32_t reserved_638[626]; + a9mpcore_idist idist; +} a9mpcore; + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h b/bsps/arm/include/bsp/arm-a9mpcore-start.h new file mode 100644 index 0000000000..7d6185b39e --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h @@ -0,0 +1,172 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A9MPCORE_START Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H + +#include + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + /* + * For now we assume that every Cortex-A9 MPCore has the Security Extensions. + * Later it might be necessary to evaluate the ID_PFR1 register. + */ + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate( + volatile a9mpcore_scu *scu, + uint32_t cpu_id, + uint32_t ways +) +{ + scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu) +{ + if (arm_errata_is_applicable_processor_errata_764369()) { + scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE; + } +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu) +{ + scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN; + arm_a9mpcore_start_errata_764369_handler(scu); +} + +#ifdef RTEMS_SMP +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_on_secondary_processor(void) +{ + uint32_t ctrl; + + arm_a9mpcore_start_set_vector_base(); + + arm_gic_irq_initialize_secondary_cpu(); + + ctrl = arm_cp15_start_setup_mmu_and_cache( + 0, + ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z + ); + + arm_cp15_set_domain_access_control( + ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) + ); + + /* FIXME: Sharing the translation table between processors is brittle */ + arm_cp15_set_translation_table_base( + (uint32_t *) bsp_translation_table_base + ); + + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + arm_cp15_set_control(ctrl); + + _SMP_Start_multitasking_on_secondary_processor(); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_enable_smp_in_auxiliary_control(void) +{ + /* + * Enable cache coherency support and cache/MMU maintenance broadcasts for + * this processor. + */ + uint32_t actlr = arm_cp15_get_auxiliary_control(); + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; + arm_cp15_set_auxiliary_control(actlr); +} +#endif + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) +{ + volatile a9mpcore_scu *scu = + (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE; + uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); + + arm_cp15_branch_predictor_invalidate_all(); + + if (cpu_id == 0) { + arm_a9mpcore_start_scu_enable(scu); + } + +#ifdef RTEMS_SMP + arm_a9mpcore_start_enable_smp_in_auxiliary_control(); +#endif + + arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf); + +#ifdef RTEMS_SMP + if (cpu_id != 0) { + arm_a9mpcore_start_on_secondary_processor(); + } +#endif +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void) +{ + volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE; + + gt->ctrl = 0; + gt->cntrlower = 0; + gt->cntrupper = 0; + gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN; +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void) +{ + arm_a9mpcore_start_global_timer(); + arm_a9mpcore_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-cp15-start.h b/bsps/arm/include/bsp/arm-cp15-start.h new file mode 100644 index 0000000000..a749f7dc98 --- /dev/null +++ b/bsps/arm/include/bsp/arm-cp15-start.h @@ -0,0 +1,187 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief Arm CP15 start. + */ + + +/* + * Copyright (c) 2013 Hesham AL-Matary. + * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H +#define LIBBSP_ARM_SHARED_ARM_CP15_START_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t begin; + uint32_t end; + uint32_t flags; +} arm_cp15_start_section_config; + +#define ARMV7_CP15_START_DEFAULT_SECTIONS \ + { \ + .begin = (uint32_t) bsp_section_fast_text_begin, \ + .end = (uint32_t) bsp_section_fast_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_fast_data_begin, \ + .end = (uint32_t) bsp_section_fast_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_start_begin, \ + .end = (uint32_t) bsp_section_start_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_vector_begin, \ + .end = (uint32_t) bsp_section_vector_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_text_begin, \ + .end = (uint32_t) bsp_section_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_rodata_begin, \ + .end = (uint32_t) bsp_section_rodata_end, \ + .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_data_begin, \ + .end = (uint32_t) bsp_section_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_bss_begin, \ + .end = (uint32_t) bsp_section_bss_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_work_begin, \ + .end = (uint32_t) bsp_section_work_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_stack_begin, \ + .end = (uint32_t) bsp_section_stack_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_nocache_begin, \ + .end = (uint32_t) bsp_section_nocache_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_section_nocachenoload_begin, \ + .end = (uint32_t) bsp_section_nocachenoload_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_translation_table_base, \ + .end = (uint32_t) bsp_translation_table_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + } + +BSP_START_DATA_SECTION extern const arm_cp15_start_section_config + arm_cp15_start_mmu_config_table[]; + +BSP_START_DATA_SECTION extern const size_t + arm_cp15_start_mmu_config_table_size; + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_set_translation_table_entries( + uint32_t *ttb, + const arm_cp15_start_section_config *config +) +{ + uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); + uint32_t iend = + ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); + uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U; + + if (config->begin != config->end) { + while (i != iend) { + ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; + i = (i + 1U) & index_mask; + } + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table( + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT); + size_t i; + + arm_cp15_set_domain_access_control(dac); + arm_cp15_set_translation_table_base(ttb); + + /* Initialize translation table with invalid entries */ + for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { + ttb [i] = 0; + } + + for (i = 0; i < config_count; ++i) { + arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]); + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( + uint32_t ctrl, + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + arm_cp15_start_setup_translation_table( + ttb, + client_domain, + config_table, + config_count + ); + + /* Enable MMU and cache */ + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + + arm_cp15_set_control(ctrl); +} + +BSP_START_TEXT_SECTION static inline uint32_t +arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set) +{ + uint32_t ctrl = arm_cp15_get_control(); + + ctrl &= ~ctrl_clear; + ctrl |= ctrl_set; + + arm_cp15_set_control(ctrl); + + arm_cp15_tlb_invalidate(); + + return ctrl; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */ diff --git a/bsps/arm/include/bsp/arm-errata.h b/bsps/arm/include/bsp/arm-errata.h new file mode 100644 index 0000000000..5108c98f15 --- /dev/null +++ b/bsps/arm/include/bsp/arm-errata.h @@ -0,0 +1,121 @@ +/** + * @file arm-errata.h + * + * @ingroup arm_shared + * + * @brief Create #defines which state which erratas shall get applied + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_ERRATA_H_ +#define ARM_ERRATA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline arm_release_id arm_errata_get_processor_release(void) +{ + const uint32_t MIDR = arm_cp15_get_id_code(); + const uint8_t REVISION = (MIDR & 0xF00000U) >> 20; + const uint8_t PATCH_LEVEL = (MIDR & 0xFU); + + return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( + REVISION, + PATCH_LEVEL + ); +} + +static inline bool arm_errata_is_applicable_processor_errata_764369(void) +{ +#if defined(RTEMS_SMP) + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R4_P1: + case ARM_RELEASE_ID_R4_P4: + case ARM_RELEASE_ID_R3_P0: + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + case ARM_RELEASE_ID_R2_P0: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +#else + return false; +#endif +} + +static inline bool arm_errata_is_applicable_processor_errata_775420(void) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_ERRATA_H_ */ diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h new file mode 100644 index 0000000000..09d3fe5ac2 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-irq.h @@ -0,0 +1,112 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC IRQ + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ARM_GIC_IRQ_SGI_0 0 +#define ARM_GIC_IRQ_SGI_1 1 +#define ARM_GIC_IRQ_SGI_2 2 +#define ARM_GIC_IRQ_SGI_3 3 +#define ARM_GIC_IRQ_SGI_5 5 +#define ARM_GIC_IRQ_SGI_6 6 +#define ARM_GIC_IRQ_SGI_7 7 +#define ARM_GIC_IRQ_SGI_8 8 +#define ARM_GIC_IRQ_SGI_9 9 +#define ARM_GIC_IRQ_SGI_10 10 +#define ARM_GIC_IRQ_SGI_11 11 +#define ARM_GIC_IRQ_SGI_12 12 +#define ARM_GIC_IRQ_SGI_13 13 +#define ARM_GIC_IRQ_SGI_14 14 +#define ARM_GIC_IRQ_SGI_15 15 + +#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +); + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +typedef enum { + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF +} arm_gic_irq_software_irq_target_filter; + +static inline rtems_status_code arm_gic_irq_generate_software_irq( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (vector <= ARM_GIC_IRQ_SGI_15) { + volatile gic_dist *dist = ARM_GIC_DIST; + + dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) + | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) + | GIC_DIST_ICDSGIR_SGIINTID(vector); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +static inline uint32_t arm_gic_irq_processor_count(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; +} + +void arm_gic_irq_initialize_secondary_cpu(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-gic-regs.h new file mode 100644 index 0000000000..2375b5cf74 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-regs.h @@ -0,0 +1,138 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H +#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H + +#include + +typedef struct { + uint32_t iccicr; +#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) + uint32_t iccpmr; +#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t iccbpr; +#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t icciar; +#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t icceoir; +#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccrpr; +#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t icchpir; +#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccabpr; +#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t reserved_20[55]; + uint32_t icciidr; +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +} gic_cpuif; + +typedef struct { + uint32_t icddcr; +#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) + uint32_t icdictr; +#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) +#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) +#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t icdiidr; +#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + uint32_t reserved_0c[29]; + uint32_t icdisr[32]; + uint32_t icdiser[32]; + uint32_t icdicer[32]; + uint32_t icdispr[32]; + uint32_t icdicpr[32]; + uint32_t icdabr[32]; + uint32_t reserved_380[32]; + uint8_t icdipr[256]; + uint32_t reserved_500[192]; + uint8_t icdiptr[256]; + uint32_t reserved_900[192]; + uint32_t icdicfr[64]; + uint32_t reserved_d00[128]; + uint32_t icdsgir; +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define GIC_DIST_ICDSGIR_SATT BSP_BIT32(15) +#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +} gic_dist; + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-gic-tm27.h b/bsps/arm/include/bsp/arm-gic-tm27.h new file mode 100644 index 0000000000..95f3077716 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-tm27.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC TM27 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H +#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H + +#include + +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 + +#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 + +#define ARM_GIC_TM27_PRIO_LOW 0x80 + +#define ARM_GIC_TM27_PRIO_HIGH 0x00 + +static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_LOW, + "tm27 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_TM27_PRIO_LOW + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_HIGH, + "tm27 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_TM27_PRIO_HIGH + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Cause_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Clear_tm27_intr(void) +{ + /* Nothing to do */ +} + +static inline void Lower_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/arm/include/bsp/arm-gic.h b/bsps/arm/include/bsp/arm-gic.h new file mode 100644 index 0000000000..ab5840919a --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic.h @@ -0,0 +1,207 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H +#define LIBBSP_ARM_SHARED_ARM_GIC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_gic ARM GIC + * + * @ingroup arm_shared + * + * @brief ARM_GIC Support Package + */ + +#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) +#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) + +#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) +#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) + +static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdiser[i] & bit) != 0; +} + +static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdiser[i] = bit; +} + +static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicer[i] = bit; +} + +static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdispr[i] & bit) != 0; +} + +static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdispr[i] = bit; +} + +static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicpr[i] = bit; +} + +static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdabr[i] & bit) != 0; +} + +static inline void gic_id_set_priority( + volatile gic_dist *dist, + uint32_t id, + uint8_t priority +) +{ + dist->icdipr[id] = priority; +} + +static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdipr[id]; +} + +static inline void gic_id_set_targets( + volatile gic_dist *dist, + uint32_t id, + uint8_t targets +) +{ + dist->icdiptr[id] = targets; +} + +static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdiptr[id]; +} + +typedef enum { + GIC_LEVEL_SENSITIVE, + GIC_EDGE_TRIGGERED +} gic_trigger_mode; + +static inline gic_trigger_mode gic_id_get_trigger_mode( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? + GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; +} + +static inline void gic_id_set_trigger_mode( + volatile gic_dist *dist, + uint32_t id, + gic_trigger_mode mode +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = mode << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +typedef enum { + GIC_N_TO_N, + GIC_1_TO_N +} gic_handling_model; + +static inline gic_handling_model gic_id_get_handling_model( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; +} + +static inline void gic_id_set_handling_model( + volatile gic_dist *dist, + uint32_t id, + gic_handling_model model +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = model << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h b/bsps/arm/include/bsp/arm-pl011-regs.h new file mode 100644 index 0000000000..2b930f4b4c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011-regs.h @@ -0,0 +1,130 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H + +#include + +typedef struct { + uint32_t uartdr; +#define PL011_UARTDR_OE BSP_BIT32(11) +#define PL011_UARTDR_BE BSP_BIT32(10) +#define PL011_UARTDR_PE BSP_BIT32(9) +#define PL011_UARTDR_FE BSP_BIT32(8) +#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartrsr_uartecr; +#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3) +#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2) +#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1) +#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0) + uint32_t reserved_08[4]; + uint32_t uartfr; +#define PL011_UARTFR_RI BSP_BIT32(8) +#define PL011_UARTFR_TXFE BSP_BIT32(7) +#define PL011_UARTFR_RXFF BSP_BIT32(6) +#define PL011_UARTFR_TXFF BSP_BIT32(5) +#define PL011_UARTFR_RXFE BSP_BIT32(4) +#define PL011_UARTFR_BUSY BSP_BIT32(3) +#define PL011_UARTFR_DCD BSP_BIT32(2) +#define PL011_UARTFR_DSR BSP_BIT32(1) +#define PL011_UARTFR_CTS BSP_BIT32(0) + uint32_t reserved_1c; + uint32_t uartilpr; +#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartibrd; +#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t uartfbrd; +#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t uartlcr_h; +#define PL011_UARTLCR_H_SPS BSP_BIT32(7) +#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6) +#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define PL011_UARTLCR_H_WLEN_5 0x00U +#define PL011_UARTLCR_H_WLEN_6 0x01U +#define PL011_UARTLCR_H_WLEN_7 0x02U +#define PL011_UARTLCR_H_WLEN_8 0x03U +#define PL011_UARTLCR_H_FEN BSP_BIT32(4) +#define PL011_UARTLCR_H_STP2 BSP_BIT32(3) +#define PL011_UARTLCR_H_EPS BSP_BIT32(2) +#define PL011_UARTLCR_H_PEN BSP_BIT32(1) +#define PL011_UARTLCR_H_BRK BSP_BIT32(0) + uint32_t uartcr; +#define PL011_UARTCR_CTSEN BSP_BIT32(15) +#define PL011_UARTCR_RTSEN BSP_BIT32(14) +#define PL011_UARTCR_OUT2 BSP_BIT32(13) +#define PL011_UARTCR_OUT1 BSP_BIT32(12) +#define PL011_UARTCR_RTS BSP_BIT32(11) +#define PL011_UARTCR_DTR BSP_BIT32(10) +#define PL011_UARTCR_RXE BSP_BIT32(9) +#define PL011_UARTCR_TXE BSP_BIT32(8) +#define PL011_UARTCR_LBE BSP_BIT32(7) +#define PL011_UARTCR_SIRLP BSP_BIT32(3) +#define PL011_UARTCR_SIREN BSP_BIT32(2) +#define PL011_UARTCR_UARTEN BSP_BIT32(1) + uint32_t uartifls; +#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t uartimsc; + uint32_t uartris; + uint32_t uartmis; + uint32_t uarticr; +#define PL011_UARTI_OEI BSP_BIT32(10) +#define PL011_UARTI_BEI BSP_BIT32(9) +#define PL011_UARTI_PEI BSP_BIT32(8) +#define PL011_UARTI_FEI BSP_BIT32(7) +#define PL011_UARTI_RTI BSP_BIT32(6) +#define PL011_UARTI_TXI BSP_BIT32(5) +#define PL011_UARTI_RXI BSP_BIT32(4) +#define PL011_UARTI_DSRMI BSP_BIT32(3) +#define PL011_UARTI_DCDMI BSP_BIT32(2) +#define PL011_UARTI_CTSMI BSP_BIT32(1) +#define PL011_UARTI_RIMI BSP_BIT32(0) + uint32_t uartdmacr; +#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2) +#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1) +#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0) + uint32_t reserved_4c[997]; + uint32_t uartperiphid0; + uint32_t uartperiphid1; + uint32_t uartperiphid2; + uint32_t uartperiphid3; + uint32_t uartpcellid0; + uint32_t uartpcellid1; + uint32_t uartpcellid2; + uint32_t uartpcellid3; +} pl011; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/arm/include/bsp/arm-pl011.h new file mode 100644 index 0000000000..08189c477c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Support Package + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_H +#define LIBBSP_ARM_SHARED_ARM_PL011_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl011 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl011_context; + +bool arm_pl011_probe(rtems_termios_device_context *base); + +void arm_pl011_write_polled(rtems_termios_device_context *base, char c); + +extern const rtems_termios_device_handler arm_pl011_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_H */ diff --git a/bsps/arm/include/bsp/arm-pl050-regs.h b/bsps/arm/include/bsp/arm-pl050-regs.h new file mode 100644 index 0000000000..f90aeb6cf9 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050-regs.h @@ -0,0 +1,57 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Register Definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL050_REGS_H + +#include + +typedef struct { + uint32_t kmicr; +#define PL050_KMICR_KMITYPE BSP_BIT32(5) +#define PL050_KMICR_KMIRXINTREN BSP_BIT32(4) +#define PL050_KMICR_KMITXINTREN BSP_BIT32(3) +#define PL050_KMICR_KMIEN BSP_BIT32(2) +#define PL050_KMICR_FKMID BSP_BIT32(1) +#define PL050_KMICR_FKMIC BSP_BIT32(0) + uint32_t kmistat; +#define PL050_KMISTAT_TXEMPTY BSP_BIT32(6) +#define PL050_KMISTAT_TXBUSY BSP_BIT32(5) +#define PL050_KMISTAT_RXFULL BSP_BIT32(4) +#define PL050_KMISTAT_RXBUSY BSP_BIT32(3) +#define PL050_KMISTAT_RXPARITY BSP_BIT32(2) +#define PL050_KMISTAT_KMIC BSP_BIT32(1) +#define PL050_KMISTAT_KMID BSP_BIT32(0) + uint32_t kmidata; +#define PL050_KMIDATA_KMIDATA(val) BSP_FLD32(val, 0, 7) +#define PL050_KMIDATA_KMIDATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL050_KMIDATA_KMIDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t kmiclkdiv; +#define PL050_KMICLKDIV_KMICLKDIV(val) BSP_FLD32(val, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t kmiir; +#define PL050_KMIIR_KMITXINTR BSP_BIT32(1) +#define PL050_KMIIR_KMIRXINTR BSP_BIT32(0) +} pl050; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl050.h b/bsps/arm/include/bsp/arm-pl050.h new file mode 100644 index 0000000000..af4e246124 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_H +#define LIBBSP_ARM_SHARED_ARM_PL050_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl050 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl050_context; + +extern const rtems_termios_device_handler arm_pl050_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-fb.h b/bsps/arm/include/bsp/arm-pl111-fb.h new file mode 100644 index 0000000000..0c8c6231e1 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-fb.h @@ -0,0 +1,44 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 FB Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_FB_H +#define LIBBSP_ARM_SHARED_ARM_PL111_FB_H + +#include + +typedef struct pl111_fb_config { + volatile pl111 *regs; + uint32_t timing0; + uint32_t timing1; + uint32_t timing2; + uint32_t timing3; + uint32_t control; + uint32_t power_delay_in_us; + void (*set_up)(const struct pl111_fb_config *cfg); + void (*pins_set_up)(const struct pl111_fb_config *cfg); + void (*pins_tear_down)(const struct pl111_fb_config *cfg); + void (*tear_down)(const struct pl111_fb_config *cfg); +} pl111_fb_config; + +const pl111_fb_config *arm_pl111_fb_get_config(void); + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_FB_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-regs.h b/bsps/arm/include/bsp/arm-pl111-regs.h new file mode 100644 index 0000000000..ed27ba41a0 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-regs.h @@ -0,0 +1,184 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H + +#include + +typedef struct { + uint32_t timing0; +#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7) +#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7) +#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15) +#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing1; +#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9) +#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15) +#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing2; +#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5) +#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10) +#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define PL111_LCD_TIMING2_IVS BSP_BIT32(11) +#define PL111_LCD_TIMING2_IHS BSP_BIT32(12) +#define PL111_LCD_TIMING2_IPC BSP_BIT32(13) +#define PL111_LCD_TIMING2_IOE BSP_BIT32(14) +#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25) +#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_LCD_TIMING2_BCD BSP_BIT32(26) +#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31) + uint32_t timing3; +#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6) +#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define PL111_LCD_TIMING3_LEE BSP_BIT32(16) + uint32_t upbase; + uint32_t lpbase; + uint32_t control; +#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0) +#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U +#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U +#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U +#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U +#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x06U +#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U +#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4) +#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5) +#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6) +#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7) +#define PL111_LCD_CONTROL_BGR BSP_BIT32(8) +#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9) +#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10) +#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11) +#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16) + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#define PL111_LCD_I_FUF BSP_BIT32(1) +#define PL111_LCD_I_LNBU BSP_BIT32(2) +#define PL111_LCD_I_VCOMP BSP_BIT32(3) +#define PL111_LCD_I_MBERROR BSP_BIT32(4) + uint32_t upcurr; + uint32_t lpcurr; + uint32_t reserved_34[115]; + uint16_t pal[256]; +#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4) +#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4) +#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9) +#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9) +#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14) +#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14) +#define PL111_LCD_PAL_I BSP_BIT16(15) +} pl111_lcd; + +typedef struct { + uint8_t image[1024]; + uint32_t ctrl; +#define PL111_CRSR_CTRL_ON BSP_BIT32(0) +#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) + uint32_t config; +#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0) +#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1) + uint32_t palette0; + uint32_t palette1; +#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7) +#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) + uint32_t xy; +#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9) +#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11) +#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25) +#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27) +#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27) +#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27) + uint32_t clip; +#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5) +#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13) +#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) + uint32_t imsc; + uint32_t icr; + uint32_t ris; + uint32_t mis; +#define PL111_CRSR_I_CRSR BSP_BIT32(0) +} pl111_crsr; + +typedef struct { + pl111_lcd lcd; + uint32_t reserved_400[256]; + pl111_crsr crsr; +} pl111; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-release-id.h b/bsps/arm/include/bsp/arm-release-id.h new file mode 100644 index 0000000000..e06be006da --- /dev/null +++ b/bsps/arm/include/bsp/arm-release-id.h @@ -0,0 +1,152 @@ +/** + * @file arm-release-id.h + * + * @ingroup arm_shared + * + * @brief Create #defines for release IDs + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_RELEASE_ID_H_ +#define ARM_RELEASE_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* #define the IDs which identify a release. This must be done + * prior to #including bsp.h */ +#define ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( release_no, patch_level ) \ + ( ( ( ( release_no ) & 0xFFFF ) << 16 ) + ( ( patch_level ) & 0xFFFF ) ) + +typedef enum { + ARM_RELEASE_ID_R0_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 0 ), + ARM_RELEASE_ID_R0_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 1 ), + ARM_RELEASE_ID_R0_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 2 ), + ARM_RELEASE_ID_R0_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 3 ), + ARM_RELEASE_ID_R0_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 4 ), + ARM_RELEASE_ID_R0_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 5 ), + ARM_RELEASE_ID_R0_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 6 ), + ARM_RELEASE_ID_R0_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 7 ), + ARM_RELEASE_ID_R0_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 8 ), + ARM_RELEASE_ID_R0_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 9 ), + ARM_RELEASE_ID_R0_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 10 ), + ARM_RELEASE_ID_R1_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 0 ), + ARM_RELEASE_ID_R1_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 1 ), + ARM_RELEASE_ID_R1_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 2 ), + ARM_RELEASE_ID_R1_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 3 ), + ARM_RELEASE_ID_R1_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 4 ), + ARM_RELEASE_ID_R1_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 5 ), + ARM_RELEASE_ID_R1_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 6 ), + ARM_RELEASE_ID_R1_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 7 ), + ARM_RELEASE_ID_R1_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 8 ), + ARM_RELEASE_ID_R1_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 9 ), + ARM_RELEASE_ID_R1_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 10 ), + ARM_RELEASE_ID_R2_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 0 ), + ARM_RELEASE_ID_R2_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 1 ), + ARM_RELEASE_ID_R2_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 2 ), + ARM_RELEASE_ID_R2_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 3 ), + ARM_RELEASE_ID_R2_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 4 ), + ARM_RELEASE_ID_R2_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 5 ), + ARM_RELEASE_ID_R2_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 6 ), + ARM_RELEASE_ID_R2_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 7 ), + ARM_RELEASE_ID_R2_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 8 ), + ARM_RELEASE_ID_R2_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 9 ), + ARM_RELEASE_ID_R2_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 10 ), + ARM_RELEASE_ID_R3_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 0 ), + ARM_RELEASE_ID_R3_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 1 ), + ARM_RELEASE_ID_R3_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 2 ), + ARM_RELEASE_ID_R3_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 3 ), + ARM_RELEASE_ID_R3_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 4 ), + ARM_RELEASE_ID_R3_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 5 ), + ARM_RELEASE_ID_R3_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 6 ), + ARM_RELEASE_ID_R3_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 7 ), + ARM_RELEASE_ID_R3_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 8 ), + ARM_RELEASE_ID_R3_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 9 ), + ARM_RELEASE_ID_R3_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 10 ), + ARM_RELEASE_ID_R4_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 0 ), + ARM_RELEASE_ID_R4_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 1 ), + ARM_RELEASE_ID_R4_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 2 ), + ARM_RELEASE_ID_R4_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 3 ), + ARM_RELEASE_ID_R4_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 4 ), + ARM_RELEASE_ID_R4_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 5 ), + ARM_RELEASE_ID_R4_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 6 ), + ARM_RELEASE_ID_R4_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 7 ), + ARM_RELEASE_ID_R4_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 8 ), + ARM_RELEASE_ID_R4_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 9 ), + ARM_RELEASE_ID_R4_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 10 ), + ARM_RELEASE_ID_R5_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 0 ), + ARM_RELEASE_ID_R5_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 1 ), + ARM_RELEASE_ID_R5_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 2 ), + ARM_RELEASE_ID_R5_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 3 ), + ARM_RELEASE_ID_R5_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 4 ), + ARM_RELEASE_ID_R5_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 5 ), + ARM_RELEASE_ID_R5_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 6 ), + ARM_RELEASE_ID_R5_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 7 ), + ARM_RELEASE_ID_R5_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 8 ), + ARM_RELEASE_ID_R5_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 9 ), + ARM_RELEASE_ID_R5_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 10 ), + ARM_RELEASE_ID_R6_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 0 ), + ARM_RELEASE_ID_R6_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 1 ), + ARM_RELEASE_ID_R6_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 2 ), + ARM_RELEASE_ID_R6_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 3 ), + ARM_RELEASE_ID_R6_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 4 ), + ARM_RELEASE_ID_R6_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 5 ), + ARM_RELEASE_ID_R6_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 6 ), + ARM_RELEASE_ID_R6_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 7 ), + ARM_RELEASE_ID_R6_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 8 ), + ARM_RELEASE_ID_R6_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 9 ), + ARM_RELEASE_ID_R6_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 10 ), + ARM_RELEASE_ID_R7_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 0 ), + ARM_RELEASE_ID_R7_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 1 ), + ARM_RELEASE_ID_R7_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 2 ), + ARM_RELEASE_ID_R7_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 3 ), + ARM_RELEASE_ID_R7_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 4 ), + ARM_RELEASE_ID_R7_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 5 ), + ARM_RELEASE_ID_R7_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 6 ), + ARM_RELEASE_ID_R7_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 7 ), + ARM_RELEASE_ID_R7_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 8 ), + ARM_RELEASE_ID_R7_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 9 ), + ARM_RELEASE_ID_R7_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 10 ), + ARM_RELEASE_ID_R8_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 0 ), + ARM_RELEASE_ID_R8_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 1 ), + ARM_RELEASE_ID_R8_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 2 ), + ARM_RELEASE_ID_R8_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 3 ), + ARM_RELEASE_ID_R8_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 4 ), + ARM_RELEASE_ID_R8_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 5 ), + ARM_RELEASE_ID_R8_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 6 ), + ARM_RELEASE_ID_R8_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 7 ), + ARM_RELEASE_ID_R8_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 8 ), + ARM_RELEASE_ID_R8_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 9 ), + ARM_RELEASE_ID_R8_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 10 ), + ARM_RELEASE_ID_R9_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 0 ), + ARM_RELEASE_ID_R9_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 1 ), + ARM_RELEASE_ID_R9_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 2 ), + ARM_RELEASE_ID_R9_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 3 ), + ARM_RELEASE_ID_R9_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 4 ), + ARM_RELEASE_ID_R9_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 5 ), + ARM_RELEASE_ID_R9_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 6 ), + ARM_RELEASE_ID_R9_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 7 ), + ARM_RELEASE_ID_R9_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 8 ), + ARM_RELEASE_ID_R9_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 9 ), + ARM_RELEASE_ID_R9_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 10 ) +} arm_release_id; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_RELEASE_ID_H_ */ \ No newline at end of file diff --git a/bsps/arm/include/bsp/armv7m-irq.h b/bsps/arm/include/bsp/armv7m-irq.h new file mode 100644 index 0000000000..f91ab362e7 --- /dev/null +++ b/bsps/arm/include/bsp/armv7m-irq.h @@ -0,0 +1,36 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARMV7M Support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARMV7M_IRQ_H +#define LIBBSP_ARM_SHARED_ARMV7M_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +void _ARMV7M_NVIC_Interrupt_dispatch(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARMV7M_IRQ_H */ diff --git a/bsps/arm/include/bsp/linker-symbols.h b/bsps/arm/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..1a996f51f2 --- /dev/null +++ b/bsps/arm/include/bsp/linker-symbols.h @@ -0,0 +1,167 @@ +/** + * @file + * + * @ingroup arm_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_linker Linker Support + * + * @ingroup arm_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_stack_irq_begin) +LINKER_SYMBOL(bsp_stack_irq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_fiq_begin) +LINKER_SYMBOL(bsp_stack_fiq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_abt_begin) +LINKER_SYMBOL(bsp_stack_abt_end) +LINKER_SYMBOL(bsp_stack_abt_size) + +LINKER_SYMBOL(bsp_stack_und_begin) +LINKER_SYMBOL(bsp_stack_und_end) +LINKER_SYMBOL(bsp_stack_und_size) + +LINKER_SYMBOL(bsp_stack_hyp_begin) +LINKER_SYMBOL(bsp_stack_hyp_end) +LINKER_SYMBOL(bsp_stack_hyp_size) + +LINKER_SYMBOL(bsp_stack_svc_begin) +LINKER_SYMBOL(bsp_stack_svc_end) +LINKER_SYMBOL(bsp_stack_svc_size) + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +LINKER_SYMBOL(bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/arm/include/bsp/lpc-dma.h b/bsps/arm/include/bsp/lpc-dma.h new file mode 100644 index 0000000000..45d567b36c --- /dev/null +++ b/bsps/arm/include/bsp/lpc-dma.h @@ -0,0 +1,221 @@ +/** + * @file + * + * @ingroup lpc_dma + * + * @brief DMA support API. + */ + +/* + * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H +#define LIBBSP_ARM_SHARED_LPC_DMA_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_dma DMA Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief DMA support. + * + * @{ + */ + +/** + * @brief DMA descriptor item. + */ +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc_dma_descriptor; + +/** + * @brief DMA channel block. + */ +typedef struct { + lpc_dma_descriptor desc; + uint32_t cfg; + uint32_t reserved [3]; +} lpc_dma_channel; + +/** + * @brief DMA control block. + */ +typedef struct { + uint32_t int_stat; + uint32_t int_tc_stat; + uint32_t int_tc_clear; + uint32_t int_err_stat; + uint32_t int_err_clear; + uint32_t raw_tc_stat; + uint32_t raw_err_stat; + uint32_t enabled_channels; + uint32_t soft_burst_req; + uint32_t soft_single_req; + uint32_t soft_last_burst_req; + uint32_t soft_last_single_req; + uint32_t cfg; + uint32_t sync; + uint32_t reserved [50]; + lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT]; +} lpc_dma; + +/** + * @name DMA Configuration Register + * + * @{ + */ + +#define DMA_CFG_E BSP_BIT32(0) +#define DMA_CFG_M_0 BSP_BIT32(1) +#define DMA_CFG_M_1 BSP_BIT32(2) + +/** @} */ + +/** + * @name DMA Channel Control Register + * + * @{ + */ + +#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11) +#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff) + +#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14) +#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0) +#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1) +#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2) +#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3) +#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4) +#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5) +#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6) +#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7) + +#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17) +#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0) +#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1) +#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2) +#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3) +#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4) +#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5) +#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6) +#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7) + +#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20) +#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0) +#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1) +#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2) + +#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23) +#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0) +#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1) +#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2) + +#define DMA_CH_CTRL_S BSP_BIT32(24) +#define DMA_CH_CTRL_D BSP_BIT32(25) +#define DMA_CH_CTRL_SI BSP_BIT32(26) +#define DMA_CH_CTRL_DI BSP_BIT32(27) +#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30) +#define DMA_CH_CTRL_I BSP_BIT32(31) + +/** @} */ + +/** + * @name DMA Channel Configuration Register + * + * @{ + */ + +#define DMA_CH_CFG_E BSP_BIT32(0) +#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5) +#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10) + +#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13) +#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6) +#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7) + +#define DMA_CH_CFG_IE BSP_BIT32(14) +#define DMA_CH_CFG_ITC BSP_BIT32(15) +#define DMA_CH_CFG_L BSP_BIT32(16) +#define DMA_CH_CFG_A BSP_BIT32(17) +#define DMA_CH_CFG_H BSP_BIT32(18) + +/** @} */ + +/** + * @name LPC24XX DMA Peripherals + * + * @{ + */ + +#define LPC24XX_DMA_PER_SSP_0_TX 0 +#define LPC24XX_DMA_PER_SSP_0_RX 1 +#define LPC24XX_DMA_PER_SSP_1_TX 2 +#define LPC24XX_DMA_PER_SSP_1_RX 3 +#define LPC24XX_DMA_PER_SD_MMC 4 +#define LPC24XX_DMA_PER_I2S_CH_0 5 +#define LPC24XX_DMA_PER_I2S_CH_1 6 + +/** @} */ + +/** + * @name LPC32XX DMA Peripherals + * + * @{ + */ + +#define LPC32XX_DMA_PER_I2S_0_CH_0 0 +#define LPC32XX_DMA_PER_I2S_0_CH_1 13 +#define LPC32XX_DMA_PER_I2S_1_CH_0 2 +#define LPC32XX_DMA_PER_I2S_1_CH_1 10 +#define LPC32XX_DMA_PER_NAND_0 1 +#define LPC32XX_DMA_PER_NAND_1 12 +#define LPC32XX_DMA_PER_SD_MMC 4 +#define LPC32XX_DMA_PER_SSP_0_RX 14 +#define LPC32XX_DMA_PER_SSP_0_TX 15 +#define LPC32XX_DMA_PER_SSP_1_RX 3 +#define LPC32XX_DMA_PER_SSP_1_TX 11 +#define LPC32XX_DMA_PER_UART_1_RX 6 +#define LPC32XX_DMA_PER_UART_1_TX 5 +#define LPC32XX_DMA_PER_UART_2_RX 8 +#define LPC32XX_DMA_PER_UART_2_TX 7 +#define LPC32XX_DMA_PER_UART_7_RX 10 +#define LPC32XX_DMA_PER_UART_7_TX 9 + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */ diff --git a/bsps/arm/include/bsp/lpc-emc.h b/bsps/arm/include/bsp/lpc-emc.h new file mode 100644 index 0000000000..31cb4241c8 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-emc.h @@ -0,0 +1,170 @@ +/** + * @file + * + * @ingroup lpc_emc + * + * @brief EMC support API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H +#define LIBBSP_ARM_SHARED_LPC_EMC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_emc EMC Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief EMC Support + * + * @{ + */ + +/** + * @name EMC Control Register (EMCControl) + * + * @{ + */ + +#define EMC_CTRL_E BSP_BIT32(0) +#define EMC_CTRL_M BSP_BIT32(0) +#define EMC_CTRL_L BSP_BIT32(2) + +/** @} */ + +/** + * @name EMC Dynamic Memory Control Register (EMCDynamicControl) + * + * @{ + */ + +#define EMC_DYN_CTRL_CE BSP_BIT32(0) +#define EMC_DYN_CTRL_CS BSP_BIT32(1) +#define EMC_DYN_CTRL_SR BSP_BIT32(2) +#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3) +#define EMC_DYN_CTRL_IMCC BSP_BIT32(4) +#define EMC_DYN_CTRL_MCC BSP_BIT32(5) +#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8) +#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8) +#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8) +#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8) +#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8) +#define EMC_DYN_CTRL_DP BSP_BIT32(13) + +/** @} */ + +/** + * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) + * + * @{ + */ + +#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1) +#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4) +#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9) +#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12) + +/** @} */ + +/** + * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN) + * + * @{ + */ + +#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4) +#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2) +#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14) +#define EMC_DYN_CFG_B BSP_BIT32(19) +#define EMC_DYN_CFG_P BSP_BIT32(20) + +/** @} */ + +/** + * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN) + * + * @{ + */ + +#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3) +#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10) + +/** @} */ + +#define EMC_DYN_CHIP_COUNT 4 + +#define EMC_STATIC_CHIP_COUNT 4 + +typedef struct { + uint32_t config; + uint32_t rascas; + uint32_t reserved_0 [6]; +} lpc_emc_dynamic; + +typedef struct { + uint32_t config; + uint32_t waitwen; + uint32_t waitoen; + uint32_t waitrd; + uint32_t waitpage; + uint32_t waitwr; + uint32_t waitturn; + uint32_t reserved_0 [1]; +} lpc_emc_static; + +typedef struct { + uint32_t control; + uint32_t status; + uint32_t config; + uint32_t reserved_0 [5]; + uint32_t dynamiccontrol; + uint32_t dynamicrefresh; + uint32_t dynamicreadconfig; + uint32_t reserved_1; + uint32_t dynamictrp; + uint32_t dynamictras; + uint32_t dynamictsrex; + uint32_t dynamictapr; + uint32_t dynamictdal; + uint32_t dynamictwr; + uint32_t dynamictrc; + uint32_t dynamictrfc; + uint32_t dynamictxsr; + uint32_t dynamictrrd; + uint32_t dynamictmrd; + uint32_t dynamictcdlr; + uint32_t reserved_3 [8]; + uint32_t staticextendedwait; + uint32_t reserved_4 [31]; + lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT]; + uint32_t reserved_5 [32]; + lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT]; +} lpc_emc; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */ diff --git a/bsps/arm/include/bsp/lpc-i2s.h b/bsps/arm/include/bsp/lpc-i2s.h new file mode 100644 index 0000000000..65e951b7d7 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-i2s.h @@ -0,0 +1,132 @@ +/** + * @file + * + * @ingroup lpc_i2s + * + * @brief I2S API. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H +#define LIBBSP_ARM_SHARED_LPC_I2S_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_i2s I2S Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief I2S support. + * + * @{ + */ + +/** + * @brief I2S control block. + */ +typedef struct { + uint32_t dao; + uint32_t dai; + uint32_t txfifo; + uint32_t rxfifo; + uint32_t state; + uint32_t dma [2]; + uint32_t irq; + uint32_t txrate; + uint32_t rxrate; +} lpc_i2s; + +/** + * @name I2S Digital Audio Input and Output + * + * @{ + */ + +#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1) +#define I2S_DAIO_MONO BSP_BIT32(2) +#define I2S_DAIO_STOP BSP_BIT32(3) +#define I2S_DAIO_RESET BSP_BIT32(4) +#define I2S_DAIO_WS_SEL BSP_BIT32(5) +#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14) +#define I2S_DAIO_MUTE BSP_BIT32(15) + +/** @} */ + +/** + * @name I2S Status Feedback + * + * @{ + */ + +#define I2S_STATE_IRQ BSP_BIT32(0) +#define I2S_STATE_DMAREQ_0 BSP_BIT32(1) +#define I2S_STATE_DMAREQ_1 BSP_BIT32(2) +#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19) + +/** @} */ + +/** + * @name I2S DMA Configuration + * + * @{ + */ + +#define I2S_DMA_RX_ENABLE BSP_BIT32(0) +#define I2S_DMA_TX_ENABLE BSP_BIT32(1) +#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Interrupt Request Control + * + * @{ + */ + +#define I2S_IRQ_RX BSP_BIT32(0) +#define I2S_IRQ_TX BSP_BIT32(1) +#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Transmit and Receive Clock Rate + * + * @{ + */ + +#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9) +#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7) +#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */ diff --git a/bsps/arm/include/bsp/lpc-lcd.h b/bsps/arm/include/bsp/lpc-lcd.h new file mode 100644 index 0000000000..a3ca4fe11a --- /dev/null +++ b/bsps/arm/include/bsp/lpc-lcd.h @@ -0,0 +1,213 @@ +/** + * @file + * + * @ingroup lpc_lcd + * + * @brief LCD support API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H +#define LIBBSP_ARM_SHARED_LPC_LCD_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_lcd LCD Support + * + * @ingroup lpc + * @ingroup arm_lpc32xx + * + * @brief LCD support. + * + * @{ + */ + +typedef struct { + uint8_t img [1024]; + uint32_t ctrl; + uint32_t cfg; + uint32_t pal0; + uint32_t pal1; + uint32_t xy; + uint32_t clip; + uint32_t intmsk; + uint32_t intclr; + uint32_t intraw; + uint32_t intstat; +} lpc_cursor; + +typedef struct { + uint32_t timh; + uint32_t timv; + uint32_t pol; + uint32_t le; + uint32_t upbase; + uint32_t lpbase; + uint32_t ctrl; + uint32_t intmsk; + uint32_t intraw; + uint32_t intstat; + uint32_t intclr; + uint32_t upcurr; + uint32_t lpcurr; + uint8_t reserved_0 [0x200 - 0x034]; + uint16_t pal [256]; + uint8_t reserved_1 [0x800 - 0x400]; + lpc_cursor crsr; +} lpc_lcd; + +/** + * @name LCD Configuration Register + * + * @{ + */ + +#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4) +#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5) +#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7) +#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8) + +/** @} */ + +/** + * @name LCD Horizontal Timing Register + * + * @{ + */ + +#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7) +#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15) +#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Vertical Timing Register + * + * @{ + */ + +#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9) +#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15) +#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Clock and Signal Polarity Register + * + * @{ + */ + +#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LCD_POL_CLKSEL BSP_BIT32(5) +#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10) +#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define LCD_POL_IVS BSP_BIT32(11) +#define LCD_POL_IHS BSP_BIT32(12) +#define LCD_POL_IPC BSP_BIT32(13) +#define LCD_POL_IOE BSP_BIT32(14) +#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25) +#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define LCD_POL_BCD BSP_BIT32(26) +#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) + +/** @} */ + +/** + * @name LCD Line End Control Register + * + * @{ + */ + +#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6) +#define LCD_LE_LEE BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Control Register + * + * @{ + */ + +#define LCD_CTRL_LCDEN BSP_BIT32(0) +#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3) +#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define LCD_CTRL_LCDBW BSP_BIT32(4) +#define LCD_CTRL_LCDTFT BSP_BIT32(5) +#define LCD_CTRL_LCDMONO8 BSP_BIT32(6) +#define LCD_CTRL_LCDDUAL BSP_BIT32(7) +#define LCD_CTRL_BGR BSP_BIT32(8) +#define LCD_CTRL_BEBO BSP_BIT32(9) +#define LCD_CTRL_BEPO BSP_BIT32(10) +#define LCD_CTRL_LCDPWR BSP_BIT32(11) +#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13) +#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define LCD_CTRL_WATERMARK BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Interrupt Registers + * + * @{ + */ + +#define LCD_INT_FUF BSP_BIT32(1) +#define LCD_INT_LNBU BSP_BIT32(2) +#define LCD_INT_VCOMP BSP_BIT32(3) +#define LCD_INT_BER BSP_BIT32(4) + +/** @} */ + +/** + * @name LCD Color Palette Register + * + * @{ + */ + +#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define LCD_PAL_I BSP_BIT16(15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */ diff --git a/bsps/arm/include/bsp/lpc-timer.h b/bsps/arm/include/bsp/lpc-timer.h new file mode 100644 index 0000000000..4c7ad4f1d1 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-timer.h @@ -0,0 +1,159 @@ +/** + * @file + * + * @ingroup lpc_timer + * + * @brief Timer API. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H +#define LIBBSP_ARM_SHARED_LPC_TIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_timer Timer Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief Timer support. + * + * @{ + */ + +/** + * @name Interrupt Register Defines + * + * @{ + */ + +#define LPC_TIMER_IR_MR0 0x1U +#define LPC_TIMER_IR_MR1 0x2U +#define LPC_TIMER_IR_MR2 0x4U +#define LPC_TIMER_IR_MR3 0x8U +#define LPC_TIMER_IR_CR0 0x10U +#define LPC_TIMER_IR_CR1 0x20U +#define LPC_TIMER_IR_CR2 0x40U +#define LPC_TIMER_IR_CR3 0x80U +#define LPC_TIMER_IR_ALL 0xffU + +/** @} */ + +/** + * @name Timer Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_TCR_EN 0x1U +#define LPC_TIMER_TCR_RST 0x2U + +/** @} */ + +/** + * @name Match Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_MCR_MR0_INTR 0x1U +#define LPC_TIMER_MCR_MR0_RST 0x2U +#define LPC_TIMER_MCR_MR0_STOP 0x4U +#define LPC_TIMER_MCR_MR1_INTR 0x8U +#define LPC_TIMER_MCR_MR1_RST 0x10U +#define LPC_TIMER_MCR_MR1_STOP 0x20U +#define LPC_TIMER_MCR_MR2_INTR 0x40U +#define LPC_TIMER_MCR_MR2_RST 0x80U +#define LPC_TIMER_MCR_MR2_STOP 0x100U +#define LPC_TIMER_MCR_MR3_INTR 0x200U +#define LPC_TIMER_MCR_MR3_RST 0x400U +#define LPC_TIMER_MCR_MR3_STOP 0x800U + +/** @} */ + +/** + * @name Capture Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_CCR_CAP0_RE 0x1U +#define LPC_TIMER_CCR_CAP0_FE 0x2U +#define LPC_TIMER_CCR_CAP0_INTR 0x4U +#define LPC_TIMER_CCR_CAP1_RE 0x8U +#define LPC_TIMER_CCR_CAP1_FE 0x10U +#define LPC_TIMER_CCR_CAP1_INTR 0x20U +#define LPC_TIMER_CCR_CAP2_RE 0x40U +#define LPC_TIMER_CCR_CAP2_FE 0x80U +#define LPC_TIMER_CCR_CAP2_INTR 0x100U +#define LPC_TIMER_CCR_CAP3_RE 0x200U +#define LPC_TIMER_CCR_CAP3_FE 0x400U +#define LPC_TIMER_CCR_CAP3_INTR 0x800U + +/** @} */ + +/** + * @name External Match Register Defines + * + * @{ + */ + +#define LPC_TIMER_EMR_EM0_RE 0x1U +#define LPC_TIMER_EMR_EM1_FE 0x2U +#define LPC_TIMER_EMR_EM2_INTR 0x4U +#define LPC_TIMER_EMR_EM3_RE 0x8U +#define LPC_TIMER_EMR_EMC0_FE 0x10U +#define LPC_TIMER_EMR_EMC1_INTR 0x20U +#define LPC_TIMER_EMR_EMC2_RE 0x40U +#define LPC_TIMER_EMR_EMC3_FE 0x80U + +/** @} */ + +/** + * @brief Timer control block. + */ +typedef struct { + uint32_t ir; + uint32_t tcr; + uint32_t tc; + uint32_t pr; + uint32_t pc; + uint32_t mcr; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t ccr; + uint32_t cr0; + uint32_t cr1; + uint32_t cr2; + uint32_t cr3; + uint32_t emr; + uint32_t ctcr; +} lpc_timer; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */ diff --git a/bsps/arm/include/bsp/start.h b/bsps/arm/include/bsp/start.h new file mode 100644 index 0000000000..bf8eed4433 --- /dev/null +++ b/bsps/arm/include/bsp/start.h @@ -0,0 +1,183 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief ARM system low level start. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_START_H +#define LIBBSP_ARM_SHARED_START_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_start System Start + * + * @ingroup arm_shared + * + * @brief ARM system low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/* +* Many ARM boot loaders pass arguments to loaded OS kernel +*/ +#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS +#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int saved_dtb_adr +#else +#define BSP_START_HOOKS_LOADER_ARGS void +#endif + +/** +* @brief System start entry. +*/ +void _start(void); + +/** +* @brief Start entry hook 0. +* +* This hook will be called from the start entry code after all modes and +* stack pointers are initialized but before the copying of the exception +* vectors. +*/ +void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS); + +/** +* @brief Start entry hook 1. +* +* This hook will be called from the start entry code after copying of the +* exception vectors but before the call to boot_card(). +*/ +void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS); + +/** + * @brief Similar to standard memcpy(). + * + * The memory areas must be word aligned. Copy code will be executed from the + * stack. If @a dest equals @a src nothing will be copied. + */ +void bsp_start_memcpy(int *dest, const int *src, size_t n); + +/** + * @brief ARM entry point to bsp_start_memcpy(). + */ +void bsp_start_memcpy_arm(int *dest, const int *src, size_t n); + +/** + * @brief Copies all standard sections from the load to the runtime area. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void) +{ + /* Copy .text section */ + bsp_start_memcpy( + (int *) bsp_section_text_begin, + (const int *) bsp_section_text_load_begin, + (size_t) bsp_section_text_size + ); + + /* Copy .rodata section */ + bsp_start_memcpy( + (int *) bsp_section_rodata_begin, + (const int *) bsp_section_rodata_load_begin, + (size_t) bsp_section_rodata_size + ); + + /* Copy .data section */ + bsp_start_memcpy( + (int *) bsp_section_data_begin, + (const int *) bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy( + (int *) bsp_section_fast_text_begin, + (const int *) bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy( + (int *) bsp_section_fast_data_begin, + (const int *) bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void +bsp_start_memcpy_libc(void *dest, const void *src, size_t n) +{ + if (dest != src) { + memcpy(dest, src, n); + } +} + +/** + * @brief Copies the .data, .fast_text and .fast_data sections from the load to + * the runtime area using the C library memcpy(). + * + * Works only in case the .start, .text and .rodata sections reside in one + * memory region. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections_compact(void) +{ + /* Copy .data section */ + bsp_start_memcpy_libc( + bsp_section_data_begin, + bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy_libc( + bsp_section_fast_text_begin, + bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy_libc( + bsp_section_fast_data_begin, + bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void) +{ + memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_START_H */ diff --git a/bsps/arm/include/cmsis_gcc.h b/bsps/arm/include/cmsis_gcc.h new file mode 100644 index 0000000000..d868f2e64b --- /dev/null +++ b/bsps/arm/include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsps/arm/include/core_cm7.h b/bsps/arm/include/core_cm7.h new file mode 100644 index 0000000000..20963c148c --- /dev/null +++ b/bsps/arm/include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsps/arm/include/core_cmFunc.h b/bsps/arm/include/core_cmFunc.h new file mode 100644 index 0000000000..ca319a55cb --- /dev/null +++ b/bsps/arm/include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsps/arm/include/core_cmInstr.h b/bsps/arm/include/core_cmInstr.h new file mode 100644 index 0000000000..a0a506458d --- /dev/null +++ b/bsps/arm/include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsps/arm/include/core_cmSimd.h b/bsps/arm/include/core_cmSimd.h new file mode 100644 index 0000000000..4d76bf9018 --- /dev/null +++ b/bsps/arm/include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsps/arm/include/libcpu/am335x.h b/bsps/arm/include/libcpu/am335x.h new file mode 100644 index 0000000000..367e97cae9 --- /dev/null +++ b/bsps/arm/include/libcpu/am335x.h @@ -0,0 +1,704 @@ +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +#if !defined(_AM335X_H_) +#define _AM335X_H_ + +/* Interrupt controller memory map */ +#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller memory map */ +#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ + +#define AM335X_INT_EMUINT 0 + /* Emulation interrupt (EMUICINTR) */ +#define AM335X_INT_COMMTX 1 + /* CortexA8 COMMTX */ +#define AM335X_INT_COMMRX 2 + /* CortexA8 COMMRX */ +#define AM335X_INT_BENCH 3 + /* CortexA8 NPMUIRQ */ +#define AM335X_INT_ELM_IRQ 4 + /* Sinterrupt (Error location process completion) */ +#define AM335X_INT_NMI 7 + /* nmi_int */ +#define AM335X_INT_L3DEBUG 9 + /* l3_FlagMux_top_FlagOut1 */ +#define AM335X_INT_L3APPINT 10 + /* l3_FlagMux_top_FlagOut0 */ +#define AM335X_INT_PRCMINT 11 + /* irq_mpu */ +#define AM335X_INT_EDMACOMPINT 12 + /* tpcc_int_pend_po0 */ +#define AM335X_INT_EDMAMPERR 13 + /* tpcc_mpint_pend_po */ +#define AM335X_INT_EDMAERRINT 14 + /* tpcc_errint_pend_po */ +#define AM335X_INT_ADC_TSC_GENINT 16 + /* gen_intr_pend */ +#define AM335X_INT_USBSSINT 17 + /* usbss_intr_pend */ +#define AM335X_INT_USB0 18 + /* usb0_intr_pend */ +#define AM335X_INT_USB1 19 + /* usb1_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT0 20 + /* pr1_host_intr0_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT1 21 + /* pr1_host_intr1_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT2 22 + /* pr1_host_intr2_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT3 23 + /* pr1_host_intr3_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT4 24 + /* pr1_host_intr4_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT5 25 + /* pr1_host_intr5_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT6 26 + /* pr1_host_intr6_intr_pend */ +#define AM335X_INT_PRUSS1_EVTOUT7 27 + /* pr1_host_intr7_intr_pend */ +#define AM335X_INT_MMCSD1INT 28 + /* MMCSD1 SINTERRUPTN */ +#define AM335X_INT_MMCSD2INT 29 + /* MMCSD2 SINTERRUPT */ +#define AM335X_INT_I2C2INT 30 + /* I2C2 POINTRPEND */ +#define AM335X_INT_eCAP0INT 31 + /* ecap_intr_intr_pend */ +#define AM335X_INT_GPIOINT2A 32 + /* GPIO 2 POINTRPEND1 */ +#define AM335X_INT_GPIOINT2B 33 + /* GPIO 2 POINTRPEND2 */ +#define AM335X_INT_USBWAKEUP 34 + /* USBSS slv0p_Swakeup */ +#define AM335X_INT_LCDCINT 36 + /* LCDC lcd_irq */ +#define AM335X_INT_GFXINT 37 + /* SGX530 THALIAIRQ */ +#define AM335X_INT_ePWM2INT 39 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_3PGSWRXTHR0 40 + /* (Ethernet) c0_rx_thresh_pend (RX_THRESH_PULSE) */ +#define AM335X_INT_3PGSWRXINT0 41 + /* CPSW (Ethernet) c0_rx_pend */ +#define AM335X_INT_3PGSWTXINT0 42 + /* CPSW (Ethernet) c0_tx_pend */ +#define AM335X_INT_3PGSWMISC0 43 + /* CPSW (Ethernet) c0_misc_pend */ +#define AM335X_INT_UART3INT 44 + /* UART3 niq */ +#define AM335X_INT_UART4INT 45 + /* UART4 niq */ +#define AM335X_INT_UART5INT 46 + /* UART5 niq */ +#define AM335X_INT_eCAP1INT 47 + /* (PWM Subsystem) ecap_intr_intr_pend */ +#define AM335X_INT_DCAN0_INT0 52 + /* DCAN0 dcan_intr0_intr_pend */ +#define AM335X_INT_DCAN0_INT1 53 + /* DCAN0 dcan_intr1_intr_pend */ +#define AM335X_INT_DCAN0_PARITY 54 + /* DCAN0 dcan_uerr_intr_pend */ +#define AM335X_INT_DCAN1_INT0 55 + /* DCAN1 dcan_intr0_intr_pend */ +#define AM335X_INT_DCAN1_INT1 56 + /* DCAN1 dcan_intr1_intr_pend */ +#define AM335X_INT_DCAN1_PARITY 57 + /* DCAN1 dcan_uerr_intr_pend */ +#define AM335X_INT_ePWM0_TZINT 58 + /* eHRPWM0 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_ePWM1_TZINT 59 + /* eHRPWM1 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_ePWM2_TZINT 60 + /* eHRPWM2 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ +#define AM335X_INT_eCAP2INT 61 + /* eCAP2 (PWM Subsystem) ecap_intr_intr_pend */ +#define AM335X_INT_GPIOINT3A 62 + /* GPIO 3 POINTRPEND1 */ +#define AM335X_INT_GPIOINT3B 63 + /* GPIO 3 POINTRPEND2 */ +#define AM335X_INT_MMCSD0INT 64 + /* MMCSD0 SINTERRUPTN */ +#define AM335X_INT_SPI0INT 65 + /* McSPI0 SINTERRUPTN */ +#define AM335X_INT_TINT0 66 + /* Timer0 POINTR_PEND */ +#define AM335X_INT_TINT1_1MS 67 + /* DMTIMER_1ms POINTR_PEND */ +#define AM335X_INT_TINT2 68 + /* DMTIMER2 POINTR_PEND */ +#define AM335X_INT_TINT3 69 + /* DMTIMER3 POINTR_PEND */ +#define AM335X_INT_I2C0INT 70 + /* I2C0 POINTRPEND */ +#define AM335X_INT_I2C1INT 71 + /* I2C1 POINTRPEND */ +#define AM335X_INT_UART0INT 72 + /* UART0 niq */ +#define AM335X_INT_UART1INT 73 + /* UART1 niq */ +#define AM335X_INT_UART2INT 74 + /* UART2 niq */ +#define AM335X_INT_RTCINT 75 + /* RTC timer_intr_pend */ +#define AM335X_INT_RTCALARMINT 76 + /* RTC alarm_intr_pend */ +#define AM335X_INT_MBINT0 77 + /* Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n */ +#define AM335X_INT_M3_TXEV 78 + /* Wake M3 Subsystem TXEV */ +#define AM335X_INT_eQEP0INT 79 + /* eQEP0 (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_MCATXINT0 80 + /* McASP0 mcasp_x_intr_pend */ +#define AM335X_INT_MCARXINT0 81 + /* McASP0 mcasp_r_intr_pend */ +#define AM335X_INT_MCATXINT1 82 + /* McASP1 mcasp_x_intr_pend */ +#define AM335X_INT_MCARXINT1 83 + /* McASP1 mcasp_r_intr_pend */ +#define AM335X_INT_ePWM0INT 86 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_ePWM1INT 87 + /* (PWM Subsystem) epwm_intr_intr_pend */ +#define AM335X_INT_eQEP1INT 88 + /* (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_eQEP2INT 89 + /* (PWM Subsystem) eqep_intr_intr_pend */ +#define AM335X_INT_DMA_INTR_PIN2 90 + /* External DMA/Interrupt Pin2 */ +#define AM335X_INT_WDT1INT 91 + /* (Public Watchdog) WDTIMER1 PO_INT_PEND */ +#define AM335X_INT_TINT4 92 + /* DMTIMER4 POINTR_PEN */ +#define AM335X_INT_TINT5 93 + /* DMTIMER5 POINTR_PEN */ +#define AM335X_INT_TINT6 94 + /* DMTIMER6 POINTR_PEND */ +#define AM335X_INT_TINT7 95 + /* DMTIMER7 POINTR_PEND */ +#define AM335X_INT_GPIOINT0A 96 + /* GPIO 0 POINTRPEND1 */ +#define AM335X_INT_GPIOINT0B 97 + /* GPIO 0 POINTRPEND2 */ +#define AM335X_INT_GPIOINT1A 98 + /* GPIO 1 POINTRPEND1 */ +#define AM335X_INT_GPIOINT1B 99 + /* GPIO 1 POINTRPEND2 */ +#define AM335X_INT_GPMCINT 100 + /* GPMC gpmc_sinterrupt */ +#define AM335X_INT_DDRERR0 101 + /* EMIF sys_err_intr_pend */ +#define AM335X_INT_TCERRINT0 112 + /* TPTC0 tptc_erint_pend_po */ +#define AM335X_INT_TCERRINT1 113 + /* TPTC1 tptc_erint_pend_po */ +#define AM335X_INT_TCERRINT2 114 + /* TPTC2 tptc_erint_pend_po */ +#define AM335X_INT_ADC_TSC_PENINT 115 + /* ADC_TSC pen_intr_pend */ +#define AM335X_INT_SMRFLX_Sabertooth 120 + /* Smart Reflex 0 intrpen */ +#define AM335X_INT_SMRFLX_Core 121 + /* Smart Reflex 1 intrpend */ +#define AM335X_INT_DMA_INTR_PIN0 123 + /* pi_x_dma_event_intr0 (xdma_event_intr0) */ +#define AM335X_INT_DMA_INTR_PIN1 124 + /* pi_x_dma_event_intr1 (xdma_event_intr1) */ +#define AM335X_INT_SPI1INT 125 + /* McSPI1 SINTERRUPTN */ + +#define OMAP3_AM335X_NR_IRQ_VECTORS 125 + +#define AM335X_DMTIMER0_BASE 0x44E05000 + /* DMTimer0 Registers */ +#define AM335X_DMTIMER1_1MS_BASE 0x44E31000 + /* DMTimer1 1ms Registers (Accurate 1ms timer) */ +#define AM335X_DMTIMER2_BASE 0x48040000 + /* DMTimer2 Registers */ +#define AM335X_DMTIMER3_BASE 0x48042000 + /* DMTimer3 Registers */ +#define AM335X_DMTIMER4_BASE 0x48044000 + /* DMTimer4 Registers */ +#define AM335X_DMTIMER5_BASE 0x48046000 + /* DMTimer5 Registers */ +#define AM335X_DMTIMER6_BASE 0x48048000 + /* DMTimer6 Registers */ +#define AM335X_DMTIMER7_BASE 0x4804A000 + /* DMTimer7 Registers */ + +/* General-purpose timer registers + AM335x non 1MS timers have different offsets */ +#define AM335X_TIMER_TIDR 0x000 + /* IP revision code */ +#define AM335X_TIMER_TIOCP_CFG 0x010 + /* Controls params for GP timer L4 interface */ +#define AM335X_TIMER_IRQSTATUS_RAW 0x024 + /* Timer IRQSTATUS Raw Register */ +#define AM335X_TIMER_IRQSTATUS 0x028 + /* Timer IRQSTATUS Register */ +#define AM335X_TIMER_IRQENABLE_SET 0x02C + /* Timer IRQENABLE Set Register */ +#define AM335X_TIMER_IRQENABLE_CLR 0x030 + /* Timer IRQENABLE Clear Register */ +#define AM335X_TIMER_IRQWAKEEN 0x034 + /* Timer IRQ Wakeup Enable Register */ +#define AM335X_TIMER_TCLR 0x038 + /* Controls optional features */ +#define AM335X_TIMER_TCRR 0x03C + /* Internal counter value */ +#define AM335X_TIMER_TLDR 0x040 + /* Timer load value */ +#define AM335X_TIMER_TTGR 0x044 + /* Triggers counter reload */ +#define AM335X_TIMER_TWPS 0x048 + /* Indicates if Write-Posted pending */ +#define AM335X_TIMER_TMAR 0x04C + /* Value to be compared with counter */ +#define AM335X_TIMER_TCAR1 0x050 + /* First captured value of counter register */ +#define AM335X_TIMER_TSICR 0x054 + /* Control posted mode and functional SW reset */ +#define AM335X_TIMER_TCAR2 0x058 + /* Second captured value of counter register */ +#define AM335X_WDT_BASE 0x44E35000 + /* Watchdog timer */ +#define AM335X_WDT_WWPS 0x34 + /* Command posted status */ +#define AM335X_WDT_WSPR 0x48 + /* Activate/deactivate sequence */ + +/* RTC registers */ +#define AM335X_RTC_BASE 0x44E3E000 +#define AM335X_RTC_SECS 0x0 +#define AM335X_RTC_MINS 0x4 +#define AM335X_RTC_HOURS 0x8 +#define AM335X_RTC_DAYS 0xc +#define AM335X_RTC_MONTHS 0x10 +#define AM335X_RTC_YEARS 0x14 +#define AM335X_RTC_WEEKS 0x18 +#define AM335X_RTC_CTRL_REG 0x40 +#define AM335X_RTC_STATUS_REG 0x44 +#define AM335X_RTC_REV_REG 0x74 +#define AM335X_RTC_SYSCONFIG 0x78 +#define AM335X_RTC_KICK0 0x6c +#define AM335X_RTC_KICK1 0x70 +#define AM335X_RTC_OSC_CLOCK 0x54 + +#define AM335X_RTC_KICK0_KEY 0x83E70B13 +#define AM335X_RTC_KICK1_KEY 0x95A4F1E0 + +/* GPIO memory-mapped registers */ + +#define AM335X_GPIO0_BASE 0x44E07000 + /* GPIO Bank 0 base Register */ +#define AM335X_GPIO1_BASE 0x4804C000 + /* GPIO Bank 1 base Register */ +#define AM335X_GPIO2_BASE 0x481AC000 + /* GPIO Bank 2 base Register */ +#define AM335X_GPIO3_BASE 0x481AE000 + /* GPIO Bank 3 base Register */ + +#define AM335X_GPIO_REVISION 0x00 +#define AM335X_GPIO_SYSCONFIG 0x10 +#define AM335X_GPIO_EOI 0x20 +#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24 +#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28 +#define AM335X_GPIO_IRQSTATUS_0 0x2C +#define AM335X_GPIO_IRQSTATUS_1 0x30 +#define AM335X_GPIO_IRQSTATUS_SET_0 0x34 +#define AM335X_GPIO_IRQSTATUS_SET_1 0x38 +#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C +#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40 +#define AM335X_GPIO_IRQWAKEN_0 0x44 +#define AM335X_GPIO_IRQWAKEN_1 0x48 +#define AM335X_GPIO_SYSSTATUS 0x114 +#define AM335X_GPIO_CTRL 0x130 +#define AM335X_GPIO_OE 0x134 +#define AM335X_GPIO_DATAIN 0x138 +#define AM335X_GPIO_DATAOUT 0x13C +#define AM335X_GPIO_LEVELDETECT0 0x140 +#define AM335X_GPIO_LEVELDETECT1 0x144 +#define AM335X_GPIO_RISINGDETECT 0x148 +#define AM335X_GPIO_FALLINGDETECT 0x14C +#define AM335X_GPIO_DEBOUNCENABLE 0x150 +#define AM335X_GPIO_DEBOUNCINGTIME 0x154 +#define AM335X_GPIO_CLEARDATAOUT 0x190 +#define AM335X_GPIO_SETDATAOUT 0x194 + +/* AM335X Pad Configuration Register Base */ +#define AM335X_PADCONF_BASE 0x44E10000 + +/* Memory mapped register offset for Control Module */ +#define AM335X_CONF_GPMC_AD0 0x800 +#define AM335X_CONF_GPMC_AD1 0x804 +#define AM335X_CONF_GPMC_AD2 0x808 +#define AM335X_CONF_GPMC_AD3 0x80C +#define AM335X_CONF_GPMC_AD4 0x810 +#define AM335X_CONF_GPMC_AD5 0x814 +#define AM335X_CONF_GPMC_AD6 0x818 +#define AM335X_CONF_GPMC_AD7 0x81C +#define AM335X_CONF_GPMC_AD8 0x820 +#define AM335X_CONF_GPMC_AD9 0x824 +#define AM335X_CONF_GPMC_AD10 0x828 +#define AM335X_CONF_GPMC_AD11 0x82C +#define AM335X_CONF_GPMC_AD12 0x830 +#define AM335X_CONF_GPMC_AD13 0x834 +#define AM335X_CONF_GPMC_AD14 0x838 +#define AM335X_CONF_GPMC_AD15 0x83C +#define AM335X_CONF_GPMC_A0 0x840 +#define AM335X_CONF_GPMC_A1 0x844 +#define AM335X_CONF_GPMC_A2 0x848 +#define AM335X_CONF_GPMC_A3 0x84C +#define AM335X_CONF_GPMC_A4 0x850 +#define AM335X_CONF_GPMC_A5 0x854 +#define AM335X_CONF_GPMC_A6 0x858 +#define AM335X_CONF_GPMC_A7 0x85C +#define AM335X_CONF_GPMC_A8 0x860 +#define AM335X_CONF_GPMC_A9 0x864 +#define AM335X_CONF_GPMC_A10 0x868 +#define AM335X_CONF_GPMC_A11 0x86C +#define AM335X_CONF_GPMC_WAIT0 0x870 +#define AM335X_CONF_GPMC_WPN 0x874 +#define AM335X_CONF_GPMC_BEN1 0x878 +#define AM335X_CONF_GPMC_CSN0 0x87C +#define AM335X_CONF_GPMC_CSN1 0x880 +#define AM335X_CONF_GPMC_CSN2 0x884 +#define AM335X_CONF_GPMC_CSN3 0x888 +#define AM335X_CONF_GPMC_CLK 0x88C +#define AM335X_CONF_GPMC_ADVN_ALE 0x890 +#define AM335X_CONF_GPMC_OEN_REN 0x894 +#define AM335X_CONF_GPMC_WEN 0x898 +#define AM335X_CONF_GPMC_BEN0_CLE 0x89C +#define AM335X_CONF_LCD_DATA0 0x8A0 +#define AM335X_CONF_LCD_DATA1 0x8A4 +#define AM335X_CONF_LCD_DATA2 0x8A8 +#define AM335X_CONF_LCD_DATA3 0x8AC +#define AM335X_CONF_LCD_DATA4 0x8B0 +#define AM335X_CONF_LCD_DATA5 0x8B4 +#define AM335X_CONF_LCD_DATA6 0x8B8 +#define AM335X_CONF_LCD_DATA7 0x8BC +#define AM335X_CONF_LCD_DATA8 0x8C0 +#define AM335X_CONF_LCD_DATA9 0x8C4 +#define AM335X_CONF_LCD_DATA10 0x8C8 +#define AM335X_CONF_LCD_DATA11 0x8CC +#define AM335X_CONF_LCD_DATA12 0x8D0 +#define AM335X_CONF_LCD_DATA13 0x8D4 +#define AM335X_CONF_LCD_DATA14 0x8D8 +#define AM335X_CONF_LCD_DATA15 0x8DC +#define AM335X_CONF_LCD_VSYNC 0x8E0 +#define AM335X_CONF_LCD_HSYNC 0x8E4 +#define AM335X_CONF_LCD_PCLK 0x8E8 +#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC +#define AM335X_CONF_MMC0_DAT3 0x8F0 +#define AM335X_CONF_MMC0_DAT2 0x8F4 +#define AM335X_CONF_MMC0_DAT1 0x8F8 +#define AM335X_CONF_MMC0_DAT0 0x8FC +#define AM335X_CONF_MMC0_CLK 0x900 +#define AM335X_CONF_MMC0_CMD 0x904 +#define AM335X_CONF_MII1_COL 0x908 +#define AM335X_CONF_MII1_CRS 0x90C +#define AM335X_CONF_MII1_RX_ER 0x910 +#define AM335X_CONF_MII1_TX_EN 0x914 +#define AM335X_CONF_MII1_RX_DV 0x918 +#define AM335X_CONF_MII1_TXD3 0x91C +#define AM335X_CONF_MII1_TXD2 0x920 +#define AM335X_CONF_MII1_TXD1 0x924 +#define AM335X_CONF_MII1_TXD0 0x928 +#define AM335X_CONF_MII1_TX_CLK 0x92C +#define AM335X_CONF_MII1_RX_CLK 0x930 +#define AM335X_CONF_MII1_RXD3 0x934 +#define AM335X_CONF_MII1_RXD2 0x938 +#define AM335X_CONF_MII1_RXD1 0x93C +#define AM335X_CONF_MII1_RXD0 0x940 +#define AM335X_CONF_RMII1_REF_CLK 0x944 +#define AM335X_CONF_MDIO 0x948 +#define AM335X_CONF_MDC 0x94C +#define AM335X_CONF_SPI0_SCLK 0x950 +#define AM335X_CONF_SPI0_D0 0x954 +#define AM335X_CONF_SPI0_D1 0x958 +#define AM335X_CONF_SPI0_CS0 0x95C +#define AM335X_CONF_SPI0_CS1 0x960 +#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964 +#define AM335X_CONF_UART0_CTSN 0x968 +#define AM335X_CONF_UART0_RTSN 0x96C +#define AM335X_CONF_UART0_RXD 0x970 +#define AM335X_CONF_UART0_TXD 0x974 +#define AM335X_CONF_UART1_CTSN 0x978 +#define AM335X_CONF_UART1_RTSN 0x97C +#define AM335X_CONF_UART1_RXD 0x980 +#define AM335X_CONF_UART1_TXD 0x984 +#define AM335X_CONF_I2C0_SDA 0x988 +#define AM335X_CONF_I2C0_SCL 0x98C +#define AM335X_CONF_MCASP0_ACLKX 0x990 +#define AM335X_CONF_MCASP0_FSX 0x994 +#define AM335X_CONF_MCASP0_AXR0 0x998 +#define AM335X_CONF_MCASP0_AHCLKR 0x99C +#define AM335X_CONF_MCASP0_ACLKR 0x9A0 +#define AM335X_CONF_MCASP0_FSR 0x9A4 +#define AM335X_CONF_MCASP0_AXR1 0x9A8 +#define AM335X_CONF_MCASP0_AHCLKX 0x9AC +#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0 +#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4 +#define AM335X_CONF_WARMRSTN 0x9B8 +#define AM335X_CONF_NNMI 0x9C0 +#define AM335X_CONF_TMS 0x9D0 +#define AM335X_CONF_TDI 0x9D4 +#define AM335X_CONF_TDO 0x9D8 +#define AM335X_CONF_TCK 0x9DC +#define AM335X_CONF_TRSTN 0x9E0 +#define AM335X_CONF_EMU0 0x9E4 +#define AM335X_CONF_EMU1 0x9E8 +#define AM335X_CONF_RTC_PWRONRSTN 0x9F8 +#define AM335X_CONF_PMIC_POWER_EN 0x9FC +#define AM335X_CONF_EXT_WAKEUP 0xA00 +#define AM335X_CONF_RTC_KALDO_ENN 0xA04 +#define AM335X_CONF_USB0_DRVVBUS 0xA1C +#define AM335X_CONF_USB1_DRVVBUS 0xA34 + +/* Registers for PWM Subsystem */ +#define AM335X_PWMSS_CTRL (0x664) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL (0xD4) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL (0xCC) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL (0xD8) +#define AM335X_CONTROL_MODULE (0x44e10000) +#define AM335X_CM_PER_ADDR (0x44e00000) +#define AM335X_PWMSS_CLKSTATUS (0xC) +#define AM335X_PWMSS0_MMAP_ADDR 0x48300000 +#define AM335X_PWMSS1_MMAP_ADDR 0x48302000 +#define AM335X_PWMSS2_MMAP_ADDR 0x48304000 +#define AM335X_PWMSS_MMAP_LEN 0x1000 +#define AM335X_PWMSS_IDVER 0x0 +#define AM335X_PWMSS_SYSCONFIG 0x4 +#define AM335X_PWMSS_CLKCONFIG 0x8 +#define AM335X_PWMSS_CLK_EN_ACK 0x100 +#define AM335X_EPWM_TBCTL 0x0 +#define AM335X_EPWM_TBSTS 0x2 +#define AM335X_EPWM_TBPHSHR 0x4 +#define AM335X_EPWM_TBPHS 0x6 +#define AM335X_EPWM_TBCNT 0x8 +#define AM335X_EPWM_TBPRD 0xA +#define AM335X_EPWM_CMPCTL 0xE +#define AM335X_EPWM_CMPAHR 0x10 +#define AM335X_EPWM_CMPA 0x12 +#define AM335X_EPWM_CMPB 0x14 +#define AM335X_EPWM_AQCTLA 0x16 +#define AM335X_EPWM_AQCTLB 0x18 +#define AM335X_EPWM_AQSFRC 0x1A +#define AM335X_EPWM_AQCSFRC 0x1C +#define AM335X_EPWM_DBCTL 0x1E +#define AM335X_EPWM_DBRED 0x20 +#define AM335X_EPWM_DBFED 0x22 +#define AM335X_TBCTL_CTRMODE_UP 0x0 +#define AM335X_TBCTL_CTRMODE_DOWN 0x1 +#define AM335X_TBCTL_CTRMODE_UPDOWN 0x2 +#define AM335X_TBCTL_CTRMODE_FREEZE 0x3 +#define AM335X_EPWM_AQCTLA_ZRO_XALOW (0x0001u) +#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH (0x0002u) +#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE (0x0003u) +#define AM335X_EPWM_AQCTLA_CAU_SHIFT (0x0004u) +#define AM335X_EPWM_AQCTLA_ZRO_XBLOW (0x0001u) +#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH (0x0002u) +#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE (0x0003u) +#define AM335X_EPWM_AQCTLB_CBU_SHIFT (0x0008u) +#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u) +#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u) +#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u) +#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_TBCTL_CLKDIV_MASK (3 << 10) +#define AM335X_TBCTL_HSPCLKDIV_MASK (3 << 7) +#define AM335X_EPWM_TBCTL_CLKDIV (0x1C00u) +#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT (0x000Au) +#define AM335X_EPWM_TBCTL_HSPCLKDIV (0x0380u) +#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u) +#define AM335X_EPWM_TBCTL_PRDLD (0x0008u) +#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK AM335X_EPWM_TBCTL_PRDLD +#define AM335X_EPWM_SHADOW_WRITE_ENABLE 0x0 +#define AM335X_EPWM_SHADOW_WRITE_DISABLE 0x1 +#define AM335X_EPWM_TBCTL_PRDLD_SHIFT (0x0003u) +#define AM335X_EPWM_TBCTL_CTRMODE (0x0003u) +#define AM335X_EPWM_COUNTER_MODE_MASK AM335X_EPWM_TBCTL_CTRMODE +#define AM335X_TBCTL_FREERUN (2 << 14) +#define AM335X_TBCTL_CTRMODE_SHIFT (0x0000u) +#define AM335X_EPWM_COUNT_UP (AM335X_TBCTL_CTRMODE_UP << \ + AM335X_TBCTL_CTRMODE_SHIFT) + +#define AM335X_EPWM_REGS (0x00000200) +#define AM335X_EPWM_0_REGS (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS) +#define AM335X_EPWM_1_REGS (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS) +#define AM335X_EPWM_2_REGS (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS) + +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u) + +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u) + +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u) + + + +/* I2C registers */ +#define AM335X_I2C0_BASE 0x44e0b000 + /* I2C0 base address */ +#define AM335X_I2C1_BASE 0x4802a000 + /* I2C1 base address */ +#define AM335X_I2C2_BASE 0x4819c000 + /* I2C2 base address */ +#define AM335X_I2C_REVNB_LO 0x00 + /* Module Revision Register (low bytes) */ +#define AM335X_I2C_REVNB_HI 0x04 + /* Module Revision Register (high bytes) */ +#define AM335X_I2C_SYSC 0x10 + /* System Configuration Register */ +#define AM335X_I2C_IRQSTATUS_RAW 0x24 + /* I2C Status Raw Register */ +#define AM335X_I2C_IRQSTATUS 0x28 + /* I2C Status Register */ +#define AM335X_I2C_IRQENABLE_SET 0x2c + /* I2C Interrupt Enable Set Register */ +#define AM335X_I2C_IRQENABLE_CLR 0x30 + /* I2C Interrupt Enable Clear Register */ +#define AM335X_I2C_WE 0x34 + /* I2C Wakeup Enable Register */ +#define AM335X_I2C_DMARXENABLE_SET 0x38 + /* Receive DMA Enable Set Register */ +#define AM335X_I2C_DMATXENABLE_SET 0x3c + /* Transmit DMA Enable Set Register */ +#define AM335X_I2C_DMARXENABLE_CLR 0x40 + /* Receive DMA Enable Clear Register */ +#define AM335X_I2C_DMATXENABLE_CLR 0x44 + /* Transmit DMA Enable Clear Register */ +#define AM335X_I2C_DMARXWAKE_EN 0x48 + /* Receive DMA Wakeup Register */ +#define AM335X_I2C_DMATXWAKE_EN 0x4c + /* Transmit DMA Wakeup Register */ +#define AM335X_I2C_SYSS 0x90 + /* System Status Register */ +#define AM335X_I2C_BUF 0x94 + /* Buffer Configuration Register */ +#define AM335X_I2C_CNT 0x98 + /* Data Counter Register */ +#define AM335X_I2C_DATA 0x9c + /* Data Access Register */ +#define AM335X_I2C_CON 0xa4 + /* I2C Configuration Register */ +#define AM335X_I2C_OA 0xa8 + /* I2C Own Address Register */ +#define AM335X_I2C_SA 0xac + /* I2C Slave Address Register */ +#define AM335X_I2C_PSC 0xb0 + /* I2C Clock Prescaler Register */ +#define AM335X_I2C_SCLL 0xb4 + /* I2C SCL Low Time Register */ +#define AM335X_I2C_SCLH 0xb8 + /* I2C SCL High Time Register */ +#define AM335X_I2C_SYSTEST 0xbc + /* System Test Register */ +#define AM335X_I2C_BUFSTAT 0xc0 + /* I2C Buffer Status Register */ +#define AM335X_I2C_OA1 0xc4 + /* I2C Own Address 1 Register */ +#define AM335X_I2C_OA2 0xc8 + /* I2C Own Address 2 Register */ +#define AM335X_I2C_OA3 0xcc + /* I2C Own Address 3 Register */ +#define AM335X_I2C_ACTOA 0xd0 + /* Active Own Address Register */ +#define AM335X_I2C_SBLOCK 0xd4 + /* I2C Clock Blocking Enable Register */ + +#define AM335X_CM_PER_L4LS_CLKSTCTRL (0x0) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define AM335X_CM_PER_L4LS_CLKCTRL (0x60) +#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_I2C1_CLKCTRL (0x48) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_I2C2_CLKCTRL (0x44) +#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u) +#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) +#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_I2C_CON_XSA (0x00000100u) +#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA +#define AM335X_I2C_CON_XSA_SHIFT (0x00000008u) +#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR (0 << AM335X_I2C_CON_XSA_SHIFT) +#define AM335X_I2C_CON_I2C_EN (0x00008000u) +#define AM335X_I2C_CON_TRX (0x00000200u) +#define AM335X_I2C_CON_MST (0x00000400u) +#define AM335X_I2C_CON_STB (0x00000800u) +#define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u) + +/*I2C0 module clock registers*/ + +#define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4) +#define AM335X_CM_WKUP_CLKSTCTRL (0x0) +#define AM335X_CM_WKUP_I2C0_CLKCTRL (0xb8) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK (0x00000800u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u) +#define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400) + +/* I2C status Register */ +#define AM335X_I2C_IRQSTATUS_NACK (1 << 1) +#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11) +#define AM335X_I2C_IRQSTATUS_AL (1<<0) +#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2) +#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3) +#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4) +#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10) +#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u) +#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u) +#define AM335X_I2C_IRQSTATUS_AAS (1 << 9) +#define AM335X_I2C_IRQSTATUS_BF (1 << 8) +#define AM335X_I2C_IRQSTATUS_STC (1 << 6) +#define AM335X_I2C_IRQSTATUS_GC (1 << 5) +#define AM335X_I2C_IRQSTATUS_XDR (1 << 14) +#define AM335X_I2C_IRQSTATUS_RDR (1 << 13) + +#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY +#define AM335X_I2C_CON_STOP (0x00000002u) +#define AM335X_I2C_CON_START (0x00000001u) +#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST +#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST) +#define AM335X_I2C_IRQSTATUS_RAW_BB (0x00001000u) +#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u) +#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF + +#endif diff --git a/bsps/arm/include/libcpu/mmu.h b/bsps/arm/include/libcpu/mmu.h new file mode 100644 index 0000000000..b82e838695 --- /dev/null +++ b/bsps/arm/include/libcpu/mmu.h @@ -0,0 +1,32 @@ +/* + * ARM MMU header file + */ + +/* + * Copyright (c) 2004 by Cogent Computer Systems + * Written by Jay Monkman + */ + +#ifndef __LIBCPU_MMU_H__ +#define __LIBCPU_MMU_H__ + +#include + +#define MMU_SECT_SIZE 0x100000 + +#define MMU_CACHE_NONE 0x0 +#define MMU_CACHE_BUFFERED 0x1 +#define MMU_CACHE_WTHROUGH 0x2 +#define MMU_CACHE_WBACK 0x3 + +typedef struct { + uint32_t paddr; + uint32_t vaddr; + uint32_t size; /* in MB */ + uint8_t cache_flags; +} mmu_sect_map_t; + +void mmu_init(mmu_sect_map_t *map); +void mmu_set_cpu_async_mode(void); + +#endif /* __MMU_H__ */ diff --git a/bsps/arm/include/libcpu/omap3.h b/bsps/arm/include/libcpu/omap3.h new file mode 100644 index 0000000000..0cc43d6383 --- /dev/null +++ b/bsps/arm/include/libcpu/omap3.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2012 Claas Ziemke. All rights reserved. + * + * Claas Ziemke + * Kernerstrasse 11 + * 70182 Stuttgart + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by Ben Gras to add lots + * of beagleboard/beaglebone definitions, delete lpc32xx specific + * ones, and merge with some other header files. + */ + +/* Interrupt controller memory map */ +#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller memory map */ +#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ + +/* Interrupt controller registers */ +#define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */ +#define OMAP3_INTCPS_SYSCONFIG 0x010 /* Controls params */ +#define OMAP3_INTCPS_SYSSTATUS 0x014 /* Status */ +#define OMAP3_INTCPS_SIR_IRQ 0x040 /* Active IRQ number */ +#define OMAP3_INTCPS_SIR_FIQ 0x044 /* Active FIQ number */ +#define OMAP3_INTCPS_CONTROL 0x048 /* New int agreement bits */ +#define OMAP3_INTCPS_PROTECTION 0x04C /* Protection for other regs */ +#define OMAP3_INTCPS_IDLE 0x050 /* Clock auto-idle/gating */ +#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */ +#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */ +#define OMAP3_INTCPS_THRESHOLD 0x068 /* Priority threshold */ +#define OMAP3_INTCPS_ITR0 0x080 /* Raw pre-masking interrupt status */ +#define OMAP3_INTCPS_MIR0 0x084 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR1 0x0A4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR2 0x0C4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR3 0x0E4 /* Interrupt mask */ +#define OMAP3_INTCPS_MIR_CLEAR0 0x088 /* Clear interrupt mask bits */ +#define OMAP3_INTCPS_MIR_SET0 0x08C /* Set interrupt mask bits */ +#define OMAP3_INTCPS_ISR_SET0 0x090 /* Set software int bits */ +#define OMAP3_INTCPS_ISR_CLEAR0 0x094 /* Clear software int bits */ +#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */ +#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */ +#define OMAP3_INTCPS_ILR0 0x100 /* Priority for interrupts */ + +/* SYSCONFIG */ +#define OMAP3_SYSCONFIG_AUTOIDLE 0x01 /* SYSCONFIG.AUTOIDLE bit */ + +#define OMAP3_INTR_ITR(base,n) \ + (base + OMAP3_INTCPS_ITR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR(base,n) \ + (base + OMAP3_INTCPS_MIR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR_CLEAR(base,n) \ + (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n)) +#define OMAP3_INTR_MIR_SET(base,n) \ + (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n)) +#define OMAP3_INTR_ISR_SET(base,n) \ + (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n)) +#define OMAP3_INTR_ISR_CLEAR(base,n) \ + (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n)) +#define OMAP3_INTR_PENDING_IRQ(base,n) \ + (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n)) +#define OMAP3_INTR_PENDING_FIQ(base,n) \ + (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n)) +#define OMAP3_INTR_ILR(base,m) \ + (base + OMAP3_INTCPS_ILR0 + 0x4 * (m)) + +#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */ +#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */ +#define OMAP3_INTR_NEWIRQAGR 0x1 /* New IRQ Generation */ + +#define OMAP3_DM337X_NR_IRQ_VECTORS 96 + +/* Interrupt mappings */ +#define OMAP3_MCBSP2_ST_IRQ 4 /* Sidestone McBSP2 overflow */ +#define OMAP3_MCBSP3_ST_IRQ 5 /* Sidestone McBSP3 overflow */ +#define OMAP3_SYS_NIRQ 7 /* External source (active low) */ +#define OMAP3_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */ +#define OMAP3_SMX_APP_IRQ 10 /* L3 interconnect error for application */ +#define OMAP3_PRCM_IRQ 11 /* PRCM module */ +#define OMAP3_SDMA0_IRQ 12 /* System DMA request 0 */ +#define OMAP3_SDMA1_IRQ 13 /* System DMA request 1 */ +#define OMAP3_SDMA2_IRQ 14 /* System DMA request 2 */ +#define OMAP3_SDMA3_IRQ 15 /* System DMA request 3 */ +#define OMAP3_MCBSP1_IRQ 16 /* McBSP module 1 */ +#define OMAP3_MCBSP2_IRQ 17 /* McBSP module 2 */ +#define OMAP3_GPMC_IRQ 20 /* General-purpose memory controller */ +#define OMAP3_SGX_IRQ 21 /* 2D/3D graphics module */ +#define OMAP3_MCBSP3_IRQ 22 /* McBSP module 3 */ +#define OMAP3_MCBSP4_IRQ 23 /* McBSP module 4 */ +#define OMAP3_CAM0_IRQ 24 /* Camera interface request 0 */ +#define OMAP3_DSS_IRQ 25 /* Display subsystem module */ +#define OMAP3_MAIL_U0_IRQ 26 /* Mailbox user 0 request */ +#define OMAP3_MCBSP5_IRQ 27 /* McBSP module 5 */ +#define OMAP3_IVA2_MMU_IRQ 28 /* IVA2 MMU */ +#define OMAP3_GPIO1_IRQ 29 /* GPIO module 1 */ +#define OMAP3_GPIO2_IRQ 30 /* GPIO module 2 */ +#define OMAP3_GPIO3_IRQ 31 /* GPIO module 3 */ +#define OMAP3_GPIO4_IRQ 32 /* GPIO module 4 */ +#define OMAP3_GPIO5_IRQ 33 /* GPIO module 5 */ +#define OMAP3_GPIO6_IRQ 34 /* GPIO module 6 */ +#define OMAP3_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */ +#define OMAP3_GPT1_IRQ 37 /* General-purpose timer module 1 */ +#define OMAP3_GPT2_IRQ 38 /* General-purpose timer module 2 */ +#define OMAP3_GPT3_IRQ 39 /* General-purpose timer module 3 */ +#define OMAP3_GPT4_IRQ 40 /* General-purpose timer module 4 */ +#define OMAP3_GPT5_IRQ 41 /* General-purpose timer module 5 */ +#define OMAP3_GPT6_IRQ 42 /* General-purpose timer module 6 */ +#define OMAP3_GPT7_IRQ 43 /* General-purpose timer module 7 */ +#define OMAP3_GPT8_IRQ 44 /* General-purpose timer module 8 */ +#define OMAP3_GPT9_IRQ 45 /* General-purpose timer module 9 */ +#define OMAP3_GPT10_IRQ 46 /* General-purpose timer module 10 */ +#define OMAP3_GPT11_IRQ 47 /* General-purpose timer module 11 */ +#define OMAP3_SPI4_IRQ 48 /* McSPI module 4 */ +#define OMAP3_MCBSP4_TX_IRQ 54 /* McBSP module 4 transmit */ +#define OMAP3_MCBSP4_RX_IRQ 55 /* McBSP module 4 receive */ +#define OMAP3_I2C1_IRQ 56 /* I2C module 1 */ +#define OMAP3_I2C2_IRQ 57 /* I2C module 2 */ +#define OMAP3_HDQ_IRQ 58 /* HDQ/1-Wire */ +#define OMAP3_MCBSP1_TX_IRQ 59 /* McBSP module 1 transmit */ +#define OMAP3_MCBSP1_RX_IRQ 60 /* McBSP module 1 receive */ +#define OMAP3_I2C3_IRQ 61 /* I2C module 3 */ +#define OMAP3_MCBSP2_TX_IRQ 62 /* McBSP module 2 transmit */ +#define OMAP3_MCBSP2_RX_IRQ 63 /* McBSP module 2 receive */ +#define OMAP3_SPI1_IRQ 65 /* McSPI module 1 */ +#define OMAP3_SPI2_IRQ 66 /* McSPI module 2 */ +#define OMAP3_UART1_IRQ 72 /* UART module 1 */ +#define OMAP3_UART2_IRQ 73 /* UART module 2 */ +#define OMAP3_UART3_IRQ 74 /* UART module 3 */ +#define OMAP3_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite 1/2 */ +#define OMAP3_OHCI_IRQ 76 /* OHCI HSUSB MP Host Interrupt */ +#define OMAP3_EHCI_IRQ 77 /* EHCI HSUSB MP Host Interrupt */ +#define OMAP3_TLL_IRQ 78 /* HSUSB MP TLL Interrupt */ +#define OMAP3_MCBSP5_TX_IRQ 81 /* McBSP module 5 transmit */ +#define OMAP3_MCBSP5_RX_IRQ 82 /* McBSP module 5 receive */ +#define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */ +#define OMAP3_MMC2_IRQ 86 /* MMC/SD module 2 */ +#define OMAP3_ICR_IRQ 87 /* MPU ICR */ +#define OMAP3_D2DFRINT_IRQ 88 /* 3G coproc (in stacked modem config) */ +#define OMAP3_MCBSP3_TX_IRQ 89 /* McBSP module 3 transmit */ +#define OMAP3_MCBSP3_RX_IRQ 90 /* McBSP module 3 receive */ +#define OMAP3_SPI3_IRQ 91 /* McSPI module 3 */ +#define OMAP3_HSUSB_MC_IRQ 92 /* High-speed USB OTG */ +#define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */ +#define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */ + +/* General-purpose timer register map */ +#define OMAP3_GPTIMER1_BASE 0x48318000 + /* GPTIMER1 physical address */ +#define OMAP3_GPTIMER2_BASE 0x49032000 + /* GPTIMER2 physical address */ +#define OMAP3_GPTIMER3_BASE 0x49034000 + /* GPTIMER3 physical address */ +#define OMAP3_GPTIMER4_BASE 0x49036000 + /* GPTIMER4 physical address */ +#define OMAP3_GPTIMER5_BASE 0x49038000 + /* GPTIMER5 physical address */ +#define OMAP3_GPTIMER6_BASE 0x4903A000 + /* GPTIMER6 physical address */ +#define OMAP3_GPTIMER7_BASE 0x4903C000 + /* GPTIMER7 physical address */ +#define OMAP3_GPTIMER8_BASE 0x4903E000 + /* GPTIMER8 physical address */ +#define OMAP3_GPTIMER9_BASE 0x49040000 + /* GPTIMER9 physical address */ +#define OMAP3_GPTIMER10_BASE 0x48086000 + /* GPTIMER10 physical address */ +#define OMAP3_GPTIMER11_BASE 0x48088000 + /* GPTIMER11 physical address */ + + +/* General-purpose timer registers */ +#define OMAP3_TIMER_TIDR 0x000 + /* IP revision code */ +#define OMAP3_TIMER_TIOCP_CFG 0x010 + /* Controls params for GP timer L4 iface */ +#define OMAP3_TIMER_TISTAT 0x014 + /* Status (excl. interrupt status) */ +#define OMAP3_TIMER_TISR 0x018 + /* Pending interrupt status */ +#define OMAP3_TIMER_TIER 0x01C + /* Interrupt enable */ +#define OMAP3_TIMER_TWER 0x020 + /* Wakeup enable */ +#define OMAP3_TIMER_TCLR 0x024 + /* Controls optional features */ +#define OMAP3_TIMER_TCRR 0x028 + /* Internal counter value */ +#define OMAP3_TIMER_TLDR 0x02C + /* Timer load value */ +#define OMAP3_TIMER_TTGR 0x030 + /* Triggers counter reload */ +#define OMAP3_TIMER_TWPS 0x034 + /* Indicates if Write-Posted pending */ +#define OMAP3_TIMER_TMAR 0x038 + /* Value to be compared with counter */ +#define OMAP3_TIMER_TCAR1 0x03C + /* First captured value of counter reg */ +#define OMAP3_TIMER_TSICR 0x040 + /* Control posted mode and functional SW rst */ +#define OMAP3_TIMER_TCAR2 0x044 + /* Second captured value of counter register */ +#define OMAP3_TIMER_TPIR 0x048 + /* Positive increment (1 ms tick) */ +#define OMAP3_TIMER_TNIR 0x04C + /* Negative increment (1 ms tick) */ +#define OMAP3_TIMER_TCVR 0x050 + /* Defines TCRR is sub/over-period (1 ms tick) */ +#define OMAP3_TIMER_TOCR 0x054 + /* Masks tick interrupt */ +#define OMAP3_TIMER_TOWR 0x058 + /* Number of masked overflow interrupts */ + +/* Interrupt status register fields */ +#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ +#define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */ +#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */ + +/* Interrupt enable register fields */ +#define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */ +#define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */ +#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */ + +/* Timer control fields */ +#define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */ +#define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */ +#define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */ +#define OMAP3_TCLR_PTV (1 << 1) /* looks like "bleed" from Minix */ +#define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */ + + +#define OMAP3_CM_CLKSEL_GFX 0x48004b40 +#define OMAP3_CM_CLKEN_PLL 0x48004d00 +#define OMAP3_CM_FCLKEN1_CORE 0x48004A00 +#define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */ +#define OMAP3_CM_FCLKEN_PER 0x48005000 +#define OMAP3_CM_CLKSEL_PER 0x48005040 +#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */ + + +#define CM_MODULEMODE_MASK (0x3 << 0) +#define CM_MODULEMODE_ENABLE (0x2 << 0) +#define CM_MODULEMODE_DISABLED (0x0 << 0) + +#define CM_CLKCTRL_IDLEST (0x3 << 16) +#define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16) +#define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16) +#define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16) +#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16) + +#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */ + +#define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) + /* This register manages the TIMER1 clocks. [Memory Mapped] */ + +#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */ +#define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) + /* This register manages the TIMER7 clocks. [Memory Mapped] */ + +/* CM_DPLL registers */ + +#define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */ + +#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28) + +#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0) +#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) + /* Select CLK_M_OSC clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) + /* Select CLK_32KHZ clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) + /* Select TCLKIN clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) + /* Select CLK_RC32K clock */ +#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) + /* Selects the CLK_32768 from 32KHz Crystal Osc */ + +#define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04) +#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0) +#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ +#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ + +/*RTC CLOCK BASE & Registers*/ +#define CM_RTC_BASE 0x44E00800 +#define CM_RTC_RTC_CLKCTRL 0x0 +#define CM_RTC_CLKSTCTRL 0x4 + + +#define OMAP3_CLKSEL_GPT1 (1 << 0) +#define OMAP3_CLKSEL_GPT10 (1 << 6) +#define OMAP3_CLKSEL_GPT11 (1 << 7) + +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 + +#define ARM_TTBR_ADDR_MASK (0xffffc000) +#define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/ +#define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back */ +#define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through */ +#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */ +#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA + +/* cpu control flags */ +/* CPU control register (CP15 register 1) */ +#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ +#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ +#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ +#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ +#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ +#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ +#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ +#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ +#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ +#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ +#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ +#define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ +#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ +#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ +#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ +#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ +#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ +#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ +#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ +#define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ +#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ +#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ +#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ +#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ +#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ +#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ + +#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE + +/* VM bits */ + +/* Big page (1MB section) specific flags. */ +#define ARM_VM_SECTION (1 << 1) + /* 1MB section */ +#define ARM_VM_SECTION_PRESENT (1 << 1) + /* Section is present */ +#define ARM_VM_SECTION_B (1 << 2) + /* B Bit */ +#define ARM_VM_SECTION_C (1 << 3) + /* C Bit */ +#define ARM_VM_SECTION_DOMAIN (0xF << 5) + /* Domain Number */ +#define ARM_VM_SECTION_SUPER (0x1 << 10) + /* Super access only AP[1:0] */ +#define ARM_VM_SECTION_USER (0x3 << 10) + /* Super/User access AP[1:0] */ +#define ARM_VM_SECTION_TEX0 (1 << 12) + /* TEX[0] */ +#define ARM_VM_SECTION_TEX1 (1 << 13) + /* TEX[1] */ +#define ARM_VM_SECTION_TEX2 (1 << 14) + /* TEX[2] */ +#define ARM_VM_SECTION_RO (1 << 15) + /* Read only access AP[2] */ +#define ARM_VM_SECTION_SHAREABLE (1 << 16) + /* Shareable */ +#define ARM_VM_SECTION_NOTGLOBAL (1 << 17) + /* Not Global */ + +#define ARM_VM_SECTION_WB \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B ) +/* inner and outer write-back, write-allocate */ +#define ARM_VM_SECTION_WT \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C ) +/* inner and outer write-through, no write-allocate */ +#define ARM_VM_SECTION_WTWB \ + (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C ) +/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ + +/* shareable device */ +#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB +#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B) diff --git a/bsps/arm/include/libcpu/omap_timer.h b/bsps/arm/include/libcpu/omap_timer.h new file mode 100644 index 0000000000..ef8787a571 --- /dev/null +++ b/bsps/arm/include/libcpu/omap_timer.h @@ -0,0 +1,39 @@ +/** + * @file + * + * @brief Clock driver configuration. + */ + +#include + +typedef struct omap_timer_registers +{ + uint32_t TIDR; + uint32_t TIOCP_CFG; + uint32_t TISTAT; + uint32_t TISR; + uint32_t TIER; + uint32_t TWER; + uint32_t TCLR; + uint32_t TCRR; + uint32_t TLDR; + uint32_t TTGR; + uint32_t TWPS; + uint32_t TMAR; + uint32_t TCAR1; + uint32_t TSICR; + uint32_t TCAR2; + uint32_t TPIR; + uint32_t TNIR; + uint32_t TCVR; + uint32_t TOCR; + uint32_t TOWR; + +} omap_timer_registers_t; + +typedef struct omap_timer +{ + uint32_t base; + int irq_nr; + struct omap_timer_registers *regs; +} omap_timer_t; diff --git a/bsps/arm/include/uart.h b/bsps/arm/include/uart.h new file mode 100644 index 0000000000..742c56bda3 --- /dev/null +++ b/bsps/arm/include/uart.h @@ -0,0 +1,163 @@ +/** + * @file + * + * @ingroup arm_comm + * + * @brief UART Support + */ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + * + * Copyright (c) Canon Research France SA.] + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#include + +void BSP_uart_init(int uart, int baud, int hwFlow); +void BSP_uart_set_baud(int aurt, int baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +int BSP_uart_termios_write_com1(int minor, const char *buf, int len); +int BSP_uart_termios_write_com2(int minor, const char *buf, int len); +void BSP_uart_termios_isr_com1(); +void BSP_uart_termios_isr_com2(); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +extern unsigned BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(int val); +extern int BSPConsolePort; +extern int BSPBaseBaud; +/* + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ + +/* Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) /* No character */ +#define BSP_UART_STATUS_NOCHAR (0) /* No character */ +#define BSP_UART_STATUS_CHAR (1) /* Character present */ +#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ + +/* PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/* + * Base IO for UART + */ + +#define COM1_BASE_IO 0x3F8 +#define COM2_BASE_IO 0x2F8 + +/* + * Offsets from base + */ + +/* DLAB 0 */ +#define RBR RSRBR /* Rx Buffer Register (read) */ +#define THR RSTHR /* Tx Buffer Register (write) */ +#define IER RSIER /* Interrupt Enable Register */ + +/* DLAB X */ +#define IIR RSIIR /* Interrupt Ident Register (read) */ +#define FCR RSFCR /* FIFO Control Register (write) */ +#define LCR RSLCR /* Line Control Register */ +#define LSR RSLSR /* Line Status Register */ + +/* DLAB 1 */ +#define DLL RSDLL /* Divisor Latch, LSB */ +#define DLM RSDLH /* Divisor Latch, MSB */ + +/* Uart control */ +#define CNT RSCNT /* General Control register */ + +/* + * define bit for CNT + */ +#define UART_ENABLE 1 +#define PAD_ENABLE 2 + +/* + * Interrupt source definition via IIR + */ +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/* + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define INTERRUPT_DISABLE 0x0 + +/* + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ + +/* + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 /* Word length mask */ +#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ +#define PEN 0x08 /* Parity Enabled */ +#define EPS 0x10 /* Even Parity Select, otherwise Odd */ +#define SP 0x20 /* Stick Parity */ +#define BCB 0x40 /* Break Control Bit */ +#define DLAB 0x80 /* Enable Divisor Latch Access */ + +/* + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ +#define FIFO_EN 0x01 /* Enable the FIFO */ +#define XMIT_RESET 0x04 /* Transmit FIFO Reset */ +#define RCV_RESET 0x02 /* Receive FIFO Reset */ +#define FCR3 0x08 /* do not understand manual! */ + +#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */ +#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */ +#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */ +#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 14 byte */ +#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ + +#endif /* _BSPUART_H */ diff --git a/bsps/arm/lm3s69xx/headers.am b/bsps/arm/lm3s69xx/headers.am new file mode 100644 index 0000000000..2572e1ab9c --- /dev/null +++ b/bsps/arm/lm3s69xx/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/ssi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/syscon.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lm3s69xx/include/bsp/uart.h diff --git a/bsps/arm/lm3s69xx/include/bsp.h b/bsps/arm/lm3s69xx/include/bsp.h new file mode 100644 index 0000000000..b07656cb73 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp.h @@ -0,0 +1,52 @@ +/** + * @file + * + * @ingroup arm_lm3s69xx + * + * @brief Global BSP Definitions + */ + +/* + * Copyright (c) 2011-2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_BSP_H +#define LIBBSP_ARM_LM3S69XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (5 << 5) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (6 << 5) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY LM3S69XX_SYSTEM_CLOCK + +#ifndef ASM + +#include + +#include + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LM3S69XX_BSP_H */ + +/** + * @defgroup arm_lm3s69xx LM3S69XX Support + * + * @ingroup bsp_arm + * + * @brief LM3S69XX Support Package + */ diff --git a/bsps/arm/lm3s69xx/include/bsp/io.h b/bsps/arm/lm3s69xx/include/bsp/io.h new file mode 100644 index 0000000000..f9ddf4c8ee --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/io.h @@ -0,0 +1,191 @@ +/** + * @file + * + * @ingroup lm3s69xx_io + * + * @brief IO definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_IO_H +#define LIBBSP_ARM_LM3S69XX_IO_H +#include +#include + +/** + * @defgroup lm3s69xx_io IO Support + * + * @ingroup arm_lm3s69xx + * + * @brief IO support. + */ + +typedef enum { + LM3S69XX_GPIO_DIRECTION_INPUT, + LM3S69XX_GPIO_DIRECTION_OUTPUT +} lm3s69xx_gpio_direction; + +typedef enum { + LM3S69XX_GPIO_OTYPE_PUSH_PULL, + LM3S69XX_GPIO_OTYPE_OPEN_DRAIN +} lm3s69xx_gpio_otype; + +typedef enum { + LM3S69XX_GPIO_DRIVE_2MA, + LM3S69XX_GPIO_DRIVE_4MA, + LM3S69XX_GPIO_DRIVE_8MA +} lm3s69xx_gpio_drive; + +typedef enum { + LM3S69XX_GPIO_NO_PULL, + LM3S69XX_GPIO_PULL_UP, + LM3S69XX_GPIO_PULL_DOWN +} lm3s69xx_gpio_pull; + +typedef enum { + LM3S69XX_GPIO_DIGITAL_DISABLE, + LM3S69XX_GPIO_DIGITAL_ENABLE, +} lm3s69xx_gpio_digital; + +typedef enum { + LM3S69XX_GPIO_AF_DISABLE, + LM3S69XX_GPIO_AF_ENABLE +} lm3s69xx_gpio_af; + +typedef enum { + LM3S69XX_GPIO_ANALOG_DISABLE, + LM3S69XX_GPIO_ANALOG_ENABLE +} lm3s69xx_gpio_analog; + +typedef enum { + LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL, + LM3S69XX_GPIO_SLEW_RATE_CONTROL +} lm3s69xx_gpio_slew_rate_control; + +typedef struct { + unsigned int pin_first : 8; + unsigned int pin_last : 8; + unsigned int digital : 1; + unsigned int alternate : 1; + unsigned int analog : 1; + unsigned int dir : 1; + unsigned int otype : 1; + unsigned int drive : 2; + unsigned int pull : 2; + unsigned int slr : 1; +} lm3s69xx_gpio_config; + +typedef enum { + LM3S69XX_PORT_A, + LM3S69XX_PORT_B, + LM3S69XX_PORT_C, + LM3S69XX_PORT_D, + LM3S69XX_PORT_E, + LM3S69XX_PORT_F, + LM3S69XX_PORT_G, +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 + LM3S69XX_PORT_H +#endif +} lm3s69xx_gpio_port; + +#define LM3S69XX_GPIO_PIN(port, idx) (((port) << 3) | (idx)) +#define LM3S69XX_GPIO_PORT_OF_PIN(pin) (((pin) >> 3) & 0xf) +#define LM3S69XX_GPIO_INDEX_OF_PIN(pin) ((pin) & 0x7) + +#define LM3S69XX_PIN_UART_TX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_RX(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_PULL_UP, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_RTS(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_UART_CTS(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_ENABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_2MA, \ + .pull = LM3S69XX_GPIO_PULL_UP, \ + .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_LED(port, idx) \ + { \ + .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ + .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ + .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ + .alternate = LM3S69XX_GPIO_AF_DISABLE, \ + .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ + .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ + .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ + .drive = LM3S69XX_GPIO_DRIVE_8MA, \ + .pull = LM3S69XX_GPIO_NO_PULL, \ + .slr = LM3S69XX_GPIO_SLEW_RATE_CONTROL \ + } + +#define LM3S69XX_PIN_SSI_TX(port, idx) LM3S69XX_PIN_UART_TX(port, idx) +#define LM3S69XX_PIN_SSI_RX(port, idx) LM3S69XX_PIN_UART_RX(port, idx) + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_gpio_set_config(const lm3s69xx_gpio_config *config); +void lm3s69xx_gpio_set_config_array(const lm3s69xx_gpio_config *configs, unsigned int count); +void lm3s69xx_gpio_digital_enable(unsigned int pin, bool enable); +void lm3s69xx_gpio_analog_mode_select(unsigned int pin, bool enable); + +void lm3s69xx_gpio_set_pin(unsigned int pin, bool set); +bool lm3s69xx_gpio_get_pin(unsigned int pin); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_IO_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/irq.h b/bsps/arm/lm3s69xx/include/bsp/irq.h new file mode 100644 index 0000000000..0b380c2ce2 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/irq.h @@ -0,0 +1,107 @@ +/** + * @file + * + * @ingroup lm3s69xx_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_IRQ_H +#define LIBBSP_ARM_LM3S69XX_IRQ_H + +#ifndef ASM + +#include +#include +#include +#include + +/** + * @defgroup lm3s69xx_interrupt Interrupt Support + * + * @ingroup arm_lm3s69xx + * + * @brief Interrupt support. + */ + +#endif /* ASM */ + +#define LM3S69XX_IRQ_GPIO_PORT_A 0 +#define LM3S69XX_IRQ_GPIO_PORT_B 1 +#define LM3S69XX_IRQ_GPIO_PORT_C 2 +#define LM3S69XX_IRQ_GPIO_PORT_D 3 +#define LM3S69XX_IRQ_GPIO_PORT_E 4 +#define LM3S69XX_IRQ_UART_0 5 +#define LM3S69XX_IRQ_UART_1 6 +#define LM3S69XX_IRQ_SSI_0 7 +#define LM3S69XX_IRQ_I2C_0 8 +#define LM3S69XX_IRQ_PWM_FAULT 9 +#define LM3S69XX_IRQ_PWM_GENERATOR_0 10 +#define LM3S69XX_IRQ_PWM_GENERATOR_1 11 +#define LM3S69XX_IRQ_PWM_GENERATOR_2 12 +#define LM3S69XX_IRQ_QEI_0 13 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_0 14 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_1 15 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_2 16 +#define LM3S69XX_IRQ_ADC0_SEQUENCE_3 17 +#define LM3S69XX_IRQ_WATCHDOG_TIMER_0 18 +#define LM3S69XX_IRQ_TIMER_0_A 19 +#define LM3S69XX_IRQ_TIMER_0_B 20 +#define LM3S69XX_IRQ_TIMER_1_A 21 +#define LM3S69XX_IRQ_TIMER_1_B 22 +#define LM3S69XX_IRQ_TIMER_2_A 23 +#define LM3S69XX_IRQ_TIMER_2_B 24 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 25 +#define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 26 +#define LM3S69XX_IRQ_SYSTEM_CONTROL 28 +#define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 29 +#define LM3S69XX_IRQ_GPIO_PORT_F 30 +#define LM3S69XX_IRQ_GPIO_PORT_G 31 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_GPIO_PORT_H 32 +#define LM3S69XX_IRQ_UART_2 33 +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_SSI_1 34 +#define LM3S69XX_IRQ_TIMER_3_A 35 +#define LM3S69XX_IRQ_TIMER_3_B 36 +#define LM3S69XX_IRQ_I2C_1 37 + +/* NOTE: lm3s6965 */ +#define LM3S69XX_IRQ_QEI_1 38 +#define LM3S69XX_IRQ_ETHERNET_CONTROLLER 42 + +#define LM3S69XX_IRQ_HIBERNATION_MODULE 43 + +/* NOTE: lm3s3749 */ +#define LM3S69XX_IRQ_USB 44 +#define LM3S69XX_IRQ_PWM_GENERATOR_3 45 +#define LM3S69XX_IRQ_UDMA_SOFTWARE 46 +#define LM3S69XX_IRQ_UDMA_ERROR 47 + +#define LM3S69XX_IRQ_PRIORITY_VALUE_MIN 0 +#define LM3S69XX_IRQ_PRIORITY_VALUE_MAX 7 +#define LM3S69XX_IRQ_PRIORITY_COUNT (LM3S69XX_IRQ_PRIORITY_VALUE_MAX + 1) +#define LM3S69XX_IRQ_PRIORITY_HIGHEST LM3S69XX_IRQ_PRIORITY_VALUE_MIN +#define LM3S69XX_IRQ_PRIORITY_LOWEST LM3S69XX_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN 0 +/* NOTE: for lm3s6965 - 43 */ +#define BSP_INTERRUPT_VECTOR_MAX 47 + +#endif /* LIBBSP_ARM_LM3S69XX_IRQ_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h b/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h new file mode 100644 index 0000000000..ce3548d376 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/lm3s69xx.h @@ -0,0 +1,407 @@ +/** + * @file + * + * @ingroup lm3s69xx_reg + * + * @brief Register definitions. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H +#define LIBBSP_ARM_LM3S69XX_LM3S69XX_H +#include +#include + +/** + * @defgroup lm3s69xx_reg Register Definitions + * + * @ingroup arm_lm3s69xx + * + * @brief Register Definitions + */ + +#define LM3S69XX_SYSCON_BASE 0x400fe000 + +#define LM3S69XX_UART_0_BASE 0x4000c000 +#define LM3S69XX_UART_1_BASE 0x4000d000 +#define LM3S69XX_UART_2_BASE 0x4000e000 + +#ifdef LM3S69XX_USE_AHB_FOR_GPIO +#define LM3S69XX_GPIO_A_BASE 0x40058000 +#define LM3S69XX_GPIO_B_BASE 0x40059000 +#define LM3S69XX_GPIO_C_BASE 0x4005a000 +#define LM3S69XX_GPIO_D_BASE 0x4005b000 +#define LM3S69XX_GPIO_E_BASE 0x4005c000 +#define LM3S69XX_GPIO_F_BASE 0x4005d000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 6 +#define LM3S69XX_GPIO_G_BASE 0x4005e000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x4005f000 +#endif +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) +#else /* LM3S69XX_USE_AHB_FOR_GPIO */ +#define LM3S69XX_GPIO_A_BASE 0x40004000 +#define LM3S69XX_GPIO_B_BASE 0x40005000 +#define LM3S69XX_GPIO_C_BASE 0x40006000 +#define LM3S69XX_GPIO_D_BASE 0x40007000 +#define LM3S69XX_GPIO_E_BASE 0x40024000 +#define LM3S69XX_GPIO_F_BASE 0x40025000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 6 +#define LM3S69XX_GPIO_G_BASE 0x40026000 +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define LM3S69XX_GPIO_H_BASE 0x40027000 +#endif +#endif + +#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ + (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ + (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) +#endif /* LM3S69XX_USE_AHB_FOR_GPIO */ + +#define LM3S69XX_SSI_0_BASE 0x40008000 +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define LM3S69XX_SSI_1_BASE 0x40009000 +#if LM3S69XX_NUM_SSI_BLOCKS > 2 +#define LM3S69XX_SSI_2_BASE 0x4000A000 +#if LM3S69XX_NUM_SSI_BLOCKS > 3 +#define LM3S69XX_SSI_3_BASE 0x4000B000 +#endif +#endif +#endif + +#define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) + +#define LM3S69XX_PLL_FREQUENCY 400000000U + +typedef struct { + uint32_t data[256]; /* Masked data registers are included here. */ + uint32_t dir; + uint32_t is; + uint32_t ibe; + uint32_t iev; + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t afsel; + + uint32_t reserved_0[55]; + + uint32_t dr2r; + uint32_t dr4r; + uint32_t dr8r; + uint32_t odr; + uint32_t pur; + uint32_t pdr; + uint32_t slr; + uint32_t den; + uint32_t lock; + uint32_t cr; + uint32_t amsel; +} lm3s69xx_gpio; + +typedef struct { + uint32_t did0; + uint32_t did1; + + uint32_t dc0; + uint32_t reserved_0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; + uint32_t dc5; + uint32_t dc6; + uint32_t dc7; + + uint32_t reserved_1; + +#define SYSCONPBORCTL_BORIOR BSP_BIT32(1) + uint32_t pborctl; + +#define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) +#define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) + uint32_t ldopctl; + + uint32_t reserved_2[2]; + + uint32_t srcr0; + uint32_t srcr1; + uint32_t srcr2; + + uint32_t reserved_3; + +#define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) +#define SYSCONRIS_USBPLLRIS BSP_BIT32(7) +#define SYSCONRIS_PLLLRIS BSP_BIT32(6) +#define SYSCONRIS_BORRIS BSP_BIT32(1) + uint32_t ris; + +#define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) +#define SYSCONIMC_USBPLLLIM BSP_BIT32(7) +#define SYSCONIMC_PLLLIM BSP_BIT32(6) +#define SYSCONIMC_BORIM BSP_BIT32(1) + uint32_t imc; + +#define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) +#define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) +#define SYSCONMISC_PLLLMIS BSP_BIT32(6) +#define SYSCONMISC_BORMIS BSP_BIT32(1) + uint32_t misc; + +#define SYSCONRESC_MOSCFAIL BSP_BIT32(16) +#define SYSCONRESC_SW BSP_BIT32(4) +#define SYSCONRESC_WDT BSP_BIT32(3) +#define SYSCONRESC_BOR BSP_BIT32(2) +#define SYSCONRESC_POR BSP_BIT32(1) +#define SYSCONRESC_EXT BSP_BIT32(0) + uint32_t resc; + +#define SYSCONRCC_AGC BSP_BIT32(27) +#define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) +#define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) +#define SYSCONRCC_USESYSDIV BSP_BIT32(22) +#define SYSCONRCC_USEPWMDIV BSP_BIT32(20) +#define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) +#define SYSCONRCC_PWMDIV_DIV2_VAL 0 +#define SYSCONRCC_PWMDIV_DIV4_VAL 1 +#define SYSCONRCC_PWMDIV_DIV8_VAL 2 +#define SYSCONRCC_PWMDIV_DIV16_VAL 3 +#define SYSCONRCC_PWMDIV_DIV32_VAL 4 +#define SYSCONRCC_PWMDIV_DIV64_VAL 5 +#define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) +#define SYSCONRCC_PWRDN BSP_BIT32(13) +#define SYSCONRCC_BYPASS BSP_BIT32(11) +#define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) +#define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) +#define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) +#define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) +#define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) +#define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) +#define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) +#define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) +#define SYSCONRCC_IOSCDIS BSP_BIT32(1) +#define SYSCONRCC_MOSCDIS BSP_BIT32(0) + uint32_t rcc; + +#define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) +#define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) +#define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) +#define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) + uint32_t pllcfg; + + uint32_t reserved_4; + +#define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) +#define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) +#define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) +#define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) +#define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) +#define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) +#define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) +#define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) + uint32_t gpiohbctl; + +#define SYSCONRCC2_USERCC2 BSP_BIT32(31) +#define SYSCONRCC2_DIV400 BSP_BIT32(30) +#define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) +#define SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28) +#define SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28) +#define SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28) +#define SYSCONRCC2_USBPWRDN BSP_BIT32(14) +#define SYSCONRCC2_PWRDN2 BSP_BIT32(13) +#define SYSCONRCC2_BYPASS2 BSP_BIT32(11) +#define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) +#define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) + uint32_t rcc2; + + uint32_t reserved_5[2]; + +#define SYSCONMOSCCTL_CVAL BSP_BIT32(0) + uint32_t moscctl; + + uint32_t reserved_6[32]; + +#define SYSCONRCGC0_PWM BSP_BIT32(20) +#define SYSCONRCGC0_ADC BSP_BIT32(16) +#define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) +#define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) +#define SYSCONRCGC0_HIB BSP_BIT32(6) +#define SYSCONRCGC0_WDT BSP_BIT32(3) + uint32_t rcgc0; + +#define SYSCONRCGC1_COMP1 BSP_BIT32(25) +#define SYSCONRCGC1_COMP0 BSP_BIT32(24) +#define SYSCONRCGC1_TIMER3 BSP_BIT32(19) +#define SYSCONRCGC1_TIMER2 BSP_BIT32(18) +#define SYSCONRCGC1_TIMER1 BSP_BIT32(17) +#define SYSCONRCGC1_TIMER0 BSP_BIT32(16) +#define SYSCONRCGC1_I2C1 BSP_BIT32(14) +#define SYSCONRCGC1_I2C0 BSP_BIT32(12) +#define SYSCONRCGC1_QEI0 BSP_BIT32(8) +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +#define SYSCONRCGC1_SSI1 BSP_BIT32(5) +#endif +#define SYSCONRCGC1_SSI0 BSP_BIT32(4) +#define SYSCONRCGC1_UART2 BSP_BIT32(2) +#define SYSCONRCGC1_UART1 BSP_BIT32(1) +#define SYSCONRCGC1_UART0 BSP_BIT32(0) + uint32_t rcgc1; + +#define SYSCONRCGC2_USB0 BSP_BIT32(16) +#define SYSCONRCGC2_UDMA BSP_BIT32(13) +#if LM3S69XX_NUM_GPIO_BLOCKS > 7 +#define SYSCONRCGC2_GPIOH BSP_BIT32(7) +#endif +#define SYSCONRCGC2_GPIOG BSP_BIT32(6) +#define SYSCONRCGC2_GPIOF BSP_BIT32(5) +#define SYSCONRCGC2_GPIOE BSP_BIT32(4) +#define SYSCONRCGC2_GPIOD BSP_BIT32(3) +#define SYSCONRCGC2_GPIOC BSP_BIT32(2) +#define SYSCONRCGC2_GPIOB BSP_BIT32(1) +#define SYSCONRCGC2_GPIOA BSP_BIT32(0) + uint32_t rcgc2; + + uint32_t reserved_7; + + uint32_t scgc0; + uint32_t scgc1; + uint32_t scgc2; + + uint32_t reserved_8; + + uint32_t dcgc0; + uint32_t dcgc1; + uint32_t dcgc2; + + uint32_t reserved_9[6]; + +#define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) +#define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) +#define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) +#define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) + uint32_t dslpclkcfg; +} lm3s69xx_syscon; + +typedef struct { +#define UARTDR_OE BSP_BIT32(11) +#define UARTDR_BE BSP_BIT32(10) +#define UARTDR_PE BSP_BIT32(9) +#define UARTDR_FE BSP_BIT32(8) +#define UARTDR_ERROR_MSK BSP_MSK32(8, 11) +#define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) +#define UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) + uint32_t dr; + + uint32_t rsr_ecr; + uint32_t reserved_0[4]; + +#define UARTFR_TXFE BSP_BIT32(7) +#define UARTFR_RXFF BSP_BIT32(6) +#define UARTFR_TXFF BSP_BIT32(5) +#define UARTFR_RXFE BSP_BIT32(4) +#define UARTFR_BUSY BSP_BIT32(3) + uint32_t fr; + + uint32_t reserved_1; + + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + +#define UARTLCRH_SPS BSP_BIT32(7) +#define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) +#define UARTLCRH_FEN BSP_BIT32(4) +#define UARTLCRH_STP2 BSP_BIT32(3) +#define UARTLCRH_EPS BSP_BIT32(2) +#define UARTLCRH_PEN BSP_BIT32(1) +#define UARTLCRH_BRK BSP_BIT32(0) + uint32_t lcrh; + +#define UARTCTL_RXE BSP_BIT32(9) +#define UARTCTL_TXE BSP_BIT32(8) +#define UARTCTL_LBE BSP_BIT32(7) +#define UARTCTL_SIRLP BSP_BIT32(2) +#define UARTCTL_SIREN BSP_BIT32(1) +#define UARTCTL_UARTEN BSP_BIT32(0) + uint32_t ctl; + +#define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) + uint32_t ifls; + +#define UARTI_OE BSP_BIT32(10) +#define UARTI_BE BSP_BIT32(9) +#define UARTI_PE BSP_BIT32(8) +#define UARTI_FE BSP_BIT32(7) +#define UARTI_RT BSP_BIT32(6) +#define UARTI_TX BSP_BIT32(5) +#define UARTI_RX BSP_BIT32(4) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#if LM3S69XX_HAS_UDMA + uint32_t dmactl; +#endif +} lm3s69xx_uart; + +typedef struct { +#define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) +#define SSICR0_SPH BSP_BIT32(7) +#define SSICR0_SPO BSP_BIT32(6) +#define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) +#define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) + uint32_t cr0; + +#define SSICR1_SOD BSP_BIT32(3) +#define SSICR1_MS BSP_BIT32(2) +#define SSICR1_SSE BSP_BIT32(1) +#define SSICR1_LBM BSP_BIT32(0) + uint32_t cr1; + uint32_t dr; + +#define SSISR_BSY BSP_BIT32(4) +#define SSISR_RFF BSP_BIT32(3) +#define SSISR_RNE BSP_BIT32(2) +#define SSISR_TNF BSP_BIT32(1) +#define SSISR_TFE BSP_BIT32(0) + uint32_t sr; + +#define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) + uint32_t cpsr; + +#define SSII_TX BSP_BIT32(3) +#define SSII_RX BSP_BIT32(2) +#define SSII_RT BSP_BIT32(1) +#define SSII_ROR BSP_BIT32(0) + uint32_t im; + uint32_t ris; + uint32_t mis; + uint32_t icr; + +#if LM3S69XX_HAS_UDMA +#define SSIDMACTL_TXDMAE BSP_BIT32(1) +#define SSIDMACTL_RXDMAE BSP_BIT32(0) + uint32_t dmactl; +#endif /* LM3S69XX_HAS_UDMA */ +} lm3s69xx_ssi; + +#endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/ssi.h b/bsps/arm/lm3s69xx/include/bsp/ssi.h new file mode 100644 index 0000000000..e6e44c5aae --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/ssi.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup lm3s69xx_ssi + * + * @brief SSI support. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SSI_H +#define LIBBSP_ARM_LM3S69XX_SSI_H +#include +#include + +/** + * @defgroup lm3s69xx_ssi SSI Support + * + * @ingroup arm_lm3s69xx + * + * @brief SSI Support + */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_0; + +#if LM3S69XX_NUM_SSI_BLOCKS > 1 +extern rtems_libi2c_bus_t * const lm3s69xx_ssi_1; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SSI_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/syscon.h b/bsps/arm/lm3s69xx/include/bsp/syscon.h new file mode 100644 index 0000000000..016839b5e5 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/syscon.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup lm3s69xx_syscon + * + * @brief Syscon support. + */ + +/* + * Copyright © 2013 Eugeniy Meshcheryakov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_ARM_LM3S69XX_SYSCON_H +#define LIBBSP_ARM_LM3S69XX_SYSCON_H +#include + +/** + * @defgroup lm3s69xx_syscon Syscon Support + * + * @ingroup arm_lm3s69xx + * + * @brief Syscon Support + */ + +#ifdef __cplusplus +extern "C" { +#endif + +void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable); +void lm3s69xx_syscon_enable_pwm_clock(bool enable); +void lm3s69xx_syscon_set_pwmdiv(unsigned int div); +void lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_LM3S69XX_SYSCON_H */ diff --git a/bsps/arm/lm3s69xx/include/bsp/uart.h b/bsps/arm/lm3s69xx/include/bsp/uart.h new file mode 100644 index 0000000000..544fed55eb --- /dev/null +++ b/bsps/arm/lm3s69xx/include/bsp/uart.h @@ -0,0 +1,46 @@ +/** + * @file + * + * @ingroup lm3s69xx_uart + * + * brief UART support. + */ + +/* + * Copyright (c) 2011 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LM3S69XX_UART_H +#define LIBBSP_ARM_LM3S69XX_UART_H + +#include + +/** + * defgroup lm3s69xx_uart UART Support + * + * @ingroup arm_lm3s69xx + * + * @brief UART support. + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const console_fns lm3s69xx_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LM3S69XX_UART_H */ diff --git a/bsps/arm/lm3s69xx/include/tm27.h b/bsps/arm/lm3s69xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lm3s69xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc176x/headers.am b/bsps/arm/lpc176x/headers.am new file mode 100644 index 0000000000..aceb1c4fa5 --- /dev/null +++ b/bsps/arm/lpc176x/headers.am @@ -0,0 +1,30 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc176x/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/adc-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/adc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/can-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/can.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/common-types.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/gpio-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/io-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/lpc176x.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/mbed-pinmap.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/pwmout-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/pwmout.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/system-clocks.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/timer-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/timer.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/watchdog-defs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc176x/include/bsp/watchdog.h diff --git a/bsps/arm/lpc176x/include/bsp.h b/bsps/arm/lpc176x/include/bsp.h new file mode 100644 index 0000000000..e81e1cd53c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc176x + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_BSP_H +#define LIBBSP_ARM_LPC176X_BSP_H + +#include + +#define LPC176X_PCLK ( LPC176X_CCLK / LPC176X_PCLKDIV ) +#define LPC176X_MPU_REGION_COUNT 8u + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT ( 29u << 3u ) +#define BSP_ARMV7M_SYSTICK_PRIORITY ( 30u << 3u ) +#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC176X_CCLK + +#ifndef ASM + +#include +#include + +/** Define operation count for Tests */ +#define OPERATION_COUNT 4 + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** + * @defgroup lpc176x LPC176X Support + * + * @ingroup bsp_arm + * + * @brief LPC176X support package. + * + * @{ + */ + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor + * clock to be stopped, while on-chip peripherals remain active. + * Any enabled interrupt from a peripheral or an external interrupt source + * will cause the processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread + * + * #include + * @endcode + */ +void*bsp_idle_thread( uintptr_t ignored ); + +#define BSP_CONSOLE_UART_BASE 0x4000C000U + +/** + * @brief Restarts the bsp with "addr" address + * @param addr Address used to restart the bsp + */ +void bsp_restart( const void *addr ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC176X_BSP_H */ diff --git a/bsps/arm/lpc176x/include/bsp/adc-defs.h b/bsps/arm/lpc176x/include/bsp/adc-defs.h new file mode 100755 index 0000000000..3daca807b7 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/adc-defs.h @@ -0,0 +1,96 @@ +/** + * @file adc-defs.h + * + * @ingroup lpc176x + * + * @brief ADC library for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LPC176X_ADC_DEFS_H +#define LPC176X_ADC_DEFS_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief The ADC inputs of the board. + */ +typedef enum { + ADC_0, + ADC_1, + ADC_2, + ADC_3, + ADC_4, + ADC_5, + ADC_6, + ADC_7, + ADC_DEVICES_COUNT +} lpc176x_adc_number; + +#define MAX_ADC_CLK 13000000u + +#define ADC_RANGE 0xFFFu + +#define ADC_NUMBER_VALID( number ) ( ( (uint32_t) number ) < \ + ADC_DEVICES_COUNT ) + +#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) +#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) +#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) +#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) +#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) +#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) +#define ADC_CR_BURST BSP_BIT32( 16 ) +#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) +#define ADC_CR_PDN BSP_BIT32( 21 ) +#define ADC_CR_START_NOW BSP_BIT32( 24 ) +#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) +#define ADC_CR_EDGE BSP_BIT32( 27 ) + +#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 4, 15 ) +#define ADC_DR_OVERRUN BSP_BIT32( 30 ) +#define ADC_DR_DONE BSP_BIT32( 31 ) + +#define ADC_DATA_CONVERSION_DONE( val ) ( ( val & ADC_DR_DONE ) != 0u ) + +/** + * @brief The ADC low-level device. + */ +typedef struct { + volatile uint32_t ADCR; + volatile uint32_t ADGDR; + volatile uint32_t RESERVED0; + volatile uint32_t ADINTEN; + volatile uint32_t ADDR[ ADC_DEVICES_COUNT ]; + volatile uint32_t ADSTAT; + volatile uint32_t ADTRM; +} lpc176x_adc_device; + +/** + * @brief Represents the pin and function for each ADC input. + */ +typedef struct { + uint32_t pin_number; + lpc176x_pin_function pin_function; +} lpc176x_adc_pin_map; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/adc.h b/bsps/arm/lpc176x/include/bsp/adc.h new file mode 100755 index 0000000000..34df8b7efd --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/adc.h @@ -0,0 +1,60 @@ +/** + * @file adc.h + * + * @ingroup lpc176x + * + * @brief ADC library for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_ADC_H +#define LPC176X_ADC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Opens and initializes the ADC device. + * + * @param adc_number The ADC pin number to be initialized. + * @return RTEMS_SUCCESSFUL if the initialization was succesful, + * RTEMS_INVALID_NUMBER if wrong parameter. + */ +rtems_status_code adc_open( const lpc176x_pin_number pin_number ); + +/** + * @brief Closes the ADC device. + * + * @return RTEMS_SUCCESSFUL if closed succesfully. + */ +rtems_status_code adc_close( void ); + +/** + * @brief Starts a conversion, waits for it to finish and reads the value. + * + * @param pin_number The port to read the value. + * @param result The read result. (In a percentage between 0.0f and 1.0f). + */ +rtems_status_code adc_read( + const lpc176x_pin_number pin_number , + float *const result +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/can-defs.h b/bsps/arm/lpc176x/include/bsp/can-defs.h new file mode 100755 index 0000000000..4db229eb1c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/can-defs.h @@ -0,0 +1,183 @@ +/** + * @file can-defs.h + * + * @ingroup lpc176x + * + * @brief CAN controller for the lpc176x controller. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_TIMER_DEFS_H +#define LPC176X_TIMER_DEFS_H + +#include +#include + +/* CAN ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0x4003C000 + +#define CAN_DRIVER_IS_MINOR_VALID( minor ) ( minor < CAN_DEVICES_NUMBER ) +#define CAN_DEFAULT_BAUD_RATE 1000000u +#define CAN_DEFAULT_INTERRUPT_CONFIGURATION 0 + +#define MAX_NUMBER_OF_CAN_BITS 25u +#define MIN_NUMBER_OF_CAN_BITS 4u +#define CAN_BRP_EXTRA_BIT 1u +#define CAN_TSEG_EXTRA_BITS 3u +#define MAX_TSEG1_TSEG2_BITS 22u + +#define CAN_GSR_RBS_MASK 1u +#define CAN_CMR_RRB_MASK 4u + +#define CAN_MAXIMUM_DATA_SIZE 8u +#define CAN10_MAXIMUM_ID 0x7FFu + +/** + * @brief The Time segments of a CAN bit. + */ +typedef enum { + CAN_TSEG1, + CAN_TSEG2, + CAN_NUMBER_OF_TSEG, +} can_tseg_number; + +#define CAN_BTR_TSEG1_SHIFT 16u +#define CAN_BTR_TSEG2_SHIFT 20u +#define CAN_BTR_SJW_SHIFT 14u +#define CAN_BTR_BRP_SHIFT 0u + +#define CAN_BTR_TSEG1_MASK 0x000F0000U +#define CAN_BTR_TSEG2_MASK 0x00700000U +#define CAN_BTR_SJW_MASK 0x0000C000U +#define CAN_BTR_BRP_MASK 0x000003FFU + +#define WRONG_BTR_VALUE 0xFFFFFFFF + +/** + * @brief The transmit buffers of the CAN device. + */ +typedef enum { + CAN_TRANSMIT1, + CAN_TRANSMIT2, + CAN_TRANSMIT3, + CAN_NUMBER_OF_TRANSMIT_BUFFERS +} can_transmit_number; + +/** + * @brief The CAN status and control masks to send a message + * for each transmit buffer. + */ +typedef struct { + uint32_t can_status_mask; + uint32_t not_cc_cmr_value; +} can_transmit_info; + +/** @brief Represents the CAN controller registers.*/ +typedef struct { + volatile uint32_t MOD; + volatile uint32_t CMR; + volatile uint32_t GSR; + volatile uint32_t ICR; + volatile uint32_t IER; + volatile uint32_t BTR; + volatile uint32_t EWL; + volatile uint32_t SR; + volatile registers_can_message receive; + volatile registers_can_message transmit[ CAN_NUMBER_OF_TRANSMIT_BUFFERS ]; +} can_device; + +/** + * @brief A TX or RX pin for each CAN device . + */ +typedef enum { + CAN_TX_PIN, + CAN_RX_PIN, + NUMBER_OF_CAN_PINS +} can_pin_number; + +/** + * @brief A driver entry for each low level device. + */ +typedef struct { + can_device *const device; + const lpc176x_module module; + const uint32_t pconp_pin; + const uint32_t pins[ NUMBER_OF_CAN_PINS ]; + const lpc176x_pin_function pinfunction; +} can_driver_entry; + +/** @brief Represents the CAN centralized registers. */ +typedef struct { + volatile uint32_t TX_SR; + volatile uint32_t RX_SR; + volatile uint32_t MSR; +} can_central; + +/** @brief Represents the acceptance filter registers. */ +typedef struct { + volatile uint32_t AFMR; + volatile uint32_t SFF_SA; + volatile uint32_t SFF_GRP_SA; + volatile uint32_t EFF_SA; + volatile uint32_t EFF_GRP_SA; + volatile uint32_t EOT; + volatile uint32_t LUT_ERR_ADR; + volatile uint32_t LUT_ERR; + volatile uint32_t FCANIE; + volatile uint32_t FCANIC0; + volatile uint32_t FCANIC1; +} can_acceptance_filter; + +/** + * @brief The possible CAN formats for a message. + */ +typedef enum { + CANStandard = 0, + CANExtended = 1, + CANAny = 2 +} can_format; + +/** + * @brief The types of message. + */ +typedef enum { + CANData = 0, + CANRemote = 1 +} can_type; + +#define CAN_INTERRUPT_TYPE_MASK 0x1ffu + +/** + * @brief The vector with all the callbacks for the CAN isr. + */ +typedef lpc176x_can_isr lpc176x_can_isr_vector[ CAN_IRQ_NUMBER ]; + +#define CAN_MOD_RM 0x00000001U + +#define CAN_ACCF_AFMR_ACCOF 0x00000001U +#define CAN_ACCF_AFMR_ACCBP 0x00000002U +#define CAN_ACCF_AFMR_EFCAN 0x00000004U + +#define CAN_IER_RIE 0x000000001U +#define CAN_IER_TIE1 0x000000002U +#define CAN_IER_EIE 0x000000004U +#define CAN_IER_DOIE 0x000000008U +#define CAN_IER_WUIE 0x000000010U +#define CAN_IER_EPIEX 0x000000020U +#define CAN_IER_ALIEX 0x000000040U +#define CAN_IER_BEIEX 0x000000080U +#define CAN_IER_IDIEX 0x000000100U +#define CAN_IER_TIE2 0x000000200U +#define CAN_IER_TIE3 0x000000400U + +#endif /*LPC176X_TIMER_DEFS_H*/ diff --git a/bsps/arm/lpc176x/include/bsp/can.h b/bsps/arm/lpc176x/include/bsp/can.h new file mode 100755 index 0000000000..7515ec2f53 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/can.h @@ -0,0 +1,179 @@ +/** + * @file can.h + * + * @ingroup lpc176x + * + * @brief CAN controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_CAN_H +#define LPC176X_CAN_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief The CAN devices of the board. + */ +typedef enum { + CAN_0, + CAN_1, + CAN_DEVICES_NUMBER +} lpc176x_can_number; + +/** + * @brief A CAN message represented for the registers of the device. + */ +typedef struct { + uint32_t info; + uint32_t id; + uint32_t data_a; + uint32_t data_b; +} registers_can_message; + +/** + * @brief A CAN message represented with each logical parts + */ +typedef struct { + unsigned int reserved1 : 16; + unsigned int dlc : 4; /* Bits 16..19: DLC - Data Length Counter*/ + unsigned int reserved0 : 10; + unsigned int rtr : 1; /* Bit 30: Set if this is a RTR message*/ + unsigned int type : 1; /* Bit 31: Set if this is a 29-bit ID message*/ + unsigned int id; /* CAN Message ID (11-bit or 29-bit)*/ + unsigned char data[ 8 ]; /* CAN Message Data Bytes 0-7*/ +} low_level_can_message; + +/** + * @brief A CAN message represented of both forms. + */ +typedef union { + low_level_can_message low_level; + registers_can_message registers; +} can_message; + +/** + * @brief The possible interrupt sources for CAN. + */ +typedef enum { + IRQ_RX = 0, + IRQ_TX, + IRQ_ERROR, + IRQ_OVERRUN, + IRQ_WAKEUP, + IRQ_PASSIVE, + IRQ_ARB, + IRQ_BUS, + IRQ_READY, + CAN_IRQ_NUMBER +} can_irq_type; + +/** + * @brief An isr for a CAN interrupt + * + * @param number The CAN which rised the interrupt. + */ +typedef void (*lpc176x_can_isr) ( lpc176x_can_number number ); + +/** + * @brief A CAN frequency value + */ +typedef unsigned int can_freq; + +/** + * @brief Opens CAN device. + * @details It enables the module and gives it a clock, sets the pins, + * disables the interrupts, sets the frequency and bypasses + * the acceptance filter. + * + * @param minor The device to open. + * @param freq The desired frequency. + * @return RTEMS_SUCCESFUL on success. + */ +rtems_status_code can_open( lpc176x_can_number minor, can_freq freq ); + +/** + * @brief Closes the passed CAN device and shut it down. + * + * @param minor The device to close. + * @return RTEMS_SUCCESSFUL if ok, RTEMS_INVALID_NUMBER for a bad parameter. + */ +rtems_status_code can_close( lpc176x_can_number minor ); + +/** + * @brief Reads the CAN device. + * + * @param minor The CAN device to read. + * @param message The read message. + * @return RTEMS_SUCCESSFUL if read ok, RTEMS_IO_ERROR otherwise. + */ +rtems_status_code can_read( + const lpc176x_can_number minor, + can_message *message +); + +/** + * @brief Writes the passed CAN message into the selected CAN device. + * + * @param minor The device to write. + * @param message The message to write. + * @return RTEMS_SUCCESFUL if write ok. RTEMS_IO_ERROR otherwise. + */ +rtems_status_code can_write( + const lpc176x_can_number minor, + const can_message *const message +); + +/** + * @brief Registers an isr in the driver vector, and enables the interrupt +* in the device. + * + * @param number The CAN device to set + * @param type The interrupt type. + * @param isr The isr to register. + * @return RTEMS_SUCCESSFUL if ok RTEMS_INVALID_NUMBER otherwise. + */ +rtems_status_code can_register_isr( + const lpc176x_can_number number, + const can_irq_type type, + const lpc176x_can_isr isr +); + +/** + * @brief Creates a CAN message. + * @details [long description] + * + * @param msg The created message. + * @param _id The can id for the message. + * @param _data The data of the message. + * @param _len The length of the message. + * @return RTEMS_SUCCESFUL if created, RTEMS_INVALID_NUMBER otherwise. + */ +rtems_status_code create_can_message( + can_message *const msg, + const int _id, + const char *const _data, + const char _len +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ifndef LPC176X_CAN_H */ diff --git a/bsps/arm/lpc176x/include/bsp/common-types.h b/bsps/arm/lpc176x/include/bsp/common-types.h new file mode 100644 index 0000000000..943ff288a9 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/common-types.h @@ -0,0 +1,118 @@ +/** + * @file common-types.h + * + * @ingroup lpc176x + * + * @brief Definitions types used by some devices in common. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_COMMON_TYPES_H +#define LIBBSP_ARM_LPC176X_COMMON_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief A pin of the board. + */ +typedef uint32_t lpc176x_pin_number; + +/** + * @brief Microseconds representation. + */ +typedef uint32_t lpc176x_microseconds; + +/** + * @brief lpc176x module representation. + * + * Enumerated type to define the set of modules for a lpc176x board. + */ +typedef enum { + LPC176X_MODULE_WD, + LPC176X_MODULE_ADC, + LPC176X_MODULE_CAN_0, + LPC176X_MODULE_CAN_1, + LPC176X_MODULE_ACCF, + LPC176X_MODULE_DAC, + LPC176X_MODULE_GPDMA, + LPC176X_MODULE_GPIO, + LPC176X_MODULE_I2S, + LPC176X_MODULE_MCI, + LPC176X_MODULE_MCPWM, + LPC176X_MODULE_PCB, + LPC176X_MODULE_PWM_0, + LPC176X_MODULE_PWM_1, + LPC176X_MODULE_QEI, + LPC176X_MODULE_RTC, + LPC176X_MODULE_SYSCON, + LPC176X_MODULE_TIMER_0, + LPC176X_MODULE_TIMER_1, + LPC176X_MODULE_TIMER_2, + LPC176X_MODULE_TIMER_3, + LPC176X_MODULE_UART_0, + LPC176X_MODULE_UART_1, + LPC176X_MODULE_UART_2, + LPC176X_MODULE_UART_3, + LPC176X_MODULE_USB +} lpc176x_module; + +/** + * @brief Defines all the clock modules. + * + * Enumerated type to define the set of clock modules for a lpc176x board. + */ +typedef enum { + LPC176X_MODULE_PCLK_DEFAULT = 0x4U, + LPC176X_MODULE_CCLK = 0x1U, + LPC176X_MODULE_CCLK_2 = 0x2U, + LPC176X_MODULE_CCLK_4 = 0x0U, + LPC176X_MODULE_CCLK_6 = 0x3U, + LPC176X_MODULE_CCLK_8 = 0x3U +} lpc176x_module_clock; + +/** + * @brief Fast Input/Output registers representation. + */ +typedef struct { + /** + * @brief Direction control register. + */ + uint32_t dir; + uint32_t reserved[ 3U ]; + /** + * @brief Mask register for port. + */ + uint32_t mask; + /** + * @brief Pinvalue register using 'mask'. + */ + uint32_t pin; + /** + * @brief Output Set register using 'mask'. + */ + uint32_t set; + /** + * @brief Output Clear register using 'maks'. + */ + uint32_t clr; +} lpc176x_fio; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_COMMON_TYPES_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/dma.h b/bsps/arm/lpc176x/include/bsp/dma.h new file mode 100644 index 0000000000..65edfc4e30 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/dma.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc176x_dma + * + * @brief Direct memory access (DMA) support. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_DMA_H +#define LIBBSP_ARM_LPC176X_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc176x_dma DMA Support + * + * @ingroup lpc176x + * + * @brief Direct memory access (DMA) support. + * + * @{ + */ + +/** + * @brief Initializes the general purpose DMA. + */ +void lpc176x_dma_initialize( void ); + +/** + * @brief Tries to obtain the DMA channel @a channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid channel number. + * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. + */ +rtems_status_code lpc176x_dma_channel_obtain( unsigned channel ); + +/** + * @brief Releases the DMA channel @a channel. + * + * You must have obtained this channel with lpc176x_dma_channel_obtain() + * previously. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc176x_dma_channel_release( unsigned channel ); + +/** + * @brief Disables the DMA channel @a channel. + * + * If @a force is @c false the channel will be halted and disabled when the + * channel is inactive otherwise it will be disabled immediately. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc176x_dma_channel_disable( + unsigned channel, + bool force +); + +rtems_status_code lpc176x_dma_copy_initialize( void ); + +rtems_status_code lpc176x_dma_copy_release( void ); + +rtems_status_code lpc176x_dma_copy( + unsigned channel, + const void *dest, + const void *src, + size_t n, + size_t width +); + +rtems_status_code lpc176x_dma_copy_wait( unsigned channel ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_DMA_H */ diff --git a/bsps/arm/lpc176x/include/bsp/gpio-defs.h b/bsps/arm/lpc176x/include/bsp/gpio-defs.h new file mode 100644 index 0000000000..c6ed499d35 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/gpio-defs.h @@ -0,0 +1,218 @@ +/** + * @file gpio-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H +#define LIBBSP_ARM_LPC176X_GPIO_DEFS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* General Purpose Input/Output (GPIO) */ +#define LPC176X_GPIO_BASE_ADDR 0x40028000U +#define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U + +#define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ + 0x1CU ) ) + +/* GPIO Interrupt Registers */ +#define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x90U ) ) +#define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x94U ) ) +#define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0x84U ) ) +#define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0x88U ) ) +#define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x8CU ) ) +#define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xB0U ) ) +#define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xB4U ) ) +#define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0xA4U ) ) +#define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \ + LPC176X_GPIO_BASE_ADDR \ + + 0xA8U ) ) +#define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0xACU ) ) +#define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ + + 0x80U ) ) + +#define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U +#define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U + +#define LPC176X_MAX_PORT_NUMBER 160U +#define LPC176X_SET_BIT( reg, pin, value ) \ + reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin ) + +#define LPC176X_INT_STATUS ( *(volatile uint32_t *) \ + ( LPC176X_GPIO_INTERRUPT_STATUS ) ) +#define LPC176X_INT_STATUS_P0 1U +#define LPC176X_INT_STATUS_P2 ( 1U << 2U ) +#define LPC176X_INT_ENABLE 1U +#define LPC176X_INT_DISABLE 0U + +#define LPC176X_IRQ_EINT_3 21U + +#define LPC176X_PIN_BIT( pin ) ( 1U << pin ) + +/** + * @brief The direction of the GPIO port (input or output). + * + * Enumerated type to define the set of function types for a gpio device. + */ +typedef enum { + LPC176X_GPIO_FUNCTION_INPUT, + LPC176X_GPIO_FUNCTION_OUTPUT, + LPC176X_GPIO_FUNCTION_COUNT +} +lpc176x_gpio_direction; + +/** + * @brief The interrupt sources edge for a GPIO. + * + * Enumerated type to define the set of interrupt types for a gpio device. + */ +typedef enum { + LPC176X_GPIO_INTERRUPT_DISABLE, + LPC176X_GPIO_INTERRUPT_RISING, + LPC176X_GPIO_INTERRUPT_FALLING, + LPC176X_GPIO_INTERRUPT_BOTH, + LPC176X_GPIO_INTERRUPT_COUNT +} lpc176x_gpio_interrupt; + +/** + * @brief The ports for a GPIO. + * + * Enumerated type to define the set of ports for a gpio device. + */ +typedef enum { + LPC176X_GPIO_PORT_0, + LPC176X_GPIO_PORT_1, + LPC176X_GPIO_PORT_2, + LPC176X_GPIO_PORT_3, + LPC176X_GPIO_PORT_4, + LPC176X_GPIO_PORTS_COUNT +} lpc176x_gpio_ports; + +/** + * @brief Addresses for a GPIO. + * + * Enumerated type to define the set of fio bases addresses + * for a gpio device. + */ +typedef enum { + LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U, + LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U, + LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U, + LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U, + LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U, +} lpc176x_gpio_address; + +/** + * @brief Addresses for the two interrupts. + * + * Enumerated type to define the set of interrupt addresses + * for a gpio device. + */ +typedef enum { + LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U, + LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U, +} lpc176x_interrupt_address; + +/** + * @brief GPIO Interrupt register map. + */ +typedef struct { + /** + * @brief Interrupt Enable for Rising edge. + */ + volatile uint32_t StatR; + /** + * @brief Interrupt Enable for Falling edge. + */ + volatile uint32_t StatF; + /** + * @brief Interrupt Clear. + */ + volatile uint32_t Clr; + /** + * @brief Interrupt Enable for Rising edge. + */ + volatile uint32_t EnR; + /** + * @brief Interrupt Enable for Falling edge. + */ + volatile uint32_t EnF; +} lpc176x_interrupt_control; + +/** + * @brief A function that attends an interrupt for GPIO. + * + * @param pin Pin number. + * @param edge Interrupt. + * @return Pointer to the interrupt function. + */ +typedef void (*lpc176x_gpio_interrupt_function) ( + const lpc176x_pin_number pin, + const lpc176x_gpio_interrupt edge +); + +/** + * @brief A registered interrupt function for the pin 'pin'. + */ +typedef struct { + /** + * @brief Pin board. + */ + lpc176x_pin_number pin; + /** + * @brief A function that attends an interrupt for 'pin'. + */ + lpc176x_gpio_interrupt_function function; +} lpc176x_registered_interrupt_function; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/io-defs.h b/bsps/arm/lpc176x/include/bsp/io-defs.h new file mode 100644 index 0000000000..f9cf3dbbbd --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/io-defs.h @@ -0,0 +1,142 @@ +/** + * @file io-defs.h + * + * @ingroup lpc176x + * + * @brief Input/output module definitions. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IO_DEFS_H +#define LIBBSP_ARM_LPC176X_IO_DEFS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC176X_PLL0CON 0XAAU +#define LPC176X_PLL0CFG 0X55U + +#define LPC176X_CCLK_PRESCALER_DIVISOR 1000000U + +#define LPC176X_PINSEL ( &PINSEL0 ) +#define LPC176X_PINMODE ( &PINMODE0 ) + +#define LPC176X_PIN_SELECT( index ) ( ( index ) >> 4U ) +#define LPC176X_PIN_SELECT_SHIFT( index ) ( ( ( index ) & 0xFU ) << 1U ) +#define LPC176X_PIN_SELECT_MASK 0x3U +#define LPC176X_PIN_SELECT_MASK_SIZE 2U +#define LPC176X_PIN_UART_0_TXD 2U +#define LPC176X_PIN_UART_0_RXD 3U +#define LPC176X_PIN_UART_1_TXD 15U +#define LPC176X_PIN_UART_1_RXD 16U +#define LPC176X_PIN_UART_2_TXD 10U +#define LPC176X_PIN_UART_2_RXD 11U +#define LPC176X_PIN_UART_3_TXD 0U +#define LPC176X_PIN_UART_3_RXD 1U + +#define LPC176X_MODULE_BITS_COUNT 32U +#define LPC176X_MODULE_COUNT ( LPC176X_MODULE_USB + 1U ) + +#define LPC176X_IO_PORT_COUNT 5U +#define LPC176X_IO_INDEX_MAX ( LPC176X_IO_PORT_COUNT * \ + LPC176X_MODULE_BITS_COUNT ) +#define LPC176X_IO_INDEX_BY_PORT( port, bit ) ( ( ( port ) << 5U ) + ( bit ) ) +#define LPC176X_IO_PORT( index ) ( ( index ) >> 5U ) +#define LPC176X_IO_PORT_BIT( index ) ( ( index ) & 0x1FU ) + +/** + * @brief Defines the functions according to the pin. + * + * Enumerated type to define the set of pin function for a io device. + */ +typedef enum { + LPC176X_PIN_FUNCTION_00, + LPC176X_PIN_FUNCTION_01, + LPC176X_PIN_FUNCTION_10, + LPC176X_PIN_FUNCTION_11, + LPC176X_PIN_FUNCTION_COUNT +} +lpc176x_pin_function; + +/** + * @brief Defines the pin modes. + * + */ +typedef enum { + LPC176X_PIN_MODE_PULLUP, + LPC176X_PIN_MODE_REPEATER, + LPC176X_PIN_MODE_NONE, + LPC176X_PIN_MODE_PULLDOWN, + LPC176X_PIN_MODE_COUNT +} +lpc176x_pin_mode; + +/** + * @brief Defines all type of pins. + * + * Enumerated type to define the set of pin type for a io device. + */ +typedef enum { + LPC176X_PIN_TYPE_DEFAULT, + LPC176X_PIN_TYPE_ADC, + LPC176X_PIN_TYPE_DAC, + LPC176X_PIN_TYPE_OPEN_DRAIN +} lpc176x_pin_type; + +/** + * @brief Represents each pclksel number. + * + * Enumerated type to define the set of values for a pcklsel. + */ +typedef enum { + LPC176X_SCB_PCLKSEL0, + LPC176X_SCB_PCLKSEL1, + LPC176X_SCB_PCLKSEL_COUNT +} lpc176x_scb_value_pclksel; + +/** + * @brief Defines the module entry. + */ +typedef struct { + /** + * @brief Power entry bit. + */ + unsigned char power : 1; + /** + * @brief Clock entry bit. + */ + unsigned char clock : 1; + /** + * @brief Index entry bits. + */ + unsigned char index : 6; +} lpc176x_module_entry; + +#define LPC176X_MODULE_ENTRY( mod, pwr, clk, idx ) \ + [ mod ] = { \ + .power = pwr, \ + .clock = clk, \ + .index = idx \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_IO_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/io.h b/bsps/arm/lpc176x/include/bsp/io.h new file mode 100644 index 0000000000..4a8510479c --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/io.h @@ -0,0 +1,88 @@ +/** + * @file io.h + * + * @ingroup lpc176x + * + * @brief Input/output module methods definitions. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IO_H +#define LIBBSP_ARM_LPC176X_IO_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Sets pin to the selected function. + * + * @param pin The pin to set. + * @param function Defines the function to set. + */ +void lpc176x_pin_select( + uint32_t pin, + lpc176x_pin_function function +); + +/** + * @brief Sets pin to the selected mode. + * + * @param pin The pin to set. + * @param mode Defines the mode to set. + */ +void lpc176x_pin_set_mode( + const uint32_t pin, + const lpc176x_pin_mode mode +); + +/** + * @brief Enables the module power and clock. + * + * @param module Represents the module to be enabled. + * @param clock Represents the clock to set for this module. + * @return RTEMS_SUCCESFULL if the module was enabled succesfully. + */ +rtems_status_code lpc176x_module_enable( + lpc176x_module module, + lpc176x_module_clock clock +); + +/** + * @brief Checks if the current module is turned off and disables a module. + * + * @param module Represents the module to be disabled. + * @return RTEMS_SUCCESFULL if the module was disabled succesfully. + */ +rtems_status_code lpc176x_module_disable( lpc176x_module module ); + +/** + * @brief Checks if the current module is enabled or not. + * + * @param module Represents the module to be checked. + * @return TRUE if the module is enabled. + * FALSE otherwise. + */ +bool lpc176x_module_is_enabled( lpc176x_module module ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_IO_H */ diff --git a/bsps/arm/lpc176x/include/bsp/irq.h b/bsps/arm/lpc176x/include/bsp/irq.h new file mode 100644 index 0000000000..719608c8f7 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/irq.h @@ -0,0 +1,108 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief LPC176X interrupt definitions. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_IRQ_H +#define LIBBSP_ARM_LPC176X_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0U + +#define LPC176X_IRQ_WDT 0U +#define LPC176X_IRQ_TIMER_0 1U +#define LPC176X_IRQ_TIMER_1 2U +#define LPC176X_IRQ_TIMER_2 3U +#define LPC176X_IRQ_TIMER_3 4U +#define LPC176X_IRQ_UART_0 5U +#define LPC176X_IRQ_UART_1 6U +#define LPC176X_IRQ_UART_2 7U +#define LPC176X_IRQ_UART_3 8U +#define LPC176X_IRQ_PWM_1 9U +#define LPC176X_IRQ_PLL 16U +#define LPC176X_IRQ_RTC 17U +#define LPC176X_IRQ_EINT_0 18U +#define LPC176X_IRQ_EINT_1 19U +#define LPC176X_IRQ_EINT_2 20U +#define LPC176X_IRQ_EINT_3 21U +#define LPC176X_IRQ_ADC_0 22U +#define LPC176X_IRQ_BOD 23U +#define LPC176X_IRQ_USB 24U +#define LPC176X_IRQ_CAN 25U +#define LPC176X_IRQ_DMA 26U +#define LPC176X_IRQ_I2S 27U +#define LPC176X_IRQ_SD_MMC 29U +#define LPC176X_IRQ_MCPWM 30U +#define LPC176X_IRQ_QEI 31U +#define LPC176X_IRQ_PLL_ALT 32U +#define LPC176X_IRQ_USB_ACTIVITY 33U +#define LPC176X_IRQ_CAN_ACTIVITY 34U +#define LPC176X_IRQ_UART_4 35U +#define LPC176X_IRQ_GPIO 38U +#define LPC176X_IRQ_PWM 39U +#define LPC176X_IRQ_EEPROM 40U + +#define BSP_INTERRUPT_VECTOR_MAX 40 + +#define LPC176X_IRQ_PRIORITY_VALUE_MIN 0U + +#define LPC176X_IRQ_PRIORITY_VALUE_MAX 31U + +#define LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN +#define LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Sets the priority according to the current interruption. + * + * @param vector Interrupt to be attended. + * @param priority Interrupts priority. + */ +void lpc176x_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets the priority number according to the current interruption. + * + * @param vector Interrupts to be attended. + * @return The priority number according to the current interruption. + */ +unsigned lpc176x_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_LPC176X_IRQ_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h b/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..3eef02152e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc-clock-config.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup lpc176x + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_CLOCK_INTERRUPT LPC176X_IRQ_TIMER_0 +#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR +#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR +#define LPC_CLOCK_REFERENCE LPC176X_PCLK +#define LPC_CLOCK_MODULE_ENABLE() \ + lpc176x_module_enable( LPC176X_MODULE_TIMER_0, LPC176X_MODULE_PCLK_DEFAULT ) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc-gpio.h b/bsps/arm/lpc176x/include/bsp/lpc-gpio.h new file mode 100644 index 0000000000..9cb23df142 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc-gpio.h @@ -0,0 +1,100 @@ +/** + * @file lpc-gpio.h + * + * @ingroup lpc176x + * + * @brief API of the GPIO driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_GPIO_H +#define LIBBSP_ARM_LPC176X_GPIO_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Configures the pin as input or output GPIO. + * + * @param pin The pin to configure + * @param dir Input or output. + */ +rtems_status_code lpc176x_gpio_config( + lpc176x_pin_number pin, + lpc176x_gpio_direction dir +); + +/** + * @brief Configures the pin as input, enables interrupt for an + * edge/s and sets isrfunct as the function to call when that + * interrupt occurs. + * + * @param pin The pin to configure. + * @param edge Which edge or edges will activate the interrupt. + * @param isrfunct The function that is called when the interrupt occurs. + * @return RTEMS_SUCCESSFULL if the configurations was success. + */ +rtems_status_code lpc176x_gpio_config_input_with_interrupt( + lpc176x_pin_number pin, + lpc176x_gpio_interrupt edge, + lpc176x_gpio_interrupt_function isrfunct +); + +/** + * @brief Sets the output pin to 1. + * + * @param pin The pin to set + */ +rtems_status_code lpc176x_gpio_set_pin( lpc176x_pin_number pin ); + +/** + * @brief Sets the output pin to 0. + * + * @param pin The pin to set + */ +rtems_status_code lpc176x_gpio_clear_pin( lpc176x_pin_number pin ); + +/** + * @brief Sets the output pin to 0 or 1 according to value. + * + * @param pin The pin to set + * @param value the value to set. + */ +rtems_status_code lpc176x_gpio_write_pin( + lpc176x_pin_number pin, + bool value +); + +/** + * @brief Returns the value at the given input pin. + * + * @param pin The pin where to read the value. + * @param pin_value TRUE if the pin value was getted successfuly. + * @return RTEMS_SUCCESSFUL if the pin value was getted successfuly. + */ +rtems_status_code lpc176x_gpio_get_pin_value( + lpc176x_pin_number pin, + bool *pin_value +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_GPIO_H */ diff --git a/bsps/arm/lpc176x/include/bsp/lpc176x.h b/bsps/arm/lpc176x/include/bsp/lpc176x.h new file mode 100644 index 0000000000..f10991f346 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/lpc176x.h @@ -0,0 +1,1585 @@ +/** + * @file lpc176x.h + * + * @ingroup lpc176x + * + * @brief Specific register definitions according to lpc176x family boards. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_H +#define LIBBSP_ARM_LPC176X_H + +#include + +#define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 ) +#define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 ) +#define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 ) +#define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 ) +#define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 ) +#define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 ) +#define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 ) +#define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 ) +#define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 ) +#define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 ) +#define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 ) + +/** + * @brief Phase-Locked Loop representation. + */ +typedef struct { + /** + * @brief PLL Control Register. + */ + uint32_t con; + /** + * @brief PLL Configuration Register. + */ + uint32_t cfg; + /** + * @brief PLL Status Register. + */ + uint32_t stat; + /** + * @brief PLL Feed Register. + */ + uint32_t feed; +} lpc176x_pll; + +#define LPC176X_SCB_BASE_ADDR 0x400FC000U +#define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 ) +#define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 ) +#define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \ + 12, 15 ) +#define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 ) +/* POWER MODE CONTROL REGISTER (PCON) */ +/* Power mode control bit 0 */ +#define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 ) +/* Power mode control bit 1 */ +#define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 ) +/* Brown-Out Reduced ower Down */ +#define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 ) +/* Brown-Out Global Disable */ +#define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 ) +/* Brown-Out Reset Disable */ +#define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 ) +/* Sleep Mode entry flag */ +#define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 ) +/* Deep Sleep entry flag */ +#define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 ) +/* Power-Down entry flag */ +#define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 ) +/* Deep Power-Down entry flag */ +#define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 ) +/* POWER CONTROL for PERIPHERALS REGISTER (PCONP) */ +/* 0 - Reserved */ +/* Timer/Counter 0 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 ) +/* Timer/Counter 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 ) +/* UART 0 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 ) +/* UART 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 ) +/* 5 - Reserved */ +/* PWM 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 ) +/* The I2C0 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 ) +/* The SPI interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 ) +/* The RTC power/clock control bit */ +#define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 ) +/* The SSP1 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 ) +/* 11 - Reserved */ +/* A/D converter (ADC) power/clock control bit */ +#define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 ) +/* CAN Controller 1 power/clock control bit */ +#define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 ) +/* CAN Controller 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 ) +/* Power/clock control bit for IOCON, GPIO, and GPIO interrupts*/ +#define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 ) +/* Repetitive Interrupt Timer power/clock control bit */ +#define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 ) +/* Motor Control PWM */ +#define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 ) +/* Quadrate Encoder Interface power/clock control bit */ +#define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 ) +/* The IC21 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 ) +/* 20 - Reserved */ +/* The SSP0 interface power/clock control bit */ +#define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 ) +/* Timer 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 ) +/* Timer 3 power/clock control bit */ +#define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 ) +/* UART 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 ) +/* UART 3 power/clock control bit */ +#define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 ) +/* I2C interface 2 power/clock control bit */ +#define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 ) +/* I2S interface power/clock control bit */ +#define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 ) +/* 28 - Reserved */ +/* GPDMA function power/clock control bit */ +#define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 ) +/* Ethernet block power/clock control bit */ +#define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 ) +/* USB interface power/clock control bit */ +#define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 7 ) +#define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) +#define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 4 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 ) +#define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 8, \ + 9 ) +#define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 ) +#define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 ) +#define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 ) +#define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 ) +#define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) +#define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, \ + 0, \ + 4 ) +#define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \ + val, 3, 0 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \ + val, 7, 4 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 ) +#define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 ) + +/** + * @brief System Control Block representation. + */ +typedef struct { + /** + * @brief Flash Accelerator Configuration Register. + */ + uint32_t flashcfg; + uint32_t reserved_04[ 15 ]; + /** + * @brief Memopry Map Control. + */ + uint32_t memmap; + uint32_t reserved_44[ 15 ]; + /** + * @brief Phase-Locked Loop 0. + */ + lpc176x_pll pll_0; + uint32_t reserved_90[ 4 ]; + /** + * @brief Phase-Locked Loop 1. + */ + lpc176x_pll pll_1; + uint32_t reserved_b0[ 4 ]; + /** + * @brief Power Mode Control register. + */ + uint32_t pcon; + /** + * @brief Power Control for Peripherals register. + */ + uint32_t pconp; + uint32_t reserved_c8[ 15 ]; + /** + *@brief Selects the divide valuefor creating the CPU clock from the + * PPL0 output. + */ + uint32_t cclksel; + /** + * @brief Selects the divide value for creating the USB clock from the + * PPL0 output. + */ + uint32_t usbclksel; + /** + * @brief Clock Source Select register. + */ + uint32_t clksrcsel; + uint32_t reserved_110[ 12 ]; + /** + * @brief External Interrupt flag register. + */ + uint32_t extint; + uint32_t reserved_144; + /** + * @brief External Interrupt Mode register. + */ + uint32_t extmode; + /** + * @brief External Interrupt Polarity register. + */ + uint32_t extpolar; + uint32_t reserved_150[ 12 ]; + /** + * @brief Reset Source Identification Register. + */ + uint32_t rsid; + uint32_t reserved_184[ 7 ]; + /** + * @brief System Controls and Status Register. + */ + uint32_t scs; + uint32_t reserved_1a4; + /** + * @brief Peripheral Clock Selection registers 0 and 1. + */ + uint32_t pclksel[ 2 ]; + /** + * @brief Peripheral boost. + */ + uint32_t pboost; + uint32_t reserved_1b4[ 5 ]; + /** + * @brief Clock Output Configuration Register. + */ + uint32_t clkoutcfg; + /** + * @brief Reset Control bit 0 and 1. + */ + uint32_t rstcon[ 2 ]; + uint32_t reserved_1d4[ 4 ]; +} lpc176x_scb; + +#define LPC176X_BASE 0x00u +#define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) ) + +/* Fast I/O setup */ +#define LPC176X_FIO_BASE_ADDR 0x2009C000U +#define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR ) + +#define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) + +#define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) + +#define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) + +#define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) + +#define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) +#define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) +#define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) +#define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) +#define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) + +#define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) ) +#define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) +#define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) ) +#define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) ) +#define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) ) + +#define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) +#define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) +#define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) +#define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) +#define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) + +#define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) ) +#define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) ) +#define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) ) +#define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) ) +#define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) ) + +#define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) +#define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) +#define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) +#define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) +#define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) + +#define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) +#define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) +#define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) +#define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) +#define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) + +#define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) + +#define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) ) +#define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) +#define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) ) +#define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) ) +#define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) ) + +#define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) +#define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) +#define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) +#define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) +#define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) + +#define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) ) +#define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) ) +#define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) ) +#define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) ) +#define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) ) + +#define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) +#define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) +#define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) +#define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) +#define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) + +#define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) +#define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) +#define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) +#define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) +#define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) + +#define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) + +#define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) ) +#define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) ) +#define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) ) +#define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) ) +#define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) ) + +#define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) +#define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) +#define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) +#define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) +#define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) + +#define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) ) +#define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) ) +#define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) ) +#define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) ) +#define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) ) + +#define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) +#define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) +#define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) +#define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) +#define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) + +#define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) +#define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) +#define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) +#define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) +#define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) + +#define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) + +#define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) ) +#define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) ) +#define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) ) +#define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) ) +#define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) ) + +#define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) +#define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) +#define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) +#define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) +#define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) + +#define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) ) +#define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) ) +#define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) ) +#define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) ) +#define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) ) + +#define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) +#define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) +#define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) +#define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) +#define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) + +#define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) +#define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) +#define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) +#define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) +#define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) + +#define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) +#define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) +#define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) +#define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) +#define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +#define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) ) +#define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) ) +#define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) ) +#define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) ) +#define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) ) + +#define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) +#define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) +#define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) +#define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) +#define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) ) + +#define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) ) +#define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) ) +#define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) ) +#define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) ) +#define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) ) + +#define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) +#define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) +#define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) +#define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) +#define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) + +#define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) +#define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) +#define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) +#define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) +#define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) ) + +#define LPC176X_USB_CLOCK 48000000U +#define LPC176X_MODULE_CLOCK_MASK 0x3U + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0x4002C000U + +#define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) ) +#define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) ) +#define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) ) +#define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) ) +#define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) ) +#define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) ) +#define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) ) +#define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) ) +#define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) ) +#define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) ) +#define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) ) +#define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) ) + +#define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) ) +#define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) ) +#define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) ) +#define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) ) +#define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) ) +#define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) ) +#define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) ) +#define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) ) +#define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) ) +#define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) ) + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0x40014000 + +#define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) ) +#define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) ) +#define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) ) +#define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) ) +#define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) ) +#define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) ) +#define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) ) +#define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) ) +#define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) ) +#define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) ) +#define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) ) +#define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) ) +#define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) ) +#define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) ) +#define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) ) +#define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) ) +#define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) ) +#define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) ) +#define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) ) +#define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) ) +#define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) ) +#define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) ) + +#define PWM1_BASE_ADDR 0x40018000 + +#define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) ) +#define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) ) +#define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) ) +#define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) ) +#define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) ) +#define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) ) +#define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) ) +#define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) ) +#define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) ) +#define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) ) +#define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) ) +#define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) ) +#define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) ) +#define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) ) +#define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) ) +#define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) ) +#define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) ) +#define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) ) +#define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) ) +#define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) ) +#define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) ) +#define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) ) + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0x4000C000 + +#define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) +#define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) +#define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) +#define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) +#define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) +#define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) ) +#define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) ) +#define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) ) +#define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) ) +#define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) ) +#define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) ) +#define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0x40010000 + +#define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) +#define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) +#define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) +#define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) +#define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) +#define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) ) +#define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) ) +#define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) ) +#define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) ) +#define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) ) +#define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) ) +#define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) ) +#define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0x40098000 + +#define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) +#define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) +#define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) +#define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) +#define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) +#define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) ) +#define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) ) +#define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) ) +#define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) ) +#define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) ) +#define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) ) +#define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) ) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0x4009C000 + +#define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) +#define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) +#define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) +#define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) +#define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) +#define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) ) +#define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) ) +#define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) ) +#define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) ) +#define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) ) +#define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) ) +#define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) ) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) ) +#define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) ) +#define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) ) +#define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) ) +#define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) ) + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0x40024000 + +#define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) ) +#define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) ) +#define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) ) +#define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) ) +#define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) ) +#define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) ) +#define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) ) +#define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) ) +#define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) ) +#define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) ) +#define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) ) +#define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) ) +#define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) ) +#define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) ) +#define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) ) +#define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) ) +#define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) ) +#define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) ) +#define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) ) +#define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) ) +#define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) ) +#define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) ) +#define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) ) +#define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) ) +#define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) ) +#define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) ) +#define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) ) + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0x40034000 + +#define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) ) +#define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) ) +#define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) ) +#define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) +#define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) +#define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) ) +#define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) ) +#define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) ) +#define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) ) +#define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) ) +#define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) ) +#define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) ) +#define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) ) + +/* D/A Converter */ +#define DAC_BASE_ADDR 0x4008C000 + +#define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) ) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0x4003C000 + +#define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) ) +#define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) ) +#define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x08 ) ) +#define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) ) +#define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x10 ) ) +#define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) ) +#define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ + 0x18 ) ) +#define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) ) + +#define CAN_CENTRAL_BASE_ADDR 0x40040000 + +#define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) ) +#define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) ) +#define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) ) + +#define CAN1_BASE_ADDR 0x40044000 + +#define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) ) +#define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) ) +#define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) ) +#define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) ) +#define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) ) +#define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) ) +#define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) ) +#define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) ) +#define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) ) +#define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) ) +#define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) ) +#define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) ) + +#define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) ) +#define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) ) +#define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) ) +#define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) ) +#define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) ) +#define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) ) +#define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) ) +#define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) ) +#define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) ) +#define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) ) +#define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) ) +#define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) ) + +#define CAN2_BASE_ADDR 0x40048000 + +#define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) ) +#define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) ) +#define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) ) +#define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) ) +#define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) ) +#define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) ) +#define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) ) +#define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) ) +#define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) ) +#define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) ) +#define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) ) +#define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) ) + +#define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) ) +#define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) ) +#define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) ) +#define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) ) +#define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) ) +#define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) ) +#define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) ) +#define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) ) +#define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) ) +#define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) ) +#define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) ) +#define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) ) + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0x400c0000 + +#define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) ) +#define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) ) +#define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) ) +#define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) ) +#define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) ) +#define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) ) +#define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) ) +#define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) ) +#define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) ) +#define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) ) +#define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) ) +#define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) ) +#define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) ) +#define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) ) +#define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) ) +#define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) ) +#define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) ) +#define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) ) +#define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) ) + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0x400a8000 + +#define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) ) +#define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) ) +#define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) ) +#define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) ) +#define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) ) +#define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) ) +#define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) ) +#define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) ) +#define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) ) +#define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) ) + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0x50004000 + +#define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) ) +#define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) ) +#define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) ) +#define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) ) +#define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) ) +#define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ + 0x014 ) ) +#define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ + 0x018 ) ) +#define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) ) +#define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) ) +#define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) ) +#define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) ) +#define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) ) +#define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) ) +#define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) ) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 ) +#define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) ) +#define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) ) +#define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) ) +#define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) ) +#define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) ) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 ) +#define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) ) +#define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) ) +#define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) ) +#define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) ) +#define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) ) + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0x400fc1c0 +#define USB_BASE_ADDR 0x2008c200 + +#define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) ) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) ) +#define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) ) +#define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) ) +#define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) ) +#define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) ) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) ) +#define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) ) +#define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) ) +#define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) ) +#define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) ) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) ) +#define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) ) +#define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) ) + +/* USB Device Command Reagisters */ +#define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) ) +#define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) ) + +/* USB Device Data Transfer Registers */ +#define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) ) +#define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) ) +#define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) ) +#define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) ) +#define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) ) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) ) +#define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) ) +#define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) ) +#define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) ) +#define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) ) +#define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) ) +#define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) ) +#define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) ) +#define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) ) +#define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) ) +#define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) ) +#define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) ) +#define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) ) +#define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) ) +#define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) ) +#define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) ) +#define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) ) +#define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) ) + +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0x2008c000 + +#define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) ) +#define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) ) +#define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) ) +#define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) ) +#define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) ) +#define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) ) +#define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) ) +#define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) ) +#define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) ) +#define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) ) +#define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) ) +#define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) ) +#define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) ) +#define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) ) +#define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) ) +#define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) ) +#define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) ) +#define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) ) +#define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) ) +#define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) ) +#define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) ) +#define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) ) +#define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) ) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0x2008c100 + +#define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) ) +#define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) ) +#define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) ) +#define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) ) +#define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) ) +#define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) ) + +#define USBOTG_I2C_BASE_ADDR 0x2008c300 + +#define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) +#define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) +#define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) ) +#define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) ) +#define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ + 0x0C ) ) +#define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ + 0x10 ) ) + +#define USBOTG_CLK_BASE_ADDR 0x2008CFF0U + +#define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ + 0x04U ) ) +#define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ + 0x08U ) ) + +/* Register Fields */ +#define GET_FIELD( val, mask, shift ) \ + ( ( ( val ) & ( mask ) ) >> ( shift ) ) + +#define SET_FIELD( val, field, mask, shift ) \ + ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) ) + +/* CLKSRCSEL */ +#define CLKSRCSEL_CLKSRC_MASK 0x00000003U + +#define GET_CLKSRCSEL_CLKSRC( reg ) \ + GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 ) + +#define SET_CLKSRCSEL_CLKSRC( reg, val ) \ + SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 ) + +/* PLLCON */ +#define PLLCON_PLLE 0x00000001U + +#define PLLCON_PLLC 0x00000002U + +/* PLLCFG */ +#define PLLCFG_MSEL_MASK 0x00007fffU + +#define GET_PLLCFG_MSEL( reg ) \ + GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 ) + +#define SET_PLLCFG_MSEL( reg, val ) \ + SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 ) + +#define PLLCFG_NSEL_MASK 0x00ff0000U + +#define GET_PLLCFG_NSEL( reg ) \ + GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 ) + +#define SET_PLLCFG_NSEL( reg, val ) \ + SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 ) + +/* PLLSTAT */ +#define PLLSTAT_MSEL_MASK 0x00007fffU + +#define GET_PLLSTAT_MSEL( reg ) \ + GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 ) + +#define SET_PLLSTAT_MSEL( reg, val ) \ + SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 ) + +#define PLLSTAT_NSEL_MASK 0x00ff0000U + +#define GET_PLLSTAT_NSEL( reg ) \ + GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 ) + +#define SET_PLLSTAT_NSEL( reg, val ) \ + SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 ) + +#define PLLSTAT_PLLE 0x01000000U + +#define PLLSTAT_PLLC 0x02000000U + +#define PLLSTAT_PLOCK 0x04000000U + +/* CCLKCFG */ +#define CCLKCFG_CCLKSEL_MASK 0x000000ffU + +#define GET_CCLKCFG_CCLKSEL( reg ) \ + GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 ) + +#define SET_CCLKCFG_CCLKSEL( reg, val ) \ + SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 ) + +/* MEMMAP */ +#define MEMMAP_MAP_MASK 0x00000003U + +#define GET_MEMMAP_MAP( reg ) \ + GET_FIELD( reg, MEMMAP_MAP_MASK, 0 ) + +#define SET_MEMMAP_MAP( reg, val ) \ + SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 ) + +/* TIR */ +#define TIR_MR0 0x00000001U +#define TIR_MR1 0x00000002U +#define TIR_MR2 0x00000004U +#define TIR_MR3 0x00000008U +#define TIR_CR0 0x00000010U +#define TIR_CR1 0x00000020U +#define TIR_CR2 0x00000040U +#define TIR_CR3 0x00000080U + +/* TCR */ +#define TCR_EN 0x00000001U +#define TCR_RST 0x00000002U + +/* TMCR */ +#define TMCR_MR0I 0x00000001U +#define TMCR_MR0R 0x00000002U +#define TMCR_MR0S 0x00000004U +#define TMCR_MR1I 0x00000008U +#define TMCR_MR1R 0x00000010U +#define TMCR_MR1S 0x00000020U +#define TMCR_MR2I 0x00000040U +#define TMCR_MR2R 0x00000080U +#define TMCR_MR2S 0x00000100U +#define TMCR_MR3I 0x00000200U +#define TMCR_MR3R 0x00000400U +#define TMCR_MR3S 0x00000800U + +/* PCLKSEL0 */ +#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U + +#define GET_PCLKSEL0_PCLK_WDT( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 ) + +#define SET_PCLKSEL0_PCLK_WDT( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 ) + +#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU + +#define GET_PCLKSEL0_PCLK_TIMER0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) + +#define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) + +#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U + +#define GET_PCLKSEL0_PCLK_TIMER1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) + +#define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) + +#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U + +#define GET_PCLKSEL0_PCLK_UART0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 ) + +#define SET_PCLKSEL0_PCLK_UART0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 ) + +#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U + +#define GET_PCLKSEL0_PCLK_UART1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 ) + +#define SET_PCLKSEL0_PCLK_UART1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 ) + +#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U + +#define GET_PCLKSEL0_PCLK_PWM0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 ) + +#define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 ) + +#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U + +#define GET_PCLKSEL0_PCLK_PWM1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 ) + +#define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 ) + +#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U + +#define GET_PCLKSEL0_PCLK_I2C0( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 ) + +#define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 ) + +#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U + +#define GET_PCLKSEL0_PCLK_SPI( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 ) + +#define SET_PCLKSEL0_PCLK_SPI( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 ) + +#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U + +#define GET_PCLKSEL0_PCLK_RTC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 ) + +#define SET_PCLKSEL0_PCLK_RTC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 ) + +#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U + +#define GET_PCLKSEL0_PCLK_SSP1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 ) + +#define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 ) + +#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U + +#define GET_PCLKSEL0_PCLK_DAC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 ) + +#define SET_PCLKSEL0_PCLK_DAC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 ) + +#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U + +#define GET_PCLKSEL0_PCLK_ADC( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 ) + +#define SET_PCLKSEL0_PCLK_ADC( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 ) + +#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U + +#define GET_PCLKSEL0_PCLK_CAN1( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 ) + +#define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 ) + +#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U + +#define GET_PCLKSEL0_PCLK_CAN2( reg ) \ + GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 ) + +#define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 ) + +/* PCLKSEL1 */ +#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U + +#define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) + +#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) + +#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU + +#define GET_PCLKSEL1_PCLK_GPIO( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 ) + +#define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 ) + +#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U + +#define GET_PCLKSEL1_PCLK_PCB( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 ) + +#define SET_PCLKSEL1_PCLK_PCB( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 ) + +#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U + +#define GET_PCLKSEL1_PCLK_I2C1( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 ) + +#define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 ) + +#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U + +#define GET_PCLKSEL1_PCLK_SSP0( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 ) + +#define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 ) + +#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U + +#define GET_PCLKSEL1_PCLK_TIMER2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) + +#define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) + +#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U + +#define GET_PCLKSEL1_PCLK_TIMER3( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) + +#define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) + +#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U + +#define GET_PCLKSEL1_PCLK_UART2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 ) + +#define SET_PCLKSEL1_PCLK_UART2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 ) + +#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U + +#define GET_PCLKSEL1_PCLK_UART3( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 ) + +#define SET_PCLKSEL1_PCLK_UART3( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 ) + +#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U + +#define GET_PCLKSEL1_PCLK_I2C2( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 ) + +#define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 ) + +#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U + +#define GET_PCLKSEL1_PCLK_I2S( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 ) + +#define SET_PCLKSEL1_PCLK_I2S( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 ) + +#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U + +#define GET_PCLKSEL1_PCLK_MCI( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 ) + +#define SET_PCLKSEL1_PCLK_MCI( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 ) + +#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U + +#define GET_PCLKSEL1_PCLK_SYSCON( reg ) \ + GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) + +#define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \ + SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) + +/* RTC_ILR */ +#define RTC_ILR_RTCCIF 0x00000001U +#define RTC_ILR_RTCALF 0x00000002U +#define RTC_ILR_RTSSF 0x00000004U + +/* RTC_CCR */ +#define RTC_CCR_CLKEN 0x00000001U +#define RTC_CCR_CTCRST 0x00000002U +#define RTC_CCR_CLKSRC 0x00000010U + +/* GPDMA */ +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc176x_dma_descriptor; + +typedef struct { + lpc176x_dma_descriptor desc; + uint32_t cfg; +} lpc176x_dma_channel; + +#define GPDMA_CH_NUMBER 2 +#define GPDMA_STATUS_CH_0 0x00000001U +#define GPDMA_STATUS_CH_1 0x00000002U +#define GPDMA_CH_BASE_ADDR( i ) \ + ( (volatile lpc176x_dma_channel *) \ + ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) ) + +/* GPDMA_CONFIG */ +#define GPDMA_CONFIG_EN 0x00000001U +#define GPDMA_CONFIG_MODE 0x00000002U + +/* GPDMA_ENABLED_CHNS */ +#define GPDMA_ENABLED_CHNS_CH0 0x00000001U +#define GPDMA_ENABLED_CHNS_CH1 0x00000002U + +/* GPDMA_CH_CTRL */ +#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU + +#define GET_GPDMA_CH_CTRL_TSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 ) + +#define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 ) + +#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU + +#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U + +#define GET_GPDMA_CH_CTRL_SBSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) + +#define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) + +#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U + +#define GET_GPDMA_CH_CTRL_DBSZ( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) + +#define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) + +#define GPDMA_CH_CTRL_BSZ_1 0x00000000U + +#define GPDMA_CH_CTRL_BSZ_4 0x00000001U + +#define GPDMA_CH_CTRL_BSZ_8 0x00000002U + +#define GPDMA_CH_CTRL_BSZ_16 0x00000003U + +#define GPDMA_CH_CTRL_BSZ_32 0x00000004U + +#define GPDMA_CH_CTRL_BSZ_64 0x00000005U + +#define GPDMA_CH_CTRL_BSZ_128 0x00000006U + +#define GPDMA_CH_CTRL_BSZ_256 0x00000007U + +#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U + +#define GET_GPDMA_CH_CTRL_SW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 ) + +#define SET_GPDMA_CH_CTRL_SW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 ) + +#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U + +#define GET_GPDMA_CH_CTRL_DW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 ) + +#define SET_GPDMA_CH_CTRL_DW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 ) + +#define GPDMA_CH_CTRL_W_8 0x00000000U + +#define GPDMA_CH_CTRL_W_16 0x00000001U + +#define GPDMA_CH_CTRL_W_32 0x00000002U + +#define GPDMA_CH_CTRL_SI 0x04000000U + +#define GPDMA_CH_CTRL_DI 0x08000000U + +#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U + +#define GET_GPDMA_CH_CTRL_PROT( reg ) \ + GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 ) + +#define SET_GPDMA_CH_CTRL_PROT( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 ) + +#define GPDMA_CH_CTRL_ITC 0x80000000U + +/* GPDMA_CH_CFG */ +#define GPDMA_CH_CFG_EN 0x00000001U + +#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU + +#define GET_GPDMA_CH_CFG_SRCPER( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 ) + +#define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 ) + +#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U + +#define GET_GPDMA_CH_CFG_DESTPER( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 ) + +#define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 ) + +#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U + +#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U + +#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U + +#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U + +#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U + +#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U + +#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U + +#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U + +#define GET_GPDMA_CH_CFG_FLOW( reg ) \ + GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 ) + +#define SET_GPDMA_CH_CFG_FLOW( reg, val ) \ + SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 ) + +#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U + +#define GPDMA_CH_CFG_IE 0x00004000U + +#define GPDMA_CH_CFG_ITC 0x00008000U + +#define GPDMA_CH_CFG_LOCK 0x00010000U + +#define GPDMA_CH_CFG_ACTIVE 0x00020000U + +#define GPDMA_CH_CFG_HALT 0x00040000U + +/* AHBCFG */ +#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U + +#define AHBCFG_BREAK_BURST_MASK 0x00000006U + +#define GET_AHBCFG_BREAK_BURST( reg ) \ + GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 ) + +#define SET_AHBCFG_BREAK_BURST( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 ) + +#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U + +#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U + +#define GET_AHBCFG_QUANTUM_SIZE( reg ) \ + GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 ) + +#define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 ) + +#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U + +#define GET_AHBCFG_DEFAULT_MASTER( reg ) \ + GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 ) + +#define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 ) + +#define AHBCFG_EP1_MASK 0x00007000U + +#define GET_AHBCFG_EP1( reg ) \ + GET_FIELD( reg, AHBCFG_EP1_MASK, 12 ) + +#define SET_AHBCFG_EP1( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 ) + +#define AHBCFG_EP2_MASK 0x00070000U + +#define GET_AHBCFG_EP2( reg ) \ + GET_FIELD( reg, AHBCFG_EP2_MASK, 16 ) + +#define SET_AHBCFG_EP2( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 ) + +#define AHBCFG_EP3_MASK 0x00700000U + +#define GET_AHBCFG_EP3( reg ) \ + GET_FIELD( reg, AHBCFG_EP3_MASK, 20 ) + +#define SET_AHBCFG_EP3( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 ) + +#define AHBCFG_EP4_MASK 0x07000000U + +#define GET_AHBCFG_EP4( reg ) \ + GET_FIELD( reg, AHBCFG_EP4_MASK, 24 ) + +#define SET_AHBCFG_EP4( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 ) + +#define AHBCFG_EP5_MASK 0x70000000U + +#define GET_AHBCFG_EP5( reg ) \ + GET_FIELD( reg, AHBCFG_EP5_MASK, 28 ) + +#define SET_AHBCFG_EP5( reg, val ) \ + SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 ) + +/* I2S */ +static volatile lpc_i2s * const lpc176x_i2s = (lpc_i2s *) I2S_BASE_ADDR; + +/* ADC */ +#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) +#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) +#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) +#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) +#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) +#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) +#define ADC_CR_BURST BSP_BIT32( 16 ) +#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) +#define ADC_CR_PDN BSP_BIT32( 21 ) +#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) +#define ADC_CR_EDGE BSP_BIT32( 27 ) + +#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 6, 15 ) +#define ADC_DR_OVERRUN BSP_BIT32( 30 ) +#define ADC_DR_DONE BSP_BIT32( 31 ) + +/* DAC */ +#define DAC_STEPS 1024 +#define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 ) +#define DAC_BIAS BSP_BIT32( 16 ) + +#endif /* LIBBSP_ARM_LPC176X_H */ diff --git a/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h b/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h new file mode 100755 index 0000000000..3556bc5fbf --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/mbed-pinmap.h @@ -0,0 +1,50 @@ +/** + * @file mbed-pinmap.h + * + * @ingroup lpc176x + * + * @brief Pins of the mbed lpc1768 + * See http://mbed.org/media/uploads/chris/mbed-005.1.pdf for references + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#define DIP5 9U +#define DIP6 8U +#define DIP7 7U +#define DIP8 6U +#define DIP9 0U +#define DIP10 1U +#define DIP11 18U +#define DIP12 17U +#define DIP13 15U +#define DIP14 16U +#define DIP15 23U +#define DIP16 24U +#define DIP17 25U +#define DIP18 26U +#define DIP19 62U +#define DIP20 63U +#define DIP21 69U +#define DIP22 68U +#define DIP23 67U +#define DIP24 66U +#define DIP25 65U +#define DIP26 64U +#define DIP27 11U +#define DIP28 10U +#define DIP29 5U +#define DIP30 4U +#define LED1 50U +#define LED2 52U +#define LED3 53U +#define LED4 55U diff --git a/bsps/arm/lpc176x/include/bsp/pwmout-defs.h b/bsps/arm/lpc176x/include/bsp/pwmout-defs.h new file mode 100755 index 0000000000..f55b154a05 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/pwmout-defs.h @@ -0,0 +1,105 @@ +/** + * @file pwmout-defs.h + * + * @ingroup lpc176x + * + * @brief PWM-Out controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_PWMOUT_DEFS_H +#define LPC176X_PWMOUT_DEFS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define PWM_DEFAULT_PERIOD 20000u +#define PWM_DEFAULT_PULSEWIDTH 0u + +#define PWM_PRESCALER_USECOND ( LPC176X_CCLK / 1000000 ) +#define PWM_MCR_RESET_ON_MATCH0 ( 1 << 1 ) +#define PWM_PCR_ENABLE_PWM( pwmout ) ( 1 << ( 9 + pwmout ) ) +#define PWM_TCR_RESET ( 1 << 1 ) +#define PWM_TCR_ENABLE ( 1u ) +#define PWM_TCR_PWM ( 1 << 3 ) +#define PWM_LER_LATCH_MATCH_0 1u +#define PWM_LER_LATCH( match ) ( 1 << ( ( match ) + 1 ) ) + +/** + * @brief The low-level PWM output device. + */ +typedef struct { + volatile uint32_t IR; + volatile uint32_t TCR; + volatile uint32_t TC; + volatile uint32_t PR; + volatile uint32_t PC; + volatile uint32_t MCR; + volatile uint32_t MR0; + volatile uint32_t MR1; + volatile uint32_t MR2; + volatile uint32_t MR3; + volatile uint32_t CCR; + volatile uint32_t CR0; + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t CR3; + volatile uint32_t RESERVED0; + volatile uint32_t MR4; + volatile uint32_t MR5; + volatile uint32_t MR6; + volatile uint32_t PCR; + volatile uint32_t LER; + volatile uint32_t RESERVED1[ 7 ]; + volatile uint32_t CTCR; +} lpc176x_pwm_device; + +/** + * @brief Represents one pin and the respective function to be set + * for each PWM output. + */ +typedef struct { + uint32_t pin_number; + lpc176x_pin_function pin_function; +} lpc176x_pwm_pin; + +/** + * @brief The PWM outputs of the board. + */ +typedef enum { + PWMO_1, + PWMO_2, + PWMO_3, + PWMO_4, + PWMO_5, + PWMO_6, + PWM_OUTPUT_NUMBER +} lpc176x_pwm_number; + +/** + * @brief A pin for each PWM output. + */ +typedef enum { + PWM_FIRST_PIN, + PWM_SECOND_PIN, + PWM_NUMBER_OF_PINS +} lpc176x_pwm_pin_number; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/pwmout.h b/bsps/arm/lpc176x/include/bsp/pwmout.h new file mode 100755 index 0000000000..1427fc5f3e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/pwmout.h @@ -0,0 +1,73 @@ +/** + * @file pwmout.h + * + * @ingroup lpc176x + * + * @brief PWM-Out controller for the mbed lpc1768 board. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC176X_PWMOUT_H +#define LPC176X_PWMOUT_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Initializes the PWM output device and sets an initial period + * of 20000us. + * + * @param pin_number The PWM output pin. + * @return RTEMS_SUCCESSFULL if the PWM initialization was OK, + * RTEMS_INVALID_NUMBER for a wrong parameter. + */ +rtems_status_code pwm_init( const lpc176x_pin_number pin_number ); + +/** + * @brief Sets a period for the PWM output. (Note that this changes the period + * for all the PWM outputs.) + * + * @param pin_number The pin whose period we want to change. + * @param period The desired period in microseconds. + * + * @return RTEMS_SUCCESSFULL if the period's setting was OK, + * RTEMS_INVALID_NUMBER for a bad parameter. + */ +rtems_status_code pwm_period( + const lpc176x_pin_number pin_number, + const lpc176x_microseconds period +); + +/** + * @brief Sets a pulsewidth for the PWM output. + * + * @param pin_number The pin whose pulsewidth we want to change. + * @param pwidth The desired pulsewidth in microseconds. + * + * @return RTEMS_SUCCESSFULL if the pulsewidth's setting was OK, + * RTEMS_INVALID_NUMBER for a wrong parameter. + */ +rtems_status_code pwm_pulsewidth( + const lpc176x_pin_number pin_number, + const lpc176x_microseconds pwidth +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/lpc176x/include/bsp/system-clocks.h b/bsps/arm/lpc176x/include/bsp/system-clocks.h new file mode 100644 index 0000000000..26087ff3e9 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/system-clocks.h @@ -0,0 +1,91 @@ +/** + * @file + * + * @ingroup lpc176x_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc176x_clock System Clocks + * + * @ingroup lpc176x + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Initializes the standard timer. + * + * This function uses Timer 1. + */ +void lpc176x_timer_initialize( void ); + +/** + * @brief Returns current standard timer value in CPU clocks. + * + * @return This function uses Timer 1. + */ +static inline unsigned lpc176x_get_timer1( void ) +{ + return LPC176X_T1TC; +} + +/** + * @brief Delay for @a us micro seconds. + * + * This function uses the standard timer and assumes that the CPU + * frequency is in whole MHz numbers. The delay value @a us will be + * converted to CPU ticks and there is no protection against integer + * overflows. + * + * This function uses Timer 1. + */ +void lpc176x_micro_seconds_delay( unsigned us ); + +/** + * @brief Returns the PLL output clock frequency in [Hz]. + * + * @return Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc176x_pllclk( void ); + +/** + * @brief Returns the CPU clock frequency in [Hz]. + * + * @return Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc176x_cclk( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/timer-defs.h b/bsps/arm/lpc176x/include/bsp/timer-defs.h new file mode 100644 index 0000000000..3827aa9279 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/timer-defs.h @@ -0,0 +1,449 @@ +/** + * @file timer-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the for the timer of the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H +#define LIBBSP_ARM_LPC176X_TIMER_DEFS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Timer 0 */ +#define LPC176X_TMR0_BASE_ADDR 0x40004000U + +#define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 1 */ +#define LPC176X_TMR1_BASE_ADDR 0x40008000U + +#define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 2 */ +#define LPC176X_TMR2_BASE_ADDR 0x40090000U + +#define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ + 0x70U ) ) + +/* Timer 3 */ +#define LPC176X_TMR3_BASE_ADDR 0x40094000U + +#define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x00U ) ) +#define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x04U ) ) +#define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x08U ) ) +#define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x0CU ) ) +#define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x10U ) ) +#define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x14U ) ) +#define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x18U ) ) +#define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x1CU ) ) +#define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x20U ) ) +#define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x24U ) ) +#define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x28U ) ) +#define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x2CU ) ) +#define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x30U ) ) +#define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x34U ) ) +#define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x38U ) ) +#define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x3CU ) ) +#define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ + 0x70U ) ) + +/** + * @brief Represents the timer device registers. + */ +typedef struct { + /** + * @brief Interrupt Register. + */ + volatile uint32_t IR; + /** + * @brief Timer Control Register. + */ + volatile uint32_t TCR; + /** + * @brief Timer Counter. + */ + volatile uint32_t TC; + /** + * @brief Prescale Register. + */ + volatile uint32_t PR; + /** + * @brief Prescale Counter. + */ + volatile uint32_t PC; + /** + * @brief Match Control Register. + */ + volatile uint32_t MCR; + /** + * @brief Match Register (0, 1, 2, 3) + */ + volatile uint32_t MR[ 4 ]; + /** + * @brief Capture Control Register. + */ + volatile uint32_t CCR; + /** + * @brief Capture Register (0, 1) + */ + volatile uint32_t CR[ 2 ]; + volatile uint32_t reserved0; + volatile uint32_t reserved1; + /** + * @brief External Match Register. + */ + volatile uint32_t EMR; + volatile uint32_t reserved2[ 12 ]; + /** + * @brief Count Control Register. + */ + volatile uint32_t CTCR; +} lpc176x_timer_device; + +#define LPC176X_PIN_SELECT_TIMER 3U +#define LPC176X_PINSEL_NO_PORT 999U + +#define LPC176X_TIMER_RESET ( 1U << 1U ) +#define LPC176X_TIMER_START 1U +#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U +#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U ) +#define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U } +#define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U } +#define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U } +#define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U } +#define LPC176X_TIMER0_EMATCH_PORTS { 60U, \ + 61U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER1_EMATCH_PORTS { 54U, \ + 57U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U } +#define LPC176X_TIMER3_EMATCH_PORTS { 10U, \ + 11U, \ + LPC176X_PINSEL_NO_PORT, \ + LPC176X_PINSEL_NO_PORT } +#define LPC176X_TIMER_DEFAULT_RESOLUTION 1U +#define LPC176X_TIMER_MCR_MASK 7U +#define LPC176X_TIMER_MCR_MASK_SIZE 3U +#define LPC176X_TIMER_CCR_MASK 7U +#define LPC176X_TIMER_CCR_MASK_SIZE 3U +#define LPC176X_TIMER_EMR_MASK 3U +#define LPC176X_TIMER_EMR_MASK_SIZE 2U +#define LPC176X_TIMER_EMR_MASK_OFFSET 4U +#define LPC176X_TIMER_CLEAR_FUNCTION 0U +#define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U +#define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U ) +#define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i ) +#define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U +#define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U + +#define LPC176X_ISR_NAME_STRING_SIZE 10U + +#define LPC176X_SET_MCR( mcr, match_port, function ) \ + SET_FIELD( mcr, \ + function, \ + ( 0x7U << ( 3U * match_port ) ), \ + ( 3U * match_port ) ) +#define LPC176X_SET_CCR( mcr, capture_port, function ) \ + SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \ + ( 3U * capture_port ) ) +#define LPC176X_SET_EMR( mcr, match_port, function ) \ + SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \ + ( 2U * match_port + 4U ) ) + +/** + * @brief Capture ports of a timer. + * + * Enumerated type to define the set of capture ports for a timer device. + */ +typedef enum { + LPC176X_CAPn_0, + LPC176X_CAPn_1, + LPC176X_CAPTURE_PORTS_COUNT +} lpc176x_capture_port; + +/** + * @brief Match ports of a timer. + * + * Enumerated type to define the set of match ports for a timer device. + */ +typedef enum { + LPC176X_MATn_0, + LPC176X_MATn_1, + LPC176X_MATn_2, + LPC176X_MATn_3, + LPC176X_EMATCH_PORTS_COUNT +} lpc176x_match_port; + +/** + * @brief Timer modes of a timer. + * + * Enumerated type to define the set of modes for a timer device. + */ +typedef enum { + LPC176X_TIMER_MODE_TIMER, + LPC176X_TIMER_MODE_COUNTER_RISING_CAP0, + LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0, + LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0, + LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ), + LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ), + LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ), +} lpc176x_timer_mode; + +/** + * @brief The timer devices in the board. + * + * Enumerated type to define the timer device's numbers. + */ +typedef enum { + LPC176X_TIMER_0, + LPC176X_TIMER_1, + LPC176X_TIMER_2, + LPC176X_TIMER_3, + LPC176X_TIMER_COUNT +} lpc176x_timer_number; + +/** + * @brief The index for the isr_funct_vector representing the functions + * that attends each possible interrupt source for a timer. + * + * Enumerated type to define the set of isr timer functions . + */ +typedef enum { + LPC176X_MAT0_ISR_FUNCTION, + LPC176X_MAT1_ISR_FUNCTION, + LPC176X_MAT2_ISR_FUNCTION, + LPC176X_MAT3_ISR_FUNCTION, + LPC176X_CAP0_ISR_FUNCTION, + LPC176X_CAP1_ISR_FUNCTION, + LPC176X_ISR_FUNCTIONS_COUNT +} lpc176x_isr_function; + +/** + * @brief The possible functions at match. This options could be + * used together. + * + * Enumerated type to define the set of functions at mach for a + * timer device. + */ +typedef enum { + LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U, + LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U, + LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ), + LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U ) +} lpc176x_match_function; + +/** + * @brief The possible functions at capture. This options could + * be used together. + * + * Enumerated type to define the set of functions at capture for + * a timer device. + */ +typedef enum { + LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U, + LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U, + LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ), + LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U ) +} lpc176x_capture_function; + +/** + * @brief The possible functions at match, for the external ports. + * + * Enumerated type to define the set of functions at match, for external + * ports, for a timer device. + */ +typedef enum { + LPC176X_TIMER_EXTMATCH_FUNCTION_NONE, + LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR, + LPC176X_TIMER_EXTMATCH_FUNCTION_SET, + LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE +} lpc176x_ext_match_function; + +/** + * @brief A function that attends an interruption for a timer. + * + * @param tnumber Timer number. + * @return Pointer to the match function. + */ +typedef void (*lpc176x_isr_funct) ( const lpc176x_timer_number tnumber ); + +/** + * @brief The vector of functions that attends each possible interrupt + * source for a timer. + */ +typedef lpc176x_isr_funct const lpc176x_isr_funct_vector[ + LPC176X_ISR_FUNCTIONS_COUNT ]; + +/** + * @brief The Timer device representation. + */ +typedef struct { + /** + * @brief The address of the controlling registers for the timer. + */ + lpc176x_timer_device *const device; + /** + * @brief The module for the RTEMS module starting (power and clock). + */ + const lpc176x_module module; + /** + * @brief The Pins for the Capture ports of this timer. + */ + const lpc176x_pin_number pinselcap[ LPC176X_CAPTURE_PORTS_COUNT ]; + /** + * @brief The Pins for the external match ports of this timer. + */ + const lpc176x_pin_number pinselemat[ LPC176X_EMATCH_PORTS_COUNT ]; +} lpc176x_timer; + +/** + * @brief The Timer functions. + */ +typedef struct { + /** + * @brief The vector of isr functions for this timer. + */ + const lpc176x_isr_funct_vector *funct_vector; +} lpc176x_timer_functions; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_TIMER_DEFS_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/timer.h b/bsps/arm/lpc176x/include/bsp/timer.h new file mode 100644 index 0000000000..6805b55f0e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/timer.h @@ -0,0 +1,195 @@ +/** + * @file timer.h + * + * @ingroup lpc176x + * + * @brief Timer API for the lpc176x bsp. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_TIMER_H +#define LIBBSP_ARM_LPC176X_TIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief resets timer counter and stops it. + * + * @param tnumber the device to be reseted + * @return RTEMS_SUCCESSFUL if the timer was reseted successfuly. + */ +rtems_status_code lpc176x_timer_reset( lpc176x_timer_number tnumber ); + +/** + * @brief Sets mode of the timer (timer, counter rising, counter falling + * or counter both edges) + * + * @param tnumber: the device to be setted + * @param mode: the desired mode + * @return RTEMS_SUCCESSFUL if the timer's mode was setted successfuly. + */ +rtems_status_code lpc176x_timer_set_mode( + lpc176x_timer_number tnumber, + lpc176x_timer_mode mode +); + +/** + * @brief Starts the timer counter + * + * @param tnumber: the device to be started + * @return RTEMS_SUCCESSFUL if the timer's was started successfuly. + */ +rtems_status_code lpc176x_timer_start( lpc176x_timer_number tnumber ); + +/** + * @brief true if timer is started. + * + * @param tnumber: the timer number to check. + * @param is_started: TRUE if the timer is running. + * @return RTEMS_SUCCESSFUL if the started timer check was successfuly. + */ +rtems_status_code lpc176x_timer_is_started( + lpc176x_timer_number tnumber, + bool *is_started +); + +/** + * @brief sets the resolution in microseconds of the timer + * + * @param tnumber: the device to be modified. + * @param resolution: how many microseconds will mean each timer + * counter unit. + * @return RTEMS_SUCCESSFUL if the timer resolution was setted successfuly. + */ +rtems_status_code lpc176x_timer_set_resolution( + lpc176x_timer_number tnumber, + lpc176x_microseconds resolution +); + +/** + * @brief Configures the timer match + * + * @param tnumber: the device to be modified + * @param match_port: which port of this timer will be setted + * @param function: what the timer should do when match: stop timer, clear, + * and/or interrupt + * @param match_value: the value that the timer should match. + * @return RTEMS_SUCCESSFUL if the timer was configured successfuly. + */ +rtems_status_code lpc176x_timer_match_config( + lpc176x_timer_number tnumber, + lpc176x_match_port match_port, + lpc176x_match_function function, + uint32_t match_value +); + +/** + * @brief Configures the capture ports + * + * @param tnumber: the device to be modified + * @param capture_port: which port of this timer will be setted + * @param function: At which edge/s will the capture work, and + * if it will interrupt + */ +rtems_status_code lpc176x_timer_capture_config( + lpc176x_timer_number tnumber, + lpc176x_capture_port capture_port, + lpc176x_capture_function function +); + +/** + * @brief Configures the external match ports + * + * @param tnumber: the device to be modified + * @param match_port: which match for this timer + * @param function: what should do when match: set, clear toggle or nothing + */ +rtems_status_code lpc176x_timer_external_match_config( + lpc176x_timer_number tnumber, + lpc176x_match_port match_port, + lpc176x_ext_match_function function +); + +/** + * @brief Gets the captured value + * + * @param tnumber: the device to be modified + * @param capnumber: which capture port for this timer + * @return the captured value + */ +uint32_t lpc176x_timer_get_capvalue( + lpc176x_timer_number tnumber, + lpc176x_capture_port capnumber +); + +/** + * @brief Gets the timer value + * + * @param tnumber: the device + * @return the timer value + */ +uint32_t lpc176x_timer_get_timer_value( lpc176x_timer_number tnumber ); + +/** + * @brief Sets the timer value + * + * @param tnumber: the timer to modify. + * @param timer_value the value to set. + */ +rtems_status_code lpc176x_timer_set_timer_value( + lpc176x_timer_number tnumber, + uint32_t lpc176x_timer_value +); + +/** + * @brief Timer generic isroutine. + * + * @param timernumber the number of timer. + */ +void lpc176x_timer_isr( void *lpc176x_timer_number ); + +/** + * @brief Initializes timer in timer mode and resets counter but + * without starting it, and without any capture or + * match function. + * + * @param tnumber which timer + * @return RTEMS_SUCCESSFUL when everything ok. + */ +rtems_status_code lpc176x_timer_init( lpc176x_timer_number tnumber ); + +/** + * @brief Initializes timer in timer mode and resets counter but + * without starting it, and without any capture or + * match function. + * + * @param tnumber which timer to init + * @param vector the functions to be used by the isr. + * @return RTEMS_SUCCESSFUL when everything ok. + */ +rtems_status_code lpc176x_timer_init_with_interrupt( + lpc176x_timer_number tnumber, + const lpc176x_isr_funct_vector *vector +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_TIMER_H */ \ No newline at end of file diff --git a/bsps/arm/lpc176x/include/bsp/watchdog-defs.h b/bsps/arm/lpc176x/include/bsp/watchdog-defs.h new file mode 100644 index 0000000000..44ea80527e --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/watchdog-defs.h @@ -0,0 +1,65 @@ +/** + * @file watchdog-defs.h + * + * @ingroup lpc176x + * + * @brief API definitions of the Watchdog driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H +#define LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC176X_WDMOD_BASE 0x40000000U +#define LPC176X_WDFEED_CON 0XAAU +#define LPC176X_WDFEED_CFG 0X55U +#define LPC176X_WD_PRESCALER_DIVISOR 4000000U +#define LPC176X_WWDT_MOD_WDEN BSP_BIT32( 0 ) +#define LPC176X_WWDT_MOD_WDRESET BSP_BIT32( 1 ) +#define LPC176X_WWDT_MOD_WDTOF BSP_BIT32( 2 ) +#define LPC176X_WWDT_MOD_WDINT BSP_BIT32( 3 ) +#define LPC176X_WWDT_CLKSEL_WDSEL_IRC 0x0U +#define LPC176X_WWDT_CLKSEL_WDSEL_PCLK 0x1U +#define LPC176X_WWDT_CLKSEL_WDSEL_RTC 0x2U +#define LPC176X_WD_INTERRUPT_VECTOR_NUMBER 0U +#define LPC176X_WDMOD ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x00U ) ) +#define LPC176X_WDTC ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x04U ) ) +#define LPC176X_WDFEED ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ + 0x08U ) ) +#define LPC176X_WDTV ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x0CU ) ) +#define LPC176X_WDCLKSEL ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ + 0x10U ) ) + +/** + * @brief A function that attends an interruption for a watchdog. + */ +typedef rtems_interrupt_handler lpc176x_wd_isr_funct; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H */ diff --git a/bsps/arm/lpc176x/include/bsp/watchdog.h b/bsps/arm/lpc176x/include/bsp/watchdog.h new file mode 100644 index 0000000000..8b5f033605 --- /dev/null +++ b/bsps/arm/lpc176x/include/bsp/watchdog.h @@ -0,0 +1,70 @@ +/** + * @file watchdog.h + * + * @ingroup lpc176x + * + * @brief API of the Watchdog driver for the lpc176x bsp in RTEMS. + */ + +/* + * Copyright (c) 2014 Taller Technologies. + * + * @author Boretto Martin (martin.boretto@tallertechnologies.com) + * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) + * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) + * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_H +#define LIBBSP_ARM_LPC176X_WATCHDOG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Checks if the watchdog was executed by software or not. Set when + * the watchdog timer times out, cleared by software. + * + * @return TRUE if the watchdog was executed. + * FALSE otherwise. + */ +bool lpc176x_been_reset_by_watchdog( void ); + +/** + * @brief Resets the watchdog timer. + */ +void lpc176x_watchdog_reset( void ); + +/** + * @brief Configures the watchdog's timer. + * + * @param tcount Timer's out value. + * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully. + */ +rtems_status_code lpc176x_watchdog_config( lpc176x_microseconds tcount ); + +/** + * @brief Configures the timer watchdog using interrupt. + * + * @param tcount Timer's out value. + * @param interrupt Interrupt to register. + * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully + * with interrupts. + */ +rtems_status_code lpc176x_watchdog_config_with_interrupt( + lpc176x_wd_isr_funct interrupt, + lpc176x_microseconds tcount +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_H */ diff --git a/bsps/arm/lpc176x/include/tm27.h b/bsps/arm/lpc176x/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lpc176x/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc24xx/headers.am b/bsps/arm/lpc24xx/headers.am new file mode 100644 index 0000000000..e2f4d26042 --- /dev/null +++ b/bsps/arm/lpc24xx/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/dma.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lcd.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc17xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/lpc24xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/ssp.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/start-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc24xx/include/bsp/system-clocks.h diff --git a/bsps/arm/lpc24xx/include/bsp.h b/bsps/arm/lpc24xx/include/bsp.h new file mode 100644 index 0000000000..5424808841 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_BSP_H +#define LIBBSP_ARM_LPC24XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define LPC24XX_PCLK (LPC24XX_CCLK / LPC24XX_PCLKDIV) + +#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV) + +#define LPC24XX_MPU_REGION_COUNT 8 + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (29 << 3) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (30 << 3) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC24XX_CCLK + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +struct rtems_termios_device_context; + +/** + * @defgroup lpc24xx LPC24XX Support + * + * @ingroup bsp_arm + * + * @brief LPC24XX support package. + * + * @{ + */ + +/** + * @brief Network driver attach and detach function. + */ +int lpc_eth_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +/** + * @brief Standard network driver attach and detach function. + */ +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach + +/** + * @brief Standard network driver name. + */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor clock + * to be stopped, while on-chip peripherals remain active. Any enabled + * interrupt from a peripheral or an external interrupt source will cause the + * processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread + * + * #include + * @endcode + */ +void *bsp_idle_thread(uintptr_t ignored); + +#ifdef ARM_MULTILIB_ARCH_V4 + #define BSP_CONSOLE_UART_BASE 0xe000c000 +#else + #define BSP_CONSOLE_UART_BASE 0x4000c000 +#endif + +void bsp_restart(void *addr); + +bool lpc24xx_uart_probe_1(struct rtems_termios_device_context *context); + +bool lpc24xx_uart_probe_2(struct rtems_termios_device_context *context); + +bool lpc24xx_uart_probe_3(struct rtems_termios_device_context *context); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC24XX_BSP_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/dma.h b/bsps/arm/lpc24xx/include/bsp/dma.h new file mode 100644 index 0000000000..b2e6c3e665 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/dma.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup lpc24xx_dma + * + * @brief Direct memory access (DMA) support. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_DMA_H +#define LIBBSP_ARM_LPC24XX_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_dma DMA Support + * + * @ingroup lpc24xx + * + * @brief Direct memory access (DMA) support. + * + * @{ + */ + +/** + * @brief Initializes the general purpose DMA. + */ +void lpc24xx_dma_initialize(void); + +/** + * @brief Tries to obtain the DMA channel @a channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid channel number. + * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. + */ +rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel); + +/** + * @brief Releases the DMA channel @a channel. + * + * You must have obtained this channel with lpc24xx_dma_channel_obtain() + * previously. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc24xx_dma_channel_release(unsigned channel); + +/** + * @brief Disables the DMA channel @a channel. + * + * If @a force is @c false the channel will be halted and disabled when the + * channel is inactive otherwise it will be disabled immediately. + * + * If the channel number @a channel is out of range nothing will happen. + */ +void lpc24xx_dma_channel_disable(unsigned channel, bool force); + +rtems_status_code lpc24xx_dma_copy_initialize(void); + +rtems_status_code lpc24xx_dma_copy_release(void); + +rtems_status_code lpc24xx_dma_copy( + unsigned channel, + void *dest, + const void *src, + size_t n, + size_t width +); + +rtems_status_code lpc24xx_dma_copy_wait(unsigned channel); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_DMA_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/i2c.h b/bsps/arm/lpc24xx/include/bsp/i2c.h new file mode 100644 index 0000000000..42836ddfa8 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/i2c.h @@ -0,0 +1,71 @@ +/** + * @file + * + * @ingroup lpc24xx_libi2c + * + * @brief LibI2C bus driver for the I2C modules. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_I2C_H +#define LIBBSP_ARM_LPC24XX_I2C_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_libi2c LPC24XX Bus Drivers + * + * @ingroup libi2c + * + * @brief LibI2C bus drivers for LPC24XX. + * + * @{ + */ + +typedef struct { + rtems_libi2c_bus_t bus; + volatile lpc24xx_i2c *regs; + size_t index; + const lpc24xx_pin_range *pins; + rtems_vector_number vector; + rtems_id state_update; + uint8_t *volatile data; + uint8_t *volatile end; +} lpc24xx_i2c_bus_entry; + +extern const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_0; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_1; + +extern rtems_libi2c_bus_t *const lpc24xx_i2c_2; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_I2C_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/io.h b/bsps/arm/lpc24xx/include/bsp/io.h new file mode 100644 index 0000000000..9f58ee8efb --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/io.h @@ -0,0 +1,1154 @@ +/** + * @file + * + * @ingroup lpc24xx_io + * + * @brief Input and output module. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_IO_H +#define LIBBSP_ARM_LPC24XX_IO_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_io IO Support and Configuration + * + * @ingroup lpc24xx + * + * @brief Input and output module. + * + * @{ + */ + +#define LPC24XX_IO_PORT_COUNT 5U + +#define LPC24XX_IO_INDEX_MAX (LPC24XX_IO_PORT_COUNT * 32U) + +#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit)) + +#define LPC24XX_IO_PORT(index) ((index) >> 5U) + +#define LPC24XX_IO_PORT_BIT(index) ((index) & 0x1fU) + +typedef enum { + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_ACF, + #endif + LPC24XX_MODULE_ADC, + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_BAT_RAM, + #endif + LPC24XX_MODULE_CAN_0, + LPC24XX_MODULE_CAN_1, + LPC24XX_MODULE_DAC, + LPC24XX_MODULE_EMC, + LPC24XX_MODULE_ETHERNET, + LPC24XX_MODULE_GPDMA, + LPC24XX_MODULE_GPIO, + LPC24XX_MODULE_I2C_0, + LPC24XX_MODULE_I2C_1, + LPC24XX_MODULE_I2C_2, + LPC24XX_MODULE_I2S, + LPC24XX_MODULE_LCD, + LPC24XX_MODULE_MCI, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_MCPWM, + #endif + LPC24XX_MODULE_PCB, + LPC24XX_MODULE_PWM_0, + LPC24XX_MODULE_PWM_1, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_QEI, + #endif + LPC24XX_MODULE_RTC, + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_SPI, + #endif + LPC24XX_MODULE_SSP_0, + LPC24XX_MODULE_SSP_1, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_SSP_2, + #endif + LPC24XX_MODULE_SYSCON, + LPC24XX_MODULE_TIMER_0, + LPC24XX_MODULE_TIMER_1, + LPC24XX_MODULE_TIMER_2, + LPC24XX_MODULE_TIMER_3, + LPC24XX_MODULE_UART_0, + LPC24XX_MODULE_UART_1, + LPC24XX_MODULE_UART_2, + LPC24XX_MODULE_UART_3, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC24XX_MODULE_UART_4, + #endif + #ifdef ARM_MULTILIB_ARCH_V4 + LPC24XX_MODULE_WDT, + #endif + LPC24XX_MODULE_USB +} lpc24xx_module; + +#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_USB + 1) + +typedef enum { + LPC24XX_MODULE_PCLK_DEFAULT = 0x4U, + LPC24XX_MODULE_CCLK = 0x1U, + LPC24XX_MODULE_CCLK_2 = 0x2U, + LPC24XX_MODULE_CCLK_4 = 0x0U, + LPC24XX_MODULE_CCLK_6 = 0x3U, + LPC24XX_MODULE_CCLK_8 = 0x3U +} lpc24xx_module_clock; + +#define LPC24XX_MODULE_CLOCK_MASK 0x3U + +typedef enum { + LPC24XX_GPIO_DEFAULT = 0x0U, + LPC24XX_GPIO_RESISTOR_PULL_UP = 0x0U, + LPC24XX_GPIO_RESISTOR_NONE = 0x1U, + LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U, + LPC24XX_GPIO_INPUT = 0x0U, + #ifdef ARM_MULTILIB_ARCH_V7M + LPC17XX_GPIO_REPEATER = 0x3U, + LPC17XX_GPIO_HYSTERESIS = IOCON_HYS, + LPC17XX_GPIO_INPUT_INVERT = IOCON_INV, + LPC17XX_GPIO_FAST_MODE = IOCON_SLEW, + LPC17XX_GPIO_OPEN_DRAIN = IOCON_OD, + LPC17XX_GPIO_INPUT_FILTER = IOCON_FILTER, + #endif + LPC24XX_GPIO_OUTPUT = 0x8000U +} lpc24xx_gpio_settings; + +rtems_status_code lpc24xx_module_enable( + lpc24xx_module module, + lpc24xx_module_clock clock +); + +rtems_status_code lpc24xx_module_disable( + lpc24xx_module module +); + +bool lpc24xx_module_is_enabled(lpc24xx_module module); + +rtems_status_code lpc24xx_gpio_config( + unsigned index, + lpc24xx_gpio_settings settings +); + +static inline void lpc24xx_gpio_set(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + LPC24XX_FIO [port].set = 1U << bit; + } +} + +static inline void lpc24xx_gpio_clear(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + LPC24XX_FIO [port].clr = 1U << bit; + } +} + +static inline void lpc24xx_gpio_write(unsigned index, bool value) +{ + if (value) { + lpc24xx_gpio_set(index); + } else { + lpc24xx_gpio_clear(index); + } +} + +static inline bool lpc24xx_gpio_get(unsigned index) +{ + if (index <= LPC24XX_IO_INDEX_MAX) { + unsigned port = LPC24XX_IO_PORT(index); + unsigned bit = LPC24XX_IO_PORT_BIT(index); + + return (LPC24XX_FIO [port].pin & (1U << bit)) != 0; + } else { + return false; + } +} + +typedef enum { + /** + * @brief Sets the pin function. + */ + LPC24XX_PIN_SET_FUNCTION, + + /** + * @brief Checks if all pins are configured with the specified function. + */ + LPC24XX_PIN_CHECK_FUNCTION, + + /** + * @brief Configures the pins as input. + */ + LPC24XX_PIN_SET_INPUT, + + /** + * @brief Checks if all pins are configured as input. + */ + LPC24XX_PIN_CHECK_INPUT +} lpc24xx_pin_action; + +typedef union { + struct { + uint16_t port : 3; + uint16_t port_bit : 5; + uint16_t function : 3; + uint16_t type : 4; + uint16_t range : 1; + } fields; + uint16_t value; +} lpc24xx_pin_range; + +typedef enum { + LPC24XX_PIN_FUNCTION_00, + LPC24XX_PIN_FUNCTION_01, + LPC24XX_PIN_FUNCTION_10, + LPC24XX_PIN_FUNCTION_11 +} lpc24xx_pin_function; + +typedef enum { + LPC17XX_PIN_TYPE_DEFAULT, + LPC17XX_PIN_TYPE_ADC, + LPC17XX_PIN_TYPE_DAC, + LPC17XX_PIN_TYPE_I2C, + LPC17XX_PIN_TYPE_I2C_FAST_PLUS, + LPC17XX_PIN_TYPE_OPEN_DRAIN +} lpc17xx_pin_type; + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f0, 0, 0 } } + #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f0, t, 0 } } + #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ + { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } } +#else + #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f1, 0, 0 } } + #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f1, t, 0 } } + #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ + { { p, i, f1, 0, 0 } }, { { p, j, f1, 0, 1 } } +#endif + +#define LPC24XX_PIN_TERMINAL { { 0x7, 0x1f, 0x7, 0xf, 0x1 } } + +/** + * @brief Performs the @a action with the @a pins + * + * @code + * #include + * #include + * + * void example(void) + * { + * static const lpc24xx_pin_range pins [] = { + * LPC24XX_PIN_I2S_RX_CLK_P0_4, + * LPC24XX_PIN_I2S_RX_WS_P0_5, + * LPC24XX_PIN_I2S_RX_SDA_P0_6, + * LPC24XX_PIN_I2S_TX_CLK_P0_7, + * LPC24XX_PIN_I2S_TX_WS_P0_8, + * LPC24XX_PIN_I2S_TX_SDA_P0_9, + * LPC24XX_PIN_TERMINAL + * }; + * rtems_status_code sc = RTEMS_SUCCESSFUL; + * + * sc = lpc24xx_module_enable(LPC24XX_MODULE_I2S, LPC24XX_MODULE_CCLK_8); + * assert(sc == RTEMS_SUCCESSFUL); + * sc = lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + * assert(sc == RTEMS_SUCCESSFUL); + * } + * @endcode + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Check failed. + * @retval RTEMS_NOT_DEFINED Invalid action. + */ +rtems_status_code lpc24xx_pin_config( + const lpc24xx_pin_range *pins, + lpc24xx_pin_action action +); + +/** + * @brief Returns the first pin index of a pin range. + */ +static inline unsigned lpc24xx_pin_get_first_index( + const lpc24xx_pin_range *range +) +{ + return LPC24XX_IO_INDEX_BY_PORT(range->fields.port, range->fields.port_bit); +} + +/** + * @name ADC Pins + * + * @{ + */ + +#define LPC24XX_PIN_ADC_CHANNEL_0 \ + LPC24XX_PIN_WITH_TYPE(0, 23, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_1 \ + LPC24XX_PIN_WITH_TYPE(0, 24, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_2 \ + LPC24XX_PIN_WITH_TYPE(0, 25, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_3 \ + LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_4 \ + LPC24XX_PIN_WITH_TYPE(1, 30, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_5 \ + LPC24XX_PIN_WITH_TYPE(1, 31, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_6 \ + LPC24XX_PIN_WITH_TYPE(0, 12, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) +#define LPC24XX_PIN_ADC_CHANNEL_7 \ + LPC24XX_PIN_WITH_TYPE(0, 13, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) + +/** @} */ + +/** + * @name CAN 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_CAN_0_RD_P0_0 \ + LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_0_RD_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_11, 4) + +#define LPC24XX_PIN_CAN_0_TD_P0_1 \ + LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_0_TD_P0_22 \ + LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_11, 4) + +/** @} */ + +/** + * @name CAN 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_CAN_1_RD_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_CAN_1_RD_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_CAN_1_TD_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_CAN_1_TD_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name DAC Pins + * + * @{ + */ + +#define LPC24XX_PIN_DAC \ + LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_DAC) + +/** @} */ + +/** + * @name Ethernet Pins + * + * @{ + */ + +#define LPC24XX_PIN_ETHERNET_MII \ + LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_ETHERNET_RMII_0 \ + LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_1 \ + LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_2 \ + LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_ETHERNET_RMII_3 \ + LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name External Interrupt Pins + * + * @{ + */ + +#define LPC24XX_PIN_EINT_0 \ + LPC24XX_PIN(2, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_1 \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_2 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EINT_3 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name External Memory Controller (EMC) Pins + * + * @{ + */ + +#define LPC24XX_PIN_EMC_CS_0 \ + LPC24XX_PIN(4, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_1 \ + LPC24XX_PIN(4, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_2 \ + LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CS_3 \ + LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_DYCS_0 \ + LPC24XX_PIN(2, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_1 \ + LPC24XX_PIN(2, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_2 \ + LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DYCS_3 \ + LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_OE \ + LPC24XX_PIN(4, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_WE \ + LPC24XX_PIN(4, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CAS \ + LPC24XX_PIN(2, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_RAS \ + LPC24XX_PIN(2, 17, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_CLK_0 \ + LPC24XX_PIN(2, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CLK_1 \ + LPC24XX_PIN(2, 19, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_CKE_0 \ + LPC24XX_PIN(2, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_1 \ + LPC24XX_PIN(2, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_2 \ + LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_CKE_3 \ + LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_DQM_0 \ + LPC24XX_PIN(2, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_1 \ + LPC24XX_PIN(2, 29, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_2 \ + LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_DQM_3 \ + LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_BLS0 \ + LPC24XX_PIN(4, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS1 \ + LPC24XX_PIN(4, 27, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS2 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_BLS3 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_D_0_15 \ + LPC24XX_PIN_RANGE(3, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_D_15_31 \ + LPC24XX_PIN_RANGE(3, 15, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_D_0_31 \ + LPC24XX_PIN_RANGE(3, 0, 31, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_EMC_A_0_12 \ + LPC24XX_PIN_RANGE(4, 0, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_13 \ + LPC24XX_PIN_RANGE(4, 0, 13, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_14 \ + LPC24XX_PIN_RANGE(4, 0, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_15 \ + LPC24XX_PIN_RANGE(4, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_16 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN(4, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_17 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 17, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_18 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_19 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 19, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_20 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_21 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_22 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_23 \ + LPC24XX_PIN_EMC_A_0_15, \ + LPC24XX_PIN_RANGE(4, 16, 23, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_24 \ + LPC24XX_PIN_EMC_A_0_23, \ + LPC24XX_PIN(5, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_EMC_A_0_25 \ + LPC24XX_PIN_EMC_A_0_23, \ + LPC24XX_PIN_RANGE(5, 24, 25, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name I2C 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_0_SDA \ + LPC24XX_PIN_WITH_TYPE(0, 27, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_0_SCL \ + LPC24XX_PIN_WITH_TYPE(0, 28, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2C 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_1_SDA_P0_0 \ + LPC24XX_PIN_WITH_TYPE(0, 0, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SDA_P0_19 \ + LPC24XX_PIN_WITH_TYPE(0, 19, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SDA_P2_14 \ + LPC24XX_PIN_WITH_TYPE(2, 14, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) + +#define LPC24XX_PIN_I2C_1_SCL_P0_1 \ + LPC24XX_PIN_WITH_TYPE(0, 1, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SCL_P0_20 \ + LPC24XX_PIN_WITH_TYPE(0, 20, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_1_SCL_P2_15 \ + LPC24XX_PIN_WITH_TYPE(2, 15, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2C 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2C_2_SDA_P0_10 \ + LPC24XX_PIN_WITH_TYPE(0, 10, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SDA_P2_30 \ + LPC24XX_PIN_WITH_TYPE(2, 30, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SDA_P4_20 \ + LPC24XX_PIN_WITH_TYPE(4, 20, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) + +#define LPC24XX_PIN_I2C_2_SCL_P0_11 \ + LPC24XX_PIN_WITH_TYPE(0, 11, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SCL_P2_31 \ + LPC24XX_PIN_WITH_TYPE(2, 31, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) +#define LPC24XX_PIN_I2C_2_SCL_P4_21 \ + LPC24XX_PIN_WITH_TYPE(4, 21, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) + +/** @} */ + +/** + * @name I2S Pins + * + * @{ + */ + +#define LPC24XX_PIN_I2S_RX_CLK_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_CLK_P0_23 \ + LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_RX_WS_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_WS_P0_24 \ + LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_RX_SDA_P0_6 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_RX_SDA_P0_25 \ + LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_I2S_TX_CLK_P0_7 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_CLK_P2_11 \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_I2S_TX_WS_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_WS_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_I2S_TX_SDA_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_I2S_TX_SDA_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +/** + * @name LCD Pins + * + * @{ + */ + +#define LPC24XX_PIN_LCD_PWR \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_LE \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_DCLK \ + LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_FP \ + LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_ENAB_M \ + LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_LP \ + LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_CLKIN \ + LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 7) + +#define LPC24XX_PIN_LCD_VD_0_P0_4 \ + LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_0_P2_6 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_1_P0_5 \ + LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_1_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_2_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_2_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 7) +#define LPC24XX_PIN_LCD_VD_3_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 6) +#define LPC24XX_PIN_LCD_VD_3_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 5) +#define LPC24XX_PIN_LCD_VD_3_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 7) +#define LPC24XX_PIN_LCD_VD_4_P2_6 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_4_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 4) +#define LPC24XX_PIN_LCD_VD_5_P2_7 \ + LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_5_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 5) +#define LPC24XX_PIN_LCD_VD_6_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_6_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_6_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 5) +#define LPC24XX_PIN_LCD_VD_7_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_7_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 7) +#define LPC24XX_PIN_LCD_VD_7_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 5) +#define LPC24XX_PIN_LCD_VD_8_P0_6 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_8_P1_22 \ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_8_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_9_P0_7 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_9_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_9_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_10_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_10_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_10_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 6) +#define LPC24XX_PIN_LCD_VD_11_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_11_P1_25 \ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_11_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 6) +#define LPC24XX_PIN_LCD_VD_12_P1_22 \ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_12_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_13_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_13_P1_27 \ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_14_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_14_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_15_P1_25 \ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_15_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 6) +#define LPC24XX_PIN_LCD_VD_16_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_17_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_18_P2_12 \ + LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_19_P2_13 \ + LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_20_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_21_P1_27 \ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_22_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 7) +#define LPC24XX_PIN_LCD_VD_23_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 7) + +/** @} */ + +/** + * @name PWM 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_PWM_0_CHANNEL_1_P1_2 \ + LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_1_P3_16 \ + LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_2_P1_3 \ + LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_2_P3_17 \ + LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_3_P1_5 \ + LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_3_P3_18 \ + LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_4_P1_6 \ + LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_4_P3_19 \ + LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_5_P1_7 \ + LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_5_P3_20 \ + LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CHANNEL_6_P1_11 \ + LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CHANNEL_6_P3_21 \ + LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_PWM_0_CAPTURE_0_P1_12 \ + LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_PWM_0_CAPTURE_0_P3_22 \ + LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +/** + * @name PWM 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P1_18 \ + LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P2_0 \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_1_P3_24 \ + LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P2_1 \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_2_P3_25 \ + LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P2_2 \ + LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_3_P3_26 \ + LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P2_3 \ + LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_4_P3_27 \ + LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P2_4 \ + LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_5_P3_28 \ + LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P1_26 \ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P2_5 \ + LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CHANNEL_6_P3_29 \ + LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11, 2) + +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P1_28 \ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P2_7 \ + LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_PWM_1_CAPTURE_0_P3_23 \ + LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_PWM_1_CAPTURE_1_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V4 + +/** + * @name SPI Pins + * + * @{ + */ + +#define LPC24XX_PIN_SPI_SCK \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_SSEL \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_MISO \ + LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11) +#define LPC24XX_PIN_SPI_MOSI \ + LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11) + +/** @} */ + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/** + * @name SSP 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_0_SCK_P0_15 \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_SCK_P1_20 \ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_SCK_P2_22 \ + LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_SSEL_P0_16 \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_SSEL_P1_21 \ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_SSP_0_SSEL_P2_23 \ + LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_MISO_P0_17 \ + LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_MISO_P1_23 \ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_MISO_P2_26 \ + LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_SSP_0_MOSI_P0_18 \ + LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_0_MOSI_P1_24 \ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11, 5) +#define LPC24XX_PIN_SSP_0_MOSI_P2_27 \ + LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11, 2) + +/** @} */ + +/** + * @name SSP 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_1_SCK_P0_6 \ + LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SCK_P0_12 \ + LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SCK_P4_20 \ + LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_SSEL_P0_7 \ + LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_SSEL_P0_13 \ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11, 2) +#define LPC24XX_PIN_SSP_1_SSEL_P4_21 \ + LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_MISO_P0_8 \ + LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MISO_P0_14 \ + LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MISO_P4_22 \ + LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_SSP_1_MOSI_P0_9 \ + LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MOSI_P1_31 \ + LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_SSP_1_MOSI_P4_23 \ + LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V7M + +/** + * @name SSP 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_SSP_2_SCK_P1_0 \ + LPC24XX_PIN(1, 0, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_SSEL_P1_8 \ + LPC24XX_PIN(1, 8, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_MISO_P1_4 \ + LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_SSP_2_MOSI_P1_1 \ + LPC24XX_PIN(1, 1, LPC24XX_PIN_FUNCTION_00, 4) + +/** @} */ + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/** + * @name UART 0 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_0_TXD \ + LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01, 1) + +#define LPC24XX_PIN_UART_0_RXD \ + LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name UART 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_1_TXD_P0_15 \ + LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_1_TXD_P2_0 \ + LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_1_TXD_P3_16 \ + LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11, 3) + +#define LPC24XX_PIN_UART_1_RXD_P0_16 \ + LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_1_RXD_P2_1 \ + LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_1_RXD_P3_17 \ + LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11, 3) + +/** @} */ + +/** + * @name UART 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_2_TXD_P0_10 \ + LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_2_TXD_P2_8 \ + LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_2_TXD_P4_22 \ + LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10, 2) + +#define LPC24XX_PIN_UART_2_RXD_P0_11 \ + LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_UART_2_RXD_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_2_RXD_P4_23 \ + LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10, 2) + +/** @} */ + +/** + * @name UART 3 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_3_TXD_P0_0 \ + LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_3_TXD_P0_25 \ + LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_UART_3_TXD_P4_28 \ + LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11, 2) + +#define LPC24XX_PIN_UART_3_RXD_P0_1 \ + LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_UART_3_RXD_P0_26 \ + LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11, 3) +#define LPC24XX_PIN_UART_3_RXD_P4_29 \ + LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2) + +/** @} */ + +#ifdef ARM_MULTILIB_ARCH_V7M + +/** + * @name UART 4 Pins + * + * @{ + */ + +#define LPC24XX_PIN_UART_4_TXD_P0_22 \ + LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_00, 3) +#define LPC24XX_PIN_UART_4_TXD_P1_29 \ + LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_00, 5) +#define LPC24XX_PIN_UART_4_TXD_P5_4 \ + LPC24XX_PIN(5, 4, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_UART_4_RXD_P2_9 \ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_00, 3) +#define LPC24XX_PIN_UART_4_RXD_P5_3 \ + LPC24XX_PIN(5, 3, LPC24XX_PIN_FUNCTION_00, 4) + +#define LPC24XX_PIN_UART_4_OE_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 3) + +#define LPC24XX_PIN_UART_4_SCLK_P0_21 \ + LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 5) + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/** @} */ + +/** + * @name USB Port 1 Pins + * + * @{ + */ + +#define LPC24XX_PIN_USB_D_PLUS_1\ + LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_D_MINUS_1\ + LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_UP_LED_1\ + LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_TX_E_1\ + LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PPWR_1\ + LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_TX_DP_1\ + LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_TX_DM_1\ + LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_RCV_1\ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PWRD_1\ + LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_RX_DP_1\ + LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_RX_DM_1\ + LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_LS_1\ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_HSTEN_1\ + LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_SSPND_1\ + LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_INT_1\ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_OVRCR_1\ + LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10, 2) +#define LPC24XX_PIN_USB_SCL_1\ + LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_SDA_1 \ + LPC24XX_PIN_WITH_TYPE( \ + 1, 29, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_OPEN_DRAIN \ + ) +#define LPC24XX_PIN_USB_CONNECT_1\ + LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** + * @name USB Port 2 Pins + * + * @{ + */ + +#define LPC24XX_PIN_USB_PPWR_2\ + LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_UP_LED_2\ + LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_HSTEN_2\ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_CONNECT_2\ + LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 3) +#define LPC24XX_PIN_USB_D_PLUS_2\ + LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_PWRD_2\ + LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01, 1) +#define LPC24XX_PIN_USB_OVRCR_2\ + LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01, 1) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_IO_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/irq.h b/bsps/arm/lpc24xx/include/bsp/irq.h new file mode 100644 index 0000000000..0f0e473a0c --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/irq.h @@ -0,0 +1,140 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief LPC24XX interrupt definitions. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_IRQ_H +#define LIBBSP_ARM_LPC24XX_IRQ_H + +#ifndef ASM + #include + #include + #include +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_IRQ_WDT 0 + #define LPC24XX_IRQ_SOFTWARE 1 + #define LPC24XX_IRQ_ARM_CORE_0 2 + #define LPC24XX_IRQ_ARM_CORE_1 3 + #define LPC24XX_IRQ_TIMER_0 4 + #define LPC24XX_IRQ_TIMER_1 5 + #define LPC24XX_IRQ_UART_0 6 + #define LPC24XX_IRQ_UART_1 7 + #define LPC24XX_IRQ_PWM 8 + #define LPC24XX_IRQ_I2C_0 9 + #define LPC24XX_IRQ_SPI_SSP_0 10 + #define LPC24XX_IRQ_SSP_1 11 + #define LPC24XX_IRQ_PLL 12 + #define LPC24XX_IRQ_RTC 13 + #define LPC24XX_IRQ_EINT_0 14 + #define LPC24XX_IRQ_EINT_1 15 + #define LPC24XX_IRQ_EINT_2 16 + #define LPC24XX_IRQ_EINT_3 17 + #define LPC24XX_IRQ_ADC_0 18 + #define LPC24XX_IRQ_I2C_1 19 + #define LPC24XX_IRQ_BOD 20 + #define LPC24XX_IRQ_ETHERNET 21 + #define LPC24XX_IRQ_USB 22 + #define LPC24XX_IRQ_CAN 23 + #define LPC24XX_IRQ_SD_MMC 24 + #define LPC24XX_IRQ_DMA 25 + #define LPC24XX_IRQ_TIMER_2 26 + #define LPC24XX_IRQ_TIMER_3 27 + #define LPC24XX_IRQ_UART_2 28 + #define LPC24XX_IRQ_UART_3 29 + #define LPC24XX_IRQ_I2C_2 30 + #define LPC24XX_IRQ_I2S 31 + + #define BSP_INTERRUPT_VECTOR_MAX 31 +#else + #define LPC24XX_IRQ_WDT 0 + #define LPC24XX_IRQ_TIMER_0 1 + #define LPC24XX_IRQ_TIMER_1 2 + #define LPC24XX_IRQ_TIMER_2 3 + #define LPC24XX_IRQ_TIMER_3 4 + #define LPC24XX_IRQ_UART_0 5 + #define LPC24XX_IRQ_UART_1 6 + #define LPC24XX_IRQ_UART_2 7 + #define LPC24XX_IRQ_UART_3 8 + #define LPC24XX_IRQ_PWM_1 9 + #define LPC24XX_IRQ_I2C_0 10 + #define LPC24XX_IRQ_I2C_1 11 + #define LPC24XX_IRQ_I2C_2 12 + #define LPC24XX_IRQ_SPI_SSP_0 14 + #define LPC24XX_IRQ_SSP_1 15 + #define LPC24XX_IRQ_PLL 16 + #define LPC24XX_IRQ_RTC 17 + #define LPC24XX_IRQ_EINT_0 18 + #define LPC24XX_IRQ_EINT_1 19 + #define LPC24XX_IRQ_EINT_2 20 + #define LPC24XX_IRQ_EINT_3 21 + #define LPC24XX_IRQ_ADC_0 22 + #define LPC24XX_IRQ_BOD 23 + #define LPC24XX_IRQ_USB 24 + #define LPC24XX_IRQ_CAN 25 + #define LPC24XX_IRQ_DMA 26 + #define LPC24XX_IRQ_I2S 27 + #define LPC24XX_IRQ_ETHERNET 28 + #define LPC24XX_IRQ_SD_MMC 29 + #define LPC24XX_IRQ_MCPWM 30 + #define LPC24XX_IRQ_QEI 31 + #define LPC24XX_IRQ_PLL_ALT 32 + #define LPC24XX_IRQ_USB_ACTIVITY 33 + #define LPC24XX_IRQ_CAN_ACTIVITY 34 + #define LPC24XX_IRQ_UART_4 35 + #define LPC24XX_IRQ_SSP_2 36 + #define LPC24XX_IRQ_LCD 37 + #define LPC24XX_IRQ_GPIO 38 + #define LPC24XX_IRQ_PWM 39 + #define LPC24XX_IRQ_EEPROM 40 + + #define BSP_INTERRUPT_VECTOR_MAX 40 +#endif + +#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0 +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15 +#else + #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 31 +#endif +#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1) +#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN +#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority); + +unsigned lpc24xx_irq_get_priority(rtems_vector_number vector); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_LPC24XX_IRQ_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lcd.h b/bsps/arm/lpc24xx/include/bsp/lcd.h new file mode 100644 index 0000000000..c415074bd4 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lcd.h @@ -0,0 +1,91 @@ +/** + * @file + * + * @ingroup lpc24xx_lcd + * + * @brief LCD support. + */ + +/* + * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LCD_H +#define LIBBSP_ARM_LPC24XX_LCD_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_dma LCD Support + * + * @ingroup lpc24xx + * + * @brief LCD support. + * + * @{ + */ + +typedef enum { + #ifdef ARM_MULTILIB_ARCH_V4 + LCD_MODE_STN_4_BIT = 0, + LCD_MODE_STN_8_BIT, + LCD_MODE_STN_DUAL_PANEL_4_BIT, + LCD_MODE_STN_DUAL_PANEL_8_BIT, + LCD_MODE_TFT_12_BIT_4_4_4, + LCD_MODE_TFT_16_BIT_5_6_5, + LCD_MODE_TFT_16_BIT_1_5_5_5, + LCD_MODE_TFT_24_BIT, + LCD_MODE_DISABLED + #else + LCD_MODE_STN_4_BIT = 0x4, + LCD_MODE_STN_8_BIT = 0x6, + LCD_MODE_STN_DUAL_PANEL_4_BIT = 0x84, + LCD_MODE_STN_DUAL_PANEL_8_BIT = 0x86, + LCD_MODE_TFT_12_BIT_4_4_4 = 0x2e, + LCD_MODE_TFT_16_BIT_5_6_5 = 0x2c, + LCD_MODE_TFT_16_BIT_1_5_5_5 = 0x28, + LCD_MODE_TFT_24_BIT = 0x2a, + LCD_MODE_DISABLED = 0xff + #endif +} lpc24xx_lcd_mode; + +/** + * @brief Set the LCD @a mode. + * + * The pins are configured according to @a pins. + * + * @see lpc24xx_pin_config(). + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Invalid mode. + */ +rtems_status_code lpc24xx_lcd_set_mode( + lpc24xx_lcd_mode mode, + const lpc24xx_pin_range *pins +); + +lpc24xx_lcd_mode lpc24xx_lcd_current_mode(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LCD_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h b/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..5e6b469e0f --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc-clock-config.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_CLOCK_INTERRUPT LPC24XX_IRQ_TIMER_0 + +#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR + +#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR + +#define LPC_CLOCK_REFERENCE LPC24XX_PCLK + +#define LPC_CLOCK_MODULE_ENABLE() \ + lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_PCLK_DEFAULT) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h b/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h new file mode 100644 index 0000000000..d24f132567 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc-ethernet-config.h @@ -0,0 +1,130 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief Ethernet driver configuration. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H +#define LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_ETH_CONFIG_INTERRUPT LPC24XX_IRQ_ETHERNET + +#define LPC_ETH_CONFIG_REG_BASE MAC_BASE_ADDR + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX 54 + + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 10 + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX 10 + + #define LPC_ETH_CONFIG_UNIT_MULTIPLE 1U + + #define LPC24XX_ETH_RAM_BEGIN 0x7fe00000U + #define LPC24XX_ETH_RAM_SIZE (16U * 1024U) +#else + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 + #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX + + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 + #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX + + #define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U + + #define LPC_ETH_CONFIG_USE_TRANSMIT_DMA + + #define LPC24XX_ETH_RAM_BEGIN 0x20000000U + #define LPC24XX_ETH_RAM_SIZE (32U * 1024U) +#endif + +#ifdef LPC24XX_ETHERNET_RMII + #define LPC_ETH_CONFIG_RMII + + static void lpc_eth_config_module_enable(void) + { + static const lpc24xx_pin_range pins [] = { + #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN + LPC24XX_PIN_ETHERNET_POWER_DOWN, + #endif + LPC24XX_PIN_ETHERNET_RMII_0, + LPC24XX_PIN_ETHERNET_RMII_1, + LPC24XX_PIN_ETHERNET_RMII_2, + LPC24XX_PIN_ETHERNET_RMII_3, + LPC24XX_PIN_TERMINAL + }; + + lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); + lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + + #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN + { + unsigned pin = lpc24xx_pin_get_first_index(&pins[0]); + + lpc24xx_gpio_config(pin, LPC24XX_GPIO_OUTPUT); + lpc24xx_gpio_set(pin); + } + #endif + } +#else + static void lpc_eth_config_module_enable(void) + { + static const lpc24xx_pin_range pins [] = { + LPC24XX_PIN_ETHERNET_MII, + LPC24XX_PIN_TERMINAL + }; + + lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); + lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); + } +#endif + +static void lpc_eth_config_module_disable(void) +{ + lpc24xx_module_disable(LPC24XX_MODULE_ETHERNET); +} + +static char *lpc_eth_config_alloc_table_area(size_t size) +{ + if (size < LPC24XX_ETH_RAM_SIZE) { + return (char *) LPC24XX_ETH_RAM_BEGIN; + } else { + return NULL; + } +} + +static void lpc_eth_config_free_table_area(char *table_area) +{ + /* Do nothing */ +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc17xx.h b/bsps/arm/lpc24xx/include/bsp/lpc17xx.h new file mode 100644 index 0000000000..9c35102e98 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc17xx.h @@ -0,0 +1,207 @@ +/** + * @file + * + * @ingroup lpc24xx_regs + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LPC17XX_REGS_H +#define LPC17XX_REGS_H + +#include + +#define LPC17XX_BASE 0x00 + +typedef struct { +#define LPC17XX_WWDT_MOD_WDEN BSP_BIT32(0) +#define LPC17XX_WWDT_MOD_WDRESET BSP_BIT32(1) +#define LPC17XX_WWDT_MOD_WDTOF BSP_BIT32(2) +#define LPC17XX_WWDT_MOD_WDINT BSP_BIT32(3) +#define LPC17XX_WWDT_MOD_WDPROTECT BSP_BIT32(4) + uint32_t mod; + uint32_t tc; + uint32_t feed; + uint32_t tv; + uint32_t reserved_10; + uint32_t warnint; + uint32_t window; + uint32_t reserved_1c; +} lpc17xx_wwdt; + +#define LPC17XX_WWDT (*(volatile lpc17xx_wwdt *) (LPC17XX_BASE + 0x40000000)) + +typedef struct { +#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0) +#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6) +#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8) +#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10) + uint32_t con; + uint32_t cfg; + uint32_t stat; + uint32_t feed; +} lpc17xx_pll; + +typedef struct { + uint32_t flashcfg; +#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15) +#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved_04 [15]; + uint32_t memmap; +#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0) + uint32_t reserved_44 [15]; + lpc17xx_pll pll_0; + uint32_t reserved_90 [4]; + lpc17xx_pll pll_1; + uint32_t reserved_b0 [4]; + uint32_t pcon; +#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0) +#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1) +#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2) +#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3) +#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4) +#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8) +#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9) +#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10) +#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11) + uint32_t pconp; +#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0) +#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1) +#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2) +#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3) +#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4) +#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5) +#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6) +#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7) +#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8) +#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9) +#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10) +#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11) +#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12) +#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13) +#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14) +#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15) +#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17) +#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18) +#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19) +#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20) +#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21) +#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22) +#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23) +#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24) +#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25) +#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26) +#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27) +#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28) +#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29) +#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30) +#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31) + uint32_t reserved_c8 [14]; + uint32_t emcclksel; +#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0) + uint32_t cclksel; +#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8) + uint32_t usbclksel; +#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9) +#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) + uint32_t clksrcsel; +#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0) + uint32_t reserved_110 [12]; + uint32_t extint; + uint32_t reserved_144; + uint32_t extmode; + uint32_t extpolar; + uint32_t reserved_150 [12]; + uint32_t rsid; + uint32_t reserved_184 [1]; + uint32_t matrixarb; + uint32_t reserved_18c [5]; + uint32_t scs; +#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0) +#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1) +#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2) +#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3) +#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4) +#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5) +#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6) + uint32_t reserved_1a4; + uint32_t pclksel; +#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t reserved_1ac; + uint32_t pboost; +#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0) + uint32_t reserved_1b4 [5]; + uint32_t clkoutcfg; +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8) +#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9) + uint32_t rstcon0; + uint32_t rstcon1; + uint32_t reserved_1d4 [2]; + uint32_t emcdlyctl; +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) + uint32_t emccal; +#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7) +#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14) +#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15) +} lpc17xx_scb; + +#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000)) + +typedef struct { + uint32_t reserved_00 [268435456]; + lpc17xx_wwdt wwdt; + uint32_t reserved_40000020 [258040]; + lpc17xx_scb scb; +} lpc17xx; + +#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE)) + +#endif /* LPC17XX_REGS_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/lpc24xx.h b/bsps/arm/lpc24xx/include/bsp/lpc24xx.h new file mode 100644 index 0000000000..64a910c041 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/lpc24xx.h @@ -0,0 +1,2206 @@ +/** + * @file + * + * @ingroup lpc24xx_regs + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H +#define LIBBSP_ARM_LPC24XX_LPC24XX_H + +#include +#include +#include + +#ifdef ARM_MULTILIB_ARCH_V7M + #include +#endif + +/** + * @defgroup lpc24xx_regs Register Definitions + * + * @ingroup lpc24xx + * + * @brief Register definitions. + * + * @{ + */ + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010)) +#define VICIntEnClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024)) + +#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100)) +#define VICVectAddr0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C)) + +#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200)) +#define VICVectPriority0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200)) +#define VICVectPriority1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204)) +#define VICVectPriority2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208)) +#define VICVectPriority3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C)) +#define VICVectPriority4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210)) +#define VICVectPriority5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214)) +#define VICVectPriority6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218)) +#define VICVectPriority7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C)) +#define VICVectPriority8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220)) +#define VICVectPriority9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224)) +#define VICVectPriority10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228)) +#define VICVectPriority11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C)) +#define VICVectPriority12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230)) +#define VICVectPriority13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234)) +#define VICVectPriority14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238)) +#define VICVectPriority15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C)) +#define VICVectPriority16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240)) +#define VICVectPriority17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244)) +#define VICVectPriority18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248)) +#define VICVectPriority19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C)) +#define VICVectPriority20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250)) +#define VICVectPriority21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254)) +#define VICVectPriority22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258)) +#define VICVectPriority23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C)) +#define VICVectPriority24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260)) +#define VICVectPriority25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264)) +#define VICVectPriority26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268)) +#define VICVectPriority27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C)) +#define VICVectPriority28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270)) +#define VICVectPriority29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274)) +#define VICVectPriority30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278)) +#define VICVectPriority31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Pin Connect Block */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define PINSEL_BASE_ADDR 0xE002C000 +#else + #define PINSEL_BASE_ADDR 0x4002C000 +#endif + +#ifdef ARM_MULTILIB_ARCH_V4 + +#define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28)) +#define PINSEL11 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C)) + +#define PINMODE0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* General Purpose Input/Output (GPIO) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define GPIO_BASE_ADDR 0xE0028000 +#else + #define GPIO_BASE_ADDR 0x40028000 +#endif +#define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80)) + +#ifdef ARM_MULTILIB_ARCH_V4 + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Fast I/O setup */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define FIO_BASE_ADDR 0x3FFFC000 +#else + #define FIO_BASE_ADDR 0x20098000 +#endif +#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C)) + +#ifdef ARM_MULTILIB_ARCH_V7M + +#define FIO5DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0)) +#define FIO5MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0)) +#define FIO5PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4)) +#define FIO5SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8)) +#define FIO5CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC)) + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E)) + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +// #define APBDIV (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* External Memory Controller (EMC) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define EMC_BASE_ADDR 0xFFE08000 +#else + #define EMC_BASE_ADDR 0x2009c000 +#endif +#define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_BASE_0 ((uint32_t *) (EMC_BASE_ADDR + 0x200)) +#define EMC_STA_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_BASE_1 ((uint32_t *) (EMC_BASE_ADDR + 0x220)) +#define EMC_STA_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_BASE_2 ((uint32_t *) (EMC_BASE_ADDR + 0x240)) +#define EMC_STA_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_BASE_3 ((uint32_t *) (EMC_BASE_ADDR + 0x260)) +#define EMC_STA_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR0_BASE_ADDR 0xE0004000 +#else + #define TMR0_BASE_ADDR 0x40004000 +#endif +#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR1_BASE_ADDR 0xE0008000 +#else + #define TMR1_BASE_ADDR 0x40008000 +#endif +#define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR2_BASE_ADDR 0xE0070000 +#else + #define TMR2_BASE_ADDR 0x40090000 +#endif +#define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define TMR3_BASE_ADDR 0xE0074000 +#else + #define TMR3_BASE_ADDR 0x40094000 +#endif +#define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define PWM0_BASE_ADDR 0xE0014000 +#else + #define PWM0_BASE_ADDR 0x40014000 +#endif +#define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define PWM1_BASE_ADDR 0xE0018000 +#else + #define PWM1_BASE_ADDR 0x40018000 +#endif +#define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART0_BASE_ADDR 0xE000C000 +#else + #define UART0_BASE_ADDR 0x4000C000 +#endif +#define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART1_BASE_ADDR 0xE0010000 +#else + #define UART1_BASE_ADDR 0x40010000 +#endif +#define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART2_BASE_ADDR 0xE0078000 +#else + #define UART2_BASE_ADDR 0x40098000 +#endif +#define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define UART3_BASE_ADDR 0xE007C000 +#else + #define UART3_BASE_ADDR 0x4009C000 +#endif +#define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C0_BASE_ADDR 0xE001C000 +#else + #define I2C0_BASE_ADDR 0x4001C000 +#endif +#define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C1_BASE_ADDR 0xE005C000 +#else + #define I2C1_BASE_ADDR 0x4005C000 +#endif +#define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2C2_BASE_ADDR 0xE0080000 +#else + #define I2C2_BASE_ADDR 0x400a0000 +#endif +#define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define SSP0_BASE_ADDR 0xE0068000 +#else + #define SSP0_BASE_ADDR 0x40088000 +#endif +#define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define SSP1_BASE_ADDR 0xE0030000 +#else + #define SSP1_BASE_ADDR 0x40030000 +#endif +#define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24)) + +#ifdef ARM_MULTILIB_ARCH_V7M + +/* SSP2 Controller */ +#define SSP2_BASE_ADDR 0x400ac000 +#define SSP2CR0 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00)) +#define SSP2CR1 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04)) +#define SSP2DR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08)) +#define SSP2SR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C)) +#define SSP2CPSR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10)) +#define SSP2IMSC (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14)) +#define SSP2RIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18)) +#define SSP2MIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C)) +#define SSP2ICR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20)) +#define SSP2DMACR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24)) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* Real Time Clock */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define RTC_BASE_ADDR 0xE0024000 +#else + #define RTC_BASE_ADDR 0x40024000 +#endif +#define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define AD0_BASE_ADDR 0xE0034000 +#else + #define AD0_BASE_ADDR 0x40034000 +#endif +#define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C)) +#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10)) +#define AD0DR0 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define DAC_BASE_ADDR 0xE006C000 +#else + #define DAC_BASE_ADDR 0x4008C000 +#endif +#define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define WDG_BASE_ADDR 0xE0000000 +#else + #define WDG_BASE_ADDR 0x40000000 +#endif +#define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#else + #define CAN_ACCEPT_BASE_ADDR 0x4003C000 +#endif +#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#else + #define CAN_CENTRAL_BASE_ADDR 0x40040000 +#endif +#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN1_BASE_ADDR 0xE0044000 +#else + #define CAN1_BASE_ADDR 0x40044000 +#endif +#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define CAN2_BASE_ADDR 0xE0048000 +#else + #define CAN2_BASE_ADDR 0x40048000 +#endif +#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define MCI_BASE_ADDR 0xE008C000 +#else + #define MCI_BASE_ADDR 0x400c0000 +#endif +#define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define I2S_BASE_ADDR 0xE0088000 +#else + #define I2S_BASE_ADDR 0x400a8000 +#endif +#define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define DMA_BASE_ADDR 0xFFE04000 +#else + #define DMA_BASE_ADDR 0x20080000 +#endif +#define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100) +#define GPDMA_CH0_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120) +#define GPDMA_CH1_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130)) + +/* USB Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USB_INT_BASE_ADDR 0xE01FC1C0 + #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#else + #define USB_INT_BASE_ADDR 0x400fc1c0 + #define USB_BASE_ADDR 0x2008c200 +#endif + +#define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0)) + +/* USB Host Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBHC_BASE_ADDR 0xFFE0C000 +#else + #define USBHC_BASE_ADDR 0x2008c000 +#endif +#define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_BASE_ADDR 0xFFE0C100 +#else + #define USBOTG_BASE_ADDR 0x2008c100 +#endif +#define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C)) +#define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#else + #define USBOTG_I2C_BASE_ADDR 0x2008c300 +#endif +#define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10)) + +#ifdef ARM_MULTILIB_ARCH_V4 + #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#else + #define USBOTG_CLK_BASE_ADDR 0x2008cff0 +#endif +#define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#ifdef ARM_MULTILIB_ARCH_V4 + #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#else + #define MAC_BASE_ADDR 0x20084000 +#endif +#define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + +/* LCD Controller */ + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8) + #define LCD_BASE_ADDR 0xFFE10000 +#else + #define LCD_CFG (*(volatile uint32_t *) 0x400FC1B8) + #define LCD_BASE_ADDR 0x20088000 +#endif +#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000)) +#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004)) +#define LCD_POL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008)) +#define LCD_LE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C)) +#define LCD_UPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010)) +#define LCD_LPBASE (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014)) +#define LCD_CTRL (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018)) +#define LCD_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C)) +#define LCD_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020)) +#define LCD_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024)) +#define LCD_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028)) +#define LCD_UPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C)) +#define LCD_LPCURR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030)) +#define LCD_PAL_ADDR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200)) +#define CRSR_IMG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800)) +#define CRSR_CTLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00)) +#define CRSR_CFG (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04)) +#define CRSR_PAL0 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08)) +#define CRSR_PAL1 (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C)) +#define CRSR_XY (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10)) +#define CRSR_CLIP (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14)) +#define CRSR_INTMSK (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20)) +#define CRSR_INTCLR (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24)) +#define CRSR_INTRAW (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28)) +#define CRSR_INTSTAT (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C)) + +/* Register Fields */ + +#define GET_FIELD( val, mask, shift) \ + (((val) & (mask)) >> (shift)) + +#define SET_FIELD( val, field, mask, shift) \ + (((val) & ~(mask)) | (((field) << (shift)) & (mask))) + +/* CLKSRCSEL */ + +#define CLKSRCSEL_CLKSRC_MASK 0x00000003U + +#define GET_CLKSRCSEL_CLKSRC(reg) \ + GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0) + +#define SET_CLKSRCSEL_CLKSRC(reg, val) \ + SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0) + +/* PLLCON */ + +#define PLLCON_PLLE 0x00000001U + +#define PLLCON_PLLC 0x00000002U + +/* PLLCFG */ + +#define PLLCFG_MSEL_MASK 0x00007fffU + +#define GET_PLLCFG_MSEL(reg) \ + GET_FIELD(reg, PLLCFG_MSEL_MASK, 0) + +#define SET_PLLCFG_MSEL(reg, val) \ + SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0) + +#define PLLCFG_NSEL_MASK 0x00ff0000U + +#define GET_PLLCFG_NSEL(reg) \ + GET_FIELD(reg, PLLCFG_NSEL_MASK, 16) + +#define SET_PLLCFG_NSEL(reg, val) \ + SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16) + +/* PLLSTAT */ + +#define PLLSTAT_MSEL_MASK 0x00007fffU + +#define GET_PLLSTAT_MSEL(reg) \ + GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0) + +#define SET_PLLSTAT_MSEL(reg, val) \ + SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0) + +#define PLLSTAT_NSEL_MASK 0x00ff0000U + +#define GET_PLLSTAT_NSEL(reg) \ + GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16) + +#define SET_PLLSTAT_NSEL(reg, val) \ + SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16) + +#define PLLSTAT_PLLE 0x01000000U + +#define PLLSTAT_PLLC 0x02000000U + +#define PLLSTAT_PLOCK 0x04000000U + +/* CCLKCFG */ + +#define CCLKCFG_CCLKSEL_MASK 0x000000ffU + +#define GET_CCLKCFG_CCLKSEL(reg) \ + GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0) + +#define SET_CCLKCFG_CCLKSEL(reg, val) \ + SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0) + +/* MEMMAP */ + +#define MEMMAP_MAP_MASK 0x00000003U + +#define GET_MEMMAP_MAP(reg) \ + GET_FIELD(reg, MEMMAP_MAP_MASK, 0) + +#define SET_MEMMAP_MAP(reg, val) \ + SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0) + +/* TIR */ + +#define TIR_MR0 0x00000001U + +#define TIR_MR1 0x00000002U + +#define TIR_MR2 0x00000004U + +#define TIR_MR3 0x00000008U + +#define TIR_CR0 0x00000010U + +#define TIR_CR1 0x00000020U + +#define TIR_CR2 0x00000040U + +#define TIR_CR3 0x00000080U + +/* TCR */ + +#define TCR_EN 0x00000001U + +#define TCR_RST 0x00000002U + +/* TMCR */ + +#define TMCR_MR0I 0x00000001U + +#define TMCR_MR0R 0x00000002U + +#define TMCR_MR0S 0x00000004U + +#define TMCR_MR1I 0x00000008U + +#define TMCR_MR1R 0x00000010U + +#define TMCR_MR1S 0x00000020U + +#define TMCR_MR2I 0x00000040U + +#define TMCR_MR2R 0x00000080U + +#define TMCR_MR2S 0x00000100U + +#define TMCR_MR3I 0x00000200U + +#define TMCR_MR3R 0x00000400U + +#define TMCR_MR3S 0x00000800U + +/* PCLKSEL0 */ + +#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U + +#define GET_PCLKSEL0_PCLK_WDT(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0) + +#define SET_PCLKSEL0_PCLK_WDT(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0) + +#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU + +#define GET_PCLKSEL0_PCLK_TIMER0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2) + +#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2) + +#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U + +#define GET_PCLKSEL0_PCLK_TIMER1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4) + +#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4) + +#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U + +#define GET_PCLKSEL0_PCLK_UART0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6) + +#define SET_PCLKSEL0_PCLK_UART0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6) + +#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U + +#define GET_PCLKSEL0_PCLK_UART1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8) + +#define SET_PCLKSEL0_PCLK_UART1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8) + +#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U + +#define GET_PCLKSEL0_PCLK_PWM0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10) + +#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10) + +#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U + +#define GET_PCLKSEL0_PCLK_PWM1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12) + +#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12) + +#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U + +#define GET_PCLKSEL0_PCLK_I2C0(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14) + +#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14) + +#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U + +#define GET_PCLKSEL0_PCLK_SPI(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16) + +#define SET_PCLKSEL0_PCLK_SPI(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16) + +#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U + +#define GET_PCLKSEL0_PCLK_RTC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18) + +#define SET_PCLKSEL0_PCLK_RTC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18) + +#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U + +#define GET_PCLKSEL0_PCLK_SSP1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20) + +#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20) + +#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U + +#define GET_PCLKSEL0_PCLK_DAC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22) + +#define SET_PCLKSEL0_PCLK_DAC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22) + +#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U + +#define GET_PCLKSEL0_PCLK_ADC(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24) + +#define SET_PCLKSEL0_PCLK_ADC(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24) + +#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U + +#define GET_PCLKSEL0_PCLK_CAN1(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26) + +#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26) + +#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U + +#define GET_PCLKSEL0_PCLK_CAN2(reg) \ + GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28) + +#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28) + +/* PCLKSEL1 */ + +#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U + +#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0) + +#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0) + +#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU + +#define GET_PCLKSEL1_PCLK_GPIO(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2) + +#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2) + +#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U + +#define GET_PCLKSEL1_PCLK_PCB(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4) + +#define SET_PCLKSEL1_PCLK_PCB(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4) + +#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U + +#define GET_PCLKSEL1_PCLK_I2C1(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6) + +#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6) + +#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U + +#define GET_PCLKSEL1_PCLK_SSP0(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10) + +#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10) + +#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U + +#define GET_PCLKSEL1_PCLK_TIMER2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12) + +#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12) + +#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U + +#define GET_PCLKSEL1_PCLK_TIMER3(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14) + +#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14) + +#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U + +#define GET_PCLKSEL1_PCLK_UART2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16) + +#define SET_PCLKSEL1_PCLK_UART2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16) + +#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U + +#define GET_PCLKSEL1_PCLK_UART3(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18) + +#define SET_PCLKSEL1_PCLK_UART3(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18) + +#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U + +#define GET_PCLKSEL1_PCLK_I2C2(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20) + +#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20) + +#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U + +#define GET_PCLKSEL1_PCLK_I2S(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22) + +#define SET_PCLKSEL1_PCLK_I2S(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22) + +#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U + +#define GET_PCLKSEL1_PCLK_MCI(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24) + +#define SET_PCLKSEL1_PCLK_MCI(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24) + +#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U + +#define GET_PCLKSEL1_PCLK_SYSCON(reg) \ + GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28) + +#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \ + SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28) + +/* RTC_ILR */ + +#define RTC_ILR_RTCCIF 0x00000001U + +#define RTC_ILR_RTCALF 0x00000002U + +#define RTC_ILR_RTSSF 0x00000004U + +/* RTC_CCR */ + +#define RTC_CCR_CLKEN 0x00000001U + +#define RTC_CCR_CTCRST 0x00000002U + +#define RTC_CCR_CLKSRC 0x00000010U + +/* SSP */ + +typedef struct { + uint32_t cr0; + uint32_t cr1; + uint32_t dr; + uint32_t sr; + uint32_t cpsr; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +} lpc24xx_ssp; + +/* SSP_CR0 */ + +#define SSP_CR0_DSS_MASK 0x0000000fU + +#define GET_SSP_CR0_DSS(reg) \ + GET_FIELD(reg, SSP_CR0_DSS_MASK, 0) + +#define SET_SSP_CR0_DSS(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0) + +#define SSP_CR0_FRF_MASK 0x00000030U + +#define GET_SSP_CR0_FRF(reg) \ + GET_FIELD(reg, SSP_CR0_FRF_MASK, 4) + +#define SET_SSP_CR0_FRF(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4) + +#define SSP_CR0_CPOL 0x00000040U + +#define SSP_CR0_CPHA 0x00000080U + +#define SSP_CR0_SCR_MASK 0x0000ff00U + +#define GET_SSP_CR0_SCR(reg) \ + GET_FIELD(reg, SSP_CR0_SCR_MASK, 8) + +#define SET_SSP_CR0_SCR(reg, val) \ + SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8) + +/* SSP_CR1 */ + +#define SSP_CR1_LBM 0x00000001U + +#define SSP_CR1_SSE 0x00000002U + +#define SSP_CR1_MS 0x00000004U + +#define SSP_CR1_SOD 0x00000008U + +/* SSP_SR */ + +#define SSP_SR_TFE 0x00000001U + +#define SSP_SR_TNF 0x00000002U + +#define SSP_SR_RNE 0x00000004U + +#define SSP_SR_RFF 0x00000008U + +#define SSP_SR_BSY 0x00000010U + +/* SSP_IMSC */ + +#define SSP_IMSC_RORIM 0x00000001U + +#define SSP_IMSC_RTIM 0x00000002U + +#define SSP_IMSC_RXIM 0x00000004U + +#define SSP_IMSC_TXIM 0x00000008U + +/* SSP_RIS */ + +#define SSP_RIS_RORRIS 0x00000001U + +#define SSP_RIS_RTRIS 0x00000002U + +#define SSP_RIS_RXRIS 0x00000004U + +#define SSP_RIS_TXRIS 0x00000008U + +/* SSP_MIS */ + +#define SSP_MIS_RORRIS 0x00000001U + +#define SSP_MIS_RTRIS 0x00000002U + +#define SSP_MIS_RXRIS 0x00000004U + +#define SSP_MIS_TXRIS 0x00000008U + +/* SSP_ICR */ + +#define SSP_ICR_RORRIS 0x00000001U + +#define SSP_ICR_RTRIS 0x00000002U + +#define SSP_ICR_RXRIS 0x00000004U + +#define SSP_ICR_TXRIS 0x00000008U + +/* SSP_DMACR */ + +#define SSP_DMACR_RXDMAE 0x00000001U + +#define SSP_DMACR_TXDMAE 0x00000002U + +/* GPDMA */ + +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc24xx_dma_descriptor; + +typedef struct { + lpc24xx_dma_descriptor desc; + uint32_t cfg; +} lpc24xx_dma_channel; + +#define GPDMA_CH_NUMBER 2 + +#define GPDMA_STATUS_CH_0 0x00000001U + +#define GPDMA_STATUS_CH_1 0x00000002U + +#define GPDMA_CH_BASE_ADDR(i) \ + ((volatile lpc24xx_dma_channel *) \ + ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR)) + +/* GPDMA_CONFIG */ + +#define GPDMA_CONFIG_EN 0x00000001U + +#define GPDMA_CONFIG_MODE 0x00000002U + +/* GPDMA_ENABLED_CHNS */ + +#define GPDMA_ENABLED_CHNS_CH0 0x00000001U + +#define GPDMA_ENABLED_CHNS_CH1 0x00000002U + +/* GPDMA_CH_CTRL */ + +#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU + +#define GET_GPDMA_CH_CTRL_TSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0) + +#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0) + +#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU + +#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U + +#define GET_GPDMA_CH_CTRL_SBSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12) + +#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12) + +#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U + +#define GET_GPDMA_CH_CTRL_DBSZ(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15) + +#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15) + +#define GPDMA_CH_CTRL_BSZ_1 0x00000000U + +#define GPDMA_CH_CTRL_BSZ_4 0x00000001U + +#define GPDMA_CH_CTRL_BSZ_8 0x00000002U + +#define GPDMA_CH_CTRL_BSZ_16 0x00000003U + +#define GPDMA_CH_CTRL_BSZ_32 0x00000004U + +#define GPDMA_CH_CTRL_BSZ_64 0x00000005U + +#define GPDMA_CH_CTRL_BSZ_128 0x00000006U + +#define GPDMA_CH_CTRL_BSZ_256 0x00000007U + +#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U + +#define GET_GPDMA_CH_CTRL_SW(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18) + +#define SET_GPDMA_CH_CTRL_SW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18) + +#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U + +#define GET_GPDMA_CH_CTRL_DW(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21) + +#define SET_GPDMA_CH_CTRL_DW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21) + +#define GPDMA_CH_CTRL_W_8 0x00000000U + +#define GPDMA_CH_CTRL_W_16 0x00000001U + +#define GPDMA_CH_CTRL_W_32 0x00000002U + +#define GPDMA_CH_CTRL_SI 0x04000000U + +#define GPDMA_CH_CTRL_DI 0x08000000U + +#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U + +#define GET_GPDMA_CH_CTRL_PROT(reg) \ + GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28) + +#define SET_GPDMA_CH_CTRL_PROT(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28) + +#define GPDMA_CH_CTRL_ITC 0x80000000U + +/* GPDMA_CH_CFG */ + +#define GPDMA_CH_CFG_EN 0x00000001U + +#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU + +#define GET_GPDMA_CH_CFG_SRCPER(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1) + +#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1) + +#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U + +#define GET_GPDMA_CH_CFG_DESTPER(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6) + +#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6) + +#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U + +#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U + +#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U + +#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U + +#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U + +#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U + +#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U + +#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U + +#define GET_GPDMA_CH_CFG_FLOW(reg) \ + GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11) + +#define SET_GPDMA_CH_CFG_FLOW(reg, val) \ + SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11) + +#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U + +#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U + +#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U + +#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U + +#define GPDMA_CH_CFG_IE 0x00004000U + +#define GPDMA_CH_CFG_ITC 0x00008000U + +#define GPDMA_CH_CFG_LOCK 0x00010000U + +#define GPDMA_CH_CFG_ACTIVE 0x00020000U + +#define GPDMA_CH_CFG_HALT 0x00040000U + +/* AHBCFG */ + +#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U + +#define AHBCFG_BREAK_BURST_MASK 0x00000006U + +#define GET_AHBCFG_BREAK_BURST(reg) \ + GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1) + +#define SET_AHBCFG_BREAK_BURST(reg, val) \ + SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1) + +#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U + +#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U + +#define GET_AHBCFG_QUANTUM_SIZE(reg) \ + GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4) + +#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \ + SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4) + +#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U + +#define GET_AHBCFG_DEFAULT_MASTER(reg) \ + GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8) + +#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \ + SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8) + +#define AHBCFG_EP1_MASK 0x00007000U + +#define GET_AHBCFG_EP1(reg) \ + GET_FIELD(reg, AHBCFG_EP1_MASK, 12) + +#define SET_AHBCFG_EP1(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12) + +#define AHBCFG_EP2_MASK 0x00070000U + +#define GET_AHBCFG_EP2(reg) \ + GET_FIELD(reg, AHBCFG_EP2_MASK, 16) + +#define SET_AHBCFG_EP2(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16) + +#define AHBCFG_EP3_MASK 0x00700000U + +#define GET_AHBCFG_EP3(reg) \ + GET_FIELD(reg, AHBCFG_EP3_MASK, 20) + +#define SET_AHBCFG_EP3(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20) + +#define AHBCFG_EP4_MASK 0x07000000U + +#define GET_AHBCFG_EP4(reg) \ + GET_FIELD(reg, AHBCFG_EP4_MASK, 24) + +#define SET_AHBCFG_EP4(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24) + +#define AHBCFG_EP5_MASK 0x70000000U + +#define GET_AHBCFG_EP5(reg) \ + GET_FIELD(reg, AHBCFG_EP5_MASK, 28) + +#define SET_AHBCFG_EP5(reg, val) \ + SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28) + +/* I2C */ + +typedef struct { + uint32_t conset; + uint32_t stat; + uint32_t dat; + uint32_t adr; + uint32_t sclh; + uint32_t scll; + uint32_t conclr; +} lpc24xx_i2c; + +#define LPC24XX_I2C_AA (1U << 2U) + +#define LPC24XX_I2C_SI (1U << 3U) + +#define LPC24XX_I2C_STO (1U << 4U) + +#define LPC24XX_I2C_STA (1U << 5U) + +#define LPC24XX_I2C_EN (1U << 6U) + +/* IO */ + +#ifdef ARM_MULTILIB_ARCH_V4 + #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0) + #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0) +#else + #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2) + #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2) + #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + #define IOCON_MODE(val) BSP_FLD32(val, 3, 4) + #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4) + #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4) + #define IOCON_HYS BSP_BIT32(5) + #define IOCON_INV BSP_BIT32(6) + #define IOCON_ADMODE BSP_BIT32(7) + #define IOCON_FILTER BSP_BIT32(8) + #define IOCON_HS BSP_BIT32(8) + #define IOCON_SLEW BSP_BIT32(9) + #define IOCON_HIDRIVE BSP_BIT32(9) + #define IOCON_OD BSP_BIT32(10) + #define IOCON_DACEN BSP_BIT32(16) + #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR) +#endif + +typedef struct { + uint32_t dir; + uint32_t reserved [3]; + uint32_t mask; + uint32_t pin; + uint32_t set; + uint32_t clr; +} lpc24xx_fio; + +#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR) + +#ifdef ARM_MULTILIB_ARCH_V4 + +/* PCONP */ + +#define PCONP_GPDMA (1U << 29) +#define PCONP_ETHERNET (1U << 30) +#define PCONP_USB (1U << 31) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +/* I2S */ + +static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR; + +/* ADC */ + +#define ADC_CR_SEL(val) BSP_FLD32(val, 0, 7) +#define ADC_CR_SEL_GET(val) BSP_FLD32GET(val, 0, 7) +#define ADC_CR_SEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define ADC_CR_CLKDIV(val) BSP_FLD32(val, 8, 15) +#define ADC_CR_CLKDIV_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define ADC_CR_CLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define ADC_CR_BURST BSP_BIT32(16) +#define ADC_CR_CLKS(val) BSP_FLD32(val, 17, 19) +#define ADC_CR_PDN BSP_BIT32(21) +#define ADC_CR_START(val) BSP_FLD32(val, 24, 26) +#define ADC_CR_EDGE BSP_BIT32(27) + +#define ADC_DR_VALUE(reg) BSP_FLD32GET(reg, 6, 15) +#define ADC_DR_OVERRUN BSP_BIT32(30) +#define ADC_DR_DONE BSP_BIT32(31) + +/* DAC */ + +#define DAC_STEPS 1024 +#define DAC_VALUE(val) BSP_FLD32(val, 6, 15) +#define DAC_BIAS BSP_BIT32(16) + +/** @} */ + +#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/ssp.h b/bsps/arm/lpc24xx/include/bsp/ssp.h new file mode 100644 index 0000000000..1a77219d0e --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/ssp.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup lpc24xx_libi2c + * + * @brief LibI2C bus driver for the Synchronous Serial Port (SSP). + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_SSP_H +#define LIBBSP_ARM_LPC24XX_SSP_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @ingroup lpc24xx_libi2c + * + * @{ + */ + +extern rtems_libi2c_bus_t * const lpc24xx_ssp_0; + +extern rtems_libi2c_bus_t * const lpc24xx_ssp_1; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_SSP_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/start-config.h b/bsps/arm/lpc24xx/include/bsp/start-config.h new file mode 100644 index 0000000000..4476cbdebe --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/start-config.h @@ -0,0 +1,121 @@ +/** + * @file + * + * @ingroup lpc24xx + * + * @brief BSP start configuration. + */ + +/* + * Copyright (c) 2011-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_START_CONFIG_H +#define LIBBSP_ARM_LPC24XX_START_CONFIG_H + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Pico seconds @a ps to clock ticks for clock frequency @a f. + */ +#define LPC24XX_PS_TO_CLK(ps, f) \ + (((((uint64_t) (ps)) * ((uint64_t) (f))) + 1000000000000ULL - 1ULL) \ + / 1000000000000ULL) + +/** + * @brief Pico seconds @a ps to EMCCLK clock ticks adjusted by @a m. + */ +#define LPC24XX_PS_TO_EMCCLK(ps, m) \ + (LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) > (m) ? \ + LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) - (m) : 0) + +typedef struct { + uint32_t refresh; + uint32_t readconfig; + uint32_t trp; + uint32_t tras; + uint32_t tsrex; + uint32_t tapr; + uint32_t tdal; + uint32_t twr; + uint32_t trc; + uint32_t trfc; + uint32_t txsr; + uint32_t trrd; + uint32_t tmrd; + uint32_t emcdlyctl; +} lpc24xx_emc_dynamic_config; + +typedef struct { + volatile lpc_emc_dynamic *chip_select; + uint32_t address; + uint32_t config; + uint32_t rascas; + uint32_t mode; +} lpc24xx_emc_dynamic_chip_config; + +typedef struct { + volatile lpc_emc_static *chip_select; + struct { + uint32_t config; + uint32_t waitwen; + uint32_t waitoen; + uint32_t waitrd; + uint32_t waitpage; + uint32_t waitwr; + uint32_t waitrun; + } config; +} lpc24xx_emc_static_chip_config; + +extern BSP_START_DATA_SECTION const lpc24xx_pin_range + lpc24xx_start_config_pinsel []; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config + lpc24xx_start_config_emc_dynamic []; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config + lpc24xx_start_config_emc_dynamic_chip []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_emc_dynamic_chip_count; + +extern BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config + lpc24xx_start_config_emc_static_chip []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_emc_static_chip_count; + +#ifdef ARM_MULTILIB_ARCH_V7M + +extern BSP_START_DATA_SECTION const ARMV7M_MPU_Region + lpc24xx_start_config_mpu_region []; + +extern BSP_START_DATA_SECTION const size_t + lpc24xx_start_config_mpu_region_count; + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_START_CONFIG_H */ diff --git a/bsps/arm/lpc24xx/include/bsp/system-clocks.h b/bsps/arm/lpc24xx/include/bsp/system-clocks.h new file mode 100644 index 0000000000..564d12ec10 --- /dev/null +++ b/bsps/arm/lpc24xx/include/bsp/system-clocks.h @@ -0,0 +1,89 @@ +/** + * @file + * + * @ingroup lpc24xx_clocks + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc24xx_clock System Clocks + * + * @ingroup lpc24xx + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Initializes the standard timer. + * + * This function uses Timer 1. + */ +void lpc24xx_timer_initialize(void); + +/** + * @brief Returns current standard timer value in CPU clocks. + * + * This function uses Timer 1. + */ +static inline unsigned lpc24xx_timer(void) +{ + return T1TC; +} + +/** + * @brief Delay for @a us micro seconds. + * + * This function uses the standard timer and assumes that the CPU frequency is + * in whole MHz numbers. The delay value @a us will be converted to CPU ticks + * and there is no protection against integer overflows. + * + * This function uses Timer 1. + */ +void lpc24xx_micro_seconds_delay(unsigned us); + +/** + * @brief Returns the PLL output clock frequency in [Hz]. + * + * Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc24xx_pllclk(void); + +/** + * @brief Returns the CPU clock frequency in [Hz]. + * + * Returns zero in case of an unexpected PLL input frequency. + */ +unsigned lpc24xx_cclk(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/lpc24xx/include/tm27.h b/bsps/arm/lpc24xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/lpc24xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/lpc32xx/headers.am b/bsps/arm/lpc32xx/headers.am new file mode 100644 index 0000000000..40c0cfdb3d --- /dev/null +++ b/bsps/arm/lpc32xx/headers.am @@ -0,0 +1,19 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/boot.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/emc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/hsu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/lpc32xx.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/lpc32xx/include/bsp/nand-mlc.h diff --git a/bsps/arm/lpc32xx/include/bsp.h b/bsps/arm/lpc32xx/include/bsp.h new file mode 100644 index 0000000000..0f9d1318cd --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp.h @@ -0,0 +1,259 @@ +/** + * @file + * + * @ingroup arm_lpc32xx + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_BSP_H +#define LIBBSP_ARM_LPC32XX_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct rtems_bsdnet_ifconfig; + +/** + * @defgroup arm_lpc32xx LPC32XX Support + * + * @ingroup bsp_arm + * + * @brief LPC32XX support package. + * + * @{ + */ + +/** + * @brief Network driver attach and detach function. + */ +int lpc_eth_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +/** + * @brief Standard network driver attach and detach function. + */ +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach + +/** + * @brief Standard network driver name. + */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor clock + * to be stopped, while on-chip peripherals remain active. Any enabled + * interrupt from a peripheral or an external interrupt source will cause the + * processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle + * + * #include + * @endcode + */ +void *lpc32xx_idle(uintptr_t ignored); + +#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1) + +static inline unsigned lpc32xx_timer(void) +{ + volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; + + return timer->tc; +} + +static inline void lpc32xx_micro_seconds_delay(unsigned us) +{ + unsigned start = lpc32xx_timer(); + unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000); + unsigned elapsed = 0; + + do { + elapsed = lpc32xx_timer() - start; + } while (elapsed < delay); +} + +#if LPC32XX_OSCILLATOR_MAIN == 13000000U + #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \ + (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1)) + #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \ + (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0)) +#else + #error "unexpected main oscillator frequency" +#endif + +bool lpc32xx_start_pll_setup( + uint32_t hclkpll_ctrl, + uint32_t hclkdiv_ctrl, + bool force +); + +uint32_t lpc32xx_sysclk(void); + +uint32_t lpc32xx_hclkpll_clk(void); + +uint32_t lpc32xx_periph_clk(void); + +uint32_t lpc32xx_hclk(void); + +uint32_t lpc32xx_arm_clk(void); + +uint32_t lpc32xx_ddram_clk(void); + +typedef enum { + LPC32XX_NAND_CONTROLLER_NONE, + LPC32XX_NAND_CONTROLLER_MLC, + LPC32XX_NAND_CONTROLLER_SLC +} lpc32xx_nand_controller; + +void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller); + +void bsp_restart(void *addr); + +void *bsp_idle_thread(uintptr_t arg); + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5 + +/** + * @brief Begin of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_begin []; + +/** + * @brief End of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_end []; + +/** + * @brief Size of magic zero area. + * + * A read from this area returns zero. Writes have no effect. + */ +extern uint32_t lpc32xx_magic_zero_size []; + +#ifdef LPC32XX_SCRATCH_AREA_SIZE + /** + * @rief Scratch area. + * + * The usage is application specific. + */ + extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE] + __attribute__((aligned(32))); +#endif + +#define LPC32XX_DO_STOP_GPDMA \ + do { \ + if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \ + if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \ + int i = 0; \ + for (i = 0; i < 8; ++i) { \ + lpc32xx.dma.channels [i].cfg = 0; \ + } \ + lpc32xx.dma.cfg &= ~DMA_CFG_E; \ + } \ + LPC32XX_DMACLK_CTRL = 0; \ + } \ + } while (0) + +#define LPC32XX_DO_STOP_ETHERNET \ + do { \ + if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \ + lpc32xx.eth.command = 0x38; \ + lpc32xx.eth.mac1 = 0xcf00; \ + lpc32xx.eth.mac1 = 0; \ + LPC32XX_MAC_CLK_CTRL = 0; \ + } \ + } while (0) + +#define LPC32XX_DO_STOP_USB \ + do { \ + if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \ + LPC32XX_OTG_CLK_CTRL = 0; \ + LPC32XX_USB_CTRL = 0x80000; \ + } \ + } while (0) + +#define LPC32XX_DO_RESTART(addr) \ + do { \ + ARM_SWITCH_REGISTERS; \ + rtems_interrupt_level level; \ + uint32_t ctrl = 0; \ + \ + rtems_interrupt_disable(level); \ + \ + arm_cp15_data_cache_test_and_clean(); \ + arm_cp15_instruction_cache_invalidate(); \ + \ + ctrl = arm_cp15_get_control(); \ + ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \ + arm_cp15_set_control(ctrl); \ + \ + __asm__ volatile ( \ + ARM_SWITCH_TO_ARM \ + "mov pc, %[addr]\n" \ + ARM_SWITCH_BACK \ + : ARM_SWITCH_OUTPUT \ + : [addr] "r" (addr) \ + ); \ + } while (0) + +/** @} */ + +/** + * @defgroup lpc LPC Support + * + * @ingroup arm_lpc32xx + * + * @brief LPC support package. + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC32XX_BSP_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/boot.h b/bsps/arm/lpc32xx/include/bsp/boot.h new file mode 100644 index 0000000000..b9c845bc8f --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/boot.h @@ -0,0 +1,114 @@ +/** + * @file + * + * @ingroup lpc32xx_boot + * + * @brief Boot support API. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_BOOT_H +#define LIBBSP_ARM_LPC32XX_BOOT_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_boot Boot Support + * + * @ingroup arm_lpc32xx + * + * @brief Boot support. + * + * The NXP internal boot program shall be the "stage-0 program". + * + * The boot program within the first page of the first or second block shall be + * "stage-1 program". It will be invoked by the stage-0 program from NXP. + * + * The program loaded by the stage-1 program will be the "stage-2 program" or the + * "boot loader". + * + * The program loaded by the stage-2 program will be the "stage-3 program" or the + * "application". + * + * The stage-1 program image must have a format specified by NXP. + * + * The stage-2 and stage-3 program images may have any format. + * + * @{ + */ + +#define LPC32XX_BOOT_BLOCK_0 0 +#define LPC32XX_BOOT_BLOCK_1 1 + +#define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0 +#define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2 +#define LPC32XX_BOOT_ICR_LP_4AC_8IF 0xb4 +#define LPC32XX_BOOT_ICR_LP_5AC_8IF 0x96 + +typedef union { + struct { + uint8_t d0; + uint8_t reserved_0 [3]; + uint8_t d1; + uint8_t reserved_1 [3]; + uint8_t d2; + uint8_t reserved_2 [3]; + uint8_t d3; + uint8_t reserved_3 [3]; + uint8_t d4; + uint8_t reserved_4 [3]; + uint8_t d5; + uint8_t reserved_5 [3]; + uint8_t d6; + uint8_t reserved_6 [3]; + uint8_t d7; + uint8_t reserved_7 [3]; + uint8_t d8; + uint8_t reserved_8 [3]; + uint8_t d9; + uint8_t reserved_9 [3]; + uint8_t d10; + uint8_t reserved_10 [3]; + uint8_t d11; + uint8_t reserved_11 [3]; + uint8_t d12; + uint8_t reserved_12 [463]; + } field; + uint32_t data [MLC_SMALL_DATA_WORD_COUNT]; +} lpc32xx_boot_block; + +void lpc32xx_setup_boot_block( + lpc32xx_boot_block *boot_block, + uint8_t icr, + uint8_t page_count +); + +void lpc32xx_set_boot_block_bad( + lpc32xx_boot_block *boot_block +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_BOOT_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/emc.h b/bsps/arm/lpc32xx/include/bsp/emc.h new file mode 100644 index 0000000000..c0ae18b395 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/emc.h @@ -0,0 +1,161 @@ +/** + * @file + * + * @ingroup lpc32xx_emc + * + * @brief EMC support API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_EMC_H +#define LIBBSP_ARM_LPC32XX_EMC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup lpc_emc + * + * @brief EMC Support + * + * @{ + */ + +/** + * @name SDRAM Clock Control Register (SDRAMCLK_CTRL) + * + * @{ + */ + +#define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0) +#define SDRAMCLK_DDR_MODE BSP_BIT32(1) +#define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6) +#define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7) +#define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8) +#define SDRAMCLK_CAL_DELAY BSP_BIT32(9) +#define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12) +#define SDRAMCLK_DCA_STATUS BSP_BIT32(13) +#define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18) +#define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19) +#define SDRAMCLK_PIN_1_FAST BSP_BIT32(20) +#define SDRAMCLK_PIN_2_FAST BSP_BIT32(21) +#define SDRAMCLK_PIN_3_FAST BSP_BIT32(22) + +/** @} */ + +/** + * @name EMC AHB Control Register (EMCAHBControl) + * + * @{ + */ + +#define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0) + +/** @} */ + +/** + * @name EMC AHB Timeout Register (EMCAHBTimeOut) + * + * @{ + */ + +#define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9) + +/** @} */ + +/** + * @name SDRAM Mode and Extended Mode Registers + * + * @{ + */ + +#define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10) +#define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11) +#define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11) + +#define SDRAM_ADDR_BANK_16MB(ba1, ba0) \ + (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22)) +#define SDRAM_ADDR_BANK_32MB(ba1, ba0) \ + (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24)) +#define SDRAM_ADDR_BANK_64MB(ba1, ba0) \ + (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24)) + +#define SDRAM_MODE_16MB(mode) \ + (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode)) +#define SDRAM_MODE_32MB(mode) \ + (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode)) +#define SDRAM_MODE_64MB(mode) \ + (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode)) + +#define SDRAM_EXTMODE_16MB(mode) \ + (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode)) +#define SDRAM_EXTMODE_32MB(mode) \ + (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode)) +#define SDRAM_EXTMODE_64MB(mode) \ + (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode)) + +#define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2) +#define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3) +#define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6) +#define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8) +#define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9) + +#define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2) +#define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6) + +/** @} */ + +typedef struct { + uint32_t size; + uint32_t config; + uint32_t rascas; + uint32_t mode; + uint32_t extmode; +} lpc32xx_emc_dynamic_chip_config; + +typedef struct { + uint32_t sdramclk_ctrl; + uint32_t nop_time_in_us; + uint32_t control; + uint32_t refresh; + uint32_t readconfig; + uint32_t trp; + uint32_t tras; + uint32_t tsrex; + uint32_t twr; + uint32_t trc; + uint32_t trfc; + uint32_t txsr; + uint32_t trrd; + uint32_t tmrd; + uint32_t tcdlr; + lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT]; +} lpc32xx_emc_dynamic_config; + +void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_EMC_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/hsu.h b/bsps/arm/lpc32xx/include/bsp/hsu.h new file mode 100644 index 0000000000..ba97dfb423 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/hsu.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup lpc32xx_hsu + * + * @brief HSU support API. + */ + +/* + * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_HSU_H +#define LIBBSP_ARM_LPC32XX_HSU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_hsu HSU Support + * + * @ingroup arm_lpc32xx + * + * @brief HSU Support + * + * @{ + */ + +typedef struct { + uint32_t fifo; + uint32_t level; + uint32_t iir; + uint32_t ctrl; + uint32_t rate; +} lpc32xx_hsu; + +typedef struct { + rtems_termios_device_context base; + volatile lpc32xx_hsu *hsu; + size_t chars_in_transmission; + rtems_vector_number irq; + uint32_t initial_baud; +} lpc32xx_hsu_context; + +extern const rtems_termios_device_handler lpc32xx_hsu_fns; + +bool lpc32xx_hsu_probe(rtems_termios_device_context *base); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_HSU_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/i2c.h b/bsps/arm/lpc32xx/include/bsp/i2c.h new file mode 100644 index 0000000000..e0bf8349ac --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/i2c.h @@ -0,0 +1,269 @@ +/** + * @file + * + * @ingroup lpc32xx_i2c + * + * @brief I2C support API. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_I2C_H +#define LIBBSP_ARM_LPC32XX_I2C_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_i2c I2C Support + * + * @ingroup arm_lpc32xx + * + * @brief I2C Support + * + * All writes and reads will be performed in master mode. Exclusive bus access + * will be assumed. + * + * @{ + */ + +/** + * @name I2C Clock Control Register (I2CCLK_CTRL) + * + * @{ + */ + +#define I2CCLK_1_EN BSP_BIT32(0) +#define I2CCLK_2_EN BSP_BIT32(1) +#define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2) +#define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3) +#define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4) + +/** @} */ + +/** + * @name I2C TX Data FIFO Register (I2Cn_TX) + * + * @{ + */ + +#define I2C_TX_READ BSP_BIT32(0) +#define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7) +#define I2C_TX_START BSP_BIT32(8) +#define I2C_TX_STOP BSP_BIT32(9) + +/** @} */ + +/** + * @name I2C Status Register (I2Cn_STAT) + * + * @{ + */ + +#define I2C_STAT_TDI BSP_BIT32(0) +#define I2C_STAT_AFI BSP_BIT32(1) +#define I2C_STAT_NAI BSP_BIT32(2) +#define I2C_STAT_DRMI BSP_BIT32(3) +#define I2C_STAT_DRSI BSP_BIT32(4) +#define I2C_STAT_ACTIVE BSP_BIT32(5) +#define I2C_STAT_SCL BSP_BIT32(6) +#define I2C_STAT_SDA BSP_BIT32(7) +#define I2C_STAT_RFF BSP_BIT32(8) +#define I2C_STAT_RFE BSP_BIT32(9) +#define I2C_STAT_TFF BSP_BIT32(10) +#define I2C_STAT_TFE BSP_BIT32(11) +#define I2C_STAT_TFFS BSP_BIT32(12) +#define I2C_STAT_TFES BSP_BIT32(13) + +/** @} */ + +/** + * @name I2C Control Register (I2Cn_CTRL) + * + * @{ + */ + +#define I2C_CTRL_TDIE BSP_BIT32(0) +#define I2C_CTRL_AFIE BSP_BIT32(1) +#define I2C_CTRL_NAIE BSP_BIT32(2) +#define I2C_CTRL_DRMIE BSP_BIT32(3) +#define I2C_CTRL_DRSIE BSP_BIT32(4) +#define I2C_CTRL_RFFIE BSP_BIT32(5) +#define I2C_CTRL_RFDAIE BSP_BIT32(6) +#define I2C_CTRL_TFFIO BSP_BIT32(7) +#define I2C_CTRL_RESET BSP_BIT32(8) +#define I2C_CTRL_SEVEN BSP_BIT32(9) +#define I2C_CTRL_TFFSIE BSP_BIT32(10) + +/** @} */ + +/** + * @brief Initializes the I2C module @a i2c. + * + * Valid @a clock_in_hz values are 100000 and 400000. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a i2c value. + * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. + */ +rtems_status_code lpc32xx_i2c_init( + volatile lpc32xx_i2c *i2c, + unsigned clock_in_hz +); + +/** + * @brief Resets the I2C module @a i2c. + */ +void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c); + +/** + * @brief Sets the I2C module @a i2c clock. + * + * Valid @a clock_in_hz values are 100000 and 400000. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. + */ +rtems_status_code lpc32xx_i2c_clock( + volatile lpc32xx_i2c *i2c, + unsigned clock_in_hz +); + +/** + * @brief Starts a write transaction on the I2C module @a i2c. + * + * The address parameter @a addr must not contain the read/write bit. + * + * The error status may be delayed to the next + * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_start( + volatile lpc32xx_i2c *i2c, + unsigned addr +); + +/** + * @brief Writes data via the I2C module @a i2c with optional stop. + * + * The error status may be delayed to the next + * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_with_optional_stop( + volatile lpc32xx_i2c *i2c, + const uint8_t *out, + size_t n, + bool stop +); + +/** + * @brief Starts a read transaction on the I2C module @a i2c. + * + * The address parameter @a addr must not contain the read/write bit. + * + * The error status may be delayed to the next + * lpc32xx_i2c_read_with_optional_stop() due to controller flaws. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_read_start( + volatile lpc32xx_i2c *i2c, + unsigned addr +); + +/** + * @brief Reads data via the I2C module @a i2c with optional stop. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. + */ +rtems_status_code lpc32xx_i2c_read_with_optional_stop( + volatile lpc32xx_i2c *i2c, + uint8_t *in, + size_t n, + bool stop +); + +/** + * @brief Writes and reads data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +rtems_status_code lpc32xx_i2c_write_and_read( + volatile lpc32xx_i2c *i2c, + unsigned addr, + const uint8_t *out, + size_t out_size, + uint8_t *in, + size_t in_size +); + +/** + * @brief Writes data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +static inline rtems_status_code lpc32xx_i2c_write( + volatile lpc32xx_i2c *i2c, + unsigned addr, + const uint8_t *out, + size_t out_size +) +{ + return lpc32xx_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); +} + +/** + * @brief Reads data via the I2C module @a i2c. + * + * This will be one bus transaction. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_IO_ERROR Received a NACK from the slave. + */ +static inline rtems_status_code lpc32xx_i2c_read( + volatile lpc32xx_i2c *i2c, + unsigned addr, + uint8_t *in, + size_t in_size +) +{ + return lpc32xx_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_I2C_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/irq.h b/bsps/arm/lpc32xx/include/bsp/irq.h new file mode 100644 index 0000000000..fbb13b5262 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/irq.h @@ -0,0 +1,179 @@ +/** + * @file + * + * @ingroup lpc32xx_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_IRQ_H +#define LIBBSP_ARM_LPC32XX_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_interrupt Interrupt Support + * + * @ingroup arm_lpc32xx + * + * @ingroup bsp_interrupt + * + * @{ + */ + +#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex)) + +#define LPC32XX_IRQ_MODULE_MIC 0U +#define LPC32XX_IRQ_MODULE_SIC_1 32U +#define LPC32XX_IRQ_MODULE_SIC_2 64U +#define LPC32XX_IRQ_MODULE_COUNT 3U + +/* MIC interrupts */ +#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0) +#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1) +#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3) +#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4) +#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5) +#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6) +#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7) +#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8) +#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9) +#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10) +#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11) +#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13) +#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14) +#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15) +#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16) +#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17) +#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18) +#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19) +#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20) +#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21) +#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22) +#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23) +#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24) +#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25) +#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26) +#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27) +#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28) +#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29) +#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30) +#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31) + +/* SIC 1 interrupts */ +#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1) +#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2) +#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4) +#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6) +#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7) +#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8) +#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12) +#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13) +#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14) +#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17) +#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18) +#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19) +#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20) +#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22) +#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23) +#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24) +#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25) +#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26) +#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27) +#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28) +#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29) +#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30) +#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31) + +/* SIC 2 interrupts */ +#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0) +#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1) +#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2) +#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3) +#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4) +#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5) +#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6) +#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7) +#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8) +#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9) +#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10) +#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11) +#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12) +#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15) +#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18) +#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19) +#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20) +#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22) +#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23) +#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24) +#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25) +#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26) +#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27) +#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28) +#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31) + +#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U +#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U +#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U) +#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN +#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ +#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK + +#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1) + +void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority); + +unsigned lpc32xx_irq_get_priority(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE, + LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE +} lpc32xx_irq_activation_polarity; + +void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity); + +lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_LEVEL_SENSITIVE, + LPC32XX_IRQ_EDGE_SENSITIVE +} lpc32xx_irq_activation_type; + +void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type); + +lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector); + +void lpc32xx_set_exception_handler(Arm_symbolic_exception_name exception, void (*handler)(void)); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h b/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h new file mode 100644 index 0000000000..2b676b433f --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc-clock-config.h @@ -0,0 +1,59 @@ +/** + * @file + * + * @ingroup lpc_clock + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_clock Clock Support + * + * @ingroup lpc + * + * @brief Clock support. + * + * @{ + */ + +#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0 + +#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0 + +#define LPC_CLOCK_TIMECOUNTER_BASE LPC32XX_BASE_TIMER_1 + +#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK + +#define LPC_CLOCK_MODULE_ENABLE() + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h b/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h new file mode 100644 index 0000000000..53e9e8415d --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc-ethernet-config.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup lpc_eth + * + * @brief Ethernet driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H +#define LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H + +#include +#include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_eth Ethernet Support + * + * @ingroup lpc + * + * @brief Ethernet support. + * + * @{ + */ + +#define LPC_ETH_CONFIG_INTERRUPT LPC32XX_IRQ_ETHERNET + +#define LPC_ETH_CONFIG_REG_BASE LPC32XX_BASE_ETHERNET + +#define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 +#define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX + +#define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 +#define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX + +#define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U + +#ifdef LPC32XX_ETHERNET_RMII + #define LPC_ETH_CONFIG_RMII + + static void lpc_eth_config_module_enable(void) + { + LPC32XX_MAC_CLK_CTRL = 0x1f; + } +#else + static void lpc_eth_config_module_enable(void) + { + LPC32XX_MAC_CLK_CTRL = 0x0f; + } +#endif + +static void lpc_eth_config_module_disable(void) +{ + LPC32XX_MAC_CLK_CTRL = 0; +} + +#define LPC_ETH_CONFIG_USE_TRANSMIT_DMA + +static char *lpc_eth_config_alloc_table_area(size_t size) +{ + return rtems_heap_allocate_aligned_with_boundary(size, 32, 0); +} + +static void lpc_eth_config_free_table_area(char *table_area) +{ + /* FIXME: Type */ + free(table_area, (int) 0xdeadbeef); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/lpc32xx.h b/bsps/arm/lpc32xx/include/bsp/lpc32xx.h new file mode 100644 index 0000000000..2edb1e334e --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/lpc32xx.h @@ -0,0 +1,641 @@ +/** + * @file + * + * @ingroup lpc32xx_reg + * + * @brief Register base addresses. + */ + +/* + * Copyright (c) 2009, 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http: + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H +#define LIBBSP_ARM_LPC32XX_LPC32XX_H + +#include + +#include +#include +#include +#include +#include + +/** + * @defgroup lpc32xx_reg Register Definitions + * + * @ingroup arm_lpc32xx + * + * @brief Register definitions. + * + * @{ + */ + +/** + * @name Register Base Addresses + * + * @{ + */ + +#define LPC32XX_BASE_ADC 0x40048000 +#define LPC32XX_BASE_SYSCON 0x40004000 +#define LPC32XX_BASE_DEBUG_CTRL 0x40040000 +#define LPC32XX_BASE_DMA 0x31000000 +#define LPC32XX_BASE_EMC 0x31080000 +#define LPC32XX_BASE_EMC_CS_0 0xe0000000 +#define LPC32XX_BASE_EMC_CS_1 0xe1000000 +#define LPC32XX_BASE_EMC_CS_2 0xe2000000 +#define LPC32XX_BASE_EMC_CS_3 0xe3000000 +#define LPC32XX_BASE_EMC_DYCS_0 0x80000000 +#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000 +#define LPC32XX_BASE_ETB_CFG 0x310c0000 +#define LPC32XX_BASE_ETB_DATA 0x310e0000 +#define LPC32XX_BASE_ETHERNET 0x31060000 +#define LPC32XX_BASE_GPIO 0x40028000 +#define LPC32XX_BASE_I2C_1 0x400a0000 +#define LPC32XX_BASE_I2C_2 0x400a8000 +#define LPC32XX_BASE_I2S_0 0x20094000 +#define LPC32XX_BASE_I2S_1 0x2009c000 +#define LPC32XX_BASE_IRAM 0x08000000 +#define LPC32XX_BASE_IROM 0x0c000000 +#define LPC32XX_BASE_KEYSCAN 0x40050000 +#define LPC32XX_BASE_LCD 0x31040000 +#define LPC32XX_BASE_MCPWM 0x400e8000 +#define LPC32XX_BASE_MIC 0x40008000 +#define LPC32XX_BASE_NAND_MLC 0x200a8000 +#define LPC32XX_BASE_NAND_SLC 0x20020000 +#define LPC32XX_BASE_PWM_1 0x4005c000 +#define LPC32XX_BASE_PWM_2 0x4005c004 +#define LPC32XX_BASE_PWM_3 0x4002c000 +#define LPC32XX_BASE_PWM_4 0x40030000 +#define LPC32XX_BASE_RTC 0x40024000 +#define LPC32XX_BASE_RTC_RAM 0x40024080 +#define LPC32XX_BASE_SDCARD 0x20098000 +#define LPC32XX_BASE_SIC_1 0x4000c000 +#define LPC32XX_BASE_SIC_2 0x40010000 +#define LPC32XX_BASE_SPI_1 0x20088000 +#define LPC32XX_BASE_SPI_2 0x20090000 +#define LPC32XX_BASE_SSP_0 0x20084000 +#define LPC32XX_BASE_SSP_1 0x2008c000 +#define LPC32XX_BASE_TIMER_0 0x40044000 +#define LPC32XX_BASE_TIMER_1 0x4004c000 +#define LPC32XX_BASE_TIMER_2 0x40058000 +#define LPC32XX_BASE_TIMER_3 0x40060000 +#define LPC32XX_BASE_TIMER_5 0x4002c000 +#define LPC32XX_BASE_TIMER_6 0x40030000 +#define LPC32XX_BASE_TIMER_HS 0x40038000 +#define LPC32XX_BASE_TIMER_MS 0x40034000 +#define LPC32XX_BASE_UART_1 0x40014000 +#define LPC32XX_BASE_UART_2 0x40018000 +#define LPC32XX_BASE_UART_3 0x40080000 +#define LPC32XX_BASE_UART_4 0x40088000 +#define LPC32XX_BASE_UART_5 0x40090000 +#define LPC32XX_BASE_UART_6 0x40098000 +#define LPC32XX_BASE_UART_7 0x4001c000 +#define LPC32XX_BASE_USB 0x31020000 +#define LPC32XX_BASE_USB_OTG_I2C 0x31020300 +#define LPC32XX_BASE_WDT 0x4003c000 + +/** @} */ + +/** + * @name Miscanellanous Registers + * + * @{ + */ + +#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0) +#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4) +#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8) +#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc) +#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0) +#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000) +#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004) +#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008) +#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8) +#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090) +#define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c) +#define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4) +#define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8) +#define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110) +#define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300) +#define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300) +#define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304) +#define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308) +#define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c) +#define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310) +#define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044) +#define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c) +#define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050) +#define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048) +#define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058) +#define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040) +#define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4) +#define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec) +#define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030) +#define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020) +#define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018) +#define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038) +#define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028) +#define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034) +#define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024) +#define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c) +#define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c) +#define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064) +#define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c) +#define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080) +#define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8) +#define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8) +#define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090) +#define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054) +#define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c) +#define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078) +#define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4) +#define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac) +#define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0) +#define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc) +#define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4) +#define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060) +#define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0) +#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8) +#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4) +#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110) +#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114) +#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068) + +/** @} */ + +/** + * @name Power Control Register (PWR_CTRL) + * + * @{ + */ + +#define PWR_STOP BSP_BIT32(0) +#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1) +#define PWR_NORMAL_RUN_MODE BSP_BIT32(2) +#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3) +#define PWR_SYSCLKEN_HIGH BSP_BIT32(4) +#define PWR_HIGHCORE_HIGH BSP_BIT32(5) +#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7) +#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8) +#define PWR_EMCSREFREQ BSP_BIT32(9) +#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10) + +/** @} */ + +/** + * @name HCLK PLL Control Register (HCLKPLL_CTRL) + * + * @{ + */ + +#define HCLK_PLL_LOCK BSP_BIT32(0) +#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8) +#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8) +#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10) +#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12) +#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13) +#define HCLK_PLL_DIRECT BSP_BIT32(14) +#define HCLK_PLL_BYPASS BSP_BIT32(15) +#define HCLK_PLL_POWER BSP_BIT32(16) + +/** @} */ + +/** + * @name HCLK Divider Control Register (HCLKDIV_CTRL) + * + * @{ + */ + +#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1) +#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6) +#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6) +#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8) +#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8) + +/** @} */ + +/** + * @name Timer Clock Control Register (TIMCLK_CTRL) + * + * @{ + */ + +#define TIMCLK_CTRL_WDT BSP_BIT32(0) +#define TIMCLK_CTRL_HST BSP_BIT32(1) + +/** @} */ + +#define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)] +#define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a] + +typedef struct { +} lpc32xx_nand_slc; + +typedef struct { +} lpc32xx_ssp; + +typedef struct { +} lpc32xx_spi; + +typedef struct { +} lpc32xx_sd_card; + +typedef struct { +} lpc32xx_usb; + +typedef struct { +} lpc32xx_lcd; + +typedef struct { +} lpc32xx_etb; + +typedef struct { +} lpc32xx_syscon; + +typedef struct { +} lpc32xx_uart_ctrl; + +typedef struct { +} lpc32xx_uart; + +typedef struct { +} lpc32xx_ms_timer; + +typedef struct { +} lpc32xx_hs_timer; + +/** + * @name Watchdog Timer Interrupt Status Register (WDTIM_INT) + * + * @{ + */ + +#define WDTTIM_INT_MATCH_INT BSP_BIT32(0) + +/** @} */ + +/** + * @name Watchdog Timer Control Register (WDTIM_CTRL) + * + * @{ + */ + +#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0) +#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1) +#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2) + +/** @} */ + +/** + * @name Watchdog Timer Match Control Register (WDTIM_MCTRL) + * + * @{ + */ + +#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0) +#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1) +#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2) +#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3) +#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4) +#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5) +#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6) + +/** @} */ + +/** + * @name Watchdog Timer External Match Control Register (WDTIM_EMR) + * + * @{ + */ + +#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0) +#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5) +#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) + +/** @} */ + +/** + * @name Watchdog Timer Reset Source Register (WDTIM_RES) + * + * @{ + */ + +#define WDTTIM_RES_WDT BSP_BIT32(0) + +/** @} */ + +typedef struct { + uint32_t intr; + uint32_t ctrl; + uint32_t counter; + uint32_t mctrl; + uint32_t match0; + uint32_t emr; + uint32_t pulse; + uint32_t res; +} lpc32xx_wdt; + +typedef struct { +} lpc32xx_debug; + +typedef struct { +} lpc32xx_adc; + +typedef struct { +} lpc32xx_keyscan; + +typedef struct { +} lpc32xx_pwm; + +typedef struct { +} lpc32xx_mcpwm; + +typedef struct { + uint32_t mac1; + uint32_t mac2; + uint32_t ipgt; + uint32_t ipgr; + uint32_t clrt; + uint32_t maxf; + uint32_t supp; + uint32_t test; + uint32_t mcfg; + uint32_t mcmd; + uint32_t madr; + uint32_t mwtd; + uint32_t mrdd; + uint32_t mind; + uint32_t reserved_0 [2]; + uint32_t sa0; + uint32_t sa1; + uint32_t sa2; + uint32_t reserved_1 [45]; + uint32_t command; + uint32_t status; + uint32_t rxdescriptor; + uint32_t rxstatus; + uint32_t rxdescriptornum; + uint32_t rxproduceindex; + uint32_t rxconsumeindex; + uint32_t txdescriptor; + uint32_t txstatus; + uint32_t txdescriptornum; + uint32_t txproduceindex; + uint32_t txconsumeindex; + uint32_t reserved_2 [10]; + uint32_t tsv0; + uint32_t tsv1; + uint32_t rsv; + uint32_t reserved_3 [3]; + uint32_t flowcontrolcnt; + uint32_t flowcontrolsts; + uint32_t reserved_4 [34]; + uint32_t rxfilterctrl; + uint32_t rxfilterwolsts; + uint32_t rxfilterwolclr; + uint32_t reserved_5 [1]; + uint32_t hashfilterl; + uint32_t hashfilterh; + uint32_t reserved_6 [882]; + uint32_t intstatus; + uint32_t intenable; + uint32_t intclear; + uint32_t intset; + uint32_t reserved_7 [1]; + uint32_t powerdown; +} lpc32xx_eth; + +typedef struct { + uint32_t er; + uint32_t rsr; + uint32_t sr; + uint32_t apr; + uint32_t atr; + uint32_t itr; +} lpc32xx_irq; + +typedef struct { + uint32_t p3_inp_state; + uint32_t p3_outp_set; + uint32_t p3_outp_clr; + uint32_t p3_outp_state; + uint32_t p2_dir_set; + uint32_t p2_dir_clr; + uint32_t p2_dir_state; + uint32_t p2_inp_state; + uint32_t p2_outp_set; + uint32_t p2_outp_clr; + uint32_t p2_mux_set; + uint32_t p2_mux_clr; + uint32_t p2_mux_state; + LPC32XX_RESERVE(0x034, 0x040); + uint32_t p0_inp_state; + uint32_t p0_outp_set; + uint32_t p0_outp_clr; + uint32_t p0_outp_state; + uint32_t p0_dir_set; + uint32_t p0_dir_clr; + uint32_t p0_dir_state; + LPC32XX_RESERVE(0x05c, 0x060); + uint32_t p1_inp_state; + uint32_t p1_outp_set; + uint32_t p1_outp_clr; + uint32_t p1_outp_state; + uint32_t p1_dir_set; + uint32_t p1_dir_clr; + uint32_t p1_dir_state; + LPC32XX_RESERVE(0x07c, 0x110); + uint32_t p3_mux_set; + uint32_t p3_mux_clr; + uint32_t p3_mux_state; + LPC32XX_RESERVE(0x11c, 0x120); + uint32_t p0_mux_set; + uint32_t p0_mux_clr; + uint32_t p0_mux_state; + LPC32XX_RESERVE(0x12c, 0x130); + uint32_t p1_mux_set; + uint32_t p1_mux_clr; + uint32_t p1_mux_state; +} lpc32xx_gpio; + +typedef struct { + uint32_t rx_or_tx; + uint32_t stat; + uint32_t ctrl; + uint32_t clk_hi; + uint32_t clk_lo; + uint32_t adr; + uint32_t rxfl; + uint32_t txfl; + uint32_t rxb; + uint32_t txb; + uint32_t s_tx; + uint32_t s_txfl; +} lpc32xx_i2c; + +typedef struct { + uint32_t ucount; + uint32_t dcount; + uint32_t match0; + uint32_t match1; + uint32_t ctrl; + uint32_t intstat; + uint32_t key; + uint32_t sram [32]; +} lpc32xx_rtc; + +typedef struct { + uint32_t control; + uint32_t status; + uint32_t timeout; + uint32_t reserved_0 [5]; +} lpc32xx_emc_ahb; + +typedef struct { + union { + uint32_t w32; + uint16_t w16; + uint8_t w8; + } buff; + uint32_t reserved_0 [8191]; + union { + uint32_t w32; + uint16_t w16; + uint8_t w8; + } data; + uint32_t reserved_1 [8191]; + uint32_t cmd; + uint32_t addr; + uint32_t ecc_enc; + uint32_t ecc_dec; + uint32_t ecc_auto_enc; + uint32_t ecc_auto_dec; + uint32_t rpr; + uint32_t wpr; + uint32_t rubp; + uint32_t robp; + uint32_t sw_wp_add_low; + uint32_t sw_wp_add_hig; + uint32_t icr; + uint32_t time; + uint32_t irq_mr; + uint32_t irq_sr; + uint32_t reserved_2; + uint32_t lock_pr; + uint32_t isr; + uint32_t ceh; +} lpc32xx_nand_mlc; + +typedef struct { + lpc32xx_nand_slc nand_slc; + LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc); + lpc32xx_ssp ssp_0; + LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp); + lpc32xx_spi spi_1; + LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi); + lpc32xx_ssp ssp_1; + LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp); + lpc32xx_spi spi_2; + LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi); + lpc_i2s i2s_0; + LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s); + lpc32xx_sd_card sd_card; + LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card); + lpc_i2s i2s_1; + LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s); + lpc32xx_nand_mlc nand_mlc; + LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc); + lpc_dma dma; + LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma); + lpc32xx_usb usb; + LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb); + lpc32xx_lcd lcd; + LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd); + lpc32xx_eth eth; + LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth); + lpc_emc emc; + LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc); + lpc32xx_emc_ahb emc_ahb [5]; + LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]); + lpc32xx_etb etb; + LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb); + lpc32xx_syscon syscon; + LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon); + lpc32xx_irq mic; + LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq); + lpc32xx_irq sic_1; + LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq); + lpc32xx_irq sic_2; + LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq); + lpc32xx_uart uart_1; + LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart); + lpc32xx_uart uart_2; + LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart); + lpc32xx_uart uart_7; + LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart); + lpc32xx_rtc rtc; + LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc); + lpc32xx_gpio gpio; + LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio); + lpc_timer timer_4; + LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer); + lpc_timer timer_5; + LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer); + lpc32xx_ms_timer ms_timer; + LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer); + lpc32xx_hs_timer hs_timer; + LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer); + lpc32xx_wdt wdt; + LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt); + lpc32xx_debug debug; + LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug); + lpc_timer timer_0; + LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer); + lpc32xx_adc adc; + LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc); + lpc_timer timer_1; + LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer); + lpc32xx_keyscan keyscan; + LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan); + lpc32xx_uart_ctrl uart_ctrl; + LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl); + lpc_timer timer_2; + LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer); + lpc32xx_pwm pwm_1_and_pwm_2; + LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm); + lpc_timer timer3; + LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer); + lpc32xx_uart uart_3; + LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart); + lpc32xx_uart uart_4; + LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart); + lpc32xx_uart uart_5; + LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart); + lpc32xx_uart uart_6; + LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart); + lpc32xx_i2c i2c_1; + LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c); + lpc32xx_i2c i2c_2; + LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c); + lpc32xx_mcpwm mcpwm; +} lpc32xx_registers; + +extern volatile lpc32xx_registers lpc32xx; + +/** @} */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/mmu.h b/bsps/arm/lpc32xx/include/bsp/mmu.h new file mode 100644 index 0000000000..32352b5ed9 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/mmu.h @@ -0,0 +1,79 @@ +/** + * @file + * + * @ingroup lpc32xx_mmu + * + * @brief MMU support API. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_MMU_H +#define LIBBSP_ARM_LPC32XX_MMU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_mmu MMU Support + * + * @ingroup arm_lpc32xx + * + * @brief MMU support. + * + * @{ + */ + +#define LPC32XX_MMU_CLIENT_DOMAIN 15U + +#define LPC32XX_MMU_READ_ONLY \ + ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_DEFAULT) + +#define LPC32XX_MMU_READ_ONLY_CACHED \ + (LPC32XX_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +#define LPC32XX_MMU_READ_WRITE \ + ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_AP_0 \ + | ARM_MMU_SECT_DEFAULT) + +#define LPC32XX_MMU_READ_WRITE_CACHED \ + (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +/** + * @brief Sets the @a section_flags for the address range [@a begin, @a end). + * + * @return Previous section flags of the first modified entry. + */ +static inline uint32_t lpc32xx_set_translation_table_entries( + const void *begin, + const void *end, + uint32_t section_flags +) +{ + return arm_cp15_set_translation_table_entries(begin, end, section_flags); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_MMU_H */ diff --git a/bsps/arm/lpc32xx/include/bsp/nand-mlc.h b/bsps/arm/lpc32xx/include/bsp/nand-mlc.h new file mode 100644 index 0000000000..2aa8312945 --- /dev/null +++ b/bsps/arm/lpc32xx/include/bsp/nand-mlc.h @@ -0,0 +1,422 @@ +/** + * @file + * + * @ingroup lpc32xx_nand_mlc + * + * @brief NAND MLC controller API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * Copyright (c) 2011 Stephan Hoffmann + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_NAND_MLC_H +#define LIBBSP_ARM_LPC32XX_NAND_MLC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc32xx_nand_mlc NAND MLC Controller + * + * @ingroup arm_lpc32xx + * + * @brief NAND MLC Controller. + * + * Timing constraints: + * + * -# (WR_LOW + 1) / HCLK >= tWP + * -# (WR_HIGH - WR_LOW) / HCLK >= tWH + * -# (WR_LOW + 1) / HCLK + (WR_HIGH - WR_LOW) / HCLK >= tWC + * -# (RD_LOW + 1) / HCLK >= tRP + * -# (RD_LOW + 1) / HCLK >= tREA + tSU + * -# (RD_HIGH - RD_LOW) / HCLK >= tREH + * -# (RD_LOW + 1) / HCLK + (RD_HIGH - RD_LOW) / HCLK >= tRC + * -# (RD_HIGH - RD_LOW) / HCLK + NAND_TA / HCLK >= tRHZ + * -# BUSY_DELAY / HCLK >= max(tWB, tRB) + * -# TCEA_DELAY / HCLK >= tCEA - tREA + * + * Known flash layouts (Format: SP = small pages, LP = large pages / address + * cycles / pages per block): + * + * -# SP/3/32 + * -# SP/4/32 + * -# LP/4/64 + * -# LP/5/64 + * -# LP/5/128 + * + * @{ + */ + +/** + * @name MLC NAND Flash Dimensions + * + * @{ + */ + +#define MLC_SMALL_PAGE_SIZE 528 +#define MLC_SMALL_DATA_SIZE 512 +#define MLC_SMALL_SPARE_SIZE 16 +#define MLC_SMALL_USER_SPARE_SIZE 6 +#define MLC_SMALL_ECC_SPARE_SIZE 10 +#define MLC_SMALL_DATA_WORD_COUNT (MLC_SMALL_DATA_SIZE / 4) +#define MLC_SMALL_SPARE_WORD_COUNT (MLC_SMALL_SPARE_SIZE / 4) +#define MLC_SMALL_PAGES_PER_LARGE_PAGE 4 +#define MLC_LARGE_PAGE_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_PAGE_SIZE) +#define MLC_LARGE_DATA_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_DATA_SIZE) +#define MLC_LARGE_SPARE_SIZE \ + (MLC_SMALL_PAGES_PER_LARGE_PAGE * MLC_SMALL_SPARE_SIZE) +#define MLC_LARGE_DATA_WORD_COUNT (MLC_LARGE_DATA_SIZE / 4) +#define MLC_LARGE_SPARE_WORD_COUNT (MLC_LARGE_SPARE_SIZE / 4) + +/** @} */ + +/** + * @name NAND Flash Clock Control Register (FLASHCLK_CTRL) + * + * @{ + */ + +#define FLASHCLK_IRQ_MLC BSP_BIT32(5) +#define FLASHCLK_MLC_DMA_RNB BSP_BIT32(4) +#define FLASHCLK_MLC_DMA_INT BSP_BIT32(3) +#define FLASHCLK_SELECT_SLC BSP_BIT32(2) +#define FLASHCLK_MLC_CLK_ENABLE BSP_BIT32(1) +#define FLASHCLK_SLC_CLK_ENABLE BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Timing Register (MLC_TIME_REG) + * + * @{ + */ + +#define MLC_TIME_WR_LOW(val) BSP_FLD32(val, 0, 3) +#define MLC_TIME_WR_HIGH(val) BSP_FLD32(val, 4, 7) +#define MLC_TIME_RD_LOW(val) BSP_FLD32(val, 8, 11) +#define MLC_TIME_RD_HIGH(val) BSP_FLD32(val, 12, 15) +#define MLC_TIME_NAND_TA(val) BSP_FLD32(val, 16, 18) +#define MLC_TIME_BUSY_DELAY(val) BSP_FLD32(val, 19, 23) +#define MLC_TIME_TCEA_DELAY(val) BSP_FLD32(val, 24, 25) + +/** @} */ + +/** + * @name MLC NAND Lock Protection Register (MLC_LOCK_PR) + * + * @{ + */ + +#define MLC_UNLOCK_PROT 0xa25e + +/** @} */ + +/** + * @name MLC NAND Status Register (MLC_ISR) + * + * @{ + */ + +#define MLC_ISR_DECODER_FAILURE BSP_BIT32(6) +#define MLC_ISR_SYMBOL_ERRORS(reg) BSP_FLD32GET(reg, 4, 5) +#define MLC_ISR_ERRORS_DETECTED BSP_BIT32(3) +#define MLC_ISR_ECC_READY BSP_BIT32(2) +#define MLC_ISR_CONTROLLER_READY BSP_BIT32(1) +#define MLC_ISR_NAND_READY BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Controller Configuration Register (MLC_ICR) + * + * @{ + */ + +#define MLC_ICR_SOFT_WRITE_PROT BSP_BIT32(3) +#define MLC_ICR_LARGE_PAGES BSP_BIT32(2) +#define MLC_ICR_ADDR_WORD_COUNT_4_5 BSP_BIT32(1) +#define MLC_ICR_IO_BUS_16 BSP_BIT32(0) + +/** @} */ + +/** + * @name MLC NAND Auto Encode Register (MLC_ECC_AUTO_ENC) + * + * @{ + */ + +#define MLC_ECC_AUTO_ENC_PROGRAM BSP_BIT32(8) + +/** @} */ + +/** + * @name NAND Status Register + * + * @{ + */ + +#define NAND_STATUS_ERROR (1U << 0) +#define NAND_STATUS_READY (1U << 6) +#define NAND_STATUS_NOT_PROTECTED (1U << 7) + +/** @} */ + +/** + * @brief MLC NAND controller configuration. + */ +typedef struct { + uint32_t flags; + + uint32_t block_count; + + /** + * @brief Value for the MLC NAND Timing Register (MLC_TIME_REG). + */ + uint32_t time; +} lpc32xx_mlc_config; + +/** + * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data) + * or large pages (2048 Bytes user data and 64 Bytes spare data) if not set. + */ +#define MLC_SMALL_PAGES 0x1U + +/** + * @Brief Selects 4/5 address cycles for small/large pages or 3/4 address + * cycles if not set. + */ +#define MLC_MANY_ADDRESS_CYCLES 0x2U + +/** + * @brief Selects 64 pages per block or 128 pages per block if not set. + * + * This flag is only valid for large pages. + */ +#define MLC_NORMAL_BLOCKS 0x4U + +/** + * @brief Selects 16-bit IO width or 8-bit IO width if not set. + */ +#define MLC_IO_WIDTH_16_BIT 0x8U + +/** + * @brief Initializes the MLC NAND controller according to @a cfg. + */ +void lpc32xx_mlc_init(const lpc32xx_mlc_config *cfg); + +uint32_t lpc32xx_mlc_page_size(void); + +uint32_t lpc32xx_mlc_pages_per_block(void); + +uint32_t lpc32xx_mlc_block_count(void); + +uint32_t lpc32xx_mlc_io_width(void); + +void lpc32xx_mlc_write_protection( + uint32_t page_index_low, + uint32_t page_index_high +); + +void lpc32xx_mlc_read_id(uint8_t *id, size_t n); + +/** + * @brief Reads the page with index @a page_index. + * + * Bytes 6 to 15 of the spare area will contain the ECC. + * + * If the read is successful, then the @a symbol_error_count will contain the + * number of detected symbol errors (0, 1, 2, 3, or 4), else the value will be + * 0xffffffff. The @a symbol_error_count pointer may be @c NULL. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a page_index value. + * @retval RTEMS_IO_ERROR Uncorrectable bit error. + */ +rtems_status_code lpc32xx_mlc_read_page( + uint32_t page_index, + void *data, + void *spare, + uint32_t *symbol_error_count +); + +/** + * @brief Checks if the block with index @a block_index is valid. + * + * The initial valid block information of the manufacturer will be used. + * Unfortunately there seems to be no standard for this. A block will be + * considered as bad if the first or second page of this block does not contain + * 0xff at the 6th byte of the spare area. This should work for flashes with + * small pages and a 8-bit IO width. + * + * @retval RTEMS_SUCCESSFUL The block is valid. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_IO_ERROR Uncorrectable bit error. + * @retval RTEMS_INCORRECT_STATE The block is bad. + * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash + * type. + */ +rtems_status_code lpc32xx_mlc_is_valid_block(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_UNSATISFIED Erase error. + */ +rtems_status_code lpc32xx_mlc_erase_block(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * In case of an erase error all pages and the spare areas of this block are + * programmed with zero values. This will hopefully mark the block as bad. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INCORRECT_STATE The block is bad. + * @retval RTEMS_INVALID_ID Invalid @a block_index value. + * @retval RTEMS_UNSATISFIED Erase error. + * @retval RTEMS_NOT_IMPLEMENTED No implementation available for this flash + * type. + */ +rtems_status_code lpc32xx_mlc_erase_block_safe(uint32_t block_index); + +/** + * @brief Erases the block with index @a block_index. + * + * Variant of lpc32xx_mlc_erase_block_safe() with more parameters for + * efficiency reasons. The @a page_begin must be the index of the first page + * of the block. The @a page_end must be the page index of the last page of + * the block plus one. + */ +rtems_status_code lpc32xx_mlc_erase_block_safe_3( + uint32_t block_index, + uint32_t page_begin, + uint32_t page_end +); + +/** + * @brief Writes zero values to the pages specified by @a page_begin and + * @a page_end. + * + * The data and spare area are cleared to zero. This marks the pages as bad. + */ +void lpc32xx_mlc_zero_pages(uint32_t page_begin, uint32_t page_end); + +/** + * @brief Writes the page with index @a page_index. + * + * Only the bytes 0 to 5 of the spare area can be used for user data, the bytes + * 6 to 15 will be used for the automatically generated ECC. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a page_index value. + * @retval RTEMS_IO_ERROR Write error. + */ +rtems_status_code lpc32xx_mlc_write_page_with_ecc( + uint32_t page_index, + const void *data, + const void *spare +); + +/** + * @brief Writes @a src_size Bytes from @a src to the flash area specified by + * @a block_begin and @a block_end. + * + * The @a page_buffer will be used as an intermediate buffer. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid @a block_begin or @a block_end value. + * @retval RTEMS_IO_ERROR Too many bad blocks or source area too big. + */ +rtems_status_code lpc32xx_mlc_write_blocks( + uint32_t block_begin, + uint32_t block_end, + const void *src, + size_t src_size, + uint32_t page_buffer [MLC_LARGE_DATA_WORD_COUNT] +); + +/** + * @brief Read blocks process function type. + * + * @see lpc32xx_mlc_read_blocks(). + * + * @retval false Continue processing. + * @retval true Stop processing. + */ +typedef bool (*lpc32xx_mlc_read_process)( + void *process_arg, + uint32_t page_index, + uint32_t page_size, + uint32_t page_data [MLC_LARGE_DATA_WORD_COUNT], + uint32_t page_spare [MLC_LARGE_SPARE_WORD_COUNT] +); + +/** + * @brief Reads the pages of block @a block_begin up to and excluding + * @a block_end. + * + * For each page @a process will be called with the @a process_arg parameter, + * the page_index, the page data and the page spare. + * + * The @a page_buffer_0 and @a page_buffer_1 will be used as + * intermediate buffers. + */ +rtems_status_code lpc32xx_mlc_read_blocks( + uint32_t block_begin, + uint32_t block_end, + lpc32xx_mlc_read_process process, + void *process_arg, + uint32_t page_buffer_0 [MLC_LARGE_DATA_WORD_COUNT], + uint32_t page_buffer_1 [MLC_LARGE_DATA_WORD_COUNT] +); + +/** + * @brief Checks if the page spare area indicates to a bad page. + * + * If the first (byte offset 0) or sixth (byte offset 5) byte of the spare area + * has a value other than 0xff, then it returns @a true (the page is bad), else + * it returns @a false (the page is not bad). + * + * Samsung uses the sixth byte to indicate a bad page. Mircon uses the first + * and sixth byte to indicate a bad page. + * + * This functions works only for small page flashes. + */ +static inline bool lpc32xx_mlc_is_bad_page(const uint32_t *spare) +{ + uint32_t first_byte_mask = 0x000000ff; + uint32_t sixth_byte_mask = 0x0000ff00; + + return (spare [0] & first_byte_mask) != first_byte_mask + || (spare [1] & sixth_byte_mask) != sixth_byte_mask; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_NAND_MLC_H */ diff --git a/bsps/arm/lpc32xx/include/tm27.h b/bsps/arm/lpc32xx/include/tm27.h new file mode 100644 index 0000000000..4cbc17a085 --- /dev/null +++ b/bsps/arm/lpc32xx/include/tm27.h @@ -0,0 +1,72 @@ +/* @file + * + * @ingroup arm_lpc32xx + * + * @brief Implementations of interrupt mechanisms for Time Test 27 + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#include + +#include +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +static void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + LPC32XX_SW_INT = 0; + + sc = rtems_interrupt_handler_install( + LPC32XX_IRQ_SW, + "SW", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static void Cause_tm27_intr(void) +{ + LPC32XX_SW_INT = 0x1; +} + +static void Clear_tm27_intr(void) +{ + LPC32XX_SW_INT = 0; + lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_LOWEST); +} + +static void Lower_tm27_intr(void) +{ + bsp_interrupt_vector_enable(LPC32XX_IRQ_SW); + lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_HIGHEST); +} + +#endif /* __tm27_h */ diff --git a/bsps/arm/raspberrypi/headers.am b/bsps/arm/raspberrypi/headers.am new file mode 100644 index 0000000000..91cd18c86f --- /dev/null +++ b/bsps/arm/raspberrypi/headers.am @@ -0,0 +1,20 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/fbcons.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/mailbox.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/raspberrypi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/rpi-fb.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/rpi-gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/spi.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/usart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/raspberrypi/include/bsp/vc.h diff --git a/bsps/arm/raspberrypi/include/bsp.h b/bsps/arm/raspberrypi/include/bsp.h new file mode 100644 index 0000000000..ecd5b6af08 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp.h @@ -0,0 +1,69 @@ +/** + * @file + * + * @ingroup arm_raspberrypi + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2015 Yang Qiao + * Copyright (c) 2013 Alan Cudmore + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_BSP_H +#define LIBBSP_ARM_RASPBERRYPI_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define RPI_L2_CACHE_ENABLE 1 + +#define BSP_GPIO_PIN_COUNT 32 +#define BSP_GPIO_PINS_PER_BANK 32 +#define BSP_GPIO_PINS_PER_SELECT_BANK 10 + +#define BSP_CONSOLE_UART0 0 +#define BSP_CONSOLE_FB 1 + +void rpi_init_cmdline(void); +const char *rpi_cmdline_get_cached(void); +const char *rpi_cmdline_get_raw(void); +const char *rpi_cmdline_get_arg(const char* arg); + +void rpi_video_init(void); +void rpi_fb_outch (char); +int rpi_video_is_initialized(void); + +void rpi_ipi_initialize(void); +void rpi_start_rtems_on_secondary_processor(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_BSP_H */ + +/** + * @defgroup arm_raspberrypi Raspberry Pi Support + * + * @ingroup bsp_arm + * + * @brief Raspberry Pi support package + * + */ diff --git a/bsps/arm/raspberrypi/include/bsp/fbcons.h b/bsps/arm/raspberrypi/include/bsp/fbcons.h new file mode 100644 index 0000000000..d0e126699a --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/fbcons.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup raspberrypi_console + * + * @brief framebuffer graphic console support. + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef _FBCONS_H_ +#define _FBCONS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This is the ASCII for "PI" in the upper word and 2835 + * in the lower which should be unique enough to + * distinguish this type of serial device from others. + */ + +#define FB_CONSOLE 0x50492835 + +bool fbcons_probe( int minor ); + +/* + * Driver function table + */ +extern const console_fns fbcons_fns; + +#ifdef __cplusplus +} +#endif + +#endif /* _FBCONS_H_ */ diff --git a/bsps/arm/raspberrypi/include/bsp/i2c.h b/bsps/arm/raspberrypi/include/bsp/i2c.h new file mode 100644 index 0000000000..4a8dbbf2ac --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/i2c.h @@ -0,0 +1,95 @@ +/** + * @file i2c.h + * + * @ingroup raspberrypi_i2c + * + * @brief Raspberry Pi specific I2C definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_I2C_H +#define LIBBSP_ARM_RASPBERRYPI_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @name I2C constants. + * + * @{ + */ + +/** + * @brief BSC controller core clock rate in Hz. + * + * This is set to 150 MHz as per the BCM2835 datasheet. + */ +#define BSC_CORE_CLK_HZ 150000000 + +/** + * @brief Default bus clock. + * + * This sets the bus with a 100 kHz clock speed. + */ +#define DEFAULT_BUS_CLOCK 100000 + +/** @} */ + +/** + * @name I2C directives. + * + * @{ + */ + +/** + * @brief Setups the Raspberry Pi GPIO header to activate the BSC I2C bus. + */ +extern void rpi_i2c_init(void); + +/** + * @brief Registers the Raspberry Pi BSC I2C bus with the + * Linux I2C User-Space API. + * + * @param[in] bus_path Path to the bus device file. + * @param[in] bus_clock Bus clock in Hz. + * + * @retval 0 Bus registered successfully. + * @retval <0 Could not register the bus. The return value is a negative + * errno code. + */ +extern int rpi_i2c_register_bus( + const char *bus_path, + uint32_t bus_clock +); + +/** + * @brief Setups the Raspberry Pi BSC I2C bus (located on the GPIO header) + * on the "/dev/i2c" device file, using the default bus clock. + * + * @retval 0 Bus configured and registered successfully. + * @retval <0 See @see rpi_i2c_register_bus(). + */ +static inline int rpi_setup_i2c_bus(void) +{ + rpi_i2c_init(); + + return rpi_i2c_register_bus("/dev/i2c", DEFAULT_BUS_CLOCK); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_I2C_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/irq.h b/bsps/arm/raspberrypi/include/bsp/irq.h new file mode 100644 index 0000000000..4600534171 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/irq.h @@ -0,0 +1,76 @@ +/** + * @file + * + * @ingroup raspberrypi_interrupt + * + * @brief Interrupt definitions. + */ + +/** + * Copyright (c) 2013 Alan Cudmore + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASBPERRYPI_IRQ_H +#define LIBBSP_ARM_RASPBERRYPI_IRQ_H + +#ifndef ASM + +#include +#include +#include + +/** + * @defgroup raspberrypi_interrupt Interrrupt Support + * + * @ingroup arm_raspberrypi + * + * @brief Interrupt support. + */ + +#define BCM2835_INTC_TOTAL_IRQ 64 + 8 + + +#define BCM2835_IRQ_ID_GPU_TIMER_M0 0 +#define BCM2835_IRQ_ID_GPU_TIMER_M1 1 +#define BCM2835_IRQ_ID_GPU_TIMER_M2 2 +#define BCM2835_IRQ_ID_GPU_TIMER_M3 3 + +#define BCM2835_IRQ_ID_USB 9 +#define BCM2835_IRQ_ID_AUX 29 +#define BCM2835_IRQ_ID_SPI_SLAVE 43 +#define BCM2835_IRQ_ID_PWA0 45 +#define BCM2835_IRQ_ID_PWA1 46 +#define BCM2835_IRQ_ID_SMI 48 +#define BCM2835_IRQ_ID_GPIO_0 49 +#define BCM2835_IRQ_ID_GPIO_1 50 +#define BCM2835_IRQ_ID_GPIO_2 51 +#define BCM2835_IRQ_ID_GPIO_3 52 +#define BCM2835_IRQ_ID_I2C 53 +#define BCM2835_IRQ_ID_SPI 54 +#define BCM2835_IRQ_ID_PCM 55 +#define BCM2835_IRQ_ID_UART 57 +#define BCM2835_IRQ_ID_SD 62 + +#define BCM2835_IRQ_ID_BASIC_BASE_ID 64 +#define BCM2835_IRQ_ID_TIMER_0 64 +#define BCM2835_IRQ_ID_MAILBOX_0 65 +#define BCM2835_IRQ_ID_DOORBELL_0 66 +#define BCM2835_IRQ_ID_DOORBELL_1 67 +#define BCM2835_IRQ_ID_GPU0_HALTED 68 +#define BCM2835_IRQ_ID_GPU1_HALTED 69 +#define BCM2835_IRQ_ID_ILL_ACCESS_1 70 +#define BCM2835_IRQ_ID_ILL_ACCESS_0 71 + +#define BSP_INTERRUPT_VECTOR_MIN (0) +#define BSP_INTERRUPT_VECTOR_MAX (BCM2835_INTC_TOTAL_IRQ - 1) + +#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ) + +#endif /* ASM */ +#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/mailbox.h b/bsps/arm/raspberrypi/include/bsp/mailbox.h new file mode 100644 index 0000000000..e6cb0f8c27 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/mailbox.h @@ -0,0 +1,32 @@ +/** + * @file + * + * @ingroup raspberrypi + * + * @brief mailbox support. + */ +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_MAILBOX_H +#define LIBBSP_ARM_RASPBERRYPI_MAILBOX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern unsigned int raspberrypi_mailbox_read(unsigned int channel); +extern void raspberrypi_mailbox_write(unsigned int channel, unsigned int data); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_MAILBOX_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/mmu.h b/bsps/arm/raspberrypi/include/bsp/mmu.h new file mode 100644 index 0000000000..45ecc5a2a4 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/mmu.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup rapberrypi_mmu + * + * @brief MMU API. + */ + +/* + * Copyright (c) 2013 Alan Cudmore. + * based on work by: + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_MMU_H +#define LIBBSP_ARM_RASPBERRYPI_MMU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup raspberrypi_mmu MMU Support + * + * @ingroup arm_raspberrypi + * + * @brief MMU support. + * + * @{ + */ + +#define RASPBERRYPI_MMU_CLIENT_DOMAIN 15U + +#define RASPBERRYPI_MMU_READ_ONLY \ + ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_DEFAULT) + +#define RASPBERRYPI_MMU_READ_ONLY_CACHED \ + (RASPBERRYPI_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +#define RASPBERRYPI_MMU_READ_WRITE \ + ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ + | ARM_MMU_SECT_AP_0 \ + | ARM_MMU_SECT_DEFAULT) + +#define RASPBERRYPI_MMU_READ_WRITE_CACHED \ + (RASPBERRYPI_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_MMU_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/raspberrypi.h b/bsps/arm/raspberrypi/include/bsp/raspberrypi.h new file mode 100644 index 0000000000..4ef5f713ad --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/raspberrypi.h @@ -0,0 +1,572 @@ +/** + * @file raspberrypi.h + * + * @ingroup raspberrypi_reg + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * Copyright (c) 2013 Alan Cudmore. + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H +#define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H + +#include +#include +#include + +/** + * @defgroup raspberrypi_reg Register Definitions + * + * @ingroup arm_raspberrypi + * + * @brief Register Definitions + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + +#define BCM2835_REG(x) (*(volatile uint32_t *)(x)) +#define BCM2835_BIT(n) (1 << (n)) + +/** @} */ + +/** + * @name Peripheral Base Register Address + * + * @{ + */ + +#if (BSP_IS_RPI2 == 1) + #define RPI_PERIPHERAL_BASE 0x3F000000 +#else + #define RPI_PERIPHERAL_BASE 0x20000000 +#endif + +#define RPI_PERIPHERAL_SIZE 0x01000000 + +/** + * @name Internal ARM Timer Registers + * + * @{ + */ + +#define BCM2835_CLOCK_FREQ 250000000 + +#define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400) + +#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00) +#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04) +#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08) +#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C) +#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10) +#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14) +#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18) +#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C) +#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20) + +#define BCM2835_TIMER_PRESCALE 0xF9 + +/** @} */ + +/** + * @name Power Management and Watchdog Registers + * + * @{ + */ + +#define BCM2835_PM_PASSWD_MAGIC 0x5a000000 + +#define BCM2835_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000) + +#define BCM2835_PM_GNRIC (BCM2835_PM_BASE + 0x00) +#define BCM2835_PM_GNRIC_POWUP 0x00000001 +#define BCM2835_PM_GNRIC_POWOK 0x00000002 +#define BCM2835_PM_GNRIC_ISPOW 0x00000004 +#define BCM2835_PM_GNRIC_MEMREP 0x00000008 +#define BCM2835_PM_GNRIC_MRDONE 0x00000010 +#define BCM2835_PM_GNRIC_ISFUNC 0x00000020 +#define BCM2835_PM_GNRIC_RSTN 0x00000fc0 +#define BCM2835_PM_GNRIC_ENAB 0x00001000 +#define BCM2835_PM_GNRIC_CFG 0x007f0000 + +#define BCM2835_PM_AUDIO (BCM2835_PM_BASE + 0x04) +#define BCM2835_PM_AUDIO_APSM 0x000fffff +#define BCM2835_PM_AUDIO_CTRLEN 0x00100000 +#define BCM2835_PM_AUDIO_RSTN 0x00200000 + +#define BCM2835_PM_STATUS (BCM2835_PM_BASE + 0x18) + +#define BCM2835_PM_RSTC (BCM2835_PM_BASE + 0x1c) +#define BCM2835_PM_RSTC_DRCFG 0x00000003 +#define BCM2835_PM_RSTC_WRCFG 0x00000030 +#define BCM2835_PM_RSTC_WRCFG_FULL 0x00000020 +#define BCM2835_PM_RSTC_SRCFG 0x00000300 +#define BCM2835_PM_RSTC_QRCFG 0x00003000 +#define BCM2835_PM_RSTC_FRCFG 0x00030000 +#define BCM2835_PM_RSTC_HRCFG 0x00300000 + +#define BCM2835_PM_RSTS (BCM2835_PM_BASE + 0x20) +#define BCM2835_PM_RSTS_HADDRQ 0x00000001 +#define BCM2835_PM_RSTS_HADDRF 0x00000002 +#define BCM2835_PM_RSTS_HADDRH 0x00000004 +#define BCM2835_PM_RSTS_HADWRQ 0x00000010 +#define BCM2835_PM_RSTS_HADWRF 0x00000020 +#define BCM2835_PM_RSTS_HADWRH 0x00000040 +#define BCM2835_PM_RSTS_HADSRQ 0x00000100 +#define BCM2835_PM_RSTS_HADSRF 0x00000200 +#define BCM2835_PM_RSTS_HADSRH 0x00000400 +#define BCM2835_PM_RSTS_HADPOR 0x00001000 + +#define BCM2835_PM_WDOG (BCM2835_PM_BASE + 0x24) + +/** @} */ + +/** + * @name GPIO Registers + * + * @{ + */ + +#define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000) + +#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04) +#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C) +#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28) +#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34) +#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40) +#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C) +#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58) +#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64) +#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70) +#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C) +#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88) +#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94) +#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98) + +/** @} */ + +/** + * @name AUX Registers + * + * @{ + */ + +#define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000) + +#define AUX_ENABLES (BCM2835_AUX_BASE + 0x04) +#define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40) +#define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44) +#define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48) +#define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C) +#define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50) +#define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54) +#define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58) +#define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C) +#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60) +#define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64) +#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68) + +/** @} */ + +/** + * @name UART 0 (PL011) Registers + * + * @{ + */ + +#define BCM2835_UART0_BASE (RPI_PERIPHERAL_BASE + 0x201000) + +#define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00) +#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE + 0x04) +#define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18) +#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20) +#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24) +#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28) +#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C) +#define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30) +#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE + 0x34) +#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE + 0x38) +#define BCM2835_UART0_RIS (BCM2835_UART0_BASE + 0x3C) +#define BCM2835_UART0_MIS (BCM2835_UART0_BASE + 0x40) +#define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44) +#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE + 0x48) +#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE + 0x80) +#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE + 0x84) +#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE + 0x88) +#define BCM2835_UART0_TDR (BCM2835_UART0_BASE + 0x8C) + +#define BCM2835_UART0_MIS_RX 0x10 +#define BCM2835_UART0_MIS_TX 0x20 +#define BCM2835_UART0_IMSC_RX 0x10 +#define BCM2835_UART0_IMSC_TX 0x20 +#define BCM2835_UART0_FR_RXFE 0x10 +#define BCM2835_UART0_FR_TXFF 0x20 +#define BCM2835_UART0_ICR_RX 0x10 +#define BCM2835_UART0_ICR_TX 0x20 + +/** @} */ + +/** + * @name I2C (BSC) Registers + * + * @{ + */ + +#define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000) + +#define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00) +#define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04) +#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08) +#define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C) +#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10) +#define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14) +#define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18) +#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C) + +/** @} */ + +/** + * @name SPI Registers + * + * @{ + */ + +#define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000) + +#define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00) +#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04) +#define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08) +#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C) +#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10) +#define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14) + +/** @} */ + +/** + * @name I2C/SPI slave BSC Registers + * + * @{ + */ + +#define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000) + +#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00) +#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04) +#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08) +#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C) +#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10) +#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14) +#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18) +#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C) +#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20) +#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24) +#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28) +#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C) +#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30) +#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34) + +/** @} */ + +/** + * @name IRQ Registers + * + * @{ + */ + +#define BCM2835_BASE_INTC (RPI_PERIPHERAL_BASE + 0xB200) + +#define BCM2835_IRQ_BASIC (BCM2835_BASE_INTC + 0x00) +#define BCM2835_IRQ_PENDING1 (BCM2835_BASE_INTC + 0x04) +#define BCM2835_IRQ_PENDING2 (BCM2835_BASE_INTC + 0x08) +#define BCM2835_IRQ_FIQ_CTRL (BCM2835_BASE_INTC + 0x0C) +#define BCM2835_IRQ_ENABLE1 (BCM2835_BASE_INTC + 0x10) +#define BCM2835_IRQ_ENABLE2 (BCM2835_BASE_INTC + 0x14) +#define BCM2835_IRQ_ENABLE_BASIC (BCM2835_BASE_INTC + 0x18) +#define BCM2835_IRQ_DISABLE1 (BCM2835_BASE_INTC + 0x1C) +#define BCM2835_IRQ_DISABLE2 (BCM2835_BASE_INTC + 0x20) +#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24) + +/** @} */ + +/** + * @name GPU Timer Registers + * + * @{ + */ + +/** + * NOTE: The GPU uses Compare registers 0 and 2 for + * it's own RTOS. 1 and 3 are available for use in + * RTEMS. + */ +#define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000) + +#define BCM2835_GPU_TIMER_CS (BCM2835_GPU_TIMER_BASE + 0x00) +#define BCM2835_GPU_TIMER_CS_M0 0x00000001 +#define BCM2835_GPU_TIMER_CS_M1 0x00000002 +#define BCM2835_GPU_TIMER_CS_M2 0x00000004 +#define BCM2835_GPU_TIMER_CS_M3 0x00000008 +#define BCM2835_GPU_TIMER_CLO (BCM2835_GPU_TIMER_BASE + 0x04) +#define BCM2835_GPU_TIMER_CHI (BCM2835_GPU_TIMER_BASE + 0x08) +#define BCM2835_GPU_TIMER_C0 (BCM2835_GPU_TIMER_BASE + 0x0C) +#define BCM2835_GPU_TIMER_C1 (BCM2835_GPU_TIMER_BASE + 0x10) +#define BCM2835_GPU_TIMER_C2 (BCM2835_GPU_TIMER_BASE + 0x14) +#define BCM2835_GPU_TIMER_C3 (BCM2835_GPU_TIMER_BASE + 0x18) + +/** @} */ + +/** + * @name EMMC Registers + * + * @{ + */ + +/** + * NOTE: Since the SD controller follows the SDHCI standard, + * the rtems-libbsd tree already provides the remaining registers. + */ + +#define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000) + +/** @} */ + +/** +* @name Mailbox Registers +* +* @{ +*/ + +#define BCM2835_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880) + +#define BCM2835_MBOX_PEEK (BCM2835_MBOX_BASE+0x10) +#define BCM2835_MBOX_READ (BCM2835_MBOX_BASE+0x00) +#define BCM2835_MBOX_WRITE (BCM2835_MBOX_BASE+0x20) +#define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18) +#define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14) +#define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C) + +#define BCM2835_MBOX_FULL 0x80000000 +#define BCM2835_MBOX_EMPTY 0x40000000 + +/** @} */ + +/** +* @name Mailbox Channels +* +* @{ +*/ + +/* Power Manager channel */ +#define BCM2835_MBOX_CHANNEL_PM 0 +/* Framebuffer channel */ +#define BCM2835_MBOX_CHANNEL_FB 1 + /* Virtual UART channel */ +#define BCM2835_MBOX_CHANNEL_VUART 2 + /* VCHIQ channel */ +#define BCM2835_MBOX_CHANNEL_VCHIQ 3 + /* LEDs channel */ +#define BCM2835_MBOX_CHANNEL_LED 4 + /* Button channel */ +#define BCM2835_MBOX_CHANNEL_BUTTON 5 + /* Touch screen channel */ +#define BCM2835_MBOX_CHANNEL_TOUCHS 6 +/* Property tags (ARM <-> VC) channel */ +#define BCM2835_MBOX_CHANNEL_PROP_AVC 8 + /* Property tags (VC <-> ARM) channel */ +#define BCM2835_MBOX_CHANNEL_PROP_VCA 9 + +/** @} */ + +/** +* @name USB Registers +* +* @{ +*/ + +#define BCM2835_USB_BASE (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */ + +/** @} */ + +/** + * @name Raspberry Pi 2 CPU Cores Local Peripherals + * + * @{ + */ + +#define BCM2836_CORE_LOCAL_PERIPH_BASE 0x40000000 +#define BCM2836_CORE_LOCAL_PERIPH_SIZE 0x00040000 + +/** @} */ + +/** + * @name Raspberry Pi 2 Mailbox Register Defines + * + * @{ + */ + +#define BCM2836_MAILBOX_0_WRITE_SET_BASE 0x40000080 +#define BCM2836_MAILBOX_1_WRITE_SET_BASE 0x40000084 +#define BCM2836_MAILBOX_2_WRITE_SET_BASE 0x40000088 +#define BCM2836_MAILBOX_3_WRITE_SET_BASE 0x4000008C +#define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0 +#define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4 +#define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8 +#define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC + +/** @} */ + +/** + * @name Raspberry Pi 2 Core Timer + * + * @{ + */ + +#define BCM2836_CORE_TIMER_CTRL 0x40000000 + +#define BCM2836_CORE_TIMER_CTRL_APB_CLK 0x00000100 +#define BCM2836_CORE_TIMER_CTRL_INC_2 0x00000200 + +#define BCM2836_CORE_TIMER_PRESCALER 0x40000008 + +#define BCM2836_CORE_TIMER_LS32 0x4000001C +#define BCM2836_CORE_TIMER_MS32 0x40000020 + +/** @} */ + +/** + * @name Raspberry Pi 2 Local Timer + * + * @{ + */ + +#define BCM2836_LOCAL_TIMER_CTRL 0x40000034 + +#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000 +#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN 0x20000000 +#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000 +#define BCM2836_LOCAL_TIMER_RELOAD 0x0FFFFFFF + +#define BCM2836_LOCAL_TIMER_IRQ_RELOAD 0x40000038 + +#define BCM2836_LOCAL_TIMER_IRQ_CLEAR 0x80000000 +#define BCM2836_LOCAL_TIMER_RELOAD_NOW 0x40000000 + +#define BCM2836_LOCAL_TIMER_IRQ_ROUTING 0x40000024 +#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ 0x00 +#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ 0x01 +#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ 0x02 +#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ 0x03 +#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ 0x04 +#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ 0x05 +#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ 0x06 +#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ 0x07 + +/** @} */ + +/** + * @name Raspberry Pi 2 IRQ Routing + * + * @{ + */ + +#define BCM2836_GPU_IRQ_ROUTING 0x4000000C + +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002 +#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003 + +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008 +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C + +#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C + + +/** @} */ + +/** + * @name Raspberry Pi 2 Interrupt Register Defines + * + * @{ + */ + +/* Timers interrupt control registers */ +#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040 +#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044 +#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048 +#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C + +#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \ + (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx)) + +/* + * Where to route timer interrupt to, IRQ/FIQ + * Setting both the IRQ and FIQ bit gives an FIQ + */ +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ 0x01 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ 0x02 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ 0x04 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ 0x08 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ 0x10 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ 0x20 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ 0x40 +#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ 0x80 + +/* CPU mailbox registers */ +#define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050 +#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \ + (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx)) +/* + * Where to route mailbox interrupt to, IRQ/FIQ + * Setting both the IRQ and FIQ bit gives an FIQ + */ +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ 0x01 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ 0x02 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ 0x04 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ 0x08 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ 0x10 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ 0x20 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ 0x40 +#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ 0x80 + +#define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060 +#define BCM2836_IRQ_SOURCE_REG(cpuidx) \ + (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) + +#define BCM2836_FIQ_SOURCE_REG_BASE 0x40000070 +#define BCM2836_FIQ_SOURCE_REG(cpuidx) \ + (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) + +#define BCM2836_IRQ_SOURCE_TIMER0 0x00000001 +#define BCM2836_IRQ_SOURCE_TIMER1 0x00000002 +#define BCM2836_IRQ_SOURCE_TIMER2 0x00000004 +#define BCM2836_IRQ_SOURCE_TIMER3 0x00000008 +#define BCM2836_IRQ_SOURCE_MBOX0 0x00000010 +#define BCM2836_IRQ_SOURCE_MBOX1 0x00000020 +#define BCM2836_IRQ_SOURCE_MBOX2 0x00000040 +#define BCM2836_IRQ_SOURCE_MBOX3 0x00000080 +#define BCM2836_IRQ_SOURCE_GPU 0x00000100 +#define BCM2836_IRQ_SOURCE_PMU 0x00000200 +#define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800 + +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/rpi-fb.h b/bsps/arm/raspberrypi/include/bsp/rpi-fb.h new file mode 100644 index 0000000000..4f3c07fea2 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/rpi-fb.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup raspberrypi_fb + * + * @brief framebuffer support and setup + * + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_FB_H +#define LIBBSP_ARM_RASPBERRYPI_FB_H + +#include + +/** + * @defgroup raspberrypi_fb + * + * @ingroup arm_raspberrypi + * + * @brief Framebuffer support and setup + * + * @{ + */ + +enum rpi_fb_init_result { + RPI_FB_INIT_OK = 0, + RPI_FB_INIT_ALREADY_INITIALIZED = 1, + RPI_FB_INIT_GENERIC_ERROR = -1, + RPI_FB_INIT_NO_DISPLAY = -2, + RPI_FB_INIT_CMDLINE_BAD_FORMAT = -3, + RPI_FB_INIT_CMDLINE_DONT_INIT = -4, + RPI_FB_INIT_CMDLINE_NO_MODE_REQ = -5, + RPI_FB_INIT_MODE_PROBE_ERROR = -6, + RPI_FB_INIT_SETUP_FAILED = -7, + RPI_FB_INIT_START_ADDR_UNKNOWN = -8, +}; + +int rpi_fb_init( void ); +int rpi_get_fix_screen_info( struct fb_fix_screeninfo *info ); +int rpi_get_var_screen_info( struct fb_var_screeninfo *info ); +bool rpi_fb_hdmi_is_present( void ); + +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_FB_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h b/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h new file mode 100644 index 0000000000..82ba4b1f2a --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/rpi-gpio.h @@ -0,0 +1,70 @@ +/** + * @file rpi-gpio.h + * + * @ingroup raspberrypi_gpio + * + * @brief Raspberry Pi specific GPIO definitions. + */ + +/* + * Copyright (c) 2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H +#define LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Raspberry Pi GPIO functions. + */ +#define RPI_DIGITAL_IN 0 +#define RPI_DIGITAL_OUT 1 +#define RPI_ALT_FUNC_0 4 +#define RPI_ALT_FUNC_1 5 +#define RPI_ALT_FUNC_2 6 +#define RPI_ALT_FUNC_3 7 +#define RPI_ALT_FUNC_4 3 +#define RPI_ALT_FUNC_5 2 +#define RPI_ALT_FUNC_MASK 7 + +/** + * @brief Setups a JTAG interface. + * + * @retval RTEMS_SUCCESSFUL JTAG interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_jtag(void); + +/** + * @brief Setups a SPI interface. + * + * @retval RTEMS_SUCCESSFUL SPI interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_spi(void); + +/** + * @brief Setups a I2C interface. + * + * @retval RTEMS_SUCCESSFUL I2C interface successfully configured. + * @retval * At least one of the required pins is currently + * occupied, @see rtems_gpio_request_pin_group(). + */ +extern rtems_status_code rpi_gpio_select_i2c(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/spi.h b/bsps/arm/raspberrypi/include/bsp/spi.h new file mode 100644 index 0000000000..1bbbc6d2a4 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/spi.h @@ -0,0 +1,77 @@ +/** + * @file spi.h + * + * @ingroup raspberrypi_spi + * + * @brief Raspberry Pi specific SPI definitions. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_SPI_H +#define LIBBSP_ARM_RASPBERRYPI_SPI_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @name SPI constants. + * + * @{ + */ + +/** + * @brief GPU processor core clock rate in Hz. + * + * Unless configured otherwise on a "config.txt" file present on the SD card + * the GPU defaults to 250 MHz. Currently only 250 MHz is supported. + */ + +/* TODO: It would be nice if this value could be probed at startup, probably + * using the Mailbox interface since the usual way of setting this on + * the hardware is through a "config.txt" text file on the SD card. + * Having this setup on the configure.ac script would require changing + * the same setting on two different places. */ +#define GPU_CORE_CLOCK_RATE 250000000 + +/** @} */ + +/** + * @name SPI directives. + * + * @{ + */ + +/** + * @brief Setups the Raspberry Pi SPI bus (located on the GPIO header) + * on the "/dev/spi" device file, and registers the bus on the + * libi2c API. + * + * @param[in] bidirectional_mode If TRUE sets the SPI bus to use 2-wire SPI, + * where the MOSI data line doubles as the + * slave out (SO) and slave in (SI) data lines. + * If FALSE the bus defaults to the usual + * 3-wire SPI, with 2 separate data lines + * (MOSI and MISO). + * + * @retval Returns libi2c bus number. + * @retval <0 Could not register the bus. See @see rtems_libi2c_register_bus(). + */ +extern int rpi_spi_init(bool bidirectional_mode); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_SPI_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/usart.h b/bsps/arm/raspberrypi/include/bsp/usart.h new file mode 100644 index 0000000000..491392b1f7 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/usart.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup raspberrypi_usart + * + * @brief USART support. + */ + + +/** + * @defgroup raspberrypi_usart USART Support + * + * @ingroup arm_raspberrypi + * + * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Support + */ + +/* + * Copyright (c) 2013 Alan Cudmore. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_USART_H +#define LIBBSP_ARM_RASPBERRYPI_USART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define USART0_DEFAULT_BAUD 115000 + +extern const console_fns bcm2835_usart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_USART_H */ diff --git a/bsps/arm/raspberrypi/include/bsp/vc.h b/bsps/arm/raspberrypi/include/bsp/vc.h new file mode 100644 index 0000000000..e863732cd5 --- /dev/null +++ b/bsps/arm/raspberrypi/include/bsp/vc.h @@ -0,0 +1,157 @@ +/** + * @file + * + * @ingroup raspberrypi_vc + * + * @brief video core support. + * + */ + +/* + * Copyright (c) 2015 Yang Qiao + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE + * + */ + +#ifndef LIBBSP_ARM_RASPBERRYPI_VC_H +#define LIBBSP_ARM_RASPBERRYPI_VC_H + +/** + * @defgroup raspberrypi_vc Register Definitions + * + * @ingroup arm_raspberrypi + * + * @brief Register Definitions + * + * @{ + */ + +typedef struct { + uint32_t width; + uint32_t height; +} bcm2835_get_display_size_entries; + +int bcm2835_mailbox_get_display_size( + bcm2835_get_display_size_entries *_entries ); + +typedef enum { + bcm2835_mailbox_pixel_order_bgr = 0, + bcm2835_mailbox_pixel_order_rgb = 1 +} bcm2835_pixel_order; + +typedef enum { + bcm2835_mailbox_alpha_mode_0_opaque = 0, + bcm2835_mailbox_alpha_mode_0_transparent = 1, + bcm2835_mailbox_alpha_mode_ignored = 2 +} bcm2835_alpha_mode; + +typedef struct { + uint32_t xres; + uint32_t yres; + uint32_t xvirt; + uint32_t yvirt; + uint32_t depth; + bcm2835_pixel_order pixel_order; + bcm2835_alpha_mode alpha_mode; + uint32_t voffset_x; + uint32_t voffset_y; + uint32_t overscan_left; + uint32_t overscan_right; + uint32_t overscan_top; + uint32_t overscan_bottom; + uint32_t base; + size_t size; + uint32_t pitch; +} bcm2835_init_frame_buffer_entries; + +int bcm2835_mailbox_init_frame_buffer( + bcm2835_init_frame_buffer_entries *_entries ); + +typedef struct { + uint32_t pitch; +} bcm2835_get_pitch_entries; + +int bcm2835_mailbox_get_pitch( bcm2835_get_pitch_entries *_entries ); + +typedef struct { + char cmdline[ 1024 ]; +} bcm2835_get_cmdline_entries; + +int bcm2835_mailbox_get_cmdline( bcm2835_get_cmdline_entries *_entries ); + +typedef enum { + bcm2835_mailbox_power_udid_sd_card = 0x00000000u, + bcm2835_mailbox_power_udid_uart0 = 0x00000001u, + bcm2835_mailbox_power_udid_uart1 = 0x00000002u, + bcm2835_mailbox_power_udid_usb_hcd = 0x00000003u, + bcm2835_mailbox_power_udid_i2c0 = 0x00000004u, + bcm2835_mailbox_power_udid_i2c1 = 0x00000005u, + bcm2835_mailbox_power_udid_i2c2 = 0x00000006u, + bcm2835_mailbox_power_udid_spi = 0x00000007u, + bcm2835_mailbox_power_udid_ccp2tx = 0x00000008u, +} bcm2835_power_device_id; + +typedef struct { + bcm2835_power_device_id dev_id; + uint32_t state; +} bcm2835_set_power_state_entries; + +#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_ON ( 1 << 0 ) +#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_WAIT ( 1 << 1 ) +#define BCM2835_MAILBOX_POWER_STATE_ON ( 1 << 0 ) +#define BCM2835_MAILBOX_POWER_STATE_NODEV ( 1 << 1 ) +int bcm2835_mailbox_set_power_state( bcm2835_set_power_state_entries *_entries ); + +int bcm2835_mailbox_get_power_state( bcm2835_set_power_state_entries *_entries ); + +typedef struct { + uint32_t base; + size_t size; +} bcm2835_get_arm_memory_entries; + +int bcm2835_mailbox_get_arm_memory( bcm2835_get_arm_memory_entries *_entries ); + +typedef struct { + uint32_t base; + size_t size; +} bcm2835_get_vc_memory_entries; + +int bcm2835_mailbox_get_vc_memory( bcm2835_get_vc_memory_entries *_entries ); + +typedef struct { + uint32_t fw_rev; +} bcm2835_mailbox_get_fw_rev_entries; + +int bcm2835_mailbox_get_firmware_revision( + bcm2835_mailbox_get_fw_rev_entries *_entries ); + +typedef struct { + uint32_t spec; +} bcm2835_get_board_spec_entries; + +int bcm2835_mailbox_get_board_model( bcm2835_get_board_spec_entries *_entries ); + +int bcm2835_mailbox_get_board_revision( + bcm2835_get_board_spec_entries *_entries ); + +typedef struct { + uint64_t board_serial; +} bcm2835_get_board_serial_entries; + +int bcm2835_mailbox_get_board_serial( + bcm2835_get_board_serial_entries *_entries ); + +typedef struct { + uint32_t clock_id; + uint32_t clock_rate; +} bcm2835_get_clock_rate_entries; + +int bcm2835_mailbox_get_clock_rate( + bcm2835_get_clock_rate_entries *_entries ); +/** @} */ + +#endif /* LIBBSP_ARM_RASPBERRYPI_VC_H */ diff --git a/bsps/arm/raspberrypi/include/tm27.h b/bsps/arm/raspberrypi/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/raspberrypi/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/realview-pbx-a9/headers.am b/bsps/arm/realview-pbx-a9/headers.am new file mode 100644 index 0000000000..be4dc1aeb4 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/realview-pbx-a9/include/bsp/irq.h diff --git a/bsps/arm/realview-pbx-a9/include/bsp.h b/bsps/arm/realview-pbx-a9/include/bsp.h new file mode 100644 index 0000000000..4423984e47 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/bsp.h @@ -0,0 +1,67 @@ +/** + * @file + * + * @ingroup arm_realview-pbx-a9 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H +#define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_HAS_FRAME_BUFFER 1 + +#ifndef ASM + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0x1f000000 + +#define BSP_ARM_GIC_CPUIF_BASE 0x1f000100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0x1f000200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0x1f000600 + +#define BSP_ARM_GIC_DIST_BASE 0x1f001000 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H */ + +/** + * @defgroup arm_realview-pbx-a9 Realview PBX-A9 + * + * @ingroup bsp_arm + * + * @brief Realview PBX-A9 support package + * + */ diff --git a/bsps/arm/realview-pbx-a9/include/bsp/irq.h b/bsps/arm/realview-pbx-a9/include/bsp/irq.h new file mode 100644 index 0000000000..3c9790e9ef --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/bsp/irq.h @@ -0,0 +1,102 @@ +/** + * @file + * + * @ingroup realview-pbx-a9_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H +#define LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include + +/** + * @defgroup realview-pbx-a9_interrupt Interrrupt Support + * + * @ingroup arm_realview-pbx-a9 + * + * @brief Interrupt support. + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define RVPBXA9_IRQ_WATCHDOG_0 32 +#define RVPBXA9_IRQ_SW_IRQ 33 +#define RVPBXA9_IRQ_TIMER_0_1 36 +#define RVPBXA9_IRQ_TIMER_2_3 37 +#define RVPBXA9_IRQ_GPIO_0 38 +#define RVPBXA9_IRQ_GPIO_1 39 +#define RVPBXA9_IRQ_GPIO_2 40 +#define RVPBXA9_IRQ_RTC 42 +#define RVPBXA9_IRQ_SSP 43 +#define RVPBXA9_IRQ_UART_0 44 +#define RVPBXA9_IRQ_UART_1 45 +#define RVPBXA9_IRQ_UART_2 46 +#define RVPBXA9_IRQ_UART_3 47 +#define RVPBXA9_IRQ_SCI 48 +#define RVPBXA9_IRQ_MCI_A 49 +#define RVPBXA9_IRQ_MCI_B 50 +#define RVPBXA9_IRQ_AACI 51 +#define RVPBXA9_IRQ_KMI0 52 +#define RVPBXA9_IRQ_KMI1 53 +#define RVPBXA9_IRQ_CLCD 55 +#define RVPBXA9_IRQ_DMAC 56 +#define RVPBXA9_IRQ_PWRFAIL 57 +#define RVPBXA9_IRQ_CF_INT 59 +#define RVPBXA9_IRQ_ETHERNET 60 +#define RVPBXA9_IRQ_USB 61 +#define RVPBXA9_IRQ_T1_INT_0 64 +#define RVPBXA9_IRQ_T1_INT_1 65 +#define RVPBXA9_IRQ_T1_INT_2 66 +#define RVPBXA9_IRQ_T1_INT_3 67 +#define RVPBXA9_IRQ_T1_INT_4 68 +#define RVPBXA9_IRQ_T1_INT_5 69 +#define RVPBXA9_IRQ_T1_INT_6 70 +#define RVPBXA9_IRQ_T1_INT_7 71 +#define RVPBXA9_IRQ_WATCHDOG_1 72 +#define RVPBXA9_IRQ_TIMER_4_5 73 +#define RVPBXA9_IRQ_TIMER_6_7 74 +#define RVPBXA9_IRQ_PCI_INTR 80 +#define RVPBXA9_IRQ_P_NMI 81 +#define RVPBXA9_IRQ_P_NINT_0 82 +#define RVPBXA9_IRQ_P_NINT_1 83 +#define RVPBXA9_IRQ_P_NINT_2 84 +#define RVPBXA9_IRQ_P_NINT_3 85 +#define RVPBXA9_IRQ_P_NINT_4 86 +#define RVPBXA9_IRQ_P_NINT_5 87 +#define RVPBXA9_IRQ_P_NINT_6 88 +#define RVPBXA9_IRQ_P_NINT_7 89 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 89 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H */ diff --git a/bsps/arm/realview-pbx-a9/include/tm27.h b/bsps/arm/realview-pbx-a9/include/tm27.h new file mode 100644 index 0000000000..c336d8d310 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/include/tm27.h @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup realview-pbx-a9_tm27 + * + * @brief GIC tmtests/tm27 support. + */ + + +/** + * @defgroup realview-pbx-a9_tm27 GIC tmtests/tm27 + * + * @ingroup arm_realview-pbx-a9 + * + * @brief GIC tmtests/tm27 support. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/rtl22xx/headers.am b/bsps/arm/rtl22xx/headers.am new file mode 100644 index 0000000000..70f14bf3ed --- /dev/null +++ b/bsps/arm/rtl22xx/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/lpc22xx.h +include_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/rtl22xx/include/bsp/irq.h diff --git a/bsps/arm/rtl22xx/include/bsp.h b/bsps/arm/rtl22xx/include/bsp.h new file mode 100644 index 0000000000..9b376daf0d --- /dev/null +++ b/bsps/arm/rtl22xx/include/bsp.h @@ -0,0 +1,226 @@ +/** + * @file + * @ingroup arm_rtl22xx + * @brief Global BSP definitions. + */ + +/* + * Philips LPC22XX/LPC21xx BSP header file + * + * by Ray,Xu + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ +#ifndef LIBBSP_ARM_RTL22XX_BSP_H +#define LIBBSP_ARM_RTL22XX_BSP_H + +#include +#include + +/** + * @defgroup arm_rtl22xx RTL22XX Support + * @ingroup bsp_arm + * @brief RTL22XX Support Package + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define CONFIG_ARM_CLK 60000000L +/* cclk=cco/(2*P) */ +/* cco = cclk*2*P */ + +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK + +/* Fcco 156M~320Mhz*/ +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK +#define LPC22xx_Fcco LPC22xx_Fcclk * 4 +/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ +#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 + + + +/** + * @name Fcclk range: 10MHz ~ MCU allowed frequency + * @{ + */ + +#define Fcclk_MIN 10000000L +#define Fcclk_MAX 60000000L + +/** @} */ + +/** + * @name Fcco range: 156MHz ~ 320MHz + * @{ + */ + +#define Fcco_MIN 156000000L +#define Fcco_MAX 320000000L + +/** @} */ + +#define PLLFEED_DATA1 0xAA +#define PLLFEED_DATA2 0x55 + +/** + * @name PLL PLLCON register bit descriptions + * @{ + */ + +#define PLLCON_ENABLE_BIT 0 +#define PLLCON_CONNECT_BIT 1 + +/** @} */ + +/** + * @name PLL PLLSTAT register bit descriptions + * @{ + */ + +#define PLLSTAT_ENABLE_BIT 8 +#define PLLSTAT_CONNECT_BIT 9 +#define PLLSTAT_LOCK_BIT 10 + +/** @} */ + +/** + * @name PM Peripheral Type + * @{ + */ + +#define PC_TIMER0 0x2 +#define PC_TIMER1 0x4 +#define PC_UART0 0x8 +#define PC_UART1 0x10 +#define PC_PWM0 0x20 +#define PC_I2C 0x80 +#define PC_SPI0 0x100 +#define PC_RTC 0x200 + +/** @} */ + +/** @brief OSC [Hz] */ +#define FOSC 11059200 +/** @brief Core clk [Hz] */ +#define FCCLK FOSC<<2 + +/** + * @name System Configure + * @{ + */ + +/** @brief osc freq,10MHz~25MHz, change to a real one if needed */ +#define Fosc 11059200 +/** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ +#define Fcclk (Fosc << 2) +/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ +#define Fcco (Fcclk <<2) +/** @brief VPB freq only(Fcclk / 4) 1~4 */ +#define Fpclk (Fcclk >>2) * 1 +/* This was M. That is a BAD BAD public constant. I renamed it to + * JOEL_M so it wouldn't conflict with user code. If you can find + * a better name, fix this. But nothing I found uses it. + */ + +/** @} */ + +#define JOEL_M Fcclk / Fosc +#define P_min Fcco_MIN / (2*Fcclk) + 1; +#define P_max Fcco_MAX / (2*Fcclk); + +#define UART_BPS 115200 + +/** @brief Time Precision time [us] */ +#define TIMER_PRECISION 10 + +/** @brief I2C Speed [bit/s] */ +#define I2CSPEED 20000 // 20 Kbit/s + +/** + * @name Uarts buffers size + * @{ + */ + +#define RXBUFSIZE 32 +#define TXBUFSIZE 32 + +/** @} */ + +/** @brief SPI Speed [bit/s] */ +#define SPISPEED 1500000 // 1.5 Mbit/s +/** @brief SPI EEPROM CS pin + * + * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) + */ +#define SPI_CS_PIN P0_13 +#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN + +/** + * @name Flash definition + * @{ + */ + +//#define RTL22XX_FLASH_SIZE (0x200000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit +/** @brief Total area of Flash region in words 8 bit */ +#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) +//#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit +#define RTL22XX_FLASH_BEGIN 0x80000000 +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define RTL22XX_FLASH_BASE (RTL22XX_FLASH_BEGIN+RTL22XX_FLASH_BOOT) + +/** @} */ + +/** + * @name SRAM definition + * @{ + */ + +/** @brief Total area of Flash region in words 8 bit */ +#define SRAM_SIZE 0x100000 +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define SRAM_BASE 0x81000000 + +/** @} */ + +/** @brief CS8900A definition */ +#define CS8900A_BASE 0x82000000 +/** @brief RTL8019AS definition */ +#define RTL8019AS_BASE 0x82000000 + +struct rtems_bsdnet_ifconfig; +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * @name Network driver configuration + * @{ + */ + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach + +/** @} */ + +/* + * Prototypes for methods used across file boundaries in the BSP. + */ +extern void UART0_Ini(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ diff --git a/bsps/arm/rtl22xx/include/bsp/irq.h b/bsps/arm/rtl22xx/include/bsp/irq.h new file mode 100644 index 0000000000..31825ca56e --- /dev/null +++ b/bsps/arm/rtl22xx/include/bsp/irq.h @@ -0,0 +1,71 @@ +/* + * Interrupt handler Header file + * + * Copyright (c) 2010 embedded brains GmbH. + * + * Copyright (c) 2006 by Ray to support LPC ARM + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#ifndef __asm__ + +#include +#include +#include + +#endif /* __asm__ */ + +/* possible interrupt sources on the LPC22xx */ +#define LPC22xx_INTERRUPT_WDINT 0 /* Watchdog int. 0 */ +#define LPC22xx_INTERRUPT_RSV0 1 /* Reserved int. 1 */ +#define LPC22xx_INTERRUPT_DBGRX 2 /* Embedded ICE DbgCommRx receive */ +#define LPC22xx_INTERRUPT_DBGTX 3 /* Embedded ICE DbgCommRx Transmit*/ +#define LPC22xx_INTERRUPT_TIMER0 4 /* Timer 0 */ +#define LPC22xx_INTERRUPT_TIMER1 5 /* Timer 1 */ +#define LPC22xx_INTERRUPT_UART0 6 /* UART 0 */ +#define LPC22xx_INTERRUPT_UART1 7 /* UART 1 */ +#define LPC22xx_INTERRUPT_PWM0 8 /* PWM */ +#define LPC22xx_INTERRUPT_I2C 9 /* I2C */ +#define LPC22xx_INTERRUPT_SPI0 10 /* SPI0 */ +#define LPC22xx_INTERRUPT_SPI1 11 /* SPI1 */ +#define LPC22xx_INTERRUPT_PLL 12 /* PLL */ +#define LPC22xx_INTERRUPT_RTC 13 /* RTC */ +#define LPC22xx_INTERRUPT_EINT0 14 /* Externel Interrupt 0 */ +#define LPC22xx_INTERRUPT_EINT1 15 /* Externel Interrupt 1 */ +#define LPC22xx_INTERRUPT_EINT2 16 /* Externel Interrupt 2 */ +#define LPC22xx_INTERRUPT_EINT3 17 /* Externel Interrupt 3 */ +#define LPC22xx_INTERRUPT_ADC 18 /* AD Converter */ +/* Following interrupt used by lpc229x */ +#define LPC22xx_INTERRUPT_CANERR 19 /* CAN LUTerr interrupt */ +#define LPC22xx_INTERRUPT_CAN1TX 20 /* CAN1 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN1RX 21 /* CAN1 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN2TX 22 /* CAN2 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN2RX 23 /* CAN2 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN3TX 24 /* CAN1 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN3RX 25 /* CAN1 Rx interrupt */ +#define LPC22xx_INTERRUPT_CAN4TX 26 /* CAN2 Tx interrupt */ +#define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ +#define BSP_MAX_INT 28 + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) +#define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) +#define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) +#define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) +#define IRQ_VECTOR_ADDR (*(u_long *)0x00000018L) +#define FIQ_VECTOR_ADDR (*(u_long *)0x0000001CL) + +#define DATA_ABORT_ISR_ADDR (*(u_long *)0x00000030L) +#define IRQ_ISR_ADDR (*(u_long *)0x00000038L) +#define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) + +#endif /* __IRQ_H__ */ diff --git a/bsps/arm/rtl22xx/include/lpc22xx.h b/bsps/arm/rtl22xx/include/lpc22xx.h new file mode 100644 index 0000000000..babaf8343d --- /dev/null +++ b/bsps/arm/rtl22xx/include/lpc22xx.h @@ -0,0 +1,475 @@ +/* + * Philips LPC22XX/LPC21xx Register definitions + * + * Copyright (c) 2006 by Ray + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __LPC22XX_H__ +#define __LPC22XX_H__ + +#include + +/* EXTERNAL MEMORY CONTROLLER (EMC) */ +#define BCFG0 (*((volatile unsigned int *) 0xFFE00000)) /* lpc22xx only */ +#define BCFG1 (*((volatile unsigned int *) 0xFFE00004)) /* lpc22xx only */ +#define BCFG2 (*((volatile unsigned int *) 0xFFE00008)) /* lpc22xx only */ +#define BCFG3 (*((volatile unsigned int *) 0xFFE0000C)) /* lpc22xx only */ + +/* External Interrupts */ +#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) +#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144)) +#ifdef CONFIG_ARCH_LPC22xx +#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/ +#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/ +#endif + +/* SMemory mapping control. */ +#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*((volatile unsigned char *) 0xE01FC080)) +#define PLLCFG (*((volatile unsigned char *) 0xE01FC084)) +#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088)) +#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C)) + +/* Power Control */ +#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) +#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) + +/* VPB Divider */ +#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) +#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) + +/* Vectored Interrupt Controller (VIC) */ +#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) +#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) +#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) +#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) +#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) +#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) +#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) +#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C)) +#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) +#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) +#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) + +#define VICVectAddrBase 0xFFFFF100 +#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) +#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) +#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) +#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) +#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) +#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) +#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) +#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) +#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) +#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) +#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) +#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) +#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) +#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) +#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) +#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) + +#define VICVectCntlBase 0xFFFFF200 +#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) +#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) +#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) +#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) +#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) +#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) +#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) +#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) +#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) +#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) +#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) +#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) +#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) +#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) +#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) +#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) + +/* Pin Connect Block */ +#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) +#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) + +#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/ + + +/* General Purpose Input/Output (GPIO) */ +#ifndef CONFIG_ARCH_LPC22xx + +#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */ +#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */ +#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */ +#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */ + +#endif + +#ifdef CONFIG_ARCH_LPC22xx +#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/ +#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/ +#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/ +#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/ + +#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/ +#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/ +#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/ +#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/ +#endif + +#ifdef CONFIG_ARCH_LPC22xx + +#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */ +#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */ +#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */ +#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */ + +#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */ +#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */ +#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */ +#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */ + +#endif + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define U0RBR (*((volatile unsigned char *) 0xE000C000)) +#define U0THR (*((volatile unsigned char *) 0xE000C000)) +#define U0IER (*((volatile unsigned char *) 0xE000C004)) +#define U0IIR (*((volatile unsigned char *) 0xE000C008)) +#define U0FCR (*((volatile unsigned char *) 0xE000C008)) +#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) +#define U0LSR (*((volatile unsigned char *) 0xE000C014)) +#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) +#define U0DLL (*((volatile unsigned char *) 0xE000C000)) +#define U0DLM (*((volatile unsigned char *) 0xE000C004)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define U1RBR (*((volatile unsigned char *) 0xE0010000)) +#define U1THR (*((volatile unsigned char *) 0xE0010000)) +#define U1IER (*((volatile unsigned char *) 0xE0010004)) +#define U1IIR (*((volatile unsigned char *) 0xE0010008)) +#define U1FCR (*((volatile unsigned char *) 0xE0010008)) +#define U1LCR (*((volatile unsigned char *) 0xE001000C)) +#define U1MCR (*((volatile unsigned char *) 0xE0010010)) +#define U1LSR (*((volatile unsigned char *) 0xE0010014)) +#define U1MSR (*((volatile unsigned char *) 0xE0010018)) +#define U1SCR (*((volatile unsigned char *) 0xE001001C)) +#define U1DLL (*((volatile unsigned char *) 0xE0010000)) +#define U1DLM (*((volatile unsigned char *) 0xE0010004)) + +/* I2C (8/16 bit data bus) */ +#define I2CONSET (*((volatile unsigned char *) 0xE001C000)) +#define I2STAT (*((volatile unsigned char *) 0xE001C004)) +#define I2DAT (*((volatile unsigned char *) 0xE001C008)) +#define I2ADR (*((volatile unsigned char *) 0xE001C00C)) +#define I2SCLH (*((volatile unsigned short *) 0xE001C010)) +#define I2SCLL (*((volatile unsigned short *) 0xE001C014)) +#define I2CONCLR (*((volatile unsigned char *) 0xE001C018)) + +/* SPI (Serial Peripheral Interface) */ + /* only for lpc210x*/ +#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000)) +#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004)) +#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008)) +#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C)) +#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C)) + +#ifdef CONFIG_ARCH_LPC22xx +#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/ +#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/ +#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/ +#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/ +#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/ + +#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/ +#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/ +#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/ +#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/ +#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/ +#endif +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1EWL (*((volatile unsigned long *) 0xE004401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1SR (*((volatile unsigned long *) 0xE0044020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RFS (*((volatile unsigned long *) 0xE0044024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2EWL (*((volatile unsigned long *) 0xE004801C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2SR (*((volatile unsigned long *) 0xE0048020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RFS (*((volatile unsigned long *) 0xE0048024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3EWL (*((volatile unsigned long *) 0xE004C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3SR (*((volatile unsigned long *) 0xE004C020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RFS (*((volatile unsigned long *) 0xE004C024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4EWL (*((volatile unsigned long *) 0xE005001C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4SR (*((volatile unsigned long *) 0xE0050020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RFS (*((volatile unsigned long *) 0xE0050024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CAN5MOD (*((volatile unsigned long *) 0xE0054000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5CMR (*((volatile unsigned long *) 0xE0054004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5GSR (*((volatile unsigned long *) 0xE0054008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5ICR (*((volatile unsigned long *) 0xE005400C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5IER (*((volatile unsigned long *) 0xE0054010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5BTR (*((volatile unsigned long *) 0xE0054014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5EWL (*((volatile unsigned long *) 0xE005401C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5SR (*((volatile unsigned long *) 0xE0054020)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RFS (*((volatile unsigned long *) 0xE0054024)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDA (*((volatile unsigned long *) 0xE0054028)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5RDB (*((volatile unsigned long *) 0xE005402C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI1 (*((volatile unsigned long *) 0xE0054030)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID1 (*((volatile unsigned long *) 0xE0054034)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA1 (*((volatile unsigned long *) 0xE0054038)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB1 (*((volatile unsigned long *) 0xE005403C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI2 (*((volatile unsigned long *) 0xE0054040)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID2 (*((volatile unsigned long *) 0xE0054044)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA2 (*((volatile unsigned long *) 0xE0054048)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB2 (*((volatile unsigned long *) 0xE005404C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TFI3 (*((volatile unsigned long *) 0xE0054050)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TID3 (*((volatile unsigned long *) 0xE0054054)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#ifdef CONFIG_ARCH_LPC22xx +#define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */ +#define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */ +#define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */ +#define CAN6ICR (*((volatile unsigned long *) 0xE005800C)) /* lpc2292\lpc2294 only */ +#define CAN6IER (*((volatile unsigned long *) 0xE0058010)) /* lpc2292\lpc2294 only */ +#define CAN6BTR (*((volatile unsigned long *) 0xE0058014)) /* lpc2292\lpc2294 only */ +#define CAN6EWL (*((volatile unsigned long *) 0xE005801C)) /* lpc2292\lpc2294 only */ +#define CAN6SR (*((volatile unsigned long *) 0xE0058020)) /* lpc2292\lpc2294 only */ +#define CAN6RFS (*((volatile unsigned long *) 0xE0058024)) /* lpc2292\lpc2294 only */ +#define CAN6RDA (*((volatile unsigned long *) 0xE0058028)) /* lpc2292\lpc2294 only */ +#define CAN6RDB (*((volatile unsigned long *) 0xE005802C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI1 (*((volatile unsigned long *) 0xE0058030)) /* lpc2292\lpc2294 only */ +#define CAN6TID1 (*((volatile unsigned long *) 0xE0058034)) /* lpc2292\lpc2294 only */ +#define CAN6TDA1 (*((volatile unsigned long *) 0xE0058038)) /* lpc2292\lpc2294 only */ +#define CAN6TDB1 (*((volatile unsigned long *) 0xE005803C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI2 (*((volatile unsigned long *) 0xE0058040)) /* lpc2292\lpc2294 only */ +#define CAN6TID2 (*((volatile unsigned long *) 0xE0058044)) /* lpc2292\lpc2294 only */ +#define CAN6TDA2 (*((volatile unsigned long *) 0xE0058048)) /* lpc2292\lpc2294 only */ +#define CAN6TDB2 (*((volatile unsigned long *) 0xE005804C)) /* lpc2292\lpc2294 only */ +#define CAN6TFI3 (*((volatile unsigned long *) 0xE0058050)) /* lpc2292\lpc2294 only */ +#define CAN6TID3 (*((volatile unsigned long *) 0xE0058054)) /* lpc2292\lpc2294 only */ +#define CAN6TDA3 (*((volatile unsigned long *) 0xE0058058)) /* lpc2292\lpc2294 only */ +#define CAN6TDB3 (*((volatile unsigned long *) 0xE005805C)) /* lpc2292\lpc2294 only */ +#endif + +#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ + +#define CANAFMR (*((volatile unsigned long *) 0xE003C000)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_sa (*((volatile unsigned long *) 0xE003C004)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANSFF_GRP_sa (*((volatile unsigned long *) 0xE003C008)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_sa (*((volatile unsigned long *) 0xE003C00C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANEFF_GRP_sa (*((volatile unsigned long *) 0xE003C010)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANENDofTable (*((volatile unsigned long *) 0xE003C014)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerrAd (*((volatile unsigned long *) 0xE003C018)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +#define CANLUTerr (*((volatile unsigned long *) 0xE003C01C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ +/* CAN Acceptance Filter RAM */ +#define CANAFRAM (*((volatile unsigned long *) 0xE0038000)) + + +/* Timer 0 */ +#define T0IR (*((volatile unsigned long *) 0xE0004000)) +#define T0TCR (*((volatile unsigned long *) 0xE0004004)) +#define T0TC (*((volatile unsigned long *) 0xE0004008)) +#define T0PR (*((volatile unsigned long *) 0xE000400C)) +#define T0PC (*((volatile unsigned long *) 0xE0004010)) +#define T0MCR (*((volatile unsigned long *) 0xE0004014)) +#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) +#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) +#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) +#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) +#define T0CCR (*((volatile unsigned long *) 0xE0004028)) +#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) +#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) +#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) +#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) +#define T0EMR (*((volatile unsigned long *) 0xE000403C)) + +/* Timer 1 */ +#define T1IR (*((volatile unsigned long *) 0xE0008000)) +#define T1TCR (*((volatile unsigned long *) 0xE0008004)) +#define T1TC (*((volatile unsigned long *) 0xE0008008)) +#define T1PR (*((volatile unsigned long *) 0xE000800C)) +#define T1PC (*((volatile unsigned long *) 0xE0008010)) +#define T1MCR (*((volatile unsigned long *) 0xE0008014)) +#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) +#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) +#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) +#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) +#define T1CCR (*((volatile unsigned long *) 0xE0008028)) +#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) +#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) +#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) +#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) +#define T1EMR (*((volatile unsigned long *) 0xE000803C)) + +/* Pulse Width Modulator (PWM) */ +#define PWMIR (*((volatile unsigned long *) 0xE0014000)) +#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) +#define PWMTC (*((volatile unsigned long *) 0xE0014008)) +#define PWMPR (*((volatile unsigned long *) 0xE001400C)) +#define PWMPC (*((volatile unsigned long *) 0xE0014010)) +#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) +#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) +#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) +#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) +#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) +#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) +#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) +#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) +#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) +#define PWMLER (*((volatile unsigned long *) 0xE0014050)) + +/* A/D CONVERTER */ +#ifndef CONFIG_ARCH_LPC2104 +#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/ +#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/ +#endif + +/* Real Time Clock */ +#define ILR (*((volatile unsigned char *) 0xE0024000)) +#define CTC (*((volatile unsigned short*) 0xE0024004)) +#define CCR (*((volatile unsigned char *) 0xE0024008)) +#define CIIR (*((volatile unsigned char *) 0xE002400C)) +#define AMR (*((volatile unsigned char *) 0xE0024010)) +#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) +#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) +#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) +#define SEC (*((volatile unsigned char *) 0xE0024020)) +#define MIN (*((volatile unsigned char *) 0xE0024024)) +#define HOUR (*((volatile unsigned char *) 0xE0024028)) +#define DOM (*((volatile unsigned char *) 0xE002402C)) +#define DOW (*((volatile unsigned char *) 0xE0024030)) +#define DOY (*((volatile unsigned short*) 0xE0024034)) +#define MONTH (*((volatile unsigned char *) 0xE0024038)) +#define YEAR (*((volatile unsigned short*) 0xE002403C)) +#define ALSEC (*((volatile unsigned char *) 0xE0024060)) +#define ALMIN (*((volatile unsigned char *) 0xE0024064)) +#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) +#define ALDOM (*((volatile unsigned char *) 0xE002406C)) +#define ALDOW (*((volatile unsigned char *) 0xE0024070)) +#define ALDOY (*((volatile unsigned short*) 0xE0024074)) +#define ALMON (*((volatile unsigned char *) 0xE0024078)) +#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) +#define PREINT (*((volatile unsigned short*) 0xE0024080)) +#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) + +/* Watchdog */ +#define WDMOD (*((volatile unsigned char *) 0xE0000000)) +#define WDTC (*((volatile unsigned long *) 0xE0000004)) +#define WDFEED (*((volatile unsigned char *) 0xE0000008)) +#define WDTV (*((volatile unsigned long *) 0xE000000C)) + +/* + Register define for constant +*/ +#define REG_U0RBR 0xE000C000 +#define REG_U1RBR 0xE0010000 + +/* PLL */ +#define REG_PLLCON 0xE01FC080 +#define REG_PLLCFG 0xE01FC084 +#define REG_PLLSTAT 0xE01FC088 +#define REG_PLLFEED 0xE01FC08C + +/* Power Control */ + +#define REG_PCON 0xE01FC0C0 +#define REG_PCOMP 0xE01FC0C4 +#define REG_PINSEL0 0xE002C000 +#define REG_MEMMAP 0xE01FC040 +#define REG_PLLSTAT 0xE01FC088 +#define REG_VPBDIV 0xE01FC100 + + +#endif /* __LPC22XX_H__ */ diff --git a/bsps/arm/rtl22xx/include/tm27.h b/bsps/arm/rtl22xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/rtl22xx/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/smdk2410/headers.am b/bsps/arm/smdk2410/headers.am new file mode 100644 index 0000000000..25d2eb723e --- /dev/null +++ b/bsps/arm/smdk2410/headers.am @@ -0,0 +1,14 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c2400.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c2410.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/s3c24xx.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/smc.h +include_HEADERS += ../../../../../../bsps/arm/smdk2410/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/smdk2410/include/bsp/irq.h diff --git a/bsps/arm/smdk2410/include/bsp.h b/bsps/arm/smdk2410/include/bsp.h new file mode 100644 index 0000000000..25764195d0 --- /dev/null +++ b/bsps/arm/smdk2410/include/bsp.h @@ -0,0 +1,80 @@ +/** + * @file + * @ingroup arm_smdk2410 + * @brief Global BSP definitons. + */ + +/* + * Copyright (c) Canon Research France SA.] + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SMDK2410_BSP_H +#define LIBBSP_ARM_SMDK2410_BSP_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +/** + * @brief functions to get the differents s3c2400 clks + * @{ + */ + +uint32_t get_FCLK(void); +uint32_t get_HCLK(void); +uint32_t get_PCLK(void); +uint32_t get_UCLK(void); + +/** @} */ + +/* What is the input clock freq in hertz? */ +/** @brief 12 MHz oscillator */ +#define BSP_OSC_FREQ 12000000 +/** @brief FCLK=133Mhz */ +#define M_MDIV 81 +#define M_PDIV 2 +#define M_SDIV 1 +/** @brief HCLK=FCLK/2, PCLK=FCLK/2 */ +#define M_CLKDIVN 2 +/** @brief enable refresh */ +#define REFEN 0x1 +/** @brief CBR(CAS before RAS)/auto refresh */ +#define TREFMD 0x0 +/** @brief 2 clk */ +#define Trp 0x0 +/** @brief 7 clk */ +#define Trc 0x3 +/** @brief 3 clk */ +#define Tchr 0x2 + +/** + * @brief This BSP provides its own IDLE thread to override the RTEMS one. + * + * So we prototype it and define the constant confdefs.h expects + * to configure a BSP specific one. + */ +void *bsp_idle_thread(uintptr_t ignored); + +/** @} */ + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ + diff --git a/bsps/arm/smdk2410/include/bsp/irq.h b/bsps/arm/smdk2410/include/bsp/irq.h new file mode 100644 index 0000000000..8882b4362b --- /dev/null +++ b/bsps/arm/smdk2410/include/bsp/irq.h @@ -0,0 +1,96 @@ +/* irq.h + * + * Copyright (c) 2010 embedded brains GmbH. + * + * CopyRight (C) 2000 Canon Research France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h + */ + +#ifndef _IRQ_H_ +#define _IRQ_H_ + +#include +#include +#include + +#include + +#ifdef CPU_S3C2400 + /* possible interrupt sources */ +#define BSP_EINT0 0 +#define BSP_EINT1 1 +#define BSP_EINT2 2 +#define BSP_EINT3 3 +#define BSP_EINT4 4 +#define BSP_EINT5 5 +#define BSP_EINT6 6 +#define BSP_EINT7 7 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UERR01 15 +#define _res0 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_MMC 21 +#define BSP_INT_SPI 22 +#define BSP_INT_URXD0 23 +#define BSP_INT_URXD1 24 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UTXD0 28 +#define BSP_INT_UTXD1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 + +#elif defined CPU_S3C2410 + /* possible interrupt sources */ +#define BSP_EINT0 0 +#define BSP_EINT1 1 +#define BSP_EINT2 2 +#define BSP_EINT3 3 +#define BSP_EINT4_7 4 +#define BSP_EINT8_23 5 +#define BSP_nBATT_FLT 7 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UART2 15 +#define BSP_INT_LCD 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_SDI 21 +#define BSP_INT_SPI0 22 +#define BSP_INT_UART1 23 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UART0 28 +#define BSP_INT_SPI1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) + +#endif /* _IRQ_H_ */ +/* end of include file */ diff --git a/bsps/arm/smdk2410/include/s3c2400.h b/bsps/arm/smdk2410/include/s3c2400.h new file mode 100644 index 0000000000..89a3cf73d8 --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c2400.h @@ -0,0 +1,676 @@ +/************************************************ + * NAME : s3c2400.h + * Version : 3.7.2002 + * + * Based on 24x.h for the Samsung Development Board + ************************************************/ + +#ifndef S3C2400_H_ +#define S3C2400_H_ + +/* to be used in assembly code */ +#define rINTOFFSET_ADDR 0x14400014 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x14000000) +#define rBANKCON0 (*(volatile unsigned *)0x14000004) +#define rBANKCON1 (*(volatile unsigned *)0x14000008) +#define rBANKCON2 (*(volatile unsigned *)0x1400000C) +#define rBANKCON3 (*(volatile unsigned *)0x14000010) +#define rBANKCON4 (*(volatile unsigned *)0x14000014) +#define rBANKCON5 (*(volatile unsigned *)0x14000018) +#define rBANKCON6 (*(volatile unsigned *)0x1400001C) +#define rBANKCON7 (*(volatile unsigned *)0x14000020) +#define rREFRESH (*(volatile unsigned *)0x14000024) +#define rBANKSIZE (*(volatile unsigned *)0x14000028) +#define rMRSRB6 (*(volatile unsigned *)0x1400002C) +#define rMRSRB7 (*(volatile unsigned *)0x14000030) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x14400000) +#define rINTMOD (*(volatile unsigned *)0x14400004) +#define rINTMSK (*(volatile unsigned *)0x14400008) +#define rPRIORITY (*(volatile unsigned *)0x1440000C) +#define rINTPND (*(volatile unsigned *)0x14400010) +#define rINTOFFSET (*(volatile unsigned *)0x14400014) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x14600000) +#define rDIDST0 (*(volatile unsigned *)0x14600004) +#define rDCON0 (*(volatile unsigned *)0x14600008) +#define rDSTAT0 (*(volatile unsigned *)0x1460000C) +#define rDCSRC0 (*(volatile unsigned *)0x14600010) +#define rDCDST0 (*(volatile unsigned *)0x14600014) +#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) +#define rDISRC1 (*(volatile unsigned *)0x14600020) +#define rDIDST1 (*(volatile unsigned *)0x14600024) +#define rDCON1 (*(volatile unsigned *)0x14600028) +#define rDSTAT1 (*(volatile unsigned *)0x1460002C) +#define rDCSRC1 (*(volatile unsigned *)0x14600030) +#define rDCDST1 (*(volatile unsigned *)0x14600034) +#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) +#define rDISRC2 (*(volatile unsigned *)0x14600040) +#define rDIDST2 (*(volatile unsigned *)0x14600044) +#define rDCON2 (*(volatile unsigned *)0x14600048) +#define rDSTAT2 (*(volatile unsigned *)0x1460004C) +#define rDCSRC2 (*(volatile unsigned *)0x14600050) +#define rDCDST2 (*(volatile unsigned *)0x14600054) +#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) +#define rDISRC3 (*(volatile unsigned *)0x14600060) +#define rDIDST3 (*(volatile unsigned *)0x14600064) +#define rDCON3 (*(volatile unsigned *)0x14600068) +#define rDSTAT3 (*(volatile unsigned *)0x1460006C) +#define rDCSRC3 (*(volatile unsigned *)0x14600070) +#define rDCDST3 (*(volatile unsigned *)0x14600074) +#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x14800000) +#define rMPLLCON (*(volatile unsigned *)0x14800004) +#define rUPLLCON (*(volatile unsigned *)0x14800008) +#define rCLKCON (*(volatile unsigned *)0x1480000C) +#define rCLKSLOW (*(volatile unsigned *)0x14800010) +#define rCLKDIVN (*(volatile unsigned *)0x14800014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x14A00000) +#define rLCDCON2 (*(volatile unsigned *)0x14A00004) +#define rLCDCON3 (*(volatile unsigned *)0x14A00008) +#define rLCDCON4 (*(volatile unsigned *)0x14A0000C) +#define rLCDCON5 (*(volatile unsigned *)0x14A00010) +#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014) +#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018) +#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C) +#define rREDLUT (*(volatile unsigned *)0x14A00020) +#define rGREENLUT (*(volatile unsigned *)0x14A00024) +#define rBLUELUT (*(volatile unsigned *)0x14A00028) +#define rDP1_2 (*(volatile unsigned *)0x14A0002C) +#define rDP4_7 (*(volatile unsigned *)0x14A00030) +#define rDP3_5 (*(volatile unsigned *)0x14A00034) +#define rDP2_3 (*(volatile unsigned *)0x14A00038) +#define rDP5_7 (*(volatile unsigned *)0x14A0003c) +#define rDP3_4 (*(volatile unsigned *)0x14A00040) +#define rDP4_5 (*(volatile unsigned *)0x14A00044) +#define rDP6_7 (*(volatile unsigned *)0x14A00048) +#define rDITHMODE (*(volatile unsigned *)0x14A0004C) +#define rTPAL (*(volatile unsigned *)0x14A00050) +#define GP32_PALETTE (*(volatile unsigned *)0x14A00400) /* SJS */ + + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x15000000) +#define rUCON0 (*(volatile unsigned short *)0x15000004) +#define rUFCON0 (*(volatile unsigned char *)0x15000008) +#define rUMCON0 (*(volatile unsigned char *)0x1500000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x15000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x15000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x15000028) + +#define rULCON1 (*(volatile unsigned char *)0x15004000) +#define rUCON1 (*(volatile unsigned short *)0x15004004) +#define rUFCON1 (*(volatile unsigned char *)0x15004008) +#define rUMCON1 (*(volatile unsigned char *)0x1500400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x15004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x15004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x15004028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x15000023) +#define rURXH0 (*(volatile unsigned char *)0x15000027) +#define rUTXH1 (*(volatile unsigned char *)0x15004023) +#define rURXH1 (*(volatile unsigned char *)0x15004027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004027) + +#define UTXH0 (0x15000020+3) /* byte_access address by DMA */ +#define URXH0 (0x15000024+3) +#define UTXH1 (0x15004020+3) +#define URXH1 (0x15004024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x15000020) +#define rURXH0 (*(volatile unsigned char *)0x15000024) +#define rUTXH1 (*(volatile unsigned char *)0x15004020) +#define rURXH1 (*(volatile unsigned char *)0x15004024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004024) + +#define UTXH0 (0x15000020) /* byte_access address by DMA */ +#define URXH0 (0x15000024) +#define UTXH1 (0x15004020) +#define URXH1 (0x15004024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x15100000) +#define rTCFG1 (*(volatile unsigned *)0x15100004) +#define rTCON (*(volatile unsigned *)0x15100008) +#define rTCNTB0 (*(volatile unsigned *)0x1510000C) +#define rTCMPB0 (*(volatile unsigned *)0x15100010) +#define rTCNTO0 (*(volatile unsigned *)0x15100014) +#define rTCNTB1 (*(volatile unsigned *)0x15100018) +#define rTCMPB1 (*(volatile unsigned *)0x1510001C) +#define rTCNTO1 (*(volatile unsigned *)0x15100020) +#define rTCNTB2 (*(volatile unsigned *)0x15100024) +#define rTCMPB2 (*(volatile unsigned *)0x15100028) +#define rTCNTO2 (*(volatile unsigned *)0x1510002C) +#define rTCNTB3 (*(volatile unsigned *)0x15100030) +#define rTCMPB3 (*(volatile unsigned *)0x15100034) +#define rTCNTO3 (*(volatile unsigned *)0x15100038) +#define rTCNTB4 (*(volatile unsigned *)0x1510003C) +#define rTCNTO4 (*(volatile unsigned *)0x15100040) + + +/* USB DEVICE */ +#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) +#define rPWR_REG (*(volatile unsigned *)0x15200144) +#define rINT_REG (*(volatile unsigned *)0x15200148) +#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C) +#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) +#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) +#define rEP0_CSR (*(volatile unsigned *)0x15200160) +#define rEP0_MAXP (*(volatile unsigned *)0x15200164) +#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) +#define rEP0_FIFO (*(volatile unsigned *)0x1520016C) +#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) +#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) +#define rEP1_FIFO (*(volatile unsigned *)0x15200188) +#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) +#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) +#define rEP2_FIFO (*(volatile unsigned *)0x15200198) +#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0) +#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4) +#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8) +#define rEP3_FIFO (*(volatile unsigned *)0x152001AC) +#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0) +#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4) +#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8) +#define rEP4_FIFO (*(volatile unsigned *)0x152001BC) +#define rDMA_CON (*(volatile unsigned *)0x152001C0) +#define rDMA_UNIT (*(volatile unsigned *)0x152001C4) +#define rDMA_FIFO (*(volatile unsigned *)0x152001C8) +#define rDMA_TX (*(volatile unsigned *)0x152001CC) +#define rTEST_MODE (*(volatile unsigned *)0x152001F4) +#define rIN_CON_REG (*(volatile unsigned *)0x152001F8) + + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x15300000) +#define rWTDAT (*(volatile unsigned *)0x15300004) +#define rWTCNT (*(volatile unsigned *)0x15300008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x15400000) +#define rIICSTAT (*(volatile unsigned *)0x15400004) +#define rIICADD (*(volatile unsigned *)0x15400008) +#define rIICDS (*(volatile unsigned *)0x1540000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x15508000) +#define rIISMOD (*(volatile unsigned *)0x15508004) +#define rIISPSR (*(volatile unsigned *)0x15508008) +#define rIISFIFCON (*(volatile unsigned *)0x1550800C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x15508012) + +#else /* Little Endian */ +#define IISFIF ((volatile unsigned short *)0x15508010) +#endif + + +/* I/O PORT */ +#define rPACON (*(volatile unsigned *)0x15600000) +#define rPADAT (*(volatile unsigned *)0x15600004) + +#define rPBCON (*(volatile unsigned *)0x15600008) +#define rPBDAT (*(volatile unsigned *)0x1560000C) +#define rPBUP (*(volatile unsigned *)0x15600010) + +#define rPCCON (*(volatile unsigned *)0x15600014) +#define rPCDAT (*(volatile unsigned *)0x15600018) +#define rPCUP (*(volatile unsigned *)0x1560001C) + +#define rPDCON (*(volatile unsigned *)0x15600020) +#define rPDDAT (*(volatile unsigned *)0x15600024) +#define rPDUP (*(volatile unsigned *)0x15600028) + +#define rPECON (*(volatile unsigned *)0x1560002C) +#define rPEDAT (*(volatile unsigned *)0x15600030) +#define rPEUP (*(volatile unsigned *)0x15600034) + +#define rPFCON (*(volatile unsigned *)0x15600038) +#define rPFDAT (*(volatile unsigned *)0x1560003C) +#define rPFUP (*(volatile unsigned *)0x15600040) + +#define rPGCON (*(volatile unsigned *)0x15600044) +#define rPGDAT (*(volatile unsigned *)0x15600048) +#define rPGUP (*(volatile unsigned *)0x1560004C) + +#define rOPENCR (*(volatile unsigned *)0x15600050) +#define rMISCCR (*(volatile unsigned *)0x15600054) +#define rEXTINT (*(volatile unsigned *)0x15600058) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x15700043) +#define rRTCALM (*(volatile unsigned char *)0x15700053) +#define rALMSEC (*(volatile unsigned char *)0x15700057) +#define rALMMIN (*(volatile unsigned char *)0x1570005B) +#define rALMHOUR (*(volatile unsigned char *)0x1570005F) +#define rALMDAY (*(volatile unsigned char *)0x15700063) +#define rALMMON (*(volatile unsigned char *)0x15700067) +#define rALMYEAR (*(volatile unsigned char *)0x1570006B) +#define rRTCRST (*(volatile unsigned char *)0x1570006F) +#define rBCDSEC (*(volatile unsigned char *)0x15700073) +#define rBCDMIN (*(volatile unsigned char *)0x15700077) +#define rBCDHOUR (*(volatile unsigned char *)0x1570007B) +#define rBCDDAY (*(volatile unsigned char *)0x1570007F) +#define rBCDDATE (*(volatile unsigned char *)0x15700083) +#define rBCDMON (*(volatile unsigned char *)0x15700087) +#define rBCDYEAR (*(volatile unsigned char *)0x1570008B) +#define rTICINT (*(volatile unsigned char *)0x15700047) + +#else /* Little Endian */ +#define rRTCCON (*(volatile unsigned char *)0x15700040) +#define rRTCALM (*(volatile unsigned char *)0x15700050) +#define rALMSEC (*(volatile unsigned char *)0x15700054) +#define rALMMIN (*(volatile unsigned char *)0x15700058) +#define rALMHOUR (*(volatile unsigned char *)0x1570005C) +#define rALMDAY (*(volatile unsigned char *)0x15700060) +#define rALMMON (*(volatile unsigned char *)0x15700064) +#define rALMYEAR (*(volatile unsigned char *)0x15700068) +#define rRTCRST (*(volatile unsigned char *)0x1570006C) +#define rBCDSEC (*(volatile unsigned char *)0x15700070) +#define rBCDMIN (*(volatile unsigned char *)0x15700074) +#define rBCDHOUR (*(volatile unsigned char *)0x15700078) +#define rBCDDAY (*(volatile unsigned char *)0x1570007C) +#define rBCDDATE (*(volatile unsigned char *)0x15700080) +#define rBCDMON (*(volatile unsigned char *)0x15700084) +#define rBCDYEAR (*(volatile unsigned char *)0x15700088) +#define rTICINT (*(volatile unsigned char *)0x15700044) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x15800000) +#define rADCDAT (*(volatile unsigned *)0x15800004) + + +/* SPI */ +#define rSPCON (*(volatile unsigned *)0x15900000) +#define rSPSTA (*(volatile unsigned *)0x15900004) +#define rSPPIN (*(volatile unsigned *)0x15900008) +#define rSPPRE (*(volatile unsigned *)0x1590000C) +#define rSPTDAT (*(volatile unsigned *)0x15900010) +#define rSPRDAT (*(volatile unsigned *)0x15900014) + + +/* MMC INTERFACE */ +#define rMMCON (*(volatile unsigned *)0x15a00000) +#define rMMCRR (*(volatile unsigned *)0x15a00004) +#define rMMFCON (*(volatile unsigned *)0x15a00008) +#define rMMSTA (*(volatile unsigned *)0x15a0000C) +#define rMMFSTA (*(volatile unsigned *)0x15a00010) +#define rMMPRE (*(volatile unsigned *)0x15a00014) +#define rMMLEN (*(volatile unsigned *)0x15a00018) +#define rMMCR7 (*(volatile unsigned *)0x15a0001C) +#define rMMRSP0 (*(volatile unsigned *)0x15a00020) +#define rMMRSP1 (*(volatile unsigned *)0x15a00024) +#define rMMRSP2 (*(volatile unsigned *)0x15a00028) +#define rMMRSP3 (*(volatile unsigned *)0x15a0002C) +#define rMMCMD0 (*(volatile unsigned *)0x15a00030) +#define rMMCMD1 (*(volatile unsigned *)0x15a00034) +#define rMMCR16 (*(volatile unsigned *)0x15a00038) +#define rMMDAT (*(volatile unsigned *)0x15a0003C) + + +#define _ISR_STARTADDRESS rtems_vector_table +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) +#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4 (0x1<<4) +#define BIT_EINT5 (0x1<<5) +#define BIT_EINT6 (0x1<<6) +#define BIT_EINT7 (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UERR01 (0x1<<15) +#define BIT_NOTUSED (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_MMC (0x1<<21) +#define BIT_SPI (0x1<<22) +#define BIT_URXD0 (0x1<<23) +#define BIT_URXD1 (0x1<<24) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UTXD0 (0x1<<28) +#define BIT_UTXD1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ + +#ifndef ASM +/* Typedefs */ +typedef union { + struct _reg { + unsigned STOP_BIT:1; /* Enters STOP mode. This bit isn't be */ + /* cleared automatically. */ + unsigned SL_IDLE:1; /* SL_IDLE mode option. This bit isn't cleared */ + /* automatically. To enter SL_IDLE mode, */ + /* CLKCON register has to be 0xe. */ + unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ + /* automatically. */ + unsigned LCDC:1; /* Controls HCLK into LCDC block */ + unsigned USB_host:1; /* Controls HCLK into USB host block */ + unsigned USB_device:1; /* Controls PCLK into USB device block */ + unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ + unsigned MMC:1; /* Controls PCLK into MMC interface block */ + unsigned UART0:1; /* Controls PCLK into UART0 block */ + unsigned UART1:1; /* Controls PCLK into UART1 block */ + unsigned GPIO:1; /* Controls PCLK into GPIO block */ + unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ + /* this bit is cleared to 0, RTC timer is alive. */ + unsigned ADC:1; /* Controls PCLK into ADC block */ + unsigned IIC:1; /* Controls PCLK into IIC block */ + unsigned IIS:1; /* Controls PCLK into IIS block */ + unsigned SPI:1; /* Controls PCLK into SPI block */ + } reg; + unsigned long all; +} CLKCON; + +typedef union +{ + struct { + unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ + unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ + /* 1110 = 16 bpp TFT skipmode */ + unsigned PNRMODE:2; /* TFT: 3 */ + unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ + /* 0 = Each Frame, 1 = The rate defined by the MVAL */ + unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ + unsigned LINECNT:10; /* (read only) These bits provide the status of the */ + /* line counter. Down count from LINEVAL to 0 */ + } reg; + unsigned long all; +} LCDCON1; + +typedef union { + struct { + unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ + /* VSYNC pulse's high level width by counting the */ + /* number of inactive lines. */ + unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ + /* inactive lines at the end of a frame, before */ + /* vertical synchronization period. */ + unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ + /* of LCD panel. */ + unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ + /* lines at the start of a frame, after */ + /* vertical synchronization period. */ + } reg; + unsigned long all; +} LCDCON2; + +typedef union { + struct { + unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ + /* VCLK periods between the end of active data */ + /* and the rising edge of HSYNC. */ + unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ + /* size of LCD panel. 2n bytes. */ + unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ + /* periods between the falling edge of HSYNC and */ + /* the start of active data. */ + } reg; + unsigned long all; +} LCDCON3; + +typedef union { + struct { + unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ + /* HSYNC pulse's high level width by counting the */ + /* number of the VCLK. */ + unsigned MVAL:8; /* STN: */ + unsigned ADDVAL:8; /* TFT: Palette Index offset value */ + unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */ + /* 0 = Disable 1 = Enable */ + } reg; + unsigned long all; +} LCDCON4; + +typedef union { + struct { + unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ + /* 0 = Disable LEND signal. */ + /* 1 = Enable LEND signal */ + unsigned RESERVED1:1; + unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */ + /* polarity. 0 = normal 1 = inverted */ + unsigned RESERVED2:1; + unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ + /* polarity. */ + /* 0 = normal 1 = inverted */ + unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ + /* pulse polarity. 0 = Normal. */ + /* 1 = VD is inverted. */ + unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ + /* VCLK active edge. 0 = The video data is */ + /* fetched at VCLK falling edge. 1 = The video */ + /* data is fetched at VCLK rising edge */ + unsigned RESERVED3:2; + unsigned SELFREF:1; /* STN: */ + unsigned SLOWCLKSYNC:1; /* STN: */ + unsigned RESERVED4:2; /* must be 0 */ + unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ + /* 00 = HSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */ + /* 00 = VSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + } reg; + unsigned long all; +} LCDCON5; + +typedef union { + struct { + unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ + /* A[21:1] of the start address of the LCD */ + /* frame buffer. */ + unsigned LCDBANK:7; /* A[28:22] */ + } reg; + unsigned long all; +} LCDSADDR1; + +typedef union { + struct { + unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ + /* of the end address of the LCD frame buffer. */ + /* LCDBASEL = ((the fame end address) >>1) + 1 */ + /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ + } reg; + unsigned long all; +} LCDSADDR2; + +typedef union { + struct { + unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ + /* words) This value defines the width of the */ + /* view port in the frame */ + unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ + /* words) This value defines the difference */ + /* between the address of the last half word */ + /* displayed on the previous LCD line and the */ + /* address of the first half word to be */ + /* displayed in the new LCD line. */ + } reg; + unsigned long all; +} LCDSADDR3; + +/* + * + */ + +typedef union { + struct { + unsigned IISIFENA:1; /* IIS interface enable (start) */ + unsigned IISPSENA:1; /* IIS prescaler enable */ + unsigned RXCHIDLE:1; /* Receive channel idle command */ + unsigned TXCHIDLE:1; /* Transmit channel idle command */ + unsigned RXDMAENA:1; /* Receive DMA service request enable */ + unsigned TXDMAENA:1; /* Transmit DMA service request enable */ + unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ + unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ + unsigned LRINDEX:1; /* Left/right channel index (read only) */ + } reg; + unsigned long all; +} IISCON; + +typedef union { + struct { + unsigned SBCLKFS:2; /* Serial bit clock frequency select */ + unsigned MCLKFS:1; /* Master clock frequency select */ + unsigned SDBITS:1; /* Serial data bit per channel */ + unsigned SIFMT:1; /* Serial interface format */ + unsigned ACTLEVCH:1; /* Active level pf left/right channel */ + unsigned TXRXMODE:2; /* Transmit/receive mode select */ + unsigned MODE:1; /* Master/slave mode select */ + } reg; + unsigned long all; +} IISMOD; + +typedef union { + struct { + unsigned PSB:5; /* Prescaler control B */ + unsigned PSA:5; /* Prescaler control A */ + } reg; + unsigned long all; +} IISPSR; + +typedef union { + struct { + unsigned RXFIFOCNT:4; /* (read only) */ + unsigned TXFIFOCNT:4; /* (read only) */ + /*signed RXFIFOENA:1; /* */ + unsigned TXFIFOENA:1; /* */ + unsigned RXFIFOMODE:1; /* */ + unsigned TXFIFOMODE:1; /* */ + } reg; + unsigned long all; +} IISSFIFCON; + +typedef union { + struct { + unsigned FENTRY:16; /* */ + } reg; + unsigned long all; +} IISSFIF; +#endif //ASM + +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) + +#define GP32_KEY_SELECT 512 +#define GP32_KEY_START 256 +#define GP32_KEY_A 64 +#define GP32_KEY_B 32 +#define GP32_KEY_L 16 +#define GP32_KEY_R 128 +#define GP32_KEY_UP 8 +#define GP32_KEY_DOWN 2 +#define GP32_KEY_LEFT 1 +#define GP32_KEY_RIGHT 4 + +#endif /*S3C2400_H_*/ diff --git a/bsps/arm/smdk2410/include/s3c2410.h b/bsps/arm/smdk2410/include/s3c2410.h new file mode 100644 index 0000000000..c6a0a0b452 --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c2410.h @@ -0,0 +1,825 @@ +/************************************************ + * NAME : s3c2410.h + * Version : 3.7.2002 + * + * Based on 24x.h for the Samsung Development Board + ************************************************/ + +#ifndef S3C2410_H_ +#define S3C2410_H_ + +/* to be used in assembly code */ +#define rINTOFFSET_ADDR 0x4A000014 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x48000000) +#define rBANKCON0 (*(volatile unsigned *)0x48000004) +#define rBANKCON1 (*(volatile unsigned *)0x48000008) +#define rBANKCON2 (*(volatile unsigned *)0x4800000C) +#define rBANKCON3 (*(volatile unsigned *)0x48000010) +#define rBANKCON4 (*(volatile unsigned *)0x48000014) +#define rBANKCON5 (*(volatile unsigned *)0x48000018) +#define rBANKCON6 (*(volatile unsigned *)0x4800001C) +#define rBANKCON7 (*(volatile unsigned *)0x48000020) +#define rREFRESH (*(volatile unsigned *)0x48000024) +#define rBANKSIZE (*(volatile unsigned *)0x48000028) +#define rMRSRB6 (*(volatile unsigned *)0x4800002C) +#define rMRSRB7 (*(volatile unsigned *)0x48000030) + +/* USB Host Controller */ +#define rHcRevision (*(volatile unsigned *)0x49000000) +#define rHcControl (*(volatile unsigned *)0x49000004) +#define rHcCommonStatus (*(volatile unsigned *)0x49000008) +#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C) +#define rHcInterruptEnable (*(volatile unsigned *)0x49000010) +#define rHcInterruptDisable (*(volatile unsigned *)0x49000014) +#define rHcHCCA (*(volatile unsigned *)0x49000018) +#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C) +#define rHcControlHeadED (*(volatile unsigned *)0x49000020) +#define rHcControlCurrentED (*(volatile unsigned *)0x49000024) +#define rHcBulkHeadED (*(volatile unsigned *)0x49000028) +#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C) +#define rHcDoneHead (*(volatile unsigned *)0x49000030) +#define rHcRmInterval (*(volatile unsigned *)0x49000034) +#define rHcFmRemaining (*(volatile unsigned *)0x49000038) +#define rHcFmNumber (*(volatile unsigned *)0x4900003C) +#define rHcPeriodicStart (*(volatile unsigned *)0x49000040) +#define rHcLSThreshold (*(volatile unsigned *)0x49000044) +#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048) +#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C) +#define rHcRhStatus (*(volatile unsigned *)0x49000050) +#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054) +#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058) + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x4A000000) +#define rINTMOD (*(volatile unsigned *)0x4A000004) +#define rINTMSK (*(volatile unsigned *)0x4A000008) +#define rPRIORITY (*(volatile unsigned *)0x4A00000C) +#define rINTPND (*(volatile unsigned *)0x4A000010) +#define rINTOFFSET (*(volatile unsigned *)0x4A000014) +#define rSUBSRCPND (*(volatile unsigned *)0x4A000018) +#define rINTSUBMSK (*(volatile unsigned *)0x4A00001c) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x4B000000) +#define rDISRCC0 (*(volatile unsigned *)0x4B000004) +#define rDIDST0 (*(volatile unsigned *)0x4B000008) +#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C) +#define rDCON0 (*(volatile unsigned *)0x4B000010) +#define rDSTAT0 (*(volatile unsigned *)0x4B000014) +#define rDCSRC0 (*(volatile unsigned *)0x4B000018) +#define rDCDST0 (*(volatile unsigned *)0x4B00001C) +#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020) +#define rDISRC1 (*(volatile unsigned *)0x4B000040) +#define rDISRCC1 (*(volatile unsigned *)0x4B000044) +#define rDIDST1 (*(volatile unsigned *)0x4B000048) +#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C) +#define rDCON1 (*(volatile unsigned *)0x4B000050) +#define rDSTAT1 (*(volatile unsigned *)0x4B000054) +#define rDCSRC1 (*(volatile unsigned *)0x4B000058) +#define rDCDST1 (*(volatile unsigned *)0x4B00005C) +#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060) +#define rDISRC2 (*(volatile unsigned *)0x4B000080) +#define rDISRCC2 (*(volatile unsigned *)0x4B000084) +#define rDIDST2 (*(volatile unsigned *)0x4B000088) +#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C) +#define rDCON2 (*(volatile unsigned *)0x4B000090) +#define rDSTAT2 (*(volatile unsigned *)0x4B000094) +#define rDCSRC2 (*(volatile unsigned *)0x4B000098) +#define rDCDST2 (*(volatile unsigned *)0x4B00009C) +#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0) +#define rDISRC3 (*(volatile unsigned *)0x4B0000C0) +#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4) +#define rDIDST3 (*(volatile unsigned *)0x4B0000C8) +#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC) +#define rDCON3 (*(volatile unsigned *)0x4B0000D0) +#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4) +#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8) +#define rDCDST3 (*(volatile unsigned *)0x4B0000DC) +#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x4C000000) +#define rMPLLCON (*(volatile unsigned *)0x4C000004) +#define rUPLLCON (*(volatile unsigned *)0x4C000008) +#define rCLKCON (*(volatile unsigned *)0x4C00000C) +#define rCLKSLOW (*(volatile unsigned *)0x4C000010) +#define rCLKDIVN (*(volatile unsigned *)0x4C000014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x4D000000) +#define rLCDCON2 (*(volatile unsigned *)0x4D000004) +#define rLCDCON3 (*(volatile unsigned *)0x4D000008) +#define rLCDCON4 (*(volatile unsigned *)0x4D00000C) +#define rLCDCON5 (*(volatile unsigned *)0x4D000010) +#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014) +#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018) +#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rDITHMODE (*(volatile unsigned *)0x4D00004C) +#define rTPAL (*(volatile unsigned *)0x4D000050) +#define rLCDINTPND (*(volatile unsigned *)0x4D000054) +#define rLCDSRCPND (*(volatile unsigned *)0x4D000058) +#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C) +#define rTCONSEL (*(volatile unsigned *)0x4D000060) +#define PALETTE 0x4d000400 + +/* NAND Flash */ +#define rNFCONF (*(volatile unsigned *)0x4E000000) +#define rNFCMD (*(volatile unsigned *)0x4E000004) +#define rNFADDR (*(volatile unsigned *)0x4E000008) +#define rNFDATA (*(volatile unsigned *)0x4E00000C) +#define rNFSTAT (*(volatile unsigned *)0x4E000010) +#define rNFECC (*(volatile unsigned *)0x4E000014) + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x50000000) +#define rUCON0 (*(volatile unsigned short *)0x50000004) +#define rUFCON0 (*(volatile unsigned char *)0x50000008) +#define rUMCON0 (*(volatile unsigned char *)0x5000000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x50000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x50000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x50000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x5000001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x50000028) + +#define rULCON1 (*(volatile unsigned char *)0x50004000) +#define rUCON1 (*(volatile unsigned short *)0x50004004) +#define rUFCON1 (*(volatile unsigned char *)0x50004008) +#define rUMCON1 (*(volatile unsigned char *)0x5000400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x50004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x50004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x50004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x5000401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x50004028) + +#define rULCON2 (*(volatile unsigned char *)0x50008000) +#define rUCON2 (*(volatile unsigned short *)0x50008004) +#define rUFCON2 (*(volatile unsigned char *)0x50008008) +#define rUTRSTAT2 (*(volatile unsigned char *)0x50008010) +#define rUERSTAT2 (*(volatile unsigned char *)0x50008014) +#define rUFSTAT2 (*(volatile unsigned short *)0x50008018) +#define rUBRDIV2 (*(volatile unsigned short *)0x50008028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x50000023) +#define rURXH0 (*(volatile unsigned char *)0x50000027) +#define rUTXH1 (*(volatile unsigned char *)0x50004023) +#define rURXH1 (*(volatile unsigned char *)0x50004027) +#define rUTXH2 (*(volatile unsigned char *)0x50008023) +#define rURXH2 (*(volatile unsigned char *)0x50008027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#define UTXH0 (0x50000020+3) /* byte_access address by DMA */ +#define URXH0 (0x50000024+3) +#define UTXH1 (0x50004020+3) +#define URXH1 (0x50004024+3) +#define UTXH2 (0x50008020+3) +#define URXH2 (0x50008024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x50000020) +#define rURXH0 (*(volatile unsigned char *)0x50000024) +#define rUTXH1 (*(volatile unsigned char *)0x50004020) +#define rURXH1 (*(volatile unsigned char *)0x50004024) +#define rUTXH2 (*(volatile unsigned char *)0x50008020) +#define rURXH2 (*(volatile unsigned char *)0x50008024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#define UTXH0 (0x50000020) +#define URXH0 (0x50000024) +#define UTXH1 (0x50004020) +#define URXH1 (0x50004024) +#define UTXH2 (0x50008020) +#define URXH2 (0x50008024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x51000000) +#define rTCFG1 (*(volatile unsigned *)0x51000004) +#define rTCON (*(volatile unsigned *)0x51000008) +#define rTCNTB0 (*(volatile unsigned *)0x5100000C) +#define rTCMPB0 (*(volatile unsigned *)0x51000010) +#define rTCNTO0 (*(volatile unsigned *)0x51000014) +#define rTCNTB1 (*(volatile unsigned *)0x51000018) +#define rTCMPB1 (*(volatile unsigned *)0x5100001C) +#define rTCNTO1 (*(volatile unsigned *)0x51000020) +#define rTCNTB2 (*(volatile unsigned *)0x51000024) +#define rTCMPB2 (*(volatile unsigned *)0x51000028) +#define rTCNTO2 (*(volatile unsigned *)0x5100002C) +#define rTCNTB3 (*(volatile unsigned *)0x51000030) +#define rTCMPB3 (*(volatile unsigned *)0x51000034) +#define rTCNTO3 (*(volatile unsigned *)0x51000038) +#define rTCNTB4 (*(volatile unsigned *)0x5100003C) +#define rTCNTO4 (*(volatile unsigned *)0x51000040) + + +/* USB DEVICE */ +#ifdef __BIG_ENDIAN +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address +#define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management +#define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear +#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte +#define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index +#define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet +#define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status +#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO +#define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO +#define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO +#define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO +#define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter +#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter +#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) +#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter +#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter +#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) +#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter +#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter +#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) +#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter +#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter +#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) +#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) + +#else // Little Endian +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address +#define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management +#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear +#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte +#define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index +#define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet +#define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status +#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO +#define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO +#define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO +#define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO +#define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter +#define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter +#define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) +#define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter +#define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter +#define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) +#define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter +#define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter +#define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) +#define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter +#define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter +#define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) +#define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) +#endif // __BIG_ENDIAN + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x53000000) +#define rWTDAT (*(volatile unsigned *)0x53000004) +#define rWTCNT (*(volatile unsigned *)0x53000008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x54000000) +#define rIICSTAT (*(volatile unsigned *)0x54000004) +#define rIICADD (*(volatile unsigned *)0x54000008) +#define rIICDS (*(volatile unsigned *)0x5400000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x55000000) +#define rIISMOD (*(volatile unsigned *)0x55000004) +#define rIISPSR (*(volatile unsigned *)0x55000008) +#define rIISFIFCON (*(volatile unsigned *)0x5500000C) + +#ifdef __BIG_ENDIAN +#define IISFIFO ((volatile unsigned short *)0x55000012) + +#else /* Little Endian */ +#define IISFIFO ((volatile unsigned short *)0x55000010) +#endif + + +/* I/O PORT */ +#define rGPACON (*(volatile unsigned *)0x56000000) //Port A control +#define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data + +#define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control +#define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data +#define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B + +#define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control +#define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data +#define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C + +#define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control +#define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data +#define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D + +#define rGPECON (*(volatile unsigned *)0x56000040) //Port E control +#define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data +#define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E + +#define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control +#define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data +#define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F + +#define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control +#define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data +#define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G + +#define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control +#define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data +#define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H + +#define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control +#define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control +#define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0 +#define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1 +#define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2 +#define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved +#define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved +#define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2 +#define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3 +#define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask +#define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending +#define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status +#define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000) + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control +#define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count +#define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control +#define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second +#define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute +#define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour +#define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon +#define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month +#define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year +#define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset +#define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second +#define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute +#define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour +#define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon +#define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon +#define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month +#define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year + +#else //Little Endian +#define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control +#define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count +#define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control +#define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second +#define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute +#define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour +#define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon +#define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month +#define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year +#define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset +#define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second +#define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute +#define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour +#define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon +#define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon +#define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month +#define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year +#endif //RTC + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x58000000) +#define rADCTSC (*(volatile unsigned *)0x58000004) +#define rADCDLY (*(volatile unsigned *)0x58000008) +#define rADCDAT0 (*(volatile unsigned *)0x5800000c) +#define rADCDAT1 (*(volatile unsigned *)0x58000010) + + +/* SPI */ +#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control +#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status +#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control +#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler +#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data +#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data + +#define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control +#define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status +#define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control +#define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler +#define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data +#define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data + +/* SD interface */ +#define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control +#define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler +#define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument +#define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control +#define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status +#define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0 +#define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1 +#define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2 +#define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3 +#define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer +#define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size +#define rSDIDATCON (*(volatile unsigned *)0x5a00002c) //SDI data control +#define rSDIDATCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter +#define rSDIDATSTA (*(volatile unsigned *)0x5a000034) //SDI data status +#define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status +#define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask. edited for 2440A + +#ifdef __BIG_ENDIAN +#define rSDIDAT (*(volatile unsigned *)0x5a00003F) //SDI data +#define SDIDAT 0x5a00003F +#else // Little Endian +#define rSDIDAT (*(volatile unsigned *)0x5a00003C) //SDI data +#define SDIDAT 0x5a00003C +#endif //SD Interface + + +#define _ISR_STARTADDRESS rtems_vector_table +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#ifndef ASM +/* Typedefs */ +typedef union { + struct _reg { + unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */ + /* cleared automatically. */ + unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */ + /* automatically. To enter SL_IDLE mode, */ + /* CLKCON register has to be 0xe. */ + unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ + /* automatically. */ + unsigned POWER_OFF:1; + unsigned NAND_flash:1; + unsigned LCDC:1; /* Controls HCLK into LCDC block */ + unsigned USB_host:1; /* Controls HCLK into USB host block */ + unsigned USB_device:1; /* Controls PCLK into USB device block */ + unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ + unsigned SDI:1; /* Controls PCLK into MMC interface block */ + unsigned UART0:1; /* Controls PCLK into UART0 block */ + unsigned UART1:1; /* Controls PCLK into UART1 block */ + unsigned UART2:1; /* Controls PCLK into UART1 block */ + unsigned GPIO:1; /* Controls PCLK into GPIO block */ + unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ + /* this bit is cleared to 0, RTC timer is alive. */ + unsigned ADC:1; /* Controls PCLK into ADC block */ + unsigned IIC:1; /* Controls PCLK into IIC block */ + unsigned IIS:1; /* Controls PCLK into IIS block */ + unsigned SPI:1; /* Controls PCLK into SPI block */ + } reg; + unsigned long all; +} CLKCON; + +typedef union +{ + struct { + unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ + unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ + /* 1110 = 16 bpp TFT skipmode */ + unsigned PNRMODE:2; /* TFT: 3 */ + unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ + /* 0 = Each Frame, 1 = The rate defined by the MVAL */ + unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ + unsigned LINECNT:10; /* (read only) These bits provide the status of the */ + /* line counter. Down count from LINEVAL to 0 */ + } reg; + unsigned long all; +} LCDCON1; + +typedef union { + struct { + unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ + /* VSYNC pulse's high level width by counting the */ + /* number of inactive lines. */ + unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ + /* inactive lines at the end of a frame, before */ + /* vertical synchronization period. */ + unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ + /* of LCD panel. */ + unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ + /* lines at the start of a frame, after */ + /* vertical synchronization period. */ + } reg; + unsigned long all; +} LCDCON2; + +typedef union { + struct { + unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ + /* VCLK periods between the end of active data */ + /* and the rising edge of HSYNC. */ + unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ + /* size of LCD panel. 2n bytes. */ + unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ + /* periods between the falling edge of HSYNC and */ + /* the start of active data. */ + } reg; + unsigned long all; +} LCDCON3; + +typedef union { + struct { + unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ + /* HSYNC pulse's high level width by counting the */ + /* number of the VCLK. */ + unsigned MVAL:8; /* STN: */ + } reg; + unsigned long all; +} LCDCON4; + +typedef union { + struct { + unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ + /* 0 = Swap Disable 1 = Swap Enable */ + unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ + /* 0 = Disable LEND signal. */ + /* 1 = Enable LEND signal */ + unsigned PWREN:1; + unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */ + /* polarity. 0 = normal 1 = inverted */ + unsigned INVPWREN:1; + unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ + /* polarity. */ + /* 0 = normal 1 = inverted */ + unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ + /* pulse polarity. 0 = Normal. */ + /* 1 = VD is inverted. */ + unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ + /* pulse polarity. 0 = normal 1 = inverted */ + unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ + /* VCLK active edge. 0 = The video data is */ + /* fetched at VCLK falling edge. 1 = The video */ + /* data is fetched at VCLK rising edge */ + unsigned FRM565:1; + unsigned BPP24BL:1; + unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ + /* 00 = HSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned _VSTATUS:2; /* TFT: Vertical Status (Read only). */ + /* 00 = VSYNC */ + /* 01 = BACK Porch. */ + /* 10 = ACTIVE */ + /* 11 = FRONT Porch */ + unsigned RESERVED:16; + } reg; + unsigned long all; +} LCDCON5; + +typedef union { + struct { + unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ + /* A[21:1] of the start address of the LCD */ + /* frame buffer. */ + unsigned LCDBANK:9; /* A[28:22] */ + } reg; + unsigned long all; +} LCDSADDR1; + +typedef union { + struct { + unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ + /* of the end address of the LCD frame buffer. */ + /* LCDBASEL = ((the fame end address) >>1) + 1 */ + /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ + } reg; + unsigned long all; +} LCDSADDR2; + +typedef union { + struct { + unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ + /* words) This value defines the width of the */ + /* view port in the frame */ + unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ + /* words) This value defines the difference */ + /* between the address of the last half word */ + /* displayed on the previous LCD line and the */ + /* address of the first half word to be */ + /* displayed in the new LCD line. */ + } reg; + unsigned long all; +} LCDSADDR3; + +/* + * + */ + +typedef union { + struct { + unsigned IISIFENA:1; /* IIS interface enable (start) */ + unsigned IISPSENA:1; /* IIS prescaler enable */ + unsigned RXCHIDLE:1; /* Receive channel idle command */ + unsigned TXCHIDLE:1; /* Transmit channel idle command */ + unsigned RXDMAENA:1; /* Receive DMA service request enable */ + unsigned TXDMAENA:1; /* Transmit DMA service request enable */ + unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ + unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ + unsigned LRINDEX:1; /* Left/right channel index (read only) */ + } reg; + unsigned long all; +} IISCON; + +typedef union { + struct { + unsigned SBCLKFS:2; /* Serial bit clock frequency select */ + unsigned MCLKFS:1; /* Master clock frequency select */ + unsigned SDBITS:1; /* Serial data bit per channel */ + unsigned SIFMT:1; /* Serial interface format */ + unsigned ACTLEVCH:1; /* Active level pf left/right channel */ + unsigned TXRXMODE:2; /* Transmit/receive mode select */ + unsigned MODE:1; /* Master/slave mode select */ + } reg; + unsigned long all; +} IISMOD; + +typedef union { + struct { + unsigned PSB:5; /* Prescaler control B */ + unsigned PSA:5; /* Prescaler control A */ + } reg; + unsigned long all; +} IISPSR; + +typedef union { + struct { + unsigned RXFIFOCNT:6; /* (read only) */ + unsigned TXFIFOCNT:6; /* (read only) */ + unsigned RXFIFOENA:1; /* */ + unsigned TXFIFOENA:1; /* */ + unsigned RXFIFOMODE:1; /* */ + unsigned TXFIFOMODE:1; /* */ + } reg; + unsigned long all; +} IISSFIFCON; + +typedef union { + struct { + unsigned FENTRY:16; /* */ + } reg; + unsigned long all; +} IISSFIF; +#endif //ASM + +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) + +#define SMDK2410_KEY_SELECT 512 +#define SMDK2410_KEY_START 256 +#define SMDK2410_KEY_A 64 +#define SMDK2410_KEY_B 32 +#define SMDK2410_KEY_L 16 +#define SMDK2410_KEY_R 128 +#define SMDK2410_KEY_UP 8 +#define SMDK2410_KEY_DOWN 2 +#define SMDK2410_KEY_LEFT 1 +#define SMDK2410_KEY_RIGHT 4 + +#endif /*S3C2410_H_*/ diff --git a/bsps/arm/smdk2410/include/s3c24xx.h b/bsps/arm/smdk2410/include/s3c24xx.h new file mode 100644 index 0000000000..914b867abf --- /dev/null +++ b/bsps/arm/smdk2410/include/s3c24xx.h @@ -0,0 +1,17 @@ +/************************************************ + * NAME : s3c2400.h + * Version : 4.18.2008 + * + * share code for different Samsung CPU + ************************************************/ + +#ifndef S3C24XX_H_ +#define S3C24XX_H_ + +#ifdef CPU_S3C2400 +#include +#elif defined CPU_S3C2410 +#include +#endif + +#endif /*S3C24XX_H_*/ diff --git a/bsps/arm/smdk2410/include/smc.h b/bsps/arm/smdk2410/include/smc.h new file mode 100644 index 0000000000..10ec14a771 --- /dev/null +++ b/bsps/arm/smdk2410/include/smc.h @@ -0,0 +1,44 @@ +/** + * @file + * @ingroup smdk2410_smc + * @brief SMC disk driver initialization entry point + */ + +#ifndef __SMC_H__ +#define __SMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "rtems/blkdev.h" + +/** + * @defgroup smdk2410_smc SMC Disk Driver + * @ingroup arm_smdk2410 + * @brief SMC Disk Driver Support + * @{ + */ + +/** + * @brief smc_initialize + * SMC disk driver initialization entry point. + */ +rtems_device_driver +smc_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#define SMC_DRIVER_TABLE_ENTRY \ + { smc_initialize, GENERIC_BLOCK_DEVICE_DRIVER_ENTRIES } + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/arm/smdk2410/include/tm27.h b/bsps/arm/smdk2410/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/smdk2410/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/stm32f4/headers.am b/bsps/arm/stm32f4/headers.am new file mode 100644 index 0000000000..f1270b546e --- /dev/null +++ b/bsps/arm/stm32f4/headers.am @@ -0,0 +1,29 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/stm32f4/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/io.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32_i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32_usart.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h +include_bsp_HEADERS += ../../../../../../bsps/arm/stm32f4/include/bsp/usart.h diff --git a/bsps/arm/stm32f4/include/bsp.h b/bsps/arm/stm32f4/include/bsp.h new file mode 100644 index 0000000000..50052bc810 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp.h @@ -0,0 +1,54 @@ +/** + * @file + * @ingroup arm_stm34f4 + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup arm_stm32f4 STM32F4 Support + * @ingroup bsp_arm + * @brief STM32f4 Support Package + * @{ + */ + +#ifndef LIBBSP_ARM_STM32F4_BSP_H +#define LIBBSP_ARM_STM32F4_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_BSP_H */ diff --git a/bsps/arm/stm32f4/include/bsp/i2c.h b/bsps/arm/stm32f4/include/bsp/i2c.h new file mode 100644 index 0000000000..fa18b1f92f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/i2c.h @@ -0,0 +1,96 @@ +/** + * @file + * @ingroup stm32f4_i2c I2C Support + * @brief I2C-module. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* The I2C-module can not run with libi2c. The reason for this is, that libi2c + * needs a possibility to generate a stop condition separately. This controller + * wants to generate the condition automatically when sending or receiving data. + */ + +#ifndef LIBBSP_ARM_STM32F4_I2C_H +#define LIBBSP_ARM_STM32F4_I2C_H + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_i2c I2C Support + * @ingroup arm_stm32f4 + * @brief I2C Module + * @{ + */ + +typedef struct { + /** + * @brief The address of the slave without the read write bit. + * A 7-Bit address should be placed in the bits [6..0] + */ + uint16_t addr; + /** @brief Read (true) or write (false) data */ + bool read; + /** @brief Size of data to read or write */ + size_t len; + /** @brief Buffer for data */ + uint8_t *buf; +} stm32f4_i2c_message; + +typedef struct { + volatile stm32f4_i2c *regs; + size_t index; + rtems_vector_number vector; + rtems_id mutex; + rtems_id task_id; + uint8_t *data; + uint8_t *last; + size_t len; + bool read; + uint8_t addr_with_rw; +} stm32f4_i2c_bus_entry; + +/** @brief Initialise the i2c module. */ +rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e); + +/** @brief Process a i2c message */ +rtems_status_code stm32f4_i2c_process_message( + stm32f4_i2c_bus_entry *e, + stm32f4_i2c_message *msg +); + +/** @brief Set another baud rate than the default one */ +rtems_status_code stm32f4_i2c_set_bitrate( + stm32f4_i2c_bus_entry *e, + uint32_t br +); + +extern stm32f4_i2c_bus_entry *const stm32f4_i2c1; +extern stm32f4_i2c_bus_entry *const stm32f4_i2c2; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_I2C_H */ diff --git a/bsps/arm/stm32f4/include/bsp/io.h b/bsps/arm/stm32f4/include/bsp/io.h new file mode 100644 index 0000000000..b7f8669cba --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/io.h @@ -0,0 +1,416 @@ +/** + * @file + * @ingroup stm32f4_io + * @brief IO support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_IO_H +#define LIBBSP_ARM_STM32F4_IO_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_io IO Support + * @ingroup arm_stm32f4 + * @brief IO Support + * @{ + */ + +#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) + +#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) + +#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @name Family F4XXXX + * @{ + */ + +typedef enum { + STM32F4_GPIO_MODE_INPUT, + STM32F4_GPIO_MODE_OUTPUT, + STM32F4_GPIO_MODE_AF, + STM32F4_GPIO_MODE_ANALOG +} stm32f4_gpio_mode; + +typedef enum { + STM32F4_GPIO_OTYPE_PUSH_PULL, + STM32F4_GPIO_OTYPE_OPEN_DRAIN +} stm32f4_gpio_otype; + +typedef enum { + STM32F4_GPIO_OSPEED_2_MHZ, + STM32F4_GPIO_OSPEED_25_MHZ, + STM32F4_GPIO_OSPEED_50_MHZ, + STM32F4_GPIO_OSPEED_100_MHZ +} stm32f4_gpio_ospeed; + +typedef enum { + STM32F4_GPIO_NO_PULL, + STM32F4_GPIO_PULL_UP, + STM32F4_GPIO_PULL_DOWN +} stm32f4_gpio_pull; + +typedef enum { + STM32F4_GPIO_AF_SYSTEM = 0, + STM32F4_GPIO_AF_TIM1 = 1, + STM32F4_GPIO_AF_TIM2 = 1, + STM32F4_GPIO_AF_TIM3 = 2, + STM32F4_GPIO_AF_TIM4 = 2, + STM32F4_GPIO_AF_TIM5 = 2, + STM32F4_GPIO_AF_TIM8 = 3, + STM32F4_GPIO_AF_TIM9 = 3, + STM32F4_GPIO_AF_TIM10 = 3, + STM32F4_GPIO_AF_TIM11 = 3, + STM32F4_GPIO_AF_I2C1 = 4, + STM32F4_GPIO_AF_I2C2 = 4, + STM32F4_GPIO_AF_I2C3 = 4, + STM32F4_GPIO_AF_SPI1 = 5, + STM32F4_GPIO_AF_SPI2 = 5, + STM32F4_GPIO_AF_SPI3 = 6, + STM32F4_GPIO_AF_USART1 = 7, + STM32F4_GPIO_AF_USART2 = 7, + STM32F4_GPIO_AF_USART3 = 7, + STM32F4_GPIO_AF_UART4 = 8, + STM32F4_GPIO_AF_UART5 = 8, + STM32F4_GPIO_AF_USART6 = 8, + STM32F4_GPIO_AF_CAN1 = 9, + STM32F4_GPIO_AF_CAN2 = 9, + STM32F4_GPIO_AF_TIM12 = 9, + STM32F4_GPIO_AF_TIM13 = 9, + STM32F4_GPIO_AF_TIM14 = 9, + STM32F4_GPIO_AF_OTG_FS = 10, + STM32F4_GPIO_AF_OTG_HS = 10, + STM32F4_GPIO_AF_ETH = 11, + STM32F4_GPIO_AF_FSMC = 12, + STM32F4_GPIO_AF_OTG_HS_FS = 12, + STM32F4_GPIO_AF_SDIO = 12, + STM32F4_GPIO_AF_DCMI = 13, + STM32F4_GPIO_AF_EVENTOUT = 15 +} stm32f4_gpio_af; + +typedef union { + struct { + uint32_t pin_first : 8; + uint32_t pin_last : 8; + uint32_t mode : 2; + uint32_t otype : 1; + uint32_t ospeed : 2; + uint32_t pupd : 2; + uint32_t output : 1; + uint32_t af : 4; + uint32_t reserved : 4; + } fields; + + uint32_t value; +} stm32f4_gpio_config; + +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name Family F10XXX + * @{ + */ + +typedef enum { + STM32F4_GPIO_MODE_INPUT, + STM32F4_GPIO_MODE_OUTPUT_10MHz, + STM32F4_GPIO_MODE_OUTPUT_2MHz, + STM32F4_GPIO_MODE_OUTPUT_50MHz +} stm32f4_gpio_mode; + +typedef enum { + STM32F4_GPIO_CNF_IN_ANALOG = 0, + STM32F4_GPIO_CNF_IN_FLOATING = 1, + STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2, + + STM32F4_GPIO_CNF_OUT_GPIO_PP = 0, + STM32F4_GPIO_CNF_OUT_GPIO_OD = 1, + STM32F4_GPIO_CNF_OUT_AF_PP = 2, + STM32F4_GPIO_CNF_OUT_AF_OD = 3, +} stm32f4_gpio_cnf; + +typedef enum { + STM32F4_GPIO_REMAP_DONT_CHANGE, + STM32F4_GPIO_REMAP_SPI1_0, + STM32F4_GPIO_REMAP_SPI1_1, + STM32F4_GPIO_REMAP_I2C1_0, + STM32F4_GPIO_REMAP_I2C1_1, + STM32F4_GPIO_REMAP_USART1_0, + STM32F4_GPIO_REMAP_USART1_1, + STM32F4_GPIO_REMAP_USART2_0, + STM32F4_GPIO_REMAP_USART2_1, + STM32F4_GPIO_REMAP_USART3_0, + STM32F4_GPIO_REMAP_USART3_1, + STM32F4_GPIO_REMAP_USART3_3, + STM32F4_GPIO_REMAP_TIM1_0, + STM32F4_GPIO_REMAP_TIM1_1, + STM32F4_GPIO_REMAP_TIM1_3, + STM32F4_GPIO_REMAP_TIM2_0, + STM32F4_GPIO_REMAP_TIM2_1, + STM32F4_GPIO_REMAP_TIM2_2, + STM32F4_GPIO_REMAP_TIM2_3, + STM32F4_GPIO_REMAP_TIM3_0, + STM32F4_GPIO_REMAP_TIM3_2, + STM32F4_GPIO_REMAP_TIM3_3, + STM32F4_GPIO_REMAP_TIM4_0, + STM32F4_GPIO_REMAP_TIM4_1, + STM32F4_GPIO_REMAP_CAN1_0, + STM32F4_GPIO_REMAP_CAN1_2, + STM32F4_GPIO_REMAP_CAN1_3, + STM32F4_GPIO_REMAP_PD01_0, + STM32F4_GPIO_REMAP_PD01_1, + STM32F4_GPIO_REMAP_TIM5CH4_0, + STM32F4_GPIO_REMAP_TIM5CH4_1, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, + STM32F4_GPIO_REMAP_ETH_0, + STM32F4_GPIO_REMAP_ETH_1, + STM32F4_GPIO_REMAP_CAN2_0, + STM32F4_GPIO_REMAP_CAN2_1, + STM32F4_GPIO_REMAP_MII_RMII_0, + STM32F4_GPIO_REMAP_MII_RMII_1, + STM32F4_GPIO_REMAP_SWJ_0, + STM32F4_GPIO_REMAP_SWJ_1, + STM32F4_GPIO_REMAP_SWJ_2, + STM32F4_GPIO_REMAP_SWJ_4, + STM32F4_GPIO_REMAP_SPI3_0, + STM32F4_GPIO_REMAP_SPI3_1, + STM32F4_GPIO_REMAP_TIM2ITR1_0, + STM32F4_GPIO_REMAP_TIM2ITR1_1, + STM32F4_GPIO_REMAP_PTP_PPS_0, + STM32F4_GPIO_REMAP_PTP_PPS_1, + STM32F4_GPIO_REMAP_TIM15_0, + STM32F4_GPIO_REMAP_TIM15_1, + STM32F4_GPIO_REMAP_TIM16_0, + STM32F4_GPIO_REMAP_TIM16_1, + STM32F4_GPIO_REMAP_TIM17_0, + STM32F4_GPIO_REMAP_TIM17_1, + STM32F4_GPIO_REMAP_CEC_0, + STM32F4_GPIO_REMAP_CEC_1, + STM32F4_GPIO_REMAP_TIM1_DMA_0, + STM32F4_GPIO_REMAP_TIM1_DMA_1, + STM32F4_GPIO_REMAP_TIM9_0, + STM32F4_GPIO_REMAP_TIM9_1, + STM32F4_GPIO_REMAP_TIM10_0, + STM32F4_GPIO_REMAP_TIM10_1, + STM32F4_GPIO_REMAP_TIM11_0, + STM32F4_GPIO_REMAP_TIM11_1, + STM32F4_GPIO_REMAP_TIM13_0, + STM32F4_GPIO_REMAP_TIM13_1, + STM32F4_GPIO_REMAP_TIM14_0, + STM32F4_GPIO_REMAP_TIM14_1, + STM32F4_GPIO_REMAP_FSMC_0, + STM32F4_GPIO_REMAP_FSMC_1, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, + STM32F4_GPIO_REMAP_TIM12_0, + STM32F4_GPIO_REMAP_TIM12_1, + STM32F4_GPIO_REMAP_MISC_0, + STM32F4_GPIO_REMAP_MISC_1, +} stm32f4_gpio_remap; + +typedef union { + struct { + uint32_t pin_first : 8; + uint32_t pin_last : 8; + uint32_t mode : 2; + uint32_t cnf : 2; + uint32_t output : 1; + uint32_t remap : 8; + uint32_t reserved : 3; + } fields; + + uint32_t value; +} stm32f4_gpio_config; + +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } } + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +extern const stm32f4_gpio_config stm32f4_start_config_gpio []; + +void stm32f4_gpio_set_clock(int pin, bool set); + +void stm32f4_gpio_set_config(const stm32f4_gpio_config *config); + +/** + * @brief Sets the GPIO configuration of an array terminated by + * STM32F4_GPIO_CONFIG_TERMINAL. + */ +void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs); + +void stm32f4_gpio_set_output(int pin, bool set); + +bool stm32f4_gpio_get_input(int pin); + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @name Family F4XXXX + * @{ + */ + +#define STM32F4_PIN_USART(port, idx, altfunc) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_AF, \ + .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \ + .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \ + .pupd = STM32F4_GPIO_PULL_UP, \ + .af = altfunc \ + } \ + } + +#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1) +#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1) + +#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2) +#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2) + +#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3) +#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3) + +#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4) +#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4) + +#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5) +#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5) + +#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6) +#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6) + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name Family F10XXX + * @{ + */ + +#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ + .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_INPUT, \ + .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1) +#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1) + +#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1) +#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1) + +#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3) +#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3) + +#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#define STM32F4_PIN_I2C(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ + .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0) +#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0) +#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1) +#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1) + +#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_IO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/irq.h b/bsps/arm/stm32f4/include/bsp/irq.h new file mode 100644 index 0000000000..4771f521fe --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/irq.h @@ -0,0 +1,141 @@ +/** + * @file + * @ingroup stm32f4_interrupt + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_IRQ_H +#define LIBBSP_ARM_STM32F4_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +/** + * @defgroup stm32f4_interrupt Interrupt Support + * @ingroup arm_stm32f4 + * @brief Interrupt Support + * @{ + */ + +#define STM32F4_IRQ_WWDG 0 +#define STM32F4_IRQ_PVD 1 +#define STM32F4_IRQ_TAMP_STAMP 2 +#define STM32F4_IRQ_RTC_WKUP 3 +#define STM32F4_IRQ_FLASH 4 +#define STM32F4_IRQ_RCC 5 +#define STM32F4_IRQ_EXTI0 6 +#define STM32F4_IRQ_EXTI1 7 +#define STM32F4_IRQ_EXTI2 8 +#define STM32F4_IRQ_EXTI3 9 +#define STM32F4_IRQ_EXTI4 10 +#define STM32F4_IRQ_DMA1_STREAM0 11 +#define STM32F4_IRQ_DMA1_STREAM1 12 +#define STM32F4_IRQ_DMA1_STREAM2 13 +#define STM32F4_IRQ_DMA1_STREAM3 14 +#define STM32F4_IRQ_DMA1_STREAM4 15 +#define STM32F4_IRQ_DMA1_STREAM5 16 +#define STM32F4_IRQ_DMA1_STREAM6 17 +#define STM32F4_IRQ_ADC 18 +#define STM32F4_IRQ_CAN1_TX 19 +#define STM32F4_IRQ_CAN1_RX0 20 +#define STM32F4_IRQ_CAN1_RX1 21 +#define STM32F4_IRQ_CAN1_SCE 22 +#define STM32F4_IRQ_EXTI9_5 23 +#define STM32F4_IRQ_TIM1_BRK_TIM9 24 +#define STM32F4_IRQ_TIM1_UP_TIM10 25 +#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26 +#define STM32F4_IRQ_TIM1_CC 27 +#define STM32F4_IRQ_TIM2 28 +#define STM32F4_IRQ_TIM3 29 +#define STM32F4_IRQ_TIM4 30 +#define STM32F4_IRQ_I2C1_EV 31 +#define STM32F4_IRQ_I2C1_ER 32 +#define STM32F4_IRQ_I2C2_EV 33 +#define STM32F4_IRQ_I2C2_ER 34 +#define STM32F4_IRQ_SPI1 35 +#define STM32F4_IRQ_SPI2 36 +#define STM32F4_IRQ_USART1 37 +#define STM32F4_IRQ_USART2 38 +#define STM32F4_IRQ_USART3 39 +#define STM32F4_IRQ_EXTI15_10 40 +#define STM32F4_IRQ_RTC_ALARM 41 +#define STM32F4_IRQ_OTG_FS_WKUP 42 +#define STM32F4_IRQ_TIM8_BRK_TIM12 43 +#define STM32F4_IRQ_TIM8_UP_TIM13 44 +#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45 +#define STM32F4_IRQ_TIM8_CC 46 +#define STM32F4_IRQ_DMA1_STREAM7 47 +#define STM32F4_IRQ_FSMC 48 +#define STM32F4_IRQ_SDIO 49 +#define STM32F4_IRQ_TIM5 50 +#define STM32F4_IRQ_SPI3 51 +#define STM32F4_IRQ_UART4 52 +#define STM32F4_IRQ_UART5 53 +#define STM32F4_IRQ_TIM6_DAC 54 +#define STM32F4_IRQ_TIM7 55 +#define STM32F4_IRQ_DMA2_STREAM0 56 +#define STM32F4_IRQ_DMA2_STREAM1 57 +#define STM32F4_IRQ_DMA2_STREAM2 58 +#define STM32F4_IRQ_DMA2_STREAM3 59 +#define STM32F4_IRQ_DMA2_STREAM4 60 +#define STM32F4_IRQ_ETH 61 +#define STM32F4_IRQ_ETH_WKUP 62 +#define STM32F4_IRQ_CAN2_TX 63 +#define STM32F4_IRQ_CAN2_RX0 64 +#define STM32F4_IRQ_CAN2_RX1 65 +#define STM32F4_IRQ_CAN2_SCE 66 +#define STM32F4_IRQ_OTG_FS 67 +#define STM32F4_IRQ_DMA2_STREAM5 68 +#define STM32F4_IRQ_DMA2_STREAM6 69 +#define STM32F4_IRQ_DMA2_STREAM7 70 +#define STM32F4_IRQ_USART6 71 +#define STM32F4_IRQ_I2C3_EV 72 +#define STM32F4_IRQ_I2C3_ER 73 +#define STM32F4_IRQ_OTG_HS_EP1_OUT 74 +#define STM32F4_IRQ_OTG_HS_EP1_IN 75 +#define STM32F4_IRQ_OTG_HS_WKUP 76 +#define STM32F4_IRQ_OTG_HS 77 +#define STM32F4_IRQ_DCMI 78 +#define STM32F4_IRQ_CRYP 79 +#define STM32F4_IRQ_HASH_RNG 80 +#define STM32F4_IRQ_FPU 81 + +#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0 +#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15 +#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1) +#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN +#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 81 + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_IRQ_H */ diff --git a/bsps/arm/stm32f4/include/bsp/rcc.h b/bsps/arm/stm32f4/include/bsp/rcc.h new file mode 100644 index 0000000000..f1bd7d173c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/rcc.h @@ -0,0 +1,196 @@ +/** + * @file + * @ingroup stm32f4_rcc + * @brief RCC support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_RCC_H +#define LIBBSP_ARM_STM32F4_RCC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup stm32f4_rcc RCC Support + * @ingroup arm_stm32f4 + * @brief RCC Support + * @{ + */ + +#define STM32F4_RCC_INDEX(reg, idx) (((reg) << 5) | (idx)) + +typedef enum { +#ifdef STM32F4_FAMILY_F4XXXX + + /** + * @name Family F4XXXX + * @{ + */ + + STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29), + STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25), + STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 22), + STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 21), + STM32F4_RCC_CRC = STM32F4_RCC_INDEX(0, 12), + STM32F4_RCC_GPIOI = STM32F4_RCC_INDEX(0, 8), + STM32F4_RCC_GPIOH = STM32F4_RCC_INDEX(0, 7), + STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(0, 6), + STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(0, 5), + STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(0, 4), + STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(0, 3), + STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(0, 2), + STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(0, 1), + STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(0, 0), + + STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(1, 7), + STM32F4_RCC_RNG = STM32F4_RCC_INDEX(1, 6), + STM32F4_RCC_HASH = STM32F4_RCC_INDEX(1, 5), + STM32F4_RCC_CRYP = STM32F4_RCC_INDEX(1, 4), + STM32F4_RCC_DCMI = STM32F4_RCC_INDEX(1, 0), + + STM32F4_RCC_FSMCR = STM32F4_RCC_INDEX(2, 0), + + STM32F4_RCC_DAC = STM32F4_RCC_INDEX(4, 29), + STM32F4_RCC_PWR = STM32F4_RCC_INDEX(4, 28), + STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(4, 26), + STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(4, 25), + STM32F4_RCC_I2C3 = STM32F4_RCC_INDEX(4, 23), + STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(4, 22), + STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(4, 21), + STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(4, 20), + STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(4, 19), + STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(4, 18), + STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(4, 17), + STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(4, 15), + STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(4, 14), + STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(4, 11), + STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(4, 8), + STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(4, 7), + STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(4, 6), + STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(4, 5), + STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(4, 4), + STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(4, 3), + STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(4, 2), + STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(4, 1), + STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(4, 0), + + STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(5, 18), + STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(5, 17), + STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(5, 16), + STM32F4_RCC_SYSCFG = STM32F4_RCC_INDEX(5, 14), + STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(5, 12), + STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(5, 11), + STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(5, 10), + STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(5, 9), + STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(5, 8), + STM32F4_RCC_USART6 = STM32F4_RCC_INDEX(5, 5), + STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(5, 4), + STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1), + STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0), + + /** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + + /** + * @name Family F10 + * @{ + */ + + STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 0), + STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 1), + STM32F4_RCC_SRAM = STM32F4_RCC_INDEX(0, 2), + STM32F4_RCC_FLITF = STM32F4_RCC_INDEX(0, 4), + STM32F4_RCC_CRCEN = STM32F4_RCC_INDEX(0, 6), + STM32F4_RCC_FSMC = STM32F4_RCC_INDEX(0, 8), + STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(0, 10), + STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(0, 12), + STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 14), + STM32F4_RCC_ETHMACTX = STM32F4_RCC_INDEX(0, 15), + STM32F4_RCC_ETHMACRX = STM32F4_RCC_INDEX(0, 16), + + STM32F4_RCC_AFIO = STM32F4_RCC_INDEX(1, 0), + STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(1, 2), + STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(1, 3), + STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(1, 4), + STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(1, 5), + STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(1, 6), + STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(1, 7), + STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(1, 8), + STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(1, 9), + STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(1, 10), + STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(1, 11), + STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(1, 12), + STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(1, 13), + STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(1, 14), + STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(1, 15), + STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(1, 19), + STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(1, 20), + STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(1, 21), + + STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(2, 0), + STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(2, 1), + STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(2, 2), + STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(2, 3), + STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(2, 4), + STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(2, 5), + STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(2, 6), + STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(2, 7), + STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(2, 8), + STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(2, 11), + STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(2, 14), + STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(2, 15), + STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(2, 17), + STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(2, 18), + STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(2, 19), + STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(2, 20), + STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(2, 21), + STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(2, 22), + STM32F4_RCC_USB = STM32F4_RCC_INDEX(2, 23), + STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(2, 24), + STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(2, 25), + STM32F4_RCC_BKP = STM32F4_RCC_INDEX(2, 27), + STM32F4_RCC_PWR = STM32F4_RCC_INDEX(2, 28), + STM32F4_RCC_DAC = STM32F4_RCC_INDEX(2, 29), + + /** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ +} stm32f4_rcc_index; + +void stm32f4_rcc_reset(stm32f4_rcc_index index); + +void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set); + +void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set); + +#ifdef STM32F4_FAMILY_F4XXXX +void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set); +#endif /* STM32F4_FAMILY_F4XXXX */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32_i2c.h b/bsps/arm/stm32f4/include/bsp/stm32_i2c.h new file mode 100644 index 0000000000..21d9b34ed1 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32_i2c.h @@ -0,0 +1,113 @@ +/** + * @file + * @ingroup stm32_i2c + * @brief STM32 I2C support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32_I2C_H +#define LIBBSP_ARM_STM32F4_STM32_I2C_H + +#include + +/** + * @defgroup stm32_i2c STM32 I2C Support + * @ingroup stm32f4_i2c + * @brief STM32 I2C Support + * @{ + */ + +typedef struct { + uint32_t cr1; +#define STM32F4_I2C_CR1_SWRST BSP_BIT32(15) +#define STM32F4_I2C_CR1_ALERT BSP_BIT32(13) +#define STM32F4_I2C_CR1_PEC BSP_BIT32(12) +#define STM32F4_I2C_CR1_POS BSP_BIT32(11) +#define STM32F4_I2C_CR1_ACK BSP_BIT32(10) +#define STM32F4_I2C_CR1_STOP BSP_BIT32(9) +#define STM32F4_I2C_CR1_START BSP_BIT32(8) +#define STM32F4_I2C_CR1_NOSTRETCH BSP_BIT32(7) +#define STM32F4_I2C_CR1_ENGC BSP_BIT32(6) +#define STM32F4_I2C_CR1_ENPEC BSP_BIT32(5) +#define STM32F4_I2C_CR1_ENARP BSP_BIT32(4) +#define STM32F4_I2C_CR1_SMBTYPE BSP_BIT32(3) +#define STM32F4_I2C_CR1_SMBUS BSP_BIT32(1) +#define STM32F4_I2C_CR1_PE BSP_BIT32(0) + uint32_t cr2; +#define STM32F4_I2C_CR2_LAST BSP_BIT32(12) +#define STM32F4_I2C_CR2_DMAEN BSP_BIT32(11) +#define STM32F4_I2C_CR2_ITBUFEN BSP_BIT32(10) +#define STM32F4_I2C_CR2_ITEVTEN BSP_BIT32(9) +#define STM32F4_I2C_CR2_ITERREN BSP_BIT32(8) +#define STM32F4_I2C_CR2_FREQ(val) BSP_FLD32(val, 0, 5) +#define STM32F4_I2C_CR2_FREQ_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_I2C_CR2_FREQ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t oar1; +#define STM32F4_I2C_OAR1_ADDMODE BSP_BIT32(15) +#define STM32F4_I2C_OAR1_ADD(val) BSP_FLD32(val, 0, 9) +#define STM32F4_I2C_OAR1_ADD_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define STM32F4_I2C_OAR1_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t oar2; +#define STM32F4_I2C_OAR2_ADD2(val) BSP_FLD32(val, 1, 7) +#define STM32F4_I2C_OAR2_ADD2_GET(reg) BSP_FLD32GET(reg, 1, 7) +#define STM32F4_I2C_OAR2_ADD2_SET(reg, val) BSP_FLD32SET(reg, val, 1, 7) +#define STM32F4_I2C_OAR2_ENDUAL BSP_BIT32(0) + uint32_t dr; +#define STM32F4_I2C_DR(val) BSP_FLD32(val, 0, 7) +#define STM32F4_I2C_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_I2C_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t sr1; +#define STM32F4_I2C_SR1_SMBALERT BSP_BIT32(15) +#define STM32F4_I2C_SR1_TIMEOUT BSP_BIT32(14) +#define STM32F4_I2C_SR1_PECERR BSP_BIT32(12) +#define STM32F4_I2C_SR1_OVR BSP_BIT32(11) +#define STM32F4_I2C_SR1_AF BSP_BIT32(10) +#define STM32F4_I2C_SR1_ARLO BSP_BIT32(9) +#define STM32F4_I2C_SR1_BERR BSP_BIT32(8) +#define STM32F4_I2C_SR1_TxE BSP_BIT32(7) +#define STM32F4_I2C_SR1_RxNE BSP_BIT32(6) +#define STM32F4_I2C_SR1_STOPF BSP_BIT32(4) +#define STM32F4_I2C_SR1_ADD10 BSP_BIT32(3) +#define STM32F4_I2C_SR1_BTF BSP_BIT32(2) +#define STM32F4_I2C_SR1_ADDR BSP_BIT32(1) +#define STM32F4_I2C_SR1_SB BSP_BIT32(0) + uint32_t sr2; +#define STM32F4_I2C_SR2_PEC(val) BSP_FLD32(val, 8, 15) +#define STM32F4_I2C_SR2_PEC_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_I2C_SR2_PEC_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_I2C_SR2_DUALF BSP_BIT32(7) +#define STM32F4_I2C_SR2_SMBHOST BSP_BIT32(6) +#define STM32F4_I2C_SR2_SMBDEFAULT BSP_BIT32(5) +#define STM32F4_I2C_SR2_GENCALL BSP_BIT32(4) +#define STM32F4_I2C_SR2_TRA BSP_BIT32(2) +#define STM32F4_I2C_SR2_BUSY BSP_BIT32(1) +#define STM32F4_I2C_SR2_MSL BSP_BIT32(0) + uint32_t ccr; +#define STM32F4_I2C_CCR_FS BSP_BIT32(15) +#define STM32F4_I2C_CCR_DUTY BSP_BIT32(14) +#define STM32F4_I2C_CCR_CCR(val) BSP_FLD32(val, 0, 11) +#define STM32F4_I2C_CCR_CCR_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_I2C_CCR_CCR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +#define STM32F4_I2C_CCR_CCR_MAX STM32F4_I2C_CCR_CCR_GET(BSP_MSK32(0, 11)) + uint32_t trise; +#define STM32F4_I2C_TRISE(val) BSP_FLD32(val, 0, 5) +#define STM32F4_I2C_TRISE_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_I2C_TRISE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +} stm32f4_i2c; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32_I2C_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32_usart.h b/bsps/arm/stm32f4/include/bsp/stm32_usart.h new file mode 100644 index 0000000000..c9c269533f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32_usart.h @@ -0,0 +1,110 @@ +/** + * @file + * @ingroup stm32_usart + * @brief STM32 USART support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32_USART_H +#define LIBBSP_ARM_STM32F4_STM32_USART_H + +#include + +/** + * @defgroup stm32_usart STM32 USART Support + * @ingroup stm32f4_usart + * @brief STM32 USART Support + * @{ + */ + +typedef struct { + uint32_t sr; +#define STM32F4_USART_SR_CTS BSP_BIT32(9) +#define STM32F4_USART_SR_LBD BSP_BIT32(8) +#define STM32F4_USART_SR_TXE BSP_BIT32(7) +#define STM32F4_USART_SR_TC BSP_BIT32(6) +#define STM32F4_USART_SR_RXNE BSP_BIT32(5) +#define STM32F4_USART_SR_IDLE BSP_BIT32(4) +#define STM32F4_USART_SR_ORE BSP_BIT32(3) +#define STM32F4_USART_SR_NF BSP_BIT32(2) +#define STM32F4_USART_SR_FE BSP_BIT32(1) +#define STM32F4_USART_SR_PE BSP_BIT32(0) + uint32_t dr; +#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t bbr; +#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15) +#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr1; +#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15) +#define STM32F4_USART_CR1_UE BSP_BIT32(13) +#define STM32F4_USART_CR1_M BSP_BIT32(12) +#define STM32F4_USART_CR1_WAKE BSP_BIT32(11) +#define STM32F4_USART_CR1_PCE BSP_BIT32(10) +#define STM32F4_USART_CR1_PS BSP_BIT32(9) +#define STM32F4_USART_CR1_PEIE BSP_BIT32(8) +#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7) +#define STM32F4_USART_CR1_TCIE BSP_BIT32(6) +#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5) +#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4) +#define STM32F4_USART_CR1_TE BSP_BIT32(3) +#define STM32F4_USART_CR1_RE BSP_BIT32(2) +#define STM32F4_USART_CR1_RWU BSP_BIT32(1) +#define STM32F4_USART_CR1_SBK BSP_BIT32(0) + uint32_t cr2; +#define STM32F4_USART_CR2_LINEN BSP_BIT32(14) +#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13) +#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11) +#define STM32F4_USART_CR2_CPOL BSP_BIT32(10) +#define STM32F4_USART_CR2_CPHA BSP_BIT32(9) +#define STM32F4_USART_CR2_LBCL BSP_BIT32(8) +#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6) +#define STM32F4_USART_CR2_LBDL BSP_BIT32(5) +#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr3; +#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11) +#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10) +#define STM32F4_USART_CR3_CTSE BSP_BIT32(9) +#define STM32F4_USART_CR3_RTSE BSP_BIT32(8) +#define STM32F4_USART_CR3_DMAT BSP_BIT32(7) +#define STM32F4_USART_CR3_DMAR BSP_BIT32(6) +#define STM32F4_USART_CR3_SCEN BSP_BIT32(5) +#define STM32F4_USART_CR3_NACK BSP_BIT32(4) +#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3) +#define STM32F4_USART_CR3_IRLP BSP_BIT32(2) +#define STM32F4_USART_CR3_IREN BSP_BIT32(1) +#define STM32F4_USART_CR3_EIE BSP_BIT32(0) + uint32_t gtpr; +#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15) +#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +} stm32f4_usart; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32_USART_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h new file mode 100644 index 0000000000..ecb4bb900c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_exti.h @@ -0,0 +1,50 @@ +/** + * @file + * @ingroup stm32f4_exti + * @brief STM32F10XXX EXTI support + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H + +#include + +/** + * @defgroup stm32f4_exti EXTI Support + * @ingroup arm_stm32f4 + * @brief STM32F10XXX EXTI Support + * @{ + */ + +typedef struct { + uint32_t imr; +#define STM32F4_EXTI_IMR(line) BSP_BIT32(line) + uint32_t emr; +#define STM32F4_EXTI_EMR(line) BSP_BIT32(line) + uint32_t rtsr; +#define STM32F4_EXTI_RTSR(line) BSP_BIT32(line) + uint32_t ftsr; +#define STM32F4_EXTI_FTSR(line) BSP_BIT32(line) + uint32_t swier; +#define STM32F4_EXTI_SWIER(line) BSP_BIT32(line) + uint32_t pr; +#define STM32F4_EXTI_PR(line) BSP_BIT32(line) +} stm32f4_exti; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h new file mode 100644 index 0000000000..ec7e675844 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_gpio.h @@ -0,0 +1,51 @@ +/** + * @file + * @ingroup stm32f4_gpio + * @brief STM32F10XXX GPIO support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H + +#include + +/** + * @defgroup stm32f4_gpio GPIO Support + * @ingroup stm32f4_io + * @brief GPIO Support + * @{ + */ + +typedef struct { + uint32_t cr[2]; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t brr; + uint32_t lckr; +} stm32f4_gpio; + +typedef struct { + uint32_t evcr; + uint32_t mapr; + uint32_t exticr[4]; + uint32_t mapr2; +} stm32f4_afio; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h new file mode 100644 index 0000000000..c1c6629810 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f10xxx_rcc.h @@ -0,0 +1,48 @@ +/** + * @file + * @ingroup stm32f10xxx_rcc + * @brief STM32F10XXX RCC support. + */ + +/* + * Copyright (c) 2013 Christian Mauderer. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H +#define LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H + +#include + +/** + * @defgroup stm32f10xxx_rcc STM32F10XXX RCC Support + * @ingroup stm32f4_rcc + * @brief STM32F10XXX RCC Support + * @{ + */ + +typedef struct { + uint32_t cr; + uint32_t cfgr; + uint32_t cir; + uint32_t apbrstr [2]; + uint32_t ahbenr [1]; + uint32_t apbenr [2]; + uint32_t bdcr; + uint32_t csr; + uint32_t ahbstr; + uint32_t cfgr2; +} stm32f4_rcc; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4.h b/bsps/arm/stm32f4/include/bsp/stm32f4.h new file mode 100644 index 0000000000..154d4f6d7b --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4.h @@ -0,0 +1,258 @@ +/** + * @file + * @ingroup stm32f4_reg + * @brief Register definitions. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4_H +#define LIBBSP_ARM_STM32F4_STM32F4_H + +#include +#include + +#define STM32F4_BASE 0x00 + +#ifdef STM32F4_FAMILY_F4XXXX + +/** + * @defgroup stm32f4_reg Register Defintions + * @ingroup arm_stm32f4 + * @brief Register Definitions + * @{ + */ + +#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000) +#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000) +#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000) +#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000) + +/** + * @name STM32f4XXXX GPIO + * @{ + */ + +#include +#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i)) + +/** @} */ + +/** + * @name STM32F4XXXX RCC + * @{ + */ + +#include +#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800)) + +/** @} */ + +/** + * @name STM32F4XXXX FLASH + * @{ + */ + +#include +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00)) + +/** @} */ + +#include + +/** + * @name STM32 I2C + * @{ + */ + +#define STM32F4_I2C3 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005C00)) +#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) +#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) + +/** @} */ + +/** + * @name STM32 USART + * @{ + */ + +#include +#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000)) +#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) +#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) +#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) +#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) +#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400)) + +/** @} */ + +/** + * @name STM32f4XXXX PWR + * @{ + */ + +#include +#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000)) + +/** @} */ + +/** + * @name STM32f4XXXX EXTI + * @{ + */ + +#include +#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX SYSCFG + * @{ + */ + +#include +#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800)) + +/** @} */ + +/** + * @name STM32f4XXXX FLASH + * @{ + */ + +#include +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX TIM + * @{ + */ + +#include +#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000)) +#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000)) +#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400)) +#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800)) +#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00)) +#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000)) +#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400)) +#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400)) +#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000)) +#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400)) +#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800)) +#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800)) +#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00)) +#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000)) + +/** @} */ + +/** + * @name STM32f4XXXX ADC + * @{ + */ + +#include +#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000)) +#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100)) +#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200)) +#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300)) + +/** @} */ + +/** + * @name STM32f4XXXX OTGFS + * @{ + */ + +#include +#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000) +#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000)) +#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800)) +#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900)) +#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00)) +#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00)) + +#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE) + +/** @} */ + +#endif /* STM32F4_FAMILY_F4XXXX */ + +#ifdef STM32F4_FAMILY_F10XXX + +/** + * @name STM32F10 EXTI + * @{ + */ + +#include +#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_BASE + 0x40010400)) + +/** @} */ + +/** + * @name STM32F10XXX GPIO + * @{ + */ + +#include +#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40010800 + i * 0x400)) +#define STM32F4_AFIO ((volatile stm32f4_afio *) (STM32F4_BASE + 0x40010000)) + +/** @} */ + +/** + * @name STM32F10XXX RCC + * @{ + */ + +#include +#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40021000)) + +/** @} */ + +/** + * @name STM32 I2C + * @{ + */ + +#include +#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) +#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) + +/** @} */ + +/** + * @name STM32 USART + * @{ + */ + +#include +#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40013800)) +#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) +#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) +#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) +#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) + +/** @} */ + +/** @} */ + +#endif /* STM32F4_FAMILY_F10XXX */ + +#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h new file mode 100644 index 0000000000..b9c1f9d5be --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2014 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H + +#include + +struct stm32f4_adc_chan_s { + uint32_t sr; // 0x00: Status register +#define STM32F4_ADC_SR_OVR BSP_BIT32(5) // Overrun +#define STM32F4_ADC_SR_STRT BSP_BIT32(4) // Regular channel start flag +#define STM32F4_ADC_SR_JSTRT BSP_BIT32(3) // Injected channel start flag +#define STM32F4_ADC_SR_JEOC BSP_BIT32(2) // Injected channel end of conversion +#define STM32F4_ADC_SR_EOC BSP_BIT32(1) // Regular channel end of conversion +#define STM32F4_ADC_SR_AWD BSP_BIT32(0) // Analog watchdog flag + + uint32_t cr1; // 0x04: Control register 1 +#define STM32F4_ADC_CR1_OVRIE BSP_BIT32(26) // Overrun interrupt enable +#define STM32F4_ADC_CR1_RES(val) BSP_FLD32(val, 24, 25) // Resolution +#define STM32F4_ADC_CR1_RES_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define STM32F4_ADC_CR1_RES_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define ADC_CR1_RES_12BIT 0 +#define ADC_CR1_RES_10BIT 1 +#define ADC_CR1_RES_8BIT 2 +#define ADC_CR1_RES_6BIT 3 +#define STM32F4_ADC_CR1_AWDEN BSP_BIT32(23) // Analog watchdog enable on regular channels +#define STM32F4_ADC_CR1_JAWDEN BSP_BIT32(22) // Analog watchdog enable on injected channels +#define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count +#define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15) +#define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) +#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels +#define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels +#define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion +#define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode +#define STM32F4_ADC_CR1_SCAN BSP_BIT32(8) // Scan mode +#define STM32F4_ADC_CR1_JEOCIE BSP_BIT32(7) // Interrupt enable for injected channels +#define STM32F4_ADC_CR1_AWDIE BSP_BIT32(6) // Analog watchdog interrupt enable +#define STM32F4_ADC_CR1_EOCIE BSP_BIT32(5) // Interrupt enable for EOC +#define STM32F4_ADC_CR1_AWDCH(val) BSP_FLD32(val, 0, 4) // Analog watchdog channel select bits +#define STM32F4_ADC_CR1_AWDCH_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + + uint32_t cr2; // 0x08: Control register 2 +#define STM32F4_ADC_CR2_SWSTART BSP_BIT32(30) // Start conversion of regular channels +#define STM32F4_ADC_CR2_EXTEN(val) BSP_FLD32(val, 28, 29) // External trigger enable for regular channels +#define STM32F4_ADC_CR2_EXTEN_GET(reg) BSP_FLD32GET(reg, 28, 29) +#define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29) +#define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21) // External trigger enable for injected channels +#define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21) +#define STM32F4_ADC_CR2_JEXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) +#define ADC_CR2_TRIGGER_DISABLE 0 +#define ADC_CR2_TRIGGER_RISING 1 +#define ADC_CR2_TRIGGER_FALLING 2 +#define ADC_CR2_TRIGGER_BOTH 3 +#define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27) // External event select for regular group +#define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27) +#define STM32F4_ADC_CR2_EXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) +#define ADC_CR2_EVT_TIMER1_CC1 0x0 +#define ADC_CR2_EVT_TIMER1_CC2 0x1 +#define ADC_CR2_EVT_TIMER1_CC3 0x2 +#define ADC_CR2_EVT_TIMER2_CC2 0x3 +#define ADC_CR2_EVT_TIMER2_CC3 0x4 +#define ADC_CR2_EVT_TIMER2_CC4 0x5 +#define ADC_CR2_EVT_TIMER2_TRGO 0x6 +#define ADC_CR2_EVT_TIMER3_CC1 0x7 +#define ADC_CR2_EVT_TIMER3_TRGO 0x8 +#define ADC_CR2_EVT_TIMER4_CC1 0x9 +#define ADC_CR2_EVT_TIMER5_CC1 0xa +#define ADC_CR2_EVT_TIMER5_CC2 0xb +#define ADC_CR2_EVT_TIMER5_CC3 0xc +#define ADC_CR2_EVT_TIMER8_CC1 0xd +#define ADC_CR2_EVT_TIMER8_TRGO 0xe +#define ADC_CR2_EVT_EXTI_11 0xf +#define STM32F4_ADC_CR2_JSWSTART BSP_BIT32(22) // Start conversion of injected channels +#define STM32F4_ADC_CR2_JEXTSEL(val) BSP_FLD32(val, 16, 19) // External event select for injected group +#define STM32F4_ADC_CR2_JEXTSEL_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define ADC_CR2_JEVT_TIMER1_CC4 0x0 +#define ADC_CR2_JEVT_TIMER1_TRGO 0x1 +#define ADC_CR2_JEVT_TIMER2_CC1 0x2 +#define ADC_CR2_JEVT_TIMER2_TRGO 0x3 +#define ADC_CR2_JEVT_TIMER3_CC2 0x4 +#define ADC_CR2_JEVT_TIMER3_CC4 0x5 +#define ADC_CR2_JEVT_TIMER4_CC1 0x6 +#define ADC_CR2_JEVT_TIMER4_CC2 0x7 +#define ADC_CR2_JEVT_TIMER4_CC3 0x8 +#define ADC_CR2_JEVT_TIMER4_TRGO 0x9 +#define ADC_CR2_JEVT_TIMER5_CC4 0xa +#define ADC_CR2_JEVT_TIMER5_TRGO 0xb +#define ADC_CR2_JEVT_TIMER8_CC2 0xc +#define ADC_CR2_JEVT_TIMER8_CC3 0xd +#define ADC_CR2_JEVT_TIMER8_CC4 0xe +#define ADC_CR2_JEVT_EXTI_15 0xf +#define STM32F4_ADC_CR2_ALIGN BSP_BIT32(11) // Data alignment +#define STM32F4_ADC_CR2_ALIGN_RIGHT 0 +#define STM32F4_ADC_CR2_ALIGN_LEFT STM32F4_ADC_CR2_ALIGN +#define STM32F4_ADC_CR2_EOCS BSP_BIT32(10) // End of conversion selection +#define STM32F4_ADC_CR2_DDS BSP_BIT32(9) // DMA disable selection (single ADC mode) +#define STM32F4_ADC_CR2_DMA BSP_BIT32(8) // DMA access mode (single ADC) +#define STM32F4_ADC_CR2_CONT BSP_BIT32(1) // Continuous conversion +#define STM32F4_ADC_CR2_ADON BSP_BIT32(0) // A/D converter ON + + uint32_t smpr1; // 0x0C: Sample time register 1 +#define ADC_SAMPLE_3CYCLE 0 +#define ADC_SAMPLE_15CYCLE 1 +#define ADC_SAMPLE_28CYCLE 2 +#define ADC_SAMPLE_56CYCLE 3 +#define ADC_SAMPLE_84CYCLE 4 +#define ADC_SAMPLE_112CYCLE 5 +#define ADC_SAMPLE_144CYCLE 6 +#define ADC_SAMPLE_480CYCLE 7 +#define STM32F4_ADC_SMP18(val) BSP_FLD32(val, 24, 26) // Channel 18 sampling time selection +#define STM32F4_ADC_SMP18_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_ADC_SMP17(val) BSP_FLD32(val, 21, 23) // Channel 17 sampling time selection +#define STM32F4_ADC_SMP17_GET(reg) BSP_FLD32GET(reg, 21, 23) +#define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) +#define STM32F4_ADC_SMP16(val) BSP_FLD32(val, 18, 20) // Channel 16 sampling time selection +#define STM32F4_ADC_SMP16_GET(reg) BSP_FLD32GET(reg, 18, 20) +#define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) +#define STM32F4_ADC_SMP15(val) BSP_FLD32(val, 15, 17) // Channel 15 sampling time selection +#define STM32F4_ADC_SMP15_GET(reg) BSP_FLD32GET(reg, 15, 17) +#define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) +#define STM32F4_ADC_SMP14(val) BSP_FLD32(val, 12, 14) // Channel 14 sampling time selection +#define STM32F4_ADC_SMP14_GET(reg) BSP_FLD32GET(reg, 12, 14) +#define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) +#define STM32F4_ADC_SMP13(val) BSP_FLD32(val, 9, 11) // Channel 13 sampling time selection +#define STM32F4_ADC_SMP13_GET(reg) BSP_FLD32GET(reg, 9, 11) +#define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) +#define STM32F4_ADC_SMP12(val) BSP_FLD32(val, 6, 8) // Channel 12 sampling time selection +#define STM32F4_ADC_SMP12_GET(reg) BSP_FLD32GET(reg, 6, 8) +#define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) +#define STM32F4_ADC_SMP11(val) BSP_FLD32(val, 3, 5) // Channel 11 sampling time selection +#define STM32F4_ADC_SMP11_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define STM32F4_ADC_SMP10(val) BSP_FLD32(val, 0, 2) // Channel 10 sampling time selection +#define STM32F4_ADC_SMP10_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t smpr2; // 0x10: Sample time register 2 +#define STM32F4_ADC_SMP9(val) BSP_FLD32(val, 27, 29) // Channel 9 sampling time selection +#define STM32F4_ADC_SMP9_GET(reg) BSP_FLD32GET(reg, 27, 29) +#define STM32F4_ADC_SMP9_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) +#define STM32F4_ADC_SMP8(val) BSP_FLD32(val, 24, 26) // Channel 8 sampling time selection +#define STM32F4_ADC_SMP8_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_ADC_SMP8_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_ADC_SMP7(val) BSP_FLD32(val, 21, 23) // Channel 7 sampling time selection +#define STM32F4_ADC_SMP7_GET(reg) BSP_FLD32GET(reg, 21, 23) +#define STM32F4_ADC_SMP7_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) +#define STM32F4_ADC_SMP6(val) BSP_FLD32(val, 18, 20) // Channel 6 sampling time selection +#define STM32F4_ADC_SMP6_GET(reg) BSP_FLD32GET(reg, 18, 20) +#define STM32F4_ADC_SMP6_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) +#define STM32F4_ADC_SMP5(val) BSP_FLD32(val, 15, 17) // Channel 5 sampling time selection +#define STM32F4_ADC_SMP5_GET(reg) BSP_FLD32GET(reg, 15, 17) +#define STM32F4_ADC_SMP5_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) +#define STM32F4_ADC_SMP4(val) BSP_FLD32(val, 12, 14) // Channel 4 sampling time selection +#define STM32F4_ADC_SMP4_GET(reg) BSP_FLD32GET(reg, 12, 14) +#define STM32F4_ADC_SMP4_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) +#define STM32F4_ADC_SMP3(val) BSP_FLD32(val, 9, 11) // Channel 3 sampling time selection +#define STM32F4_ADC_SMP3_GET(reg) BSP_FLD32GET(reg, 9, 11) +#define STM32F4_ADC_SMP3_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) +#define STM32F4_ADC_SMP2(val) BSP_FLD32(val, 6, 8) // Channel 2 sampling time selection +#define STM32F4_ADC_SMP2_GET(reg) BSP_FLD32GET(reg, 6, 8) +#define STM32F4_ADC_SMP2_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) +#define STM32F4_ADC_SMP1(val) BSP_FLD32(val, 3, 5) // Channel 1 sampling time selection +#define STM32F4_ADC_SMP1_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define STM32F4_ADC_SMP1_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define STM32F4_ADC_SMP0(val) BSP_FLD32(val, 0, 2) // Channel 0 sampling time selection +#define STM32F4_ADC_SMP0_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_ADC_SMP0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t jofr[4]; // 0x14-0x20: Injected channel data offset registers +#define STM32F4_ADC_JOFFSET(val) BSP_FLD32(val, 0, 11) // Data offset for injected channel +#define STM32F4_ADC_JOFFSET_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_JOFFSET_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t htr; // 0x24: Watchdog higher threshold register +#define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11) // Analog watchdog higher threshold +#define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_HT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t ltr; // 0x28: Watchdog lower threshold register +#define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11) // Analog watchdog lower threshold +#define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define STM32F4_ADC_LT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + + uint32_t sqr[3]; // 0x2c-0x34: Regular sequence registers +#define STM32F4_ADC_SQR_L(val) BSP_FLD32(val, 20, 23) // Regular channel sequence length +#define STM32F4_ADC_SQR_L_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) + + uint32_t jsqr; // 0x38: Injected sequence register +#define STM32F4_ADC_JSQR_JL(val) BSP_FLD32(val, 20, 21) // Injected sequence length +#define STM32F4_ADC_JSQR_JL_GET(reg) BSP_FLD32GET(reg, 20, 21) +#define STM32F4_ADC_JSQR_JL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) +#define STM32F4_ADC_JSQR_JSQ4(val) BSP_FLD32(val, 15, 19) // 4th conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ4_GET(reg) BSP_FLD32GET(reg, 15, 19) +#define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19) +#define STM32F4_ADC_JSQR_JSQ3(val) BSP_FLD32(val, 10, 14) // 3rd conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ3_GET(reg) BSP_FLD32GET(reg, 10, 14) +#define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14) +#define STM32F4_ADC_JSQR_JSQ2(val) BSP_FLD32(val, 5, 9) // 2nd conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ2_GET(reg) BSP_FLD32GET(reg, 5, 9) +#define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9) +#define STM32F4_ADC_JSQR_JSQ1(val) BSP_FLD32(val, 0, 4) // 1st conversion in injected sequence +#define STM32F4_ADC_JSQR_JSQ1_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + + uint32_t jdr[4]; // 0x3c-0x48: Injected data registers +#define STM32F4_ADC_JDATA(val) BSP_FLD32(val, 0, 15) // Injected data +#define STM32F4_ADC_JDATA_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t dr; // 0x4c: Regular data register +#define STM32F4_ADC_DATA(val) BSP_FLD32(val, 0, 15) // Regular data +#define STM32F4_ADC_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + +} __attribute__ ((packed)); +typedef struct stm32f4_adc_chan_s stm32f4_adc_chan; + +struct stm32f4_adc_com_s { + uint32_t csr; // 0x00: Common status register +#define STM32F4_ADC_CSR_OVR3 BSP_BIT32(21) // Overrun flag ADC3 +#define STM32F4_ADC_CSR_STRT3 BSP_BIT32(20) // Regular start flag ADC3 +#define STM32F4_ADC_CSR_JSTRT3 BSP_BIT32(19) // Injected start flag ADC3 +#define STM32F4_ADC_CSR_JEOC3 BSP_BIT32(18) // Injected channel end of conversion flag ADC3 +#define STM32F4_ADC_CSR_EOC3 BSP_BIT32(17) // Channel end of conversion flag ADC3 +#define STM32F4_ADC_CSR_AWD3 BSP_BIT32(16) // Analog watchdog flag ADC3 +#define STM32F4_ADC_CSR_OVR2 BSP_BIT32(13) // Overrun flag ADC2 +#define STM32F4_ADC_CSR_STRT2 BSP_BIT32(12) // Regular start flag ADC2 +#define STM32F4_ADC_CSR_JSTRT2 BSP_BIT32(11) // Injected start flag ADC2 +#define STM32F4_ADC_CSR_JEOC2 BSP_BIT32(10) // Injected channel end of conversion flag ADC2 +#define STM32F4_ADC_CSR_EOC2 BSP_BIT32(9) // Channel end of conversion flag ADC2 +#define STM32F4_ADC_CSR_AWD2 BSP_BIT32(8) // Analog watchdog flag ADC2 +#define STM32F4_ADC_CSR_OVR1 BSP_BIT32(5) // Overrun flag ADC1 +#define STM32F4_ADC_CSR_STRT1 BSP_BIT32(4) // Regular start flag ADC1 +#define STM32F4_ADC_CSR_JSTRT1 BSP_BIT32(3) // Injected start flag ADC1 +#define STM32F4_ADC_CSR_JEOC1 BSP_BIT32(2) // Injected channel end of conversion flag ADC1 +#define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1 +#define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1 + + uint32_t ccr; // 0x00: Common control register +#define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable +#define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable +#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar +#define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define ADC_ADCPRE_PCLK2_2 0 +#define ADC_ADCPRE_PCLK2_4 1 +#define ADC_ADCPRE_PCLK2_6 2 +#define ADC_ADCPRE_PCLK2_8 3 +#define STM32F4_ADC_CCR_DMA(val) BSP_FLD32(val, 14, 15) // DMA access mode for multi ADC +#define STM32F4_ADC_CCR_DMA_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define STM32F4_ADC_CCR_DMA_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define ADC_DMA_DISABLE 0 +#define ADC_DMA_MODE1 1 +#define ADC_DMA_MODE2 2 +#define ADC_DMA_MODE3 3 +#define STM32F4_ADC_CCR_DDS BSP_BIT32(13) // DMA disable selection +#define STM32F4_ADC_CCR_DELAY(val) BSP_FLD32(val, 8, 11) // Delay between sampling phases +#define STM32F4_ADC_CCR_DELAY_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define ADC_DELAY_5T 0 +#define ADC_DELAY_6T 1 +#define ADC_DELAY_7T 2 +#define ADC_DELAY_8T 3 +#define ADC_DELAY_9T 4 +#define ADC_DELAY_10T 5 +#define ADC_DELAY_11T 6 +#define ADC_DELAY_12T 7 +#define ADC_DELAY_13T 8 +#define ADC_DELAY_14T 9 +#define ADC_DELAY_15T 10 +#define ADC_DELAY_16T 11 +#define ADC_DELAY_17T 12 +#define ADC_DELAY_18T 13 +#define ADC_DELAY_19T 14 +#define ADC_DELAY_20T 15 +#define STM32F4_ADC_CCR_MULTI(val) BSP_FLD32(val, 0, 4) // Multi ADC mode +#define STM32F4_ADC_CCR_MULTI_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define ADC_MULTI_INDEPENDENT 0x00 +#define ADC_MULTI_DUAL_REG_INJ 0x01 +#define ADC_MULTI_DUAL_REG_ALT 0x02 +#define ADC_MULTI_DUAL_INJ 0x05 +#define ADC_MULTI_DUAL_REG 0x06 +#define ADC_MULTI_DUAL_INTRL 0x07 +#define ADC_MULTI_DUAL_ALT_TRIG 0x09 +#define ADC_MULTI_TRIPLE_REG_INJ 0x11 +#define ADC_MULTI_TRIPLE_REG_ALT 0x12 +#define ADC_MULTI_TRIPLE_INJ 0x15 +#define ADC_MULTI_TRIPLE_REG 0x16 +#define ADC_MULTI_TRIPLE_INTRL 0x17 +#define ADC_MULTI_TRIPLE_ALT_TRIG 0x19 + + uint32_t cdr; // 0x00: Common regular data register +#define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item +#define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_ADC_CDR_DATA1(val) BSP_FLD32(val, 0, 15) // 1st data item +#define STM32F4_ADC_CDR_DATA1_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + +} __attribute__ ((packed)); +typedef struct stm32f4_adc_com_s stm32f4_adc_com; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h new file mode 100644 index 0000000000..df44ad56e8 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_exti.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +#define STM32F4_EXTI_LINE22 BSP_BIT32(21) +#define STM32F4_EXTI_LINE21 BSP_BIT32(21) +#define STM32F4_EXTI_LINE20 BSP_BIT32(20) +#define STM32F4_EXTI_LINE19 BSP_BIT32(19) +#define STM32F4_EXTI_LINE18 BSP_BIT32(18) +#define STM32F4_EXTI_LINE17 BSP_BIT32(17) +#define STM32F4_EXTI_LINE16 BSP_BIT32(16) +#define STM32F4_EXTI_LINE15 BSP_BIT32(15) +#define STM32F4_EXTI_LINE14 BSP_BIT32(14) +#define STM32F4_EXTI_LINE13 BSP_BIT32(13) +#define STM32F4_EXTI_LINE12 BSP_BIT32(12) +#define STM32F4_EXTI_LINE11 BSP_BIT32(11) +#define STM32F4_EXTI_LINE10 BSP_BIT32(10) +#define STM32F4_EXTI_LINE9 BSP_BIT32(9) +#define STM32F4_EXTI_LINE8 BSP_BIT32(8) +#define STM32F4_EXTI_LINE7 BSP_BIT32(7) +#define STM32F4_EXTI_LINE6 BSP_BIT32(6) +#define STM32F4_EXTI_LINE5 BSP_BIT32(5) +#define STM32F4_EXTI_LINE4 BSP_BIT32(4) +#define STM32F4_EXTI_LINE3 BSP_BIT32(3) +#define STM32F4_EXTI_LINE2 BSP_BIT32(2) +#define STM32F4_EXTI_LINE1 BSP_BIT32(1) +#define STM32F4_EXTI_LINE0 BSP_BIT32(0) + +struct stm32f4_exti_s { + uint32_t imr; // Interrupt mask + uint32_t emr; // Event mask + uint32_t rtsr; // Rising trigger selection + uint32_t ftsr; // Falling trigger selection + uint32_t swier; // Software interrupt event + uint32_t pr; // Pending +} __attribute__ ((packed)); +typedef struct stm32f4_exti_s stm32f4_exti; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h new file mode 100755 index 0000000000..f81b19cd40 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H + +#include + +struct stm32f4_flash_s { + + uint32_t acr; // Access and control register +#define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset +#define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset +#define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable +#define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable +#define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable +#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency +#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t keyr; // Key register +#define STM32F4_FLASH_KEYR_KEY1 0x45670123 +#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB + + uint32_t optkeyr; // Option key register +#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B +#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F + + uint32_t sr; // Status register +#define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy +#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error +#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error +#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error +#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error +#define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error +#define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation + + uint32_t cr; // Control register +#define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock +#define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable +#define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable +#define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start +#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size +#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number +#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6) +#define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6) +#define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase +#define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase +#define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming + + uint32_t optcr; // Option control register +#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect +#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27) +#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27) +#define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect +#define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes +#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start +#define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock + +} __attribute__ ((packed)); +typedef struct stm32f4_flash_s stm32f4_flash; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h new file mode 100644 index 0000000000..b129c23595 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_gpio.h @@ -0,0 +1,39 @@ +/** + * @file + * @ingroup stm32f4_gpio + * @brief STM32F4XXXX GPIO support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H + +#include + +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t bsrr; + uint32_t lckr; + uint32_t afr [2]; + uint32_t reserved_28 [246]; +} stm32f4_gpio; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h new file mode 100755 index 0000000000..cc2eb90c4c --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_otgfs.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H + +#include + +#define USB_OTG_NUM_EPS 4 +#define USB_OTG_MAX_TX_FIFOS 4 + +#define USB_FIFO_BASE 0x1000 +#define USB_FIFO_OFFS 0x1000 + +struct stm32f4_otgfs_s { + uint32_t gotgctl; // 0x00: Control and status register +#define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid +#define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid +#define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time +#define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status +#define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable +#define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable +#define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request +#define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status +#define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request +#define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success + + uint32_t gotgint; // 0x04: Interrupt register +#define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done +#define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change +#define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected +#define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change +#define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change +#define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected + + uint32_t gahbcfg; // 0x08: AHB configuration register +#define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask + + uint32_t gusbcfg; // 0x0C: USB configuration register +#define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet +#define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode +#define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode +#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time +#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable +#define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable +#define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select +#define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration +#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t grstctl; // 0x10: Reset register +#define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle +#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10) +#define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush +#define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush +#define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset +#define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset +#define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset + + uint32_t gintsts; // 0x14: Core interrupt register +#define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt +#define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt +#define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt +#define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change +#define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt +#define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt +#define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer +#define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer +#define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer +#define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt +#define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt +#define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done +#define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset +#define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend +#define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend +#define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective +#define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective +#define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty +#define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame +#define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt +#define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt +#define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation + + uint32_t gintmsk; // 0x18: Interrupt mask register + + uint32_t grxstsr; // 0x1C: Receive status debug read + + uint32_t grxstsp; // 0x20: OTG status read and pop +#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20) +#define PKTSTS_IN_DATA (0x2) +#define PKTSTS_IN_COMPLETE (0x3) +#define PKTSTS_TOGGLE_ERR (0x5) +#define PKTSTS_HALTED (0x7) +#define PKTSTS_OUTNAK (0x1) +#define PKTSTS_OUT_DATA (0x2) +#define PKTSTS_OUT_COMPLETE (0x3) +#define PKTSTS_SETUP_COMPLETE (0x4) +#define PKTSTS_SETUP_DATA (0x6) +#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID +#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2) +#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3) +#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count +#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number +#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number +#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + + uint32_t grxfsiz; // 0x24: Receive FIFO size register +#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16 +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256 + + uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size +#define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16 +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256 +#define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t resv2C; + + uint32_t gi2cctl; // 0x30 + uint32_t resv34; // 0x34 + + uint32_t gccfg; // 0x38: General core configuration register +#define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable +#define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable +#define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device +#define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device +#define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down + + uint32_t cid; // 0x3C: Product ID + + uint32_t resv40[48]; // 0x40 - 0x9C + + uint32_t hptxfsiz; // 0x100 + + uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104 + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_s stm32f4_otgfs; + +struct stm32f4_otgfs_dregs_s { + uint32_t dcfg; // 0x800 +#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval +#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) +#define PFIVL_80 0 +#define PFIVL_85 1 +#define PFIVL_90 2 +#define PFIVL_95 3 +#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address +#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10) +#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10) +#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake +#define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed +#define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3) + + uint32_t dctl; // 0x804 +#define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done +#define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK +#define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK +#define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK +#define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK +#define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control +#define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6) +#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6) +#define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status +#define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status +#define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect +#define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling + + uint32_t dsts; // 0x808 +#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF +#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21) +#define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error +#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed +#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3) +#define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status + + uint32_t unused4; // 0x80C + + uint32_t diepmsk; // 0x810 + + uint32_t doepmsk; // 0x814 + + uint32_t daint; // 0x818 +#define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt + + uint32_t daintmsk; // 0x81C +#define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused5[2]; // 0x820 - 0x824 + + uint32_t dvbusdis; // 0x828 +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t dvbuspulse; // 0x82C +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused6; // 0x830 + + uint32_t diepempmsk; // 0x834 +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs; + +struct stm32f4_otgfs_inepregs_s { + uint32_t diepctl; // 0x900 +#define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame +#define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define EPTYPE_CTRL 0 +#define EPTYPE_ISOC 1 +#define EPTYPE_BULK 2 +#define EPTYPE_INTR 3 +#define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define EP0_MPSIZ_8 3 +#define EP0_MPSIZ_16 2 +#define EP0_MPSIZ_32 1 +#define EP0_MPSIZ_64 0 +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t reserved_04; + + uint32_t diepint; // 0x908 +#define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty +#define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective +#define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty +#define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition +#define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled +#define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t reserved_0C; + + uint32_t dieptsiz; // 0x910 +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t reserved_14; + + uint32_t dtxfsts; // 0x918 +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15) +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t reserved_1C; + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs; + +struct stm32f4_otgfs_outepregs_s { + uint32_t doepctl; // 0xBx0: Endpoint control register +#define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame +#define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode +#define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t resv04; + + uint32_t doepint; // 0xBx8: Endpoint interrupt register +#define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received +#define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled +#define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done +#define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt +#define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t doeptsiz; // 0xBy0 +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t resv14[3]; +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs; + +struct stm32f4_otgfs_pwrctlregs_s { + uint32_t pcgcctl; // 0xE00: Power and clock gating control register +#define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend +#define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK +#define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h new file mode 100755 index 0000000000..85af10738f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H + +#include + +struct stm32f4_pwr_s { + + uint32_t cr; // Control register +#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection +#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode +#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection +#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection +#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable +#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag +#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag +#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep +#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep + + uint32_t csr; // Control / status register +#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit +#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable +#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin +#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready +#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output +#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag +#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag + +} __attribute__ ((packed)); +typedef struct stm32f4_pwr_s stm32f4_pwr; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h new file mode 100755 index 0000000000..5c004328d7 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h @@ -0,0 +1,289 @@ +/** + * @file + * @ingroup stm32f4xxxx_rcc + * @brief STM32F4XXXX RCC support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H + +#include + +/** + * @defgroup stm32f4xxxx_rcc STM32F4XXXX RCC Support + * @ingroup stm32f4_rcc + * @brief STM32F4XXXX RCC Support + * @{ + */ + +typedef struct { + uint32_t cr; +#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag +#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable +#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag +#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable +#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable +#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass +#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag +#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable +#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag +#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable + + uint32_t pllcfgr; +#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) +#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source +#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC +#define STM32F4_RCC_PLLCFGR_SRC_HSI 0 +#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0) +#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1) +#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2) +#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3) +#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + + uint32_t cfgr; +#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2 +#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0) +#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1) +#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2) +#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3) +#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar +#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0) +#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4) +#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5) +#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6) +#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7) +#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar +#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0) +#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4) +#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5) +#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6) +#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7) +#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection +#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1 +#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0) +#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1) +#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2) +#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3) +#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock +#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20) +#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) +#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2) +#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0) +#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4) +#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5) +#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6) +#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7) +#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1) +#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0) +#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4) +#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) +#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) +#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) +#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar +#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0) +#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8) +#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9) +#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10) +#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11) +#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12) +#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13) +#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14) +#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15) +#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status +#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0) +#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1) +#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2) +#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch +#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0) +#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1) +#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2) + + uint32_t cir; + + uint32_t ahbrstr [3]; + + uint32_t reserved_1c; + + uint32_t apbrstr [2]; + + uint32_t reserved_28 [2]; + + uint32_t ahbenr [3]; + + uint32_t reserved_3c; + + uint32_t apbenr [2]; + + uint32_t reserved_48 [2]; + + uint32_t ahblpenr [3]; + + uint32_t reserved_5c; + + uint32_t apblpenr [2]; + + uint32_t reserved_68 [2]; + + uint32_t bdcr; + + uint32_t csr; + + uint32_t reserved_78 [2]; + + uint32_t sscgr; + + uint32_t plli2scfgr; + +} stm32f4_rcc; + +/** @} */ + +#define RCC_CR_HSION BSP_BIT32( 0 ) +#define RCC_CR_HSIRDY BSP_BIT32( 1 ) +#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 ) +#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 ) +#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 ) +#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 ) +#define RCC_CR_HSEON BSP_BIT32( 16 ) +#define RCC_CR_HSERDY BSP_BIT32( 17 ) +#define RCC_CR_HSEBYP BSP_BIT32( 18 ) +#define RCC_CR_CSSON BSP_BIT32( 19 ) +#define RCC_CR_PLLON BSP_BIT32( 24 ) +#define RCC_CR_PLLRDY BSP_BIT32( 25 ) +#define RCC_CR_PLLI2SON BSP_BIT32( 26 ) +#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 ) + +#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 ) +#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 ) +#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 ) +#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 ) + +#define RCC_PLLCFGR_PLLP 16 +#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_2 0 +#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 ) +#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 ) + +#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 ) +#define RCC_PLLCFGR_PLLSRC_HSI 0 + +#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 ) +#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 ) + +#define RCC_CFGR_SW 0 +#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 ) +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE 1 +#define RCC_CFGR_SW_PLL 2 + +#define RCC_CFGR_SWS 2 +#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 ) +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 ) +#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 ) + +#define RCC_CFGR_HPRE 4 +#define RCC_CFGR_HPRE_BY_1 0 +#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 ) +#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 ) +#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 ) +#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 ) +#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 ) +#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 ) +#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 ) +#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 ) + +#define RCC_CFGR_PPRE1 10 +#define RCC_CFGR_PPRE1_BY_1 0 +#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 ) +#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 ) + +#define RCC_CFGR_PPRE2 13 +#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 ) +#define RCC_CFGR_PPRE2_BY_1 0 +#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 ) +#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 ) + +#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 ) +#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 ) + +#define RCC_CFGR_MCO1 21 +#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 ) +#define RCC_CFGR_MCO1_HSI 0 +#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 ) +#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 ) +#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 ) + +#define RCC_CFGR_I2SSRC BSP_BIT32( 23 ) + +#define RCC_CFGR_MCO1PRE 24 +#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_1 0 +#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 ) +#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 ) + +#define RCC_CFGR_MCO2PRE 27 +#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_1 0 +#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 ) +#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 ) + +#define RCC_CFGR_MCO2 30 +#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 ) +#define RCC_CFGR_MCO2_SYSCLK 0 +#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 ) +#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) +#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h new file mode 100755 index 0000000000..5249363cef --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +struct stm32f4_syscfg_s { + uint32_t memrmp; // Memory remap +#define STM32F4_SYSCFG_MEM_MODE(val) BSP_FLD32(val, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) + uint32_t pmc; // Peripheral mode configuration +#define STM32F4_SYSCFG_RMII_SEL BSP_BIT32(23) + uint32_t exticr[4]; // External interrupt configuration +#define STM32F4_SYSCFG_EXTI0_IDX 0 +#define STM32F4_SYSCFG_EXTI0(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI0_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI1_IDX 0 +#define STM32F4_SYSCFG_EXTI1(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI1_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI2_IDX 0 +#define STM32F4_SYSCFG_EXTI2(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI2_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI3_IDX 0 +#define STM32F4_SYSCFG_EXTI3(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI3_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI4_IDX 1 +#define STM32F4_SYSCFG_EXTI4(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI4_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI4_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI5_IDX 1 +#define STM32F4_SYSCFG_EXTI5(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI5_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI5_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI6_IDX 1 +#define STM32F4_SYSCFG_EXTI6(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI6_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI6_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI7_IDX 1 +#define STM32F4_SYSCFG_EXTI7(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI7_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI7_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI8_IDX 2 +#define STM32F4_SYSCFG_EXTI8(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI8_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI8_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI9_IDX 2 +#define STM32F4_SYSCFG_EXTI9(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI9_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI9_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI10_IDX 2 +#define STM32F4_SYSCFG_EXTI10(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI10_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI10_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI11_IDX 2 +#define STM32F4_SYSCFG_EXTI11(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI11_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI11_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI12_IDX 3 +#define STM32F4_SYSCFG_EXTI12(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI12_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI13_IDX 3 +#define STM32F4_SYSCFG_EXTI13(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI13_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI13_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI14_IDX 3 +#define STM32F4_SYSCFG_EXTI14(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI14_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI14_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI15_IDX 3 +#define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t cmpcr; // Compensation cell control register +#define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8) +#define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0) +} __attribute__ ((packed)); +typedef struct stm32f4_syscfg_s stm32f4_syscfg; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h new file mode 100755 index 0000000000..45038945b8 --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_tim.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H + +#include + +struct stm32f4_tim_s { + uint16_t cr1; // Control register 1 +#define STM32F4_TIMER_CR1_CKD_DIV 0x0300 +#define STM32F4_TIMER_CR1_CKD_DIV1 0x0000 +#define STM32F4_TIMER_CR1_CKD_DIV2 0x0100 +#define STM32F4_TIMER_CR1_CKD_DIV3 0x0200 +#define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7) +#define STM32F4_TIMER_CR1_CMS 0x0060 +#define STM32F4_TIMER_CR1_CMS_EDGE 0x0000 +#define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020 +#define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040 +#define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060 +#define STM32F4_TIMER_CR1_DIR BSP_BIT16(4) +#define STM32F4_TIMER_CR1_DIR_UP 0x0000 +#define STM32F4_TIMER_CR1_DIR_DOWN 0x0010 +#define STM32F4_TIMER_CR1_DIR_OPM 0x0008 +#define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000 +#define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008 +#define STM32F4_TIMER_CR1_DIR_URS 0x0004 +#define STM32F4_TIMER_CR1_DIR_UDIS 0x0002 +#define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000 +#define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002 +#define STM32F4_TIMER_CR1_CEN 0x0001 + uint16_t reserved_02; + uint16_t cr2; // Control register 2 + uint16_t reserved_06; + uint16_t smcr; // Slave mode control register + uint16_t reserved_0a; + uint16_t dier; // DMA / interrupt enable register +#define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable +#define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable +#define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable +#define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable +#define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable +#define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable +#define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable +#define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable +#define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable +#define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable +#define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable +#define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable + + uint16_t reserved_0e; + uint16_t sr; // Status register +#define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag +#define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag +#define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag +#define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag +#define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag +#define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag +#define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag +#define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag +#define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag +#define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag + uint16_t reserved_12; + uint16_t egr; // Event generation register +#define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event +#define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event +#define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation) +#define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation) +#define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation) +#define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event + uint16_t reserved_16; + uint16_t ccmr1; // Capture / compare mode register 1 +#define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable +#define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0) +#define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1) +#define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2) +#define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5) +#define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6) +#define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7) +#define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable +#define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable +#define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0) +#define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1) +#define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2) +#define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3) +#define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable +#define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0) +#define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1) +#define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2) +#define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5) +#define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6) +#define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7) +#define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable +#define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable +#define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0) +#define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1) +#define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2) +#define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3) + uint16_t reserved_1a; + uint16_t ccmr2; // Capture / compare mode register 2 +#define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable +#define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0) +#define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1) +#define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2) +#define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5) +#define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6) +#define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7) +#define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable +#define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable +#define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0) +#define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1) +#define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2) +#define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3) +#define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable +#define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0) +#define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1) +#define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2) +#define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5) +#define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6) +#define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7) +#define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable +#define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable +#define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0) +#define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1) +#define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2) +#define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3) + uint16_t reserved_1e; + uint16_t ccer; // Capture / compare enable register +#define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable +#define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable +#define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable +#define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable + uint16_t reserved_22; + uint32_t cnt; // Counter register +#define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31) +#define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31) +#define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) + uint16_t psc; // Prescalar + uint16_t reserved_2a; + uint32_t arr; // Auto-reload register + uint16_t rcr; // Repetition counter register + uint16_t rserved_32; + uint32_t ccr[4];// Capture / compare registers + uint16_t bdtr; // Break and dead-time register + uint16_t reserved_46; + uint16_t dcr; // DMA control register + uint16_t reserved_4a; + uint16_t dmar; // DMA address for full transfer + uint16_t reserved_4e; + uint16_t or; // Option register + uint16_t reserved_52; +} __attribute__ ((packed)); +typedef struct stm32f4_tim_s stm32f4_tim; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */ diff --git a/bsps/arm/stm32f4/include/bsp/usart.h b/bsps/arm/stm32f4/include/bsp/usart.h new file mode 100644 index 0000000000..bac0f6845a --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/usart.h @@ -0,0 +1,45 @@ +/** + * @file + * @ingroup stm32f4_usart + * @brief USART (universal synchronous/asynchronous receiver/transmitter) support. + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_USART_H +#define LIBBSP_ARM_STM32F4_USART_H + +#include + +/** + * @defgroup stm32f4_usart USART Support + * @ingroup arm_stm32f4 + * @brief USART Support + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const console_fns stm32f4_usart_fns; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_STM32F4_USART_H */ diff --git a/bsps/arm/stm32f4/include/tm27.h b/bsps/arm/stm32f4/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/stm32f4/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/tms570/headers.am b/bsps/arm/tms570/headers.am new file mode 100644 index 0000000000..4dd455e338 --- /dev/null +++ b/bsps/arm/tms570/headers.am @@ -0,0 +1,63 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/tms570/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/system-clocks.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pinmux.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pins.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-pom.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-rti.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-sci-driver.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-sci.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570-vim.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_hwinit.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_selftest.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570_selftest_parity.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570lc4357-pins.h +include_bsp_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h + +include_bsp_ti_hercdir = $(includedir)/bsp/ti_herc +include_bsp_ti_herc_HEADERS = +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h +include_bsp_ti_herc_HEADERS += ../../../../../../bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h diff --git a/bsps/arm/tms570/include/bsp.h b/bsps/arm/tms570/include/bsp.h new file mode 100644 index 0000000000..456380627f --- /dev/null +++ b/bsps/arm/tms570/include/bsp.h @@ -0,0 +1,42 @@ +/** + * @file bsp.h + * + * @ingroup tms570 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_BSP_H +#define LIBBSP_ARM_TMS570_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include +#include + +#define BSP_OSCILATOR_CLOCK 8000000 +#define BSP_PLL_OUT_CLOCK 160000000 + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_BSP_H */ diff --git a/bsps/arm/tms570/include/bsp/irq.h b/bsps/arm/tms570/include/bsp/irq.h new file mode 100644 index 0000000000..2952582453 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/irq.h @@ -0,0 +1,160 @@ +/** + * @file irq.h + * + * @ingroup tms570 + * + * @brief TMS570 interrupt definitions. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_IRQ_H +#define LIBBSP_ARM_TMS570_IRQ_H + +#ifndef ASM +#include +#include +#include +#endif + +#define BSP_INTERRUPT_VECTOR_MIN 0U +#define TMS570_IRQ_ESM_HIGH 0 +#define TMS570_IRQ_RESERVED 1 +#define TMS570_IRQ_TIMER_0 2 +#define TMS570_IRQ_TIMER_1 3 +#define TMS570_IRQ_TIMER_2 4 +#define TMS570_IRQ_TIMER_3 5 +#define TMS570_IRQ_RTI_OVERFLOW_0 6 +#define TMS570_IRQ_RTI_OVERFLOW_1 7 +#define TMS570_IRQ_RTI_TIMEBASE 8 +#define TMS570_IRQ_GIO_HIGH 9 +#define TMS570_IRQ_HET_HIGH 10 +#define TMS570_IRQ_HET_TU_HIGH 11 +#define TMS570_IRQ_MIBSPI1_HIGH 12 +#define TMS570_IRQ_SCI_LEVEL_0 13 +#define TMS570_IRQ_ADC1_EVENT 14 +#define TMS570_IRQ_ADC1_GROUP_1 15 +#define TMS570_IRQ_CAN1_HIGH 16 +#define TMS570_IRQ_RESERVED 17 +#define TMS570_IRQ_FLEXRAY_HIGH 18 +#define TMS570_IRQ_CRC_1 19 +#define TMS570_IRQ_ESM_LOW 20 +#define TMS570_IRQ_SSI 21 +#define TMS570_IRQ_PMU 22 +#define TMS570_IRQ_GIO_LOW 23 +#define TMS570_IRQ_HET_LOW 24 +#define TMS570_IRQ_HET_TU_LOW 25 +#define TMS570_IRQ_MIBSPI1_LOW 26 +#define TMS570_IRQ_SCI_LEVEL_1 27 +#define TMS570_IRQ_ADC1_GROUP_2 28 +#define TMS570_IRQ_CAN1_LOW 29 +#define TMS570_IRQ_RESERVED +#define TMS570_IRQ_ADC1_MAG 31 +#define TMS570_IRQ_FLEXRAY_LOW 32 +#define TMS570_IRQ_DMA_FTCA 33 +#define TMS570_IRQ_DMA_LFSA 34 +#define TMS570_IRQ_CAN2_HIGH 35 +#define TMS570_IRQ_DMM_HIGH 36 +#define TMS570_IRQ_MIBSPI3_HIGH 37 +#define TMS570_IRQ_MIBSPI3_LOW 38 +#define TMS570_IRQ_DMA_HBCA 39 +#define TMS570_IRQ_DMA_BTCA 40 +#define TMS570_IRQ_DMA_BERA 41 +#define TMS570_IRQ_CAN2_LOW 42 +#define TMS570_IRQ_DMM_LOW 43 +#define TMS570_IRQ_CAN1_IF3 44 +#define TMS570_IRQ_CAN3_HIGH 45 +#define TMS570_IRQ_CAN2_IF3 46 +#define TMS570_IRQ_FPU 47 +#define TMS570_IRQ_FLEXRAY_TU 48 +#define TMS570_IRQ_SPI4_HIGH 49 +#define TMS570_IRQ_ADC2_EVENT 50 +#define TMS570_IRQ_ADC2_GROUP_1 51 +#define TMS570_IRQ_FLEXRAY_T0C 52 +#define TMS570_IRQ_MIBSPIP5_HIGH 53 +#define TMS570_IRQ_SPI4_LOW 54 +#define TMS570_IRQ_CAN3_LOW 55 +#define TMS570_IRQ_MIBSPIP5_LOW 56 +#define TMS570_IRQ_ADC2_GROUP_2 57 +#define TMS570_IRQ_FLEXRAY_TU_ERROR 58 +#define TMS570_IRQ_ADC2_MAG 59 +#define TMS570_IRQ_CAN3_IF3 60 +#define TMS570_IRQ_FSM_DONE 61 +#define TMS570_IRQ_FLEXRAY_T1C 62 +#define TMS570_IRQ_HET2_LEVEL_0 63 +#define TMS570_IRQ_SCI2_LEVEL_0 64 +#define TMS570_IRQ_HET_TU2_LEVEL_0 65 +#define TMS570_IRQ_IC2_INTERRUPT 66 +#define TMS570_IRQ_HET2_LEVEL_1 73 +#define TMS570_IRQ_SCI2_LEVEL_1 74 +#define TMS570_IRQ_HET_TU2_LEVEL_1 75 +#define TMS570_IRQ_EMAC_MISC 76 +#define TMS570_IRQ_EMAC_TX 77 +#define TMS570_IRQ_EMAC_THRESH 78 +#define TMS570_IRQ_EMAC_RX 79 +#define TMS570_IRQ_HWA_INT_REQ_H 80 +#define TMS570_IRQ_HWA_INT_REQ_H 81 +#define TMS570_IRQ_DCC_DONE_INTERRUPT 82 +#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 +#define TMS570_IRQ_HWAG1_INT_REQ_L 88 +#define TMS570_IRQ_HWAG2_INT_REQ_L 89 +#define BSP_INTERRUPT_VECTOR_MAX 94 + +#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U +#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U + +#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) +#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN +#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX + +#ifndef ASM + +/** + * @brief Set priority of the interrupt vector. + * + * This function is here because of compability. It should set + * priority of the interrupt vector. + * @warning It does not set any priority at HW layer. It is nearly imposible to + * @warning set priority of the interrupt on TMS570 in a nice way. + * @param[in] vector vector of isr + * @param[in] priority new priority assigned to the vector + * @return Void + */ +void tms570_irq_set_priority( + rtems_vector_number vector, + unsigned priority +); + +/** + * @brief Gets priority of the interrupt vector. + * + * This function is here because of compability. It returns priority + * of the isr vector last set by tms570_irq_set_priority function. + * + * @warning It does not return any real priority of the HW layer. + * @param[in] vector vector of isr + * @retval 0 vector is invalid. + * @retval priority priority of the interrupt + */ +unsigned tms570_irq_get_priority( rtems_vector_number vector ); + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/system-clocks.h b/bsps/arm/tms570/include/bsp/system-clocks.h new file mode 100644 index 0000000000..0e1d1301d4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/system-clocks.h @@ -0,0 +1,62 @@ +/** + * @file benchmark_timer.c + * + * @ingroup tms570 + * + * @brief System clocks. + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H +#define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup tms570_clock System Clocks + * + * @ingroup tms570 + * + * @brief System clocks. + * + * @{ + */ + +/** + * @brief Returns current standard timer value in microseconds. + * + * This function uses RTI module free running counter 0 used + * which is used as system tick timebase as well. + */ +static inline unsigned tms570_timer(void) +{ + uint32_t actual_fcr0 = TMS570_RTI.CNT[0].FRCx; + return actual_fcr0; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h new file mode 100644 index 0000000000..1649fbeb4b --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h @@ -0,0 +1,626 @@ +/* The header file is generated by make_header.py from ADC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_ADC +#define LIBBSP_ARM_TMS570_ADC + +#include + +typedef struct{ + uint32_t BUF0; /*Group 0-2 result buffer 0 register*/ + uint32_t BUF1; /*Group 0-2 result buffer 1 register*/ + uint32_t BUF2; /*Group 0-2 result buffer 2 register*/ + uint32_t BUF3; /*Group 0-2 result buffer 3 register*/ + uint32_t BUF4; /*Group 0-2 result buffer 4 register*/ + uint32_t BUF5; /*Group 0-2 result buffer 5 register*/ + uint32_t BUF6; /*Group 0-2 result buffer 6 register*/ + uint32_t BUF7; /*Group 0-2 result buffer 7 register*/ +} tms570_gxbuf_t; + +typedef struct{ + uint32_t RSTCR; /*ADC Reset Control Register*/ + uint32_t OPMODECR; /*ADC Operating Mode Control Register*/ + uint32_t CLOCKCR; /*ADC Clock Control Register*/ + uint32_t CALCR; /*ADC Calibration Mode Control Register*/ + uint32_t GxMODECR[3]; /*ADC Event Group Operating Mode Control Register*/ + uint32_t EVSRC; /*ADC Trigger Source Select Register*/ + uint32_t G1SRC; /*ADC Group1 Trigger Source Select Register*/ + uint32_t G2SRC; /*ADC Group2 Trigger Source Select Register*/ + uint32_t GxINTENA[3]; /*ADC Event Interrupt Enable Control Register*/ + uint32_t GxINTFLG[3]; /*ADC Event Group Interrupt Flag Register*/ + uint32_t GxINTCR[3]; /*ADC Event Group Threshold Interrupt Control Register*/ + uint32_t EVDMACR; /*ADC Event Group DMA Control Register*/ + uint32_t G1DMACR; /*ADC Group1 DMA Control Register*/ + uint32_t G2DMACR; /*ADC Group2 DMA Control Register*/ + uint32_t BNDCR; /*ADC Results Memory Configuration Register*/ + uint32_t BNDEND; /*ADC Results Memory Size Configuration Register*/ + uint32_t EVSAMP; /*ADC Event Group Sampling Time Configuration Register*/ + uint32_t G1SAMP; /*ADC Group1 Sampling Time Configuration Register()*/ + uint32_t G2SAMP; /*ADC Group2 Sampling Time Configuration Register*/ + uint32_t EVSR; /*ADC Event Group Status Register*/ + uint32_t G1SR; /*ADC Group1 Status Register*/ + uint32_t G2SR; /*ADC Group2 Status Register*/ + uint32_t GxSEL[3]; /*ADC Event Group Channel Select Register*/ + uint32_t CALR; /*ADC Calibration and Error Offset Correction Register*/ + uint32_t SMSTATE; /*ADC State Machine Status Register*/ + uint32_t LASTCONV; /*ADC Channel Last Conversion Value Register*/ + tms570_gxbuf_t GxBUF[3]; /*ADC Event Group Results Emulation FIFO Register*/ + uint32_t EVEMUBUFFER; /*ADC Event Group Results Emulation FIFO Register*/ + uint32_t G1EMUBUFFER; /*ADC Group1 Results Emulation FIFO Register*/ + uint32_t G2EMUBUFFER; /*ADC Group2 Results Emulation FIFO Register*/ + uint32_t EVTDIR; /*ADC ADEVT Pin Direction Control Register*/ + uint32_t EVTOUT; /*ADC ADEVT Pin Output Value Control Register*/ + uint32_t EVTIN; /*ADC ADEVT Pin Input Value Register*/ + uint32_t EVTSET; /*ADC ADEVT Pin Set Register*/ + uint32_t EVTCLR; /*ADC ADEVT Pin Clear Register*/ + uint32_t EVTPDR; /*ADC ADEVT Pin Open Drain Enable Register*/ + uint32_t EVTPDIS; /*ADC ADEVT Pin Pull Control Disable Register*/ + uint32_t EVTPSEL; /*ADC ADEVT Pin Pull Control Select Register*/ + uint32_t EVSAMPDISEN; /*ADC Event Group Sample Cap Discharge Control Register*/ + uint32_t G1SAMPDISEN; /*ADC Group1 Sample Cap Discharge Control Register*/ + uint32_t G2SAMPDISEN; /*ADC Group2 Sample Cap Discharge Control Register*/ + uint32_t MAGINTCR1; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT1MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint32_t MAGINTCR2; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT2MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint32_t MAGINTCR3; /*ADC Magnitude Compare Interrupt Control Register 2*/ + uint32_t MAGINT3MASK; /*ADC Magnitude Compare Mask Register 0*/ + uint8_t reserved1 [24]; + uint32_t MAGTHRINTENASET; /*ADC Magnitude Compare Interrupt Enable Set Register*/ + uint32_t MAGTHRINTENACLR; /*ADC Magnitude Compare Interrupt Enable Clear Register*/ + uint32_t MAGTHRINTFLG; /*ADC Magnitude Compare Interrupt Flag Register*/ + uint32_t MAGTHRINTOFFSET; /*ADC Magnitude Compare Interrupt Offset Register*/ + uint32_t GxFIFORESETCR[3]; /*ADC Event Group FIFO Reset Control Register*/ + uint32_t EVRAMWRADDR; /*ADC Event Group RAM Write Address Register*/ + uint32_t G1RAMWRADDR; /*ADC Group1 RAM Write Address Register*/ + uint32_t G2RAMWRADDR; /*ADC Group2 RAM Write Address Register*/ + uint32_t PARCR; /*ADC Parity Control Register*/ + uint32_t PARADDR; /*ADC Parity Error Address Register*/ + uint32_t PWRUPDLYCTRL; /*ADC Power-Up Delay Control Register*/ +} tms570_adc_t; + + +/*----------------------TMS570_ADC_BUFx----------------------*/ +/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */ +#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15) + +/* field: G2_CHID_10bit_mode - Group2 Channel Id. */ +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14) +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14) +#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14) + +/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */ +#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + +/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */ +#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31) + +/* field: G2_CHID_12bit_mode - Group2 Channel Id. */ +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20) +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */ +#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*----------------------TMS570_ADC_RSTCR----------------------*/ +/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */ +#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0) + + +/*--------------------TMS570_ADC_OPMODECR--------------------*/ +/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */ +#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31) + + +/*---------------------TMS570_ADC_CLOCKCR---------------------*/ +/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */ +#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4) +#define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*----------------------TMS570_ADC_CALCR----------------------*/ +/* field: SELF_TEST - ADC Self Test Enable. */ +#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24) + +/* field: CAL_ST - ADC Calibration Conversion Start. */ +#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16) + +/* field: BRIDGE_EN - Bridge Enable. */ +#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9) + +/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */ +#define TMS570_ADC_CALCR_HILO BSP_BIT32(8) + +/* field: CAL_EN - ADC Calibration Enable. */ +#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_GxMODECR--------------------*/ +/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */ +#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16) + +/* field: EV_DATA_FMT - Event Group Read Data Format. */ +#define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9) +#define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + + +/*----------------------TMS570_ADC_EVSRC----------------------*/ +/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */ +#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4) + +/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */ +#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3) + +/* field: EV_SRC - Event Group Trigger Source. */ +#define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_ADC_G1SRC----------------------*/ +/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4) + +/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3) + +/* field: G1_SRC - Group1 Trigger Source. */ +#define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_ADC_G2SRC----------------------*/ +/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4) + +/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */ +#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3) + +/* field: G2_SRC - Group2 Trigger Source. */ +#define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_ADC_GxINTENA--------------------*/ +/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */ +#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3) + +/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */ +#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1) + +/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */ +#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_GxINTFLG--------------------*/ +/* field: EV_END - Event Group Conversion End. */ +#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3) + +/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */ +#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2) + +/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */ +#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1) + +/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */ +#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0) + + +/*---------------------TMS570_ADC_GxINTCR---------------------*/ +/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */ +#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15) +#define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15) +#define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15) + +/* field: EV_THR - Event Group Threshold Counter. */ +#define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*---------------------TMS570_ADC_EVDMACR---------------------*/ +/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */ +#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3) + +/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2) + +/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */ +#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_G1DMACR---------------------*/ +/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */ +#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3) + +/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2) + +/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */ +#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_G2DMACR---------------------*/ +/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */ +#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3) + +/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2) + +/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */ +#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0) + + +/*----------------------TMS570_ADC_BNDCR----------------------*/ +/* field: BNDA - Buffer Boundary A. */ +#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24) +#define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24) +#define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24) + +/* field: BNDB - Buffer Boundary B. */ +#define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*---------------------TMS570_ADC_BNDEND---------------------*/ +/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */ +#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16) + +/* field: BNDEND - Buffer Boundary End. */ +#define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_ADC_EVSAMP---------------------*/ +/* field: EV_ACQ - Event Group Acquisition Time. */ +#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_G1SAMP---------------------*/ +/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */ +#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_G2SAMP---------------------*/ +/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */ +#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*----------------------TMS570_ADC_EVSR----------------------*/ +/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */ +#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3) + +/* field: EV_BUSY - Event Group Conversion Busy. */ +#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2) + +/* field: EV_STOP - Event Group Conversion Stopped. */ +#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1) + +/* field: EV_END - Event Group Conversions Ended. */ +#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_G1SR----------------------*/ +/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */ +#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3) + +/* field: G1_BUSY - Group1 Conversion Busy. */ +#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2) + +/* field: G1_STOP - Group1 Conversion Stopped. */ +#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1) + +/* field: G1_END - Group1 Conversions Ended. */ +#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_G2SR----------------------*/ +/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */ +#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3) + +/* field: G2_BUSY - Group2 Conversion Busy. */ +#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2) + +/* field: G2_STOP - Group2 Conversion Stopped. */ +#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1) + +/* field: G2_END - Group2 Conversions Ended. */ +#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0) + + +/*----------------------TMS570_ADC_GxSEL----------------------*/ +/* field: EV_SEL - Event Group channels selected. */ +#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15) +#define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_ADC_CALR----------------------*/ +/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */ +#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11) +#define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*---------------------TMS570_ADC_SMSTATE---------------------*/ +/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */ +#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23) +#define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_ADC_LASTCONV--------------------*/ +/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */ +#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23) +#define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*----------------------TMS570_ADC_GxBUF----------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTDIR---------------------*/ +/* field: ADEVT_DIR - ADEVT Pin Direction. */ +#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTOUT---------------------*/ +/* field: ADEVT_OUT - ADEVT Pin Output Value. */ +#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0) + + +/*----------------------TMS570_ADC_EVTIN----------------------*/ +/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */ +#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTSET---------------------*/ +/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */ +#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTCLR---------------------*/ +/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */ +#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPDR---------------------*/ +/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */ +#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPDIS---------------------*/ +/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */ +#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0) + + +/*---------------------TMS570_ADC_EVTPSEL---------------------*/ +/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */ +#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/ +/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */ +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */ +#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/ +/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */ +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */ +#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0) + + +/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/ +/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */ +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15) +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */ +#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0) + + +/*--------------------TMS570_ADC_MAGINTCRx--------------------*/ +/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */ +#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30) +#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30) +#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30) + +/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */ +#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25) +#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25) +#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25) + +/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */ +#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12) +#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + +/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */ +#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1) + +/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */ +#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0) + + +/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/ +/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */ +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/ +/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */ +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/ +/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */ +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/ +/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */ +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2) +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/ +/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */ +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_ADC_GxFIFORESETCR------------------*/ +/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */ +#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0) + + +/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/ +/* field: G1_RAM_ADDR - Group1 results memory write pointer. */ +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/ +/* field: G1_RAM_ADDR - Group1 results memory write pointer. */ +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/ +/* field: G2_RAM_ADDR - Group2 results memory write pointer. */ +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_ADC_PARCR----------------------*/ +/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */ +#define TMS570_ADC_PARCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - PARITY ENA */ +#define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_ADC_PARADDR---------------------*/ +/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */ +#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11) +#define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11) +#define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11) + + +/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/ +/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */ +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9) +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + + +#endif /* LIBBSP_ARM_TMS570_ADC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h new file mode 100644 index 0000000000..941ed54753 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h @@ -0,0 +1,72 @@ +/* The header file is generated by make_header.py from CCMSR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_CCMSR +#define LIBBSP_ARM_TMS570_CCMSR + +#include + +typedef struct{ + uint32_t CCMSR; /*CCM-R4F Status Register*/ + uint32_t CCMKEYR; /*CCM-R4F Key Register*/ +} tms570_ccmsr_t; + + +/*---------------------TMS570_CCMSR_CCMSR---------------------*/ +/* field: CMPE - Compare Error */ +#define TMS570_CCMSR_CCMSR_CMPE BSP_BIT32(16) + +/* field: STC - Self-test Complete */ +#define TMS570_CCMSR_CCMSR_STC BSP_BIT32(8) + +/* field: STET - Self-test Error Type */ +#define TMS570_CCMSR_CCMSR_STET BSP_BIT32(1) + +/* field: STE - Self-test Error */ +#define TMS570_CCMSR_CCMSR_STE BSP_BIT32(0) + + +/*--------------------TMS570_CCMSR_CCMKEYR--------------------*/ +/* field: MKEY - Mode Key */ +#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_CCMSR_CCMKEYR_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_CCMSR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h new file mode 100644 index 0000000000..f1352f67b6 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h @@ -0,0 +1,379 @@ +/* The header file is generated by make_header.py from CRC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_CRC +#define LIBBSP_ARM_TMS570_CRC + +#include + +typedef struct{ + uint32_t CTRL0; /*CRC Global Control Register*/ + uint8_t reserved1 [4]; + uint32_t CTRL1; /*CRC Global Control Register 1*/ + uint8_t reserved2 [4]; + uint32_t CTRL2; /*CRC Global Control Register 2*/ + uint8_t reserved3 [4]; + uint32_t INTS; /*CRC Interrupt Enable Set Register*/ + uint8_t reserved4 [4]; + uint32_t INTR; /*CRC Interrupt Enable Reset Register*/ + uint8_t reserved5 [4]; + uint32_t STATUS; /*CRC Interrupt Status Register*/ + uint8_t reserved6 [4]; + uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/ + uint8_t reserved7 [4]; + uint32_t BUSY; /*CRC Busy Register*/ + uint8_t reserved8 [4]; + uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/ + uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/ + uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/ + uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/ + uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/ + uint8_t reserved9 [12]; + uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/ + uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/ + uint32_t REGL1; /*Channel 1 CRC Value Low Register*/ + uint32_t REGH1; /*Channel 1 CRC Value High Register*/ + uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/ + uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/ + uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/ + uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/ + uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/ + uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/ + uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/ + uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/ + uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/ + uint8_t reserved10 [12]; + uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/ + uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/ + uint32_t REGL2; /*Channel 2 CRC Value Low Register*/ + uint32_t REGH2; /*Channel 2 CRC Value High Register*/ + uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/ + uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/ + uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/ + uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/ + uint8_t reserved11 [128]; + uint32_t BUS_SEL; /*Data Bus Selection Register*/ +} tms570_crc_t; + + +/*----------------------TMS570_CRC_CTRL0----------------------*/ +/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ +#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8) + +/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ +#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0) + + +/*----------------------TMS570_CRC_CTRL1----------------------*/ +/* field: PWDN - Power Down. */ +#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0) + + +/*----------------------TMS570_CRC_CTRL2----------------------*/ +/* field: CH2_MODE - Channel 2 Mode Selection */ +#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9) +#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */ +#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4) + +/* field: CH1_MODE - Channel 1 Mode Selection */ +#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1) +#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*----------------------TMS570_CRC_INTS----------------------*/ +/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12) + +/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11) + +/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10) + +/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9) + +/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8) + +/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4) + +/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3) + +/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2) + +/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1) + +/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0) + + +/*----------------------TMS570_CRC_INTR----------------------*/ +/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12) + +/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11) + +/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10) + +/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9) + +/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8) + +/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4) + +/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */ +#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3) + +/* field: CH1_OVERENR - CH1_OVERENR */ +#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2) + +/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1) + +/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */ +#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0) + + +/*---------------------TMS570_CRC_STATUS---------------------*/ +/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12) + +/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11) + +/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10) + +/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */ +#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9) + +/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */ +#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8) + +/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */ +#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4) + +/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */ +#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3) + +/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */ +#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2) + +/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */ +#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1) + +/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */ +#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0) + + +/*------------------TMS570_CRC_INT_OFFS_REG------------------*/ +/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */ +#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7) +#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_CRC_BUSY----------------------*/ +/* field: CH2_BUSY - CH2_BUSY. */ +#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8) + +/* field: CH1_BUSY - CH1_BUSY. */ +#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0) + + +/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/ +/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */ +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19) +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/ +/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */ +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/ +/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */ +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_CRC_WDTOPLD1--------------------*/ +/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */ +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_CRC_BCTOPLD1--------------------*/ +/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */ +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/ +/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/ +/* field: PSASIG1 - register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGL1----------------------*/ +/* field: CRC1 - Channel 1 CRC Value Low Register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGH1----------------------*/ +/* field: CRC1 - Channel 1 CRC Value Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/ +/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/ +/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/ +/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/ +/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */ +/* Whole 32 bits */ + +/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/ +/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */ +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19) +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/ +/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */ +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/ +/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */ +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15) +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_CRC_WDTOPLD2--------------------*/ +/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */ +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*--------------------TMS570_CRC_BCTOPLD2--------------------*/ +/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */ +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23) +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/ +/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/ +/* field: PSASIG2 - Channel 2 PSA Signature High Register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGL2----------------------*/ +/* field: CRC2 - stored at CRC2[31:0] register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_CRC_REGH2----------------------*/ +/* field: CRC2 - Channel 2 CRC Value High Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/ +/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */ +/* Whole 32 bits */ + +/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/ +/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/ +/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */ +/* Whole 32 bits */ + +/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/ +/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */ +/* Whole 32 bits */ + +/*---------------------TMS570_CRC_BUS_SEL---------------------*/ +/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */ +#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2) + +/* field: DTCMEn - Enable/disables the tracing of data TCM */ +#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1) + +/* field: ITCMEn - Enable/disables the tracing of instruction TCM */ +#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_CRC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h new file mode 100644 index 0000000000..c278f554ff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h @@ -0,0 +1,941 @@ +/* The header file is generated by make_header.py from DCAN.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DCAN +#define LIBBSP_ARM_TMS570_DCAN + +#include + +typedef struct{ + uint32_t CTL; /*CAN Control Register*/ + uint32_t ES; /*Error and Status Register*/ + uint32_t ERRC; /*Error Counter Register*/ + uint32_t BTR; /*Bit Timing Register*/ + uint32_t INT; /*Interrupt Register*/ + uint32_t TEST; /*Test Register*/ + uint8_t reserved1 [4]; + uint32_t PERR; /*Parity Error Code Register*/ + uint8_t reserved2 [96]; + uint32_t ABOTR; /*Auto-Bus-On Time Register*/ + uint32_t TXRQX; /*Transmission Request X Register*/ + uint32_t TXRQx[4]; /*Transmission Request Register*/ + uint32_t NWDATX; /*New Data X Register*/ + uint32_t NWDATx[4]; /*New Data Register*/ + uint32_t INTPNDX; /*Interrupt Pending X Register*/ + uint32_t INTPNDx[4]; /*Interrupt Pending Register*/ + uint32_t MSGVALX; /*Message Valid X Register*/ + uint32_t MSGVALx[4]; /*Message Valid Register*/ + uint8_t reserved3 [4]; + uint32_t INTMUXx[4]; /*Interrupt Multiplexer Register*/ + uint8_t reserved4 [24]; + uint32_t IF1CMD; /*IF1 Command Register*/ + uint32_t IF1MSK; /*IF1 Mask Register*/ + uint32_t IF1ARB; /*IF1 Arbitration Register*/ + uint32_t IF1MCTL; /*IF1 Message Control Register*/ + uint32_t IF1DATA; /*IF1 Data A Register*/ + uint32_t IF1DATB; /*IF1 Data B Register*/ + uint8_t reserved5 [8]; + uint32_t IF2CMD; /*IF2 Command Register*/ + uint32_t IF2MSK; /*IF2 Mask Register*/ + uint32_t IF2ARB; /*IF2 Arbitration Register*/ + uint32_t IF2MCTL; /*IF2 Message Control Register*/ + uint32_t IF2DATA; /*IF2 Data A Register*/ + uint32_t IF2DATB; /*IF2 Data B Register*/ + uint8_t reserved6 [8]; + uint32_t IF3OBS; /*IF3 Observation Register*/ + uint32_t IF3MSK; /*IF3 Mask Register*/ + uint32_t IF3ARB; /*IF3 Arbitration Register*/ + uint32_t IF3MCTL; /*IF3 Message Control Register*/ + uint32_t IF3DATA; /*IF3 Data A Register*/ + uint32_t IF3DATB; /*IF3 Data B Register*/ + uint8_t reserved7 [8]; + uint32_t IF3UEy[4]; /*IF3 Update Enable Register*/ + uint8_t reserved8 [112]; + uint32_t TIOC; /*CAN TX IO Control Register*/ + uint32_t RIOC; /*CAN RX IO Control Register*/ +} tms570_dcan_t; + + +/*----------------------TMS570_DCAN_CTL----------------------*/ +/* field: WUBA - Automatic wake up on bus activity when in local power down mode */ +#define TMS570_DCAN_CTL_WUBA BSP_BIT32(25) + +/* field: PDR - Request for local low power down mode */ +#define TMS570_DCAN_CTL_PDR BSP_BIT32(24) + +/* field: DE3 - Enable DMA request line for IF3 */ +#define TMS570_DCAN_CTL_DE3 BSP_BIT32(20) + +/* field: DE2 - Enable DMA request line for IF2 */ +#define TMS570_DCAN_CTL_DE2 BSP_BIT32(19) + +/* field: DE1 - Enable DMA request line for IF1 */ +#define TMS570_DCAN_CTL_DE1 BSP_BIT32(18) + +/* field: IE1 - Interrupt line 1 Enable */ +#define TMS570_DCAN_CTL_IE1 BSP_BIT32(17) + +/* field: InitDbg - Internal Init state while debug access */ +#define TMS570_DCAN_CTL_InitDbg BSP_BIT32(16) + +/* field: SWR - SW Reset Enable */ +#define TMS570_DCAN_CTL_SWR BSP_BIT32(15) + +/* field: PMD - Parity on/off */ +#define TMS570_DCAN_CTL_PMD(val) BSP_FLD32(val,10, 13) +#define TMS570_DCAN_CTL_PMD_GET(reg) BSP_FLD32GET(reg,10, 13) +#define TMS570_DCAN_CTL_PMD_SET(reg,val) BSP_FLD32SET(reg, val,10, 13) + +/* field: ABO - Auto-Bus-On Enable */ +#define TMS570_DCAN_CTL_ABO BSP_BIT32(9) + +/* field: IDS - Interruption Debug Support Enable */ +#define TMS570_DCAN_CTL_IDS BSP_BIT32(8) + +/* field: Test - Test Mode Enable */ +#define TMS570_DCAN_CTL_Test BSP_BIT32(7) + +/* field: CCE - Configuration Change Enable */ +#define TMS570_DCAN_CTL_CCE BSP_BIT32(6) + +/* field: DAR - Disable Automatic Retransmission */ +#define TMS570_DCAN_CTL_DAR BSP_BIT32(5) + +/* field: EIE - Error Interrupt Enable */ +#define TMS570_DCAN_CTL_EIE BSP_BIT32(3) + +/* field: SIE - Status Change Interrupt Enable */ +#define TMS570_DCAN_CTL_SIE BSP_BIT32(2) + +/* field: IE0 - Interrupt line 0 Enable */ +#define TMS570_DCAN_CTL_IE0 BSP_BIT32(1) + +/* field: Init - Initialization */ +#define TMS570_DCAN_CTL_Init BSP_BIT32(0) + + +/*-----------------------TMS570_DCAN_ES-----------------------*/ +/* field: PDA - Local power down mode acknowledge */ +#define TMS570_DCAN_ES_PDA BSP_BIT32(10) + +/* field: WakeUp_Pnd - Wake Up Pending */ +#define TMS570_DCAN_ES_WakeUp_Pnd BSP_BIT32(9) + +/* field: PER - Parity Error Detected */ +#define TMS570_DCAN_ES_PER BSP_BIT32(8) + +/* field: BOff - Bus-Off State */ +#define TMS570_DCAN_ES_BOff BSP_BIT32(7) + +/* field: EWarn - Warning State */ +#define TMS570_DCAN_ES_EWarn BSP_BIT32(6) + +/* field: EPass - Error Passive State */ +#define TMS570_DCAN_ES_EPass BSP_BIT32(5) + +/* field: RxOK - Received a message successfully */ +#define TMS570_DCAN_ES_RxOK BSP_BIT32(4) + +/* field: TxOK - Transmitted a message successfully */ +#define TMS570_DCAN_ES_TxOK BSP_BIT32(3) + +/* field: LEC - Last Error Code */ +#define TMS570_DCAN_ES_LEC(val) BSP_FLD32(val,0, 2) +#define TMS570_DCAN_ES_LEC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DCAN_ES_LEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_DCAN_ERRC----------------------*/ +/* field: RP - Receive Error Passive */ +#define TMS570_DCAN_ERRC_RP BSP_BIT32(15) + +/* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */ +#define TMS570_DCAN_ERRC_REC(val) BSP_FLD32(val,8, 14) +#define TMS570_DCAN_ERRC_REC_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_DCAN_ERRC_REC_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + +/* field: TEC - Transmit Error Counter. Actual state of the Transmit Error Counter. (values from 0 to 255). */ +#define TMS570_DCAN_ERRC_TEC(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_ERRC_TEC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_ERRC_TEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_DCAN_BTR----------------------*/ +/* field: BRPE - Baud Rate Prescaler Extension. */ +#define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19) +#define TMS570_DCAN_BTR_BRPE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_DCAN_BTR_BRPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: TSeg2 - Time segment after the sample point */ +#define TMS570_DCAN_BTR_TSeg2(val) BSP_FLD32(val,12, 14) +#define TMS570_DCAN_BTR_TSeg2_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DCAN_BTR_TSeg2_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: TSeg1 - Time segment before the sample point */ +#define TMS570_DCAN_BTR_TSeg1(val) BSP_FLD32(val,8, 11) +#define TMS570_DCAN_BTR_TSeg1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_DCAN_BTR_TSeg1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: SJW - Synchronization Jump Width */ +#define TMS570_DCAN_BTR_SJW(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_BTR_SJW_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_BTR_SJW_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: BRP - Baud Rate Prescaler */ +#define TMS570_DCAN_BTR_BRP(val) BSP_FLD32(val,0, 5) +#define TMS570_DCAN_BTR_BRP_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DCAN_BTR_BRP_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DCAN_INT----------------------*/ +/* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */ +#define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_INT_Int1ID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_INT_Int1ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Int0ID - Interrupt Identifier (the number here indicates the source of the interrupt) */ +#define TMS570_DCAN_INT_Int0ID(val) BSP_FLD32(val,0, 15) +#define TMS570_DCAN_INT_Int0ID_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCAN_INT_Int0ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_DCAN_TEST----------------------*/ +/* field: RDA - RAM Direct Access Enable */ +#define TMS570_DCAN_TEST_RDA BSP_BIT32(9) + +/* field: EXL - External Loop Back Mode */ +#define TMS570_DCAN_TEST_EXL BSP_BIT32(8) + +/* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */ +#define TMS570_DCAN_TEST_Rx BSP_BIT32(7) + +/* field: Tx - Control of CAN_TX pin */ +#define TMS570_DCAN_TEST_Tx(val) BSP_FLD32(val,5, 6) +#define TMS570_DCAN_TEST_Tx_GET(reg) BSP_FLD32GET(reg,5, 6) +#define TMS570_DCAN_TEST_Tx_SET(reg,val) BSP_FLD32SET(reg, val,5, 6) + +/* field: LBack - Loop Back Mode */ +#define TMS570_DCAN_TEST_LBack BSP_BIT32(4) + +/* field: Silent - Silent Mode */ +#define TMS570_DCAN_TEST_Silent BSP_BIT32(3) + + +/*----------------------TMS570_DCAN_PERR----------------------*/ +/* field: Word_Number - Word number where parity error has been detected */ +#define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10) +#define TMS570_DCAN_PERR_Word_Number_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DCAN_PERR_Word_Number_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: Message_Number - */ +#define TMS570_DCAN_PERR_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_PERR_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_PERR_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_ABOTR---------------------*/ +/* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_TXRQX---------------------*/ +/* field: TxRqstReg8 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_TXRQX_TxRqstReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_TXRQX_TxRqstReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: TxRqstReg7 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_TXRQX_TxRqstReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_TXRQX_TxRqstReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: TxRqstReg6 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_TXRQX_TxRqstReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_TXRQX_TxRqstReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: TxRqstReg5 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_TXRQX_TxRqstReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_TXRQX_TxRqstReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: TxRqstReg4 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_TXRQX_TxRqstReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_TXRQX_TxRqstReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: TxRqstReg3 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_TXRQX_TxRqstReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_TXRQX_TxRqstReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: TxRqstReg2 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_TXRQX_TxRqstReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_TXRQX_TxRqstReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: TxRqstReg1 - TxRqstReg8 */ +#define TMS570_DCAN_TXRQX_TxRqstReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_TXRQX_TxRqstReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_TXRQX_TxRqstReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_DCAN_TXRQx---------------------*/ +/* field: TxRqsX - Transmission Request Bits (for all message objects) */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_NWDATX---------------------*/ +/* field: NewDatReg8 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_NWDATX_NewDatReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_NWDATX_NewDatReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: NewDatReg7 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_NWDATX_NewDatReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_NWDATX_NewDatReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: NewDatReg6 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_NWDATX_NewDatReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_NWDATX_NewDatReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: NewDatReg5 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_NWDATX_NewDatReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_NWDATX_NewDatReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: NewDatReg4 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_NWDATX_NewDatReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_NWDATX_NewDatReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: NewDatReg3 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_NWDATX_NewDatReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_NWDATX_NewDatReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: NewDatReg2 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_NWDATX_NewDatReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_NWDATX_NewDatReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: NewDatReg1 - TxRqstReg8 */ +#define TMS570_DCAN_NWDATX_NewDatReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_NWDATX_NewDatReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_NWDATX_NewDatReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_DCAN_NWDATx---------------------*/ +/* field: NewDatX - New Data Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_INTPNDX--------------------*/ +/* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_INTPNDX_IntPndReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_INTPNDX_IntPndReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: IntPndReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_INTPNDX_IntPndReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_INTPNDX_IntPndReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: IntPndReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_INTPNDX_IntPndReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_INTPNDX_IntPndReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: IntPndReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_INTPNDX_IntPndReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_INTPNDX_IntPndReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: IntPndReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_INTPNDX_IntPndReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_INTPNDX_IntPndReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: IntPndReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_INTPNDX_IntPndReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_INTPNDX_IntPndReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: IntPndReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_INTPNDX_IntPndReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_INTPNDX_IntPndReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: IntPndReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */ +#define TMS570_DCAN_INTPNDX_IntPndReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_INTPNDX_IntPndReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_INTPNDX_IntPndReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_DCAN_INTPNDx--------------------*/ +/* field: IntPndX - Interrupt Pending Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_MSGVALX--------------------*/ +/* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15) +#define TMS570_DCAN_MSGVALX_MsgValReg8_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_DCAN_MSGVALX_MsgValReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: MsgValReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg7(val) BSP_FLD32(val,12, 13) +#define TMS570_DCAN_MSGVALX_MsgValReg7_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_DCAN_MSGVALX_MsgValReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: MsgValReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg6(val) BSP_FLD32(val,10, 11) +#define TMS570_DCAN_MSGVALX_MsgValReg6_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_DCAN_MSGVALX_MsgValReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: MsgValReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg5(val) BSP_FLD32(val,8, 9) +#define TMS570_DCAN_MSGVALX_MsgValReg5_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DCAN_MSGVALX_MsgValReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MsgValReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg4(val) BSP_FLD32(val,6, 7) +#define TMS570_DCAN_MSGVALX_MsgValReg4_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCAN_MSGVALX_MsgValReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: MsgValReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg3(val) BSP_FLD32(val,4, 5) +#define TMS570_DCAN_MSGVALX_MsgValReg3_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_DCAN_MSGVALX_MsgValReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: MsgValReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg2(val) BSP_FLD32(val,2, 3) +#define TMS570_DCAN_MSGVALX_MsgValReg2_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_DCAN_MSGVALX_MsgValReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: MsgValReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */ +#define TMS570_DCAN_MSGVALX_MsgValReg1(val) BSP_FLD32(val,0, 1) +#define TMS570_DCAN_MSGVALX_MsgValReg1_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_DCAN_MSGVALX_MsgValReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_DCAN_MSGVALx--------------------*/ +/* field: MsgVal1To32 - Message Valid Bits (for all message objects) */ +/* Whole 32 bits */ + +/*--------------------TMS570_DCAN_INTMUXx--------------------*/ +/* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DCAN_IF1CMD---------------------*/ +/* field: WR_RD - Write/Read */ +#define TMS570_DCAN_IF1CMD_WR_RD BSP_BIT32(23) + +/* field: Mask - Access Mask bits */ +#define TMS570_DCAN_IF1CMD_Mask BSP_BIT32(22) + +/* field: Arb - Access Arbitration bits */ +#define TMS570_DCAN_IF1CMD_Arb BSP_BIT32(21) + +/* field: Control - Access Control bits */ +#define TMS570_DCAN_IF1CMD_Control BSP_BIT32(20) + +/* field: ClrIntPnd - Clear Interrupt Pending bit */ +#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_BIT32(19) + +/* field: TxRqst_NewDat - Access Transmission Request bit */ +#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_BIT32(18) + +/* field: Data_A - Access Data Bytes 0-3 */ +#define TMS570_DCAN_IF1CMD_Data_A BSP_BIT32(17) + +/* field: Data_B - Access Data Bytes 4-7 */ +#define TMS570_DCAN_IF1CMD_Data_B BSP_BIT32(16) + +/* field: Busy - Busy flag */ +#define TMS570_DCAN_IF1CMD_Busy BSP_BIT32(15) + +/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */ +#define TMS570_DCAN_IF1CMD_DMA_Active BSP_BIT32(14) + +/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */ +#define TMS570_DCAN_IF1CMD_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_IF1MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF1MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF1MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF1MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF1MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF1MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF1ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF1ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF1ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF1ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF1ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF1ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF1ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF1MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF1MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF1MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF1MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF1MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF1MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF1MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF1MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - Transmit Request */ +#define TMS570_DCAN_IF1MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - Data Frame has 0-8 data bits */ +#define TMS570_DCAN_IF1MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF1MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF1MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF1MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF1DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF1DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF1DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF1DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF1DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF1DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF1DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF1DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF1DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF1DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF1DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF1DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF1DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF1DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF1DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF1DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF1DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF1DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF1DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF1DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF1DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF1DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF2CMD---------------------*/ +/* field: WR_RD - Write/Read */ +#define TMS570_DCAN_IF2CMD_WR_RD BSP_BIT32(23) + +/* field: Mask - Access Mask bits */ +#define TMS570_DCAN_IF2CMD_Mask BSP_BIT32(22) + +/* field: Arb - Access Arbitration bits */ +#define TMS570_DCAN_IF2CMD_Arb BSP_BIT32(21) + +/* field: Control - Access Control bits */ +#define TMS570_DCAN_IF2CMD_Control BSP_BIT32(20) + +/* field: ClrIntPnd - Clear Interrupt Pending bit */ +#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_BIT32(19) + +/* field: TxRqst_NewDat - Access Transmission Request bit */ +#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_BIT32(18) + +/* field: Data_A - Access Data Bytes 0-3 */ +#define TMS570_DCAN_IF2CMD_Data_A BSP_BIT32(17) + +/* field: Data_B - Access Data Bytes 4-7 */ +#define TMS570_DCAN_IF2CMD_Data_B BSP_BIT32(16) + +/* field: Busy - Busy flag */ +#define TMS570_DCAN_IF2CMD_Busy BSP_BIT32(15) + +/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */ +#define TMS570_DCAN_IF2CMD_DMA_Active BSP_BIT32(14) + +/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */ +#define TMS570_DCAN_IF2CMD_Message_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_DCAN_IF2MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF2MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF2MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF2MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF2MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF2MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF2ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF2ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF2ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF2ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF2ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF2ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF2ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF2MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF2MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF2MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF2MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF2MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF2MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF2MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF2MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - Transmit Request */ +#define TMS570_DCAN_IF2MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - Data Frame has 0-8 data bits */ +#define TMS570_DCAN_IF2MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF2MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF2MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF2MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF2DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF2DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF2DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF2DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF2DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF2DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF2DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF2DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF2DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF2DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF2DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF2DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF2DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF2DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF2DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF2DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF2DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF2DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF2DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF2DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF2DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF2DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF3OBS---------------------*/ +/* field: IF3_Upd - IF3 Update Data */ +#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_BIT32(15) + +/* field: IF3_SDB - IF3 Status of Data B read access */ +#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_BIT32(12) + +/* field: IF3_SDA - IF3 Status of Data A read access */ +#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_BIT32(11) + +/* field: IF3_SC - IF3 Status of Control bits read access */ +#define TMS570_DCAN_IF3OBS_IF3_SC BSP_BIT32(10) + +/* field: IF3_SA - IF3 Status of Arbitration data read access */ +#define TMS570_DCAN_IF3OBS_IF3_SA BSP_BIT32(9) + +/* field: IF3_SM - IF3 Status of Mask data read access */ +#define TMS570_DCAN_IF3OBS_IF3_SM BSP_BIT32(8) + +/* field: Data_B - Data B read observation */ +#define TMS570_DCAN_IF3OBS_Data_B BSP_BIT32(4) + +/* field: Data_A - Data A read observation */ +#define TMS570_DCAN_IF3OBS_Data_A BSP_BIT32(3) + +/* field: Ctrl - Ctrl read observation */ +#define TMS570_DCAN_IF3OBS_Ctrl BSP_BIT32(2) + +/* field: Arb - Arbitration data read observation */ +#define TMS570_DCAN_IF3OBS_Arb BSP_BIT32(1) + +/* field: Mask - Mask data read observation */ +#define TMS570_DCAN_IF3OBS_Mask BSP_BIT32(0) + + +/*---------------------TMS570_DCAN_IF3MSK---------------------*/ +/* field: MXtd - Mask Extended Identifier */ +#define TMS570_DCAN_IF3MSK_MXtd BSP_BIT32(31) + +/* field: MDir - Mask Message Direction */ +#define TMS570_DCAN_IF3MSK_MDir BSP_BIT32(30) + +/* field: Msk - Identifier Mask */ +#define TMS570_DCAN_IF3MSK_Msk(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF3MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF3MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*---------------------TMS570_DCAN_IF3ARB---------------------*/ +/* field: MsgVal - Message Valid */ +#define TMS570_DCAN_IF3ARB_MsgVal BSP_BIT32(31) + +/* field: Xtd - Extended Identifier */ +#define TMS570_DCAN_IF3ARB_Xtd BSP_BIT32(30) + +/* field: Dir - Message direction */ +#define TMS570_DCAN_IF3ARB_Dir BSP_BIT32(29) + +/* field: ID - Message Identifier */ +#define TMS570_DCAN_IF3ARB_ID(val) BSP_FLD32(val,0, 28) +#define TMS570_DCAN_IF3ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28) +#define TMS570_DCAN_IF3ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28) + + +/*--------------------TMS570_DCAN_IF3MCTL--------------------*/ +/* field: NewDat - New Data */ +#define TMS570_DCAN_IF3MCTL_NewDat BSP_BIT32(15) + +/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */ +#define TMS570_DCAN_IF3MCTL_MsgLst BSP_BIT32(14) + +/* field: IntPnd - Interrupt Pending */ +#define TMS570_DCAN_IF3MCTL_IntPnd BSP_BIT32(13) + +/* field: UMask - Use Acceptance Mask */ +#define TMS570_DCAN_IF3MCTL_UMask BSP_BIT32(12) + +/* field: TxIE - Transmit Interrupt Enable */ +#define TMS570_DCAN_IF3MCTL_TxIE BSP_BIT32(11) + +/* field: RxIE - Receive Interrupt Enable */ +#define TMS570_DCAN_IF3MCTL_RxIE BSP_BIT32(10) + +/* field: RmtEn - Remote Enable */ +#define TMS570_DCAN_IF3MCTL_RmtEn BSP_BIT32(9) + +/* field: TxRqst - TxRqst */ +#define TMS570_DCAN_IF3MCTL_TxRqst BSP_BIT32(8) + +/* field: EoB - End of Block */ +#define TMS570_DCAN_IF3MCTL_EoB BSP_BIT32(7) + +/* field: DLC - Data Length Code */ +#define TMS570_DCAN_IF3MCTL_DLC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCAN_IF3MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCAN_IF3MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DCAN_IF3DATA--------------------*/ +/* field: Data0 - Data 0 */ +#define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF3DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF3DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data1 - Data 1 */ +#define TMS570_DCAN_IF3DATA_Data1(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF3DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF3DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data2 - Data 2 */ +#define TMS570_DCAN_IF3DATA_Data2(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF3DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF3DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data3 - Data 3 */ +#define TMS570_DCAN_IF3DATA_Data3(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF3DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF3DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*--------------------TMS570_DCAN_IF3DATB--------------------*/ +/* field: Data4 - Data 4 */ +#define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7) +#define TMS570_DCAN_IF3DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_DCAN_IF3DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + +/* field: Data5 - Data 5 */ +#define TMS570_DCAN_IF3DATB_Data5(val) BSP_FLD32(val,8, 15) +#define TMS570_DCAN_IF3DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_DCAN_IF3DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: Data6 - Data 6 */ +#define TMS570_DCAN_IF3DATB_Data6(val) BSP_FLD32(val,16, 23) +#define TMS570_DCAN_IF3DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_DCAN_IF3DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: Data7 - Data 7 */ +#define TMS570_DCAN_IF3DATB_Data7(val) BSP_FLD32(val,24, 31) +#define TMS570_DCAN_IF3DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_DCAN_IF3DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + + +/*---------------------TMS570_DCAN_IF3UEy---------------------*/ +/* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */ +/* Whole 32 bits */ + +/*----------------------TMS570_DCAN_TIOC----------------------*/ +/* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */ +#define TMS570_DCAN_TIOC_PU BSP_BIT32(18) + +/* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */ +#define TMS570_DCAN_TIOC_PD BSP_BIT32(17) + +/* field: OD - CAN_TX open drain enable. */ +#define TMS570_DCAN_TIOC_OD BSP_BIT32(16) + +/* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */ +#define TMS570_DCAN_TIOC_Func BSP_BIT32(3) + +/* field: Dir - CAN_TX data direction. */ +#define TMS570_DCAN_TIOC_Dir BSP_BIT32(2) + +/* field: Out - CAN_TX data out write. */ +#define TMS570_DCAN_TIOC_Out BSP_BIT32(1) + + +/*----------------------TMS570_DCAN_RIOC----------------------*/ +/* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */ +#define TMS570_DCAN_RIOC_PU BSP_BIT32(18) + +/* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */ +#define TMS570_DCAN_RIOC_PD BSP_BIT32(17) + +/* field: OD - CAN_RX open drain enable. */ +#define TMS570_DCAN_RIOC_OD BSP_BIT32(16) + +/* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */ +#define TMS570_DCAN_RIOC_Func BSP_BIT32(3) + +/* field: Dir - CAN_RX data direction. */ +#define TMS570_DCAN_RIOC_Dir BSP_BIT32(2) + +/* field: Out - CAN_RX data out write. */ +#define TMS570_DCAN_RIOC_Out BSP_BIT32(1) + +/* field: In - CAN_RX data in. */ +#define TMS570_DCAN_RIOC_In BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_DCAN */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h new file mode 100644 index 0000000000..4c90276523 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h @@ -0,0 +1,183 @@ +/* The header file is generated by make_header.py from DCC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DCC +#define LIBBSP_ARM_TMS570_DCC + +#include + +typedef struct{ + uint32_t GCTRL; /*DCC Global Control Register*/ + uint32_t REV; /*DCC Revision Id Register*/ + uint32_t CNT0SEED; /*DCC Counter0 Seed Register*/ + uint32_t VALID0SEED; /*DCC Valid0 Seed Register*/ + uint32_t CNT1SEED; /*DCC Counter1 Seed Register*/ + uint32_t STAT; /*DCC Status Register*/ + uint32_t CNT0; /*DCC Counter0 Value Register*/ + uint32_t VALID0; /*DCC Valid0 Value Register*/ + uint32_t CNT1; /*DCC Counter1 Value Register*/ + uint32_t CNT1CLKSRC; /*DCC Counter1 Clock Source Selection Register*/ + uint32_t CNT0CLKSRC; /*DCC Counter0 Clock Source Selection Register*/ +} tms570_dcc_t; + + +/*----------------------TMS570_DCC_GCTRL----------------------*/ +/* field: DONE_INT_ENA - Done Interrupt Enable. */ +#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15) +#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_DCC_GCTRL_DONE_INT_ENA_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: SINGLE_SHOT - Single-Shot Mode Enable. */ +#define TMS570_DCC_GCTRL_SINGLE_SHOT(val) BSP_FLD32(val,8, 11) +#define TMS570_DCC_GCTRL_SINGLE_SHOT_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_DCC_GCTRL_SINGLE_SHOT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ERR_ENA - Error Interrupt Enable. */ +#define TMS570_DCC_GCTRL_ERR_ENA(val) BSP_FLD32(val,4, 7) +#define TMS570_DCC_GCTRL_ERR_ENA_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_DCC_GCTRL_ERR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: DCC_ENA - DCC Enable. */ +#define TMS570_DCC_GCTRL_DCC_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_GCTRL_DCC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_DCC_REV-----------------------*/ +/* field: SCHEME - Reads return 01, writes have no effect. */ +#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_DCC_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: FUNC - Functional release number. Reads return 0x000, writes have no effect. */ +#define TMS570_DCC_REV_FUNC(val) BSP_FLD32(val,16, 27) +#define TMS570_DCC_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_DCC_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: RTL - Design release number. Reads return 0x00, writes have no effect. */ +#define TMS570_DCC_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_DCC_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_DCC_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: MAJOR - Major revision number. Reads return 0x2, writes have no effect. */ +#define TMS570_DCC_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_DCC_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DCC_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CUSTOM - Custom version number. Reads return 0x0, writes have no effect. */ +#define TMS570_DCC_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_DCC_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DCC_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: MINOR - Minor revision number. Reads return 0x4, writes have no effect. */ +#define TMS570_DCC_REV_MINOR(val) BSP_FLD32(val,0, 5) +#define TMS570_DCC_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_DCC_CNT0SEED--------------------*/ +/* field: COUNT0_SEED - Seed value for DCC Counter0. */ +#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_DCC_VALID0SEED-------------------*/ +/* field: VALID0_SEED - XXX */ +#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15) +#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DCC_CNT1SEED--------------------*/ +/* field: COUNT1_SEED - Seed value for DCC Counter1. */ +#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*----------------------TMS570_DCC_STAT----------------------*/ +/* field: DONE_FLG - Single-Shot Sequence Done flag. */ +#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1) + +/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */ +#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0) + + +/*----------------------TMS570_DCC_CNT0----------------------*/ +/* field: COUNT0 - Current value of DCC Counter0. */ +#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*---------------------TMS570_DCC_VALID0---------------------*/ +/* field: VALID0 - Current value for DCC Valid0. */ +#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15) +#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_DCC_CNT1----------------------*/ +/* field: COUNT1 - Current value for DCC Counter1. */ +#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19) +#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) +#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) + + +/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/ +/* field: KEY - Key to enable clock source selection for Counter1. */ +#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15) +#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_DCC_CNT1CLKSRC_KEY_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: CNT1_CLKSRC - Clock Source for Counter1 when KEY is programmed to be 0xA. */ +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/ +/* field: CNT0_CLKSRC - Clock Source for Counter0 */ +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_DCC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h new file mode 100644 index 0000000000..717f05b010 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h @@ -0,0 +1,711 @@ +/* The header file is generated by make_header.py from DMA.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DMA +#define LIBBSP_ARM_TMS570_DMA + +#include + +typedef struct{ + uint32_t STARTADD; /*DMA Memory Protection Region start Address Register*/ + uint32_t ENDADD; /*DMA Memory Protection Region End Address Register*/ +} tms570_memory_prot_t; + +typedef struct{ + uint32_t GCTRL; /*Global Control Register*/ + uint32_t PEND; /*Channel Pending Register*/ + uint8_t reserved1 [4]; + uint32_t DMASTAT; /*DMA Status Register*/ + uint8_t reserved2 [4]; + uint32_t HWCHENAS; /*HW Channel Enable Set and Status Register*/ + uint8_t reserved3 [4]; + uint32_t HWCHENAR; /*HW Channel Enable Reset and Status Register*/ + uint8_t reserved4 [4]; + uint32_t SWCHENAS; /*SW Channel Enable Set and Status Register*/ + uint8_t reserved5 [4]; + uint32_t SWCHENAR; /*SW Channel Enable Reset and Status Register*/ + uint8_t reserved6 [4]; + uint32_t CHPRIOS; /*Channel Priority Set Register*/ + uint8_t reserved7 [4]; + uint32_t CHPRIOR; /*Channel Priority Reset Register*/ + uint8_t reserved8 [4]; + uint32_t GCHIENAS; /*Global Channel Interrupt Enable Set Register*/ + uint8_t reserved9 [4]; + uint32_t GCHIENAR; /*Global Channel Interrupt Enable Reset Register*/ + uint8_t reserved10 [4]; + uint32_t DREQASI[4]; /*DMA Request Assignment Register 0*/ + uint8_t reserved11 [48]; + uint32_t PAR0; /*Port Assignment Register 0*/ + uint32_t PAR1; /*Port Assignment Register 1*/ + uint8_t reserved12 [24]; + uint32_t FTCMAP; /*FTC Interrupt Mapping Register*/ + uint8_t reserved13 [4]; + uint32_t LFSMAP; /*LFS Interrupt Mapping Register*/ + uint8_t reserved14 [4]; + uint32_t HBCMAP; /*HBC Interrupt Mapping Register*/ + uint8_t reserved15 [4]; + uint32_t BTCMAP; /*BTC Interrupt Mapping Register*/ + uint8_t reserved16 [4]; + uint32_t BERMAP; /*BER Interrupt Mapping Register*/ + uint8_t reserved17 [4]; + uint32_t FTCINTENAS; /*FTC Interrupt Enable Set*/ + uint8_t reserved18 [4]; + uint32_t FTCINTENAR; /*FTC Interrupt Enable Reset*/ + uint8_t reserved19 [4]; + uint32_t LFSINTENAS; /*LFS Interrupt Enable Set*/ + uint8_t reserved20 [4]; + uint32_t LFSINTENAR; /*LFS Interrupt Enable Reset*/ + uint8_t reserved21 [4]; + uint32_t HBCINTENAS; /*HBC Interrupt Enable Set*/ + uint8_t reserved22 [4]; + uint32_t HBCINTENAR; /*HBC Interrupt Enable Reset*/ + uint8_t reserved23 [4]; + uint32_t BTCINTENAS; /*BTC Interrupt Enable Set*/ + uint8_t reserved24 [4]; + uint32_t BTCINTENAR; /*BTC Interrupt Enable Reset*/ + uint8_t reserved25 [4]; + uint32_t GINTFLAG; /*Global Interrupt Flag Register*/ + uint8_t reserved26 [4]; + uint32_t FTCFLAG; /*FTC Interrupt Flag Register*/ + uint8_t reserved27 [4]; + uint32_t LFSFLAG; /*LFS Interrupt Flag Register*/ + uint8_t reserved28 [4]; + uint32_t HBCFLAG; /*HBC Interrupt Flag Register*/ + uint8_t reserved29 [4]; + uint32_t BTCFLAG; /*BTC Interrupt Flag Register*/ + uint8_t reserved30 [4]; + uint32_t BERFLAG; /*BER Interrupt Flag Register*/ + uint8_t reserved31 [4]; + uint32_t FTCAOFFSET; /*FTCA Interrupt Channel Offset Register*/ + uint32_t LFSAOFFSET; /*LFSA Interrupt Channel Offset Register*/ + uint32_t HBCAOFFSET; /*HBCA Interrupt Channel Offset Register*/ + uint32_t BTCAOFFSET; /*BTCA Interrupt Channel Offset Register*/ + uint32_t BERAOFFSET; /*BERA Interrupt Channel Offset Register*/ + uint32_t FTCBOFFSET; /*FTCB Interrupt Channel Offset Register*/ + uint32_t LFSBOFFSET; /*LFSB Interrupt Channel Offset Register*/ + uint32_t HBCBOFFSET; /*HBCB Interrupt Channel Offset Register*/ + uint32_t BTCBOFFSET; /*BTCB Interrupt Channel Offset Register*/ + uint32_t BERBOFFSET; /*BERB Interrupt Channel Offset Register*/ + uint8_t reserved32 [4]; + uint32_t PTCRL; /*Port Control Register*/ + uint32_t RTCTRL; /*RAM Test Control Register*/ + uint32_t DCTRL; /*Debug Control*/ + uint32_t WPR; /*Watch Point Register*/ + uint32_t WMR; /*Watch Mask Register*/ + uint8_t reserved33 [12]; + uint32_t PBACSADDR; /*Port B Active Channel Source Address Register*/ + uint32_t PBACDADDR; /*Port B Active Channel Destination Address Register*/ + uint32_t PBACTC; /*Port B Active Channel Transfer Count Register*/ + uint8_t reserved34 [4]; + uint32_t DMAPCR; /*Parity Control Register*/ + uint32_t DMAPAR; /*DMA Parity Error Address Register*/ + uint32_t DMAMPCTRL; /*DMA Memory Protection Control Register*/ + uint32_t DMAMPST; /*DMA Memory Protection Status Register*/ + tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/ +} tms570_dma_t; + + +/*--------------------TMS570_DMA_STARTADD--------------------*/ +/* field: STARTADDRESS - Start Address defines the address at which the region begins. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DMA_ENDADD---------------------*/ +/* field: ENDADDRESS - End Address defines the address at which the region ends. */ +/* Whole 32 bits */ + +/*----------------------TMS570_DMA_GCTRL----------------------*/ +/* field: DMA_EN - DMA enable bit. */ +#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16) + +/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */ +#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14) + +/* field: DEBUG_MODE - Debug Mode. */ +#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9) +#define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: DMA_RES - DMA software reset */ +#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0) + + +/*----------------------TMS570_DMA_PEND----------------------*/ +/* field: PEND - Channel pending register. */ +#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_DMASTAT---------------------*/ +/* field: STCH - Status of DMA channels. */ +#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_HWCHENAS--------------------*/ +/* field: HWCHENA - Hardware channel enable bit. */ +#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_HWCHENAR--------------------*/ +/* field: HWCHDIS - HW channel disable bit. */ +#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_SWCHENAS--------------------*/ +/* field: SWCHENA - SW channel enable bit. */ +#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_SWCHENAR--------------------*/ +/* field: SWCHDIS - SW channel disable bit. */ +#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_CHPRIOS---------------------*/ +/* field: CPS - Channel priority set bit. */ +#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_CHPRIOR---------------------*/ +/* field: CPR - Channel priority reset bit. */ +#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GCHIENAS--------------------*/ +/* field: GCHIE - Global channel interrupt enable bit. */ +#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GCHIENAR--------------------*/ +/* field: GCHID - Global channel interrupt disable bit. */ +#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_DREQASI---------------------*/ +/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */ +#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29) +#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29) +#define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29) + +/* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */ +#define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21) +#define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */ +#define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13) +#define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */ +#define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DMA_PAR0----------------------*/ +/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */ +#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30) +#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30) +#define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30) + +/* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */ +#define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26) +#define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */ +#define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22) +#define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */ +#define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18) +#define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */ +#define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14) +#define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */ +#define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10) +#define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */ +#define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6) +#define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */ +#define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2) +#define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_DMA_PAR1----------------------*/ +/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */ +#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30) +#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30) +#define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30) + +/* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */ +#define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26) +#define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */ +#define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22) +#define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */ +#define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18) +#define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */ +#define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14) +#define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + +/* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */ +#define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10) +#define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */ +#define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6) +#define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */ +#define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2) +#define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_DMA_FTCMAP---------------------*/ +/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */ +#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_LFSMAP---------------------*/ +/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */ +#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_HBCMAP---------------------*/ +/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */ +#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BTCMAP---------------------*/ +/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */ +#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BERMAP---------------------*/ +/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */ +#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCINTENAS-------------------*/ +/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */ +#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCINTENAR-------------------*/ +/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */ +#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_LFSINTENAS-------------------*/ +/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */ +#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_LFSINTENAR-------------------*/ +/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */ +#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_HBCINTENAS-------------------*/ +/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */ +#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_HBCINTENAR-------------------*/ +/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */ +#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_BTCINTENAS-------------------*/ +/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */ +#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_BTCINTENAR-------------------*/ +/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */ +#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_DMA_GINTFLAG--------------------*/ +/* field: GINT - Global interrupt flags. */ +#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_FTCFLAG---------------------*/ +/* field: FTCI - Frame transfer complete (FTC) flags. */ +#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_LFSFLAG---------------------*/ +/* field: LFSI - Last frame started (LFS) flags. */ +#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_HBCFLAG---------------------*/ +/* field: HBCI - Half block transfer (HBC) complete flags. */ +#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BTCFLAG---------------------*/ +/* field: BTCI - Block transfer complete (BTC) flags. */ +#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_DMA_BERFLAG---------------------*/ +/* field: BERI - Bus error (BER) flags. */ +#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15) +#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/ +/* field: sbz - These bits should always be programmed as zero. */ +#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7) +#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: FTCA - Channel causing FTC interrupt Group A. */ +#define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/ +/* field: LFSA - Channel causing LFS interrupt Group A. */ +#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/ +/* field: HBCA - Channel causing HBC interrupt Group A. */ +#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/ +/* field: BTCA - Channel causing BTC interrupt Group A. */ +#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BERAOFFSET-------------------*/ +/* field: BERA - Channel causing BER interrupt Group A. */ +#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/ +/* field: FTCB - Channel causing FTC interrupt Group B. */ +#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/ +/* field: LFSB - Channel causing LFS interrupt Group B. */ +#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/ +/* field: HBCB - Channel causing HBC interrupt Group B. */ +#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/ +/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */ +#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_DMA_BERBOFFSET-------------------*/ +/* field: BERB - Channel causing BER interrupt Group B. */ +#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5) +#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_DMA_PTCRL----------------------*/ +/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */ +#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24) + +/* field: BYB - Bypass FIFO B. */ +#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18) + +/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */ +#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17) + +/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */ +#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16) + + +/*---------------------TMS570_DMA_RTCTRL---------------------*/ +/* field: RTC - RAM Test Control. */ +#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0) + + +/*----------------------TMS570_DMA_DCTRL----------------------*/ +/* field: CHNUM - Channel Number. */ +#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28) +#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: DMADBGS - DMA debug status. */ +#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16) + +/* field: DBGEN - Debug Enable. */ +#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0) + + +/*-----------------------TMS570_DMA_WPR-----------------------*/ +/* field: WP - Watch point. */ +/* Whole 32 bits */ + +/*-----------------------TMS570_DMA_WMR-----------------------*/ +/* field: WM - Watch mask. */ +/* Whole 32 bits */ + +/*--------------------TMS570_DMA_PBACSADDR--------------------*/ +/* field: PBACSA - Port B Active Channel Source Address. */ +/* Whole 32 bits */ + +/*--------------------TMS570_DMA_PBACDADDR--------------------*/ +/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */ +/* Whole 32 bits */ + +/*---------------------TMS570_DMA_PBACTC---------------------*/ +/* field: PBFTCOUNT - Port B active channel frame count. */ +#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28) +#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28) +#define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28) + +/* field: PBETCOUNT - Port B active channel element count. */ +#define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12) +#define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*---------------------TMS570_DMA_DMAPCR---------------------*/ +/* field: ERRA - Error action. */ +#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16) + +/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */ +#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Parity error detection enable. */ +#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_DMA_DMAPAR---------------------*/ +/* field: EDFLAG - Parity Error Detection Flag. */ +#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24) + +/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */ +#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11) +#define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/ +/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28) + +/* field: INT3ENA - Interrupt enable of region 3. */ +#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27) + +/* field: REG3AP - Region 3 access permission. */ +#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26) +#define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26) +#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26) + +/* field: REG3ENA - Region 3 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24) + +/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20) + +/* field: INT2ENA - Interrupt enable of region 2. */ +#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19) + +/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */ +#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18) +#define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18) +#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18) + +/* field: REG2ENA - Region 2 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16) + +/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12) + +/* field: INT1ENA - Interrupt enable of region 1. */ +#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11) + +/* field: REG1AP - Region 1 access permission. */ +#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10) +#define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: REG1ENA - Region 1 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8) + +/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */ +#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4) + +/* field: INT0ENA - Interrupt enable of region 0. */ +#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3) + +/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */ +#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2) +#define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2) +#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2) + +/* field: REG0ENA - Region 0 enable. */ +#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0) + + +/*---------------------TMS570_DMA_DMAMPST---------------------*/ +/* field: REG3FT - Region 3 fault. */ +#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24) + +/* field: REG2FT - Region 2 fault. */ +#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16) + +/* field: REG1FT - Region 1 fault. */ +#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8) + +/* field: REG0FT - Region 0 fault. */ +#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0) + + +/*--------------------TMS570_DMA_DMAMPROS--------------------*/ +/* field: STARTADDRESS - Start Address defines the address at which the region begins. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_DMA */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h new file mode 100644 index 0000000000..55d656ef86 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h @@ -0,0 +1,557 @@ +/* The header file is generated by make_header.py from DMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_DMM +#define LIBBSP_ARM_TMS570_DMM + +#include + +typedef struct{ + uint32_t GLBCTRL; /*DMM Global Control Register*/ + uint32_t INTSET; /*DMM Interrupt Set Register*/ + uint32_t INTCLR; /*DMM Interrupt Clear Register*/ + uint32_t INTLVL; /*DMM Interrupt Level Register*/ + uint32_t INTFLG; /*DMM Interrupt Flag Register*/ + uint32_t OFF1; /*DMM Interrupt Offset 1 Register*/ + uint32_t OFF2; /*DMM Interrupt Offset 2 Register*/ + uint32_t DDMDEST; /*DMM Direct Data Mode Destination Register*/ + uint32_t DDMBL; /*DMM Direct Data Mode Blocksize Register*/ + uint32_t DDMPT; /*DMM Direct Data Mode Pointer Register*/ + uint32_t INTPT; /*DMM Direct Data Mode Interrupt Pointer Register*/ + uint32_t DEST0REG1; /*DMM Destination 0 Region 1*/ + uint32_t DEST0BL1; /*DMM Destination 0 Blocksize 1*/ + uint32_t DEST0REG2; /*DMM Destination 0 Region 2*/ + uint32_t DEST0BL2; /*DMM Destination 0 Blocksize 2*/ + uint32_t DEST1REG1; /*DMM Destination 1 Region 1*/ + uint32_t DEST1BL1; /*DMM Destination 1 Blocksize 1*/ + uint32_t DEST1REG2; /*DMM Destination 1 Region 2*/ + uint32_t DEST1BL2; /*DMM Destination 1 Blocksize 2*/ + uint32_t DEST2REG1; /*DMM Destination 2 Region 1*/ + uint32_t DEST2BL1; /*DMM Destination 2 Blocksize 1*/ + uint32_t DEST2REG2; /*DMM Destination 2 Region 2*/ + uint32_t DEST2BL2; /*DMM Destination 2 Blocksize 2*/ + uint32_t DEST3REG1; /*DMM Destination 3 Region 1*/ + uint32_t DEST3BL1; /*DMM Destination 3 Blocksize 1*/ + uint32_t DEST3REG2; /*DMM Destination 3 Region 2*/ + uint32_t DEST3BL2; /*DMM Destination 3 Blocksize 2*/ + uint32_t PC0; /*DMM Pin Control 0*/ + uint32_t PC1; /*DMM Pin Control 1*/ + uint32_t PC2; /*DMM Pin Control 2*/ + uint32_t PC3; /*DMM Pin Control 3*/ + uint32_t PC4; /*DMM Pin Control 4*/ + uint32_t PC5; /*DMM Pin Control 5*/ + uint32_t PC6; /*DMM Pin Control 6*/ + uint32_t PC7; /*DMM Pin Control 7*/ + uint32_t PC8; /*DMM Pin Control 8*/ +} tms570_dmm_t; + + +/*---------------------TMS570_DMM_GLBCTRL---------------------*/ +/* field: BUSY - Busy indicator. */ +#define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24) + +/* field: CONTCLK - Continuous DMMCLK input. */ +#define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18) + +/* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */ +#define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17) + +/* field: RESET - Reset. */ +#define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16) + +/* field: DDM_WIDTH - Packet Width in direct data mode. */ +#define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10) +#define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: TM_DMM - Packet Format. */ +#define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8) + +/* field: ON_OFF - Switch module on or off */ +#define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_DMM_INTSET---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ +#define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - EO_BUFF */ +#define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - DEST1REG1 */ +#define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ +#define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Buffer Overflow. */ +#define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow. */ +#define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error. */ +#define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ +#define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error. */ +#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTCLR---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */ +#define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Set. */ +#define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */ +#define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */ +#define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Buffer Overflow. */ +#define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow. */ +#define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error. */ +#define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */ +#define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error. */ +#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTLVL---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Level */ +#define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Level */ +#define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - BMM Bus Error Response */ +#define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */ +#define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow Interrupt Level */ +#define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Level */ +#define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error Interrupt Level */ +#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0) + + +/*---------------------TMS570_DMM_INTFLG---------------------*/ +/* field: PROG_BUFF - Programmable Buffer Interrupt Flag */ +#define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17) + +/* field: EO_BUFF - End of Buffer Interrupt Flag */ +#define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16) + +/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15) + +/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14) + +/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13) + +/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12) + +/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11) + +/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10) + +/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9) + +/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8) + +/* field: BUSERROR - BMM Bus Error Response. */ +#define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7) + +/* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */ +#define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6) + +/* field: SRC_OVF - Source Overflow Interrupt Flag */ +#define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5) + +/* field: DEST3_ERR - Destination 3 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4) + +/* field: DEST2_ERR - Destination 2 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3) + +/* field: DEST1_ERR - Destination 1 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2) + +/* field: DEST0_ERR - Destination 0 Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1) + +/* field: PACKET_ERR_INT - Packet Error Interrupt Flag */ +#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0) + + +/*----------------------TMS570_DMM_OFF1----------------------*/ +/* field: OFFSET - User and privilege mode (read): */ +#define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4) +#define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*----------------------TMS570_DMM_OFF2----------------------*/ +/* field: OFFSET - User and privilege mode (read): */ +#define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4) +#define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_DMM_DDMDEST---------------------*/ +/* field: STARTADDR - These bits define the starting address of the buffer. */ +/* Whole 32 bits */ + +/*----------------------TMS570_DMM_DDMBL----------------------*/ +/* field: BLOCKSIZE - These bits define the size of the buffer region */ +#define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_DMM_DDMPT----------------------*/ +/* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */ +#define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14) +#define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14) +#define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) + + +/*----------------------TMS570_DMM_INTPT----------------------*/ +/* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */ +#define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14) +#define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14) +#define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14) + + +/*--------------------TMS570_DMM_DESTxREG1--------------------*/ +/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ +#define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31) +#define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) +#define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) + +/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ +#define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_DMM_DESTxBL1--------------------*/ +/* field: BLOCKSIZE - These bits define the length of the buffer region. */ +#define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_DMM_DESTxREG2--------------------*/ +/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */ +#define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31) +#define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31) +#define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31) + +/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */ +#define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_DMM_DESTxBL2--------------------*/ +/* field: BLOCKSIZE - These bits define the length of the buffer region. */ +#define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_DMM_PC0-----------------------*/ +/* field: ENAFUNC - Functional mode of DMMENA pin. */ +#define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18) + +/* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */ +#define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKFUNC - Functional mode of DMMCLK pin. */ +#define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1) + +/* field: SYNCFUNC - Functional mode of DMMSYNC pin. */ +#define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC1-----------------------*/ +/* field: ENADIR - Direction of DMMENA pin. */ +#define TMS570_DMM_PC1_ENADIR BSP_BIT32(18) + +/* field: DATAxDIR - Direction of DMMDATA[x] pin. */ +#define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKDIR - Direction of DMMCLK pin. */ +#define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1) + +/* field: SYNCDIR - Direction of DMMSYNC pin. */ +#define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC2-----------------------*/ +/* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_ENAIN BSP_BIT32(18) + +/* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */ +#define TMS570_DMM_PC2_CLKIN BSP_BIT32(1) + +/* field: SYNCIN - DMMSYNC input. */ +#define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC3-----------------------*/ +/* field: ENAOUT - Output state of DMMENA pin. */ +#define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18) + +/* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */ +#define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKOUT - Output state of DMMCLK pin. */ +#define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1) + +/* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */ +#define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC4-----------------------*/ +/* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */ +#define TMS570_DMM_PC4_ENASET BSP_BIT32(18) + +/* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */ +#define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKSET - Sets output state of DMMCLK pin to logic high. */ +#define TMS570_DMM_PC4_CLKSET BSP_BIT32(1) + +/* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */ +#define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC5-----------------------*/ +/* field: ENACLR - Sets output state of DMMENA pin to logic low. */ +#define TMS570_DMM_PC5_ENACLR BSP_BIT32(18) + +/* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */ +#define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */ +#define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1) + +/* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */ +#define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC6-----------------------*/ +/* field: ENAPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18) + +/* field: DATAxPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1) + +/* field: SYNCPDR - Open Drain enable. */ +#define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC7-----------------------*/ +/* field: ENAPDIS - Pull disable. */ +#define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18) + +/* field: DATAxPDIS - Pull disable. */ +#define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPDIS - Pull disable. */ +#define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1) + +/* field: SYNCPDIS - Pull disable. */ +#define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0) + + +/*-----------------------TMS570_DMM_PC8-----------------------*/ +/* field: ENAPSEL - Pull disable. */ +#define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18) + +/* field: DATAxPSEL - Pull disable. */ +#define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17) +#define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17) +#define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17) + +/* field: CLKPSEL - Pull disable. */ +#define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1) + +/* field: SYNCPSEL - Pull disable. */ +#define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_DMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h new file mode 100644 index 0000000000..decf5bbeff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h @@ -0,0 +1,126 @@ +/* The header file is generated by make_header.py from EFUSE.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EFUSE +#define LIBBSP_ARM_TMS570_EFUSE + +#include + +typedef struct{ + uint32_t EFCBOUND; /*EFC Boundary Control Register*/ + uint8_t reserved1 [12]; + uint32_t EFCPINS; /*EFC Pins Register*/ + uint8_t reserved2 [12]; + uint32_t EFC_ERR_STAT; /*EFC Error Status Register*/ + uint8_t reserved3 [8]; + uint32_t EFC_ST_CY; /*EFC Self Test Cycles Register*/ + uint32_t EFC_ST_SIG; /*EFC Self Test Signature Register*/ +} tms570_efuse_t; + + +/*-------------------TMS570_EFUSE_EFCBOUND-------------------*/ +/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_BIT32(21) + +/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_BIT32(20) + +/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_BIT32(19) + +/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */ +#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_BIT32(18) + +/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */ +#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_BIT32(17) + +/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */ +#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_BIT32(16) + +/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */ +#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_BIT32(15) + +/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */ +#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_BIT32(14) + +/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */ +#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_BIT32(13) + +/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */ +#define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3) +#define TMS570_EFUSE_EFCBOUND_Input_Enable_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_EFUSE_EFCPINS--------------------*/ +/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */ +#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_BIT32(15) + +/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */ +#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_BIT32(14) + +/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */ +#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_BIT32(12) + +/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */ +#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_BIT32(11) + +/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */ +#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_BIT32(10) + + +/*-----------------TMS570_EFUSE_EFC_ERR_STAT-----------------*/ +/* field: Instruc_Done - Instruction done. */ +#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_BIT32(5) + +/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */ +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4) +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-------------------TMS570_EFUSE_EFC_ST_CY-------------------*/ +/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */ +/* Whole 32 bits */ + +/*------------------TMS570_EFUSE_EFC_ST_SIG------------------*/ +/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_EFUSE */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h new file mode 100644 index 0000000000..c7c564cf49 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h @@ -0,0 +1,285 @@ +/* The header file is generated by make_header.py from EMACC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMACC +#define LIBBSP_ARM_TMS570_EMACC + +#include + +typedef struct{ + uint32_t REVID; /*EMAC Control Module Revision ID Register*/ + uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/ + uint8_t reserved1 [4]; + uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/ + uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/ + uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ + uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/ + uint8_t reserved2 [32]; + uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/ + uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/ + uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/ + uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/ + uint8_t reserved3 [32]; + uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/ + uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/ +} tms570_emacc_t; + + +/*---------------------TMS570_EMACC_REVID---------------------*/ +/* field: REV - Identifies the EMAC Control Module revision. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACC_SOFTRESET-------------------*/ +/* field: RESET - Software reset bit for the EMAC Control Module. */ +#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0) + + +/*------------------TMS570_EMACC_INTCONTROL------------------*/ +/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17) + +/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16) + +/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */ +#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/ +/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7) + +/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6) + +/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5) + +/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4) + +/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3) + +/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2) + +/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1) + +/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0RXEN--------------------*/ +/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0TXEN--------------------*/ +/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */ +#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7) + +/* field: TXCH6EN - TXCH6EN */ +#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6) + +/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */ +#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5) + +/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */ +#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4) + +/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */ +#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3) + +/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */ +#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2) + +/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */ +#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1) + +/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */ +#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0MISCEN-------------------*/ +/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */ +#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3) + +/* field: HOSTPENDEN - HOSTPENDEN */ +#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2) + +/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */ +#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1) + +/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */ +#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0) + + +/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/ +/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7) + +/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6) + +/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5) + +/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4) + +/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3) + +/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2) + +/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1) + +/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/ +/* field: RXCH7STAT - RXCH7STAT */ +#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7) + +/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6) + +/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5) + +/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4) + +/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3) + +/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2) + +/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1) + +/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/ +/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7) + +/* field: TXCH6STAT - TXCH6STAT */ +#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6) + +/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5) + +/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4) + +/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3) + +/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2) + +/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1) + +/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0) + + +/*------------------TMS570_EMACC_C0MISCSTAT------------------*/ +/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3) + +/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2) + +/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1) + +/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/ +/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/ +/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + + +#endif /* LIBBSP_ARM_TMS570_EMACC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h new file mode 100644 index 0000000000..c6e63210aa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h @@ -0,0 +1,898 @@ +/* The header file is generated by make_header.py from EMACM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMACM +#define LIBBSP_ARM_TMS570_EMACM + +#include + +typedef struct{ + uint32_t TXREVID; /*Transmit Revision ID Register*/ + uint32_t TXCONTROL; /*Transmit Control Register*/ + uint32_t TXTEARDOWN; /*Transmit Teardown Register*/ + uint8_t reserved1 [4]; + uint32_t RXREVID; /*Receive Revision ID Register*/ + uint32_t RXCONTROL; /*Receive Control Register*/ + uint32_t RXTEARDOWN; /*Receive Teardown Register*/ + uint8_t reserved2 [100]; + uint32_t TXINTSTATRAW; /*Transmit Interrupt Status (Unmasked) Register*/ + uint32_t TXINTSTATMASKED; /*Transmit Interrupt Status (Masked) Register*/ + uint32_t TXINTMASKSET; /*Transmit Interrupt Mask Set Register*/ + uint32_t TXINTMASKCLEAR; /*Transmit Interrupt Clear Register*/ + uint32_t MACINVECTOR; /*MAC Input Vector Register*/ + uint32_t MACEOIVECTOR; /*MAC End Of Interrupt Vector Register*/ + uint8_t reserved3 [8]; + uint32_t RXINTSTATRAW; /*Receive Interrupt Status (Unmasked) Register*/ + uint32_t RXINTSTATMASKED; /*Receive Interrupt Status (Masked) Register*/ + uint32_t RXINTMASKSET; /*Receive Interrupt Mask Set Register*/ + uint32_t RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32_t MACINTSTATRAW; /*MAC Interrupt Status (Unmasked) Register*/ + uint32_t MACINTSTATMASKED; /*MAC Interrupt Status (Masked) Register*/ + uint32_t MACINTMASKSET; /*MAC Interrupt Mask Set Register*/ + uint32_t MACINTMASKCLEAR; /*MAC Interrupt Mask Clear Register*/ + uint8_t reserved4 [64]; + uint32_t RXMBPENABLE; /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/ + uint32_t RXUNICASTSET; /*Receive Unicast Enable Set Register*/ + uint32_t RXUNICASTCLEAR; /*Receive Unicast Clear Register*/ + uint32_t RXMAXLEN; /*Receive Maximum Length Register*/ + uint32_t RXBUFFEROFFSET; /*Receive Buffer Offset Register*/ + uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/ + uint8_t reserved5 [8]; + uint32_t RXFLOWTHRESH[8]; /*Receive Channel Flow Control Threshold Register*/ + uint32_t RXFREEBUFFER[8]; /*Receive Channel Free Buffer Count Register*/ + uint32_t MACCONTROL; /*MAC Control Register*/ + uint32_t MACSTATUS; /*MAC Status Register*/ + uint32_t EMCONTROL; /*Emulation Control Register*/ + uint32_t FIFOCONTROL; /*FIFO Control Register*/ + uint32_t MACCONFIG; /*MAC Configuration Register*/ + uint32_t SOFTRESET; /*Soft Reset Register*/ + uint8_t reserved6 [88]; + uint32_t MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + uint32_t MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32_t MACHASH1; /*MAC Hash Address Register 1*/ + uint32_t MACHASH2; /*MAC Hash Address Register 2*/ + uint32_t BOFFTEST; /*Back Off Test Register*/ + uint32_t TPACETEST; /*Transmit Pacing Algorithm Test Register*/ + uint32_t RXPAUSE; /*Receive Pause Timer Register*/ + uint32_t TXPAUSE; /*Transmit Pause Timer Register*/ + uint8_t reserved7 [784]; + uint32_t MACADDRLO; /*MAC Address Low Bytes Register*/ + uint32_t MACADDRHI; /*MAC Address High Bytes Register*/ + uint32_t MACINDEX; /*MAC Index Register*/ + uint8_t reserved8 [244]; + uint32_t TXHDP[8]; /*Transmit Channel DMA Head Descriptor Pointer Register*/ + uint32_t RXHDP[8]; /*Receive Channel DMA Head Descriptor Pointer Register*/ + uint32_t TXCP[8]; /*Transmit Channel Completion Pointer Register*/ + uint32_t RXCP[8]; /*Receive Channel Completion Pointer Register*/ +} tms570_emacm_t; + + +/*--------------------TMS570_EMACM_TXREVID--------------------*/ +/* field: TXREV - Transmit module revision */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_TXCONTROL-------------------*/ +/* field: TXEN - Transmit enable */ +#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0) + + +/*------------------TMS570_EMACM_TXTEARDOWN------------------*/ +/* field: TXTDNCH - Transmit teardown channel. */ +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_EMACM_RXREVID--------------------*/ +/* field: RXREV - Receive module revision */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_RXCONTROL-------------------*/ +/* field: RXEN - Receive enable */ +#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0) + + +/*------------------TMS570_EMACM_RXTEARDOWN------------------*/ +/* field: RXTDNCH - Receive teardown channel. */ +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/ +/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7) + +/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6) + +/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5) + +/* field: TX4PEND - X4PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4) + +/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3) + +/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2) + +/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1) + +/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0) + + +/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/ +/* field: TX7PEND - TX7PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7) + +/* field: TX6PEND - TX6PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6) + +/* field: TX5PEND - TX5PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5) + +/* field: TX4PEND - TX4PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4) + +/* field: TX3PEND - TX3PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3) + +/* field: TX2PEND - TX2PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2) + +/* field: TX1PEND - TX1PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1) + +/* field: TX0PEND - TX0PEND masked interrupt read */ +#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/ +/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7) + +/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6) + +/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5) + +/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4) + +/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3) + +/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2) + +/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1) + +/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/ +/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7) + +/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6) + +/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5) + +/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4) + +/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3) + +/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2) + +/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1) + +/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0) + + +/*------------------TMS570_EMACM_MACINVECTOR------------------*/ +/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */ +#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27) + +/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */ +#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26) + +/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */ +#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25) + +/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */ +#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24) + +/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */ +#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */ +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */ +#define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/ +/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */ +#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4) +#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/ +/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15) + +/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14) + +/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13) + +/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12) + +/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11) + +/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10) + +/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9) + +/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8) + +/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7) + +/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6) + +/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5) + +/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4) + +/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3) + +/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2) + +/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1) + +/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */ +#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/ +/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15) + +/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14) + +/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13) + +/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12) + +/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11) + +/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10) + +/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9) + +/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8) + +/* field: RX7PEND - RX7PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7) + +/* field: RX6PEND - RX6PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6) + +/* field: RX5PEND - RX5PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5) + +/* field: RX4PEND - RX4PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4) + +/* field: RX3PEND - RX3PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3) + +/* field: RX2PEND - RX2PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2) + +/* field: RX1PEND - RX1PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1) + +/* field: RX0PEND - RX0PEND masked interrupt read */ +#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/ +/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15) + +/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14) + +/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13) + +/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12) + +/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11) + +/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10) + +/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9) + +/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8) + +/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7) + +/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6) + +/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5) + +/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4) + +/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3) + +/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2) + +/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1) + +/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/ +/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15) + +/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14) + +/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13) + +/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12) + +/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11) + +/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10) + +/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9) + +/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8) + +/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7) + +/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6) + +/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5) + +/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4) + +/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3) + +/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2) + +/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1) + +/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */ +#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/ +/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */ +#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1) + +/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */ +#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0) + + +/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/ +/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */ +#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1) + +/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */ +#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/ +/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1) + +/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0) + + +/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/ +/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1) + +/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */ +#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0) + + +/*------------------TMS570_EMACM_RXMBPENABLE------------------*/ +/* field: RXPASSCRC - Pass receive CRC enable bit */ +#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30) + +/* field: RXQOSEN - Receive quality of service enable bit */ +#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29) + +/* field: RXNOCHAIN - Receive no buffer chaining bit */ +#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28) + +/* field: RXCMFEN - Receive copy MAC control frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24) + +/* field: RXCSFEN - Receive copy short frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23) + +/* field: RXCEFEN - Receive copy error frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22) + +/* field: RXCAFEN - Receive copy all frames enable bit. */ +#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21) + +/* field: RXPROMCH - Receive promiscuous channel select */ +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: RXBROADEN - Receive broadcast enable. */ +#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13) + +/* field: RXBROADCH - Receive broadcast channel select */ +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10) +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: RXMULTEN - RX multicast enable. */ +#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5) + + +/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/ +/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0) + + +/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/ +/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */ +#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/ +/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */ +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/ +/* field: RXBUFFEROFFSET - Receive buffer offset value. */ +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/ +/* field: RXFILTERTHRESH - Receive filter low threshold. */ +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/ +/* field: RXnFLOWTHRESH - Receive flow threshold. */ +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/ +/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */ +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_EMACM_MACCONTROL------------------*/ +/* field: RMIISPEED - RMII interface transmit and receive speed select. */ +#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15) + +/* field: RXOFFLENBLOCK - Receive offset / length word write block. */ +#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14) + +/* field: RXOWNERSHIP - Receive ownership write bit value. */ +#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13) + +/* field: CMDIDLE - Command Idle bit */ +#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11) + +/* field: TXSHORTGAPEN - Transmit Short Gap Enable */ +#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10) + +/* field: TXPTYPE - Transmit queue priority type */ +#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9) + +/* field: TXPACE - Transmit pacing enable bit */ +#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6) + +/* field: GMIIEN - GMII enable bit */ +#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5) + +/* field: TXFLOWEN - Transmit flow control enable bit. */ +#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4) + +/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */ +#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3) + +/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */ +#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1) + +/* field: FULLDUPLEX - Full duplex mode. */ +#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_MACSTATUS-------------------*/ +/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */ +#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31) + +/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */ +#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23) +#define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23) +#define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23) + +/* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */ +#define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */ +#define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15) +#define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */ +#define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10) +#define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */ +#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2) + +/* field: RXFLOWACT - Receive flow control active bit. */ +#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1) + +/* field: TXFLOWACT - Transmit flow control active bit. */ +#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0) + + +/*-------------------TMS570_EMACM_EMCONTROL-------------------*/ +/* field: SOFT - Emulation soft bit. */ +#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1) + +/* field: FREE - Emulation free bit. */ +#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0) + + +/*------------------TMS570_EMACM_FIFOCONTROL------------------*/ +/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */ +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1) +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*-------------------TMS570_EMACM_MACCONFIG-------------------*/ +/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */ +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */ +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: ADDRESSTYPE - Address type */ +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACCFIG - MAC configuration value */ +#define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_SOFTRESET-------------------*/ +/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */ +#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0) + + +/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/ +/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */ +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */ +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/ +/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */ +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACHASH1-------------------*/ +/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_MACHASH2-------------------*/ +/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACM_BOFFTEST-------------------*/ +/* field: RNDNUM - Backoff random number generator. */ +#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25) +#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25) +#define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25) + +/* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */ +#define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15) +#define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: TXBACKOFF - Backoff count. */ +#define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9) +#define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_EMACM_TPACETEST-------------------*/ +/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */ +#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4) +#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_EMACM_RXPAUSE--------------------*/ +/* field: PAUSETIMER - Receive pause timer value. */ +#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_EMACM_TXPAUSE--------------------*/ +/* field: PAUSETIMER - Transmit pause timer value. */ +#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15) +#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_EMACM_MACADDRLO-------------------*/ +/* field: VALID - Address valid bit. */ +#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20) + +/* field: MATCHFILT - Match or filter bit */ +#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19) + +/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */ +#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18) +#define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */ +#define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACADDR1 - MAC address bits 15-8 (byte 1) */ +#define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACADDRHI-------------------*/ +/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */ +#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31) +#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */ +#define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23) +#define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */ +#define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15) +#define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */ +#define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7) +#define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_EMACM_MACINDEX-------------------*/ +/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */ +#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2) +#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_EMACM_TXHDP---------------------*/ +/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_RXHDP---------------------*/ +/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_TXCP---------------------*/ +/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */ +/* Whole 32 bits */ + +/*---------------------TMS570_EMACM_RXCP---------------------*/ +/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_EMACM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h new file mode 100644 index 0000000000..0810fd097f --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h @@ -0,0 +1,468 @@ +/* The header file is generated by make_header.py from EMIF.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMIF +#define LIBBSP_ARM_TMS570_EMIF + +#include + +typedef struct{ + uint32_t MIDR; /*Module ID Register*/ + uint32_t AWCC; /*Asynchronous Wait Cycle Configuration Register*/ + uint32_t SDCR; /*SDRAM Configuration Register*/ + uint32_t SDRCR; /*SDRAM Refresh Control Register*/ + uint32_t CE2CFG; /*Asynchronous 1 Configuration Register*/ + uint32_t CE3CFG; /*Asynchronous 2 Configuration Register*/ + uint32_t CE4CFG; /*Asynchronous 3 Configuration Register*/ + uint32_t CE5CFG; /*Asynchronous 4 Configuration Register*/ + uint32_t SDTIMR; /*SDRAM Timing Register*/ + uint8_t reserved1 [24]; + uint32_t SDSRETR; /*SDRAM Self Refresh Exit Timing Register*/ + uint32_t INTRAW; /*EMIF Interrupt Raw Register*/ + uint32_t INTMSK; /*EMIF Interrupt Mask Register*/ + uint32_t INTMSKSET; /*EMIF Interrupt Mask Set Register*/ + uint32_t INTMSKCLR; /*EMIF Interrupt Mask Clear Register*/ + uint8_t reserved2 [24]; + uint32_t PMCR; /*Page Mode Control Register*/ +} tms570_emif_t; + + +/*----------------------TMS570_EMIF_MIDR----------------------*/ +/* field: REV - Module ID of EMIF. See the device-specific data manual. */ +/* Whole 32 bits */ + +/*----------------------TMS570_EMIF_AWCC----------------------*/ +/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */ +#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29) + +/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */ +#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28) + +/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23) +#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23) +#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23) + +/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21) +#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21) +#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21) + +/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */ +#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19) +#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19) +#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19) + +/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */ +#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17) +#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */ +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7) +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_EMIF_SDCR----------------------*/ +/* field: SR - Self-Refresh mode bit. */ +#define TMS570_EMIF_SDCR_SR BSP_BIT32(31) + +/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */ +#define TMS570_EMIF_SDCR_PD BSP_BIT32(30) + +/* field: PDWR - Perform refreshes during power down. */ +#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29) + +/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */ +#define TMS570_EMIF_SDCR_NM BSP_BIT32(14) + +/* field: CL - CAS Latency. */ +#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11) +#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ +#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8) + +/* field: IBANK - Internal SDRAM Bank size. */ +#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */ +#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2) +#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_EMIF_SDRCR---------------------*/ +/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */ +#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12) +#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*---------------------TMS570_EMIF_CE2CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE3CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE4CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - Minimum Turn-Around time. */ +#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_CE5CFG---------------------*/ +/* field: SS - Select Strobe bit. */ +#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31) + +/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ +#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30) + +/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29) +#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29) +#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29) + +/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25) +#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19) +#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19) +#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19) + +/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16) +#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12) +#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12) +#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12) + +/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */ +#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3) +#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */ +#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1) +#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_EMIF_SDTIMR---------------------*/ +/* field: T_RFC - Specifies the Trfc value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31) +#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31) +#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31) + +/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */ +#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26) +#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: T_RCD - Specifies the Trcd value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22) +#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22) +#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22) + +/* field: T_WR - Specifies the Twr value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18) +#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: T_RAS - Specifies the Tras value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15) +#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: T_RC - Specifies the Trc value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11) +#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: T_RRD - Specifies the Trrd value of the SDRAM. */ +#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6) +#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + + +/*--------------------TMS570_EMIF_SDSRETR--------------------*/ +/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */ +#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4) +#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_EMIF_INTRAW---------------------*/ +/* field: WR - Wait Rise. */ +#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2) + +/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */ +#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1) + +/* field: AT - Asynchronous Timeout. */ +#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0) + + +/*---------------------TMS570_EMIF_INTMSK---------------------*/ +/* field: WR_MASKED - Wait Rise Masked. */ +#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2) + +/* field: LT_MASKED - Masked Line Trap. */ +#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1) + +/* field: AT_MASKED - Asynchronous Timeout Masked. */ +#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0) + + +/*-------------------TMS570_EMIF_INTMSKSET-------------------*/ +/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */ +#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2) + +/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */ +#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1) + +/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */ +#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0) + + +/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/ +/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */ +#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2) + +/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */ +#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1) + +/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */ +#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0) + + +/*----------------------TMS570_EMIF_PMCR----------------------*/ +/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31) +#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31) +#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31) + +/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25) + +/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */ +#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24) + +/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23) +#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23) +#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23) + +/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17) + +/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */ +#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16) + +/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */ +#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15) +#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15) +#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15) + +/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */ +#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9) + +/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */ +#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8) + +/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7) +#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7) +#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7) + +/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1) + +/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */ +#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_EMIF */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h new file mode 100644 index 0000000000..3ea4b6b43c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from ESM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_ESM +#define LIBBSP_ARM_TMS570_ESM + +#include + +typedef struct{ + uint32_t EEPAPR1; /*ESM Enable ERROR Pin Action/Response Register 1*/ + uint32_t DEPAPR1; /*ESM Disable ERROR Pin Action/Response Register 1*/ + uint32_t IESR1; /*ESM Interrupt Enable Set/Status Register 1*/ + uint32_t IECR1; /*ESM Interrupt Enable Clear/Status Register 1*/ + uint32_t ILSR1; /*Interrupt Level Set/Status Register 1*/ + uint32_t ILCR1; /*Interrupt Level Clear/Status Register 1*/ + uint32_t SR[3]; /*ESM Status Register*/ + uint32_t EPSR; /*ESM ERROR Pin Status Register*/ + uint32_t IOFFHR; /*ESM Interrupt Offset High Register*/ + uint32_t IOFFLR; /*ESM Interrupt Offset Low Register*/ + uint32_t LTCR; /*ESM Low-Time Counter Register*/ + uint32_t LTCPR; /*ESM Low-Time Counter Preload Register*/ + uint32_t EKR; /*ESM Error Key Register*/ + uint32_t SSR2; /*ESM Status Shadow Register 2*/ + uint32_t IEPSR4; /*ESM Influence ERROR Pin Set/Status Register 4*/ + uint32_t IEPCR4; /*ESM Influence ERROR Pin Clear/Status Register 4*/ + uint32_t IESR4; /*ESM Interrupt Enable Set/Status Register 4*/ + uint32_t IECR4; /*ESM Interrupt Enable Clear/Status Register 4*/ + uint32_t ILSR4; /*Interrupt Level Set/Status Register 4*/ + uint32_t ILCR4; /*Interrupt Level Clear/Status Register 4*/ + uint32_t SR4; /*ESM Status Register 4*/ +} tms570_esm_t; + + +/*---------------------TMS570_ESM_EEPAPR1---------------------*/ +/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_DEPAPR1---------------------*/ +/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IESR1----------------------*/ +/* field: INTENSET - Set interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IECR1----------------------*/ +/* field: INTENCLR - Clear Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILSR1----------------------*/ +/* field: INTLVLSET - Set Interrupt Priority */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILCR1----------------------*/ +/* field: INTLVLCLR - Clear Interrupt Priority. */ +/* Whole 32 bits */ + +/*-----------------------TMS570_ESM_SR-----------------------*/ +/* field: ESF - Error Status Flag. Provides status information on a pending error. */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_EPSR----------------------*/ +/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */ +#define TMS570_ESM_EPSR_EPSF BSP_BIT32(0) + + +/*---------------------TMS570_ESM_IOFFHR---------------------*/ +/* field: INTOFFH - Offset High Level Interrupt. */ +#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6) +#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*---------------------TMS570_ESM_IOFFLR---------------------*/ +/* field: INTOFFL - Offset Low Level Interrupt. */ +#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6) +#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*----------------------TMS570_ESM_LTCR----------------------*/ +/* field: LTC - ERROR Pin Low-Time Counter */ +#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15) +#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_ESM_LTCPR----------------------*/ +/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */ +#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15) +#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_ESM_EKR-----------------------*/ +/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */ +#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_ESM_SSR2----------------------*/ +/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_IEPSR4---------------------*/ +/* field: IEPSET - Set Influence on ERROR Pin */ +/* Whole 32 bits */ + +/*---------------------TMS570_ESM_IEPCR4---------------------*/ +/* field: IEPCLR - Clear Influence on ERROR Pin */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IESR4----------------------*/ +/* field: INTENSET - Set Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_IECR4----------------------*/ +/* field: INTENCLR - Clear Interrupt Enable */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILSR4----------------------*/ +/* field: INTLVLSET - Set Interrupt Level */ +/* Whole 32 bits */ + +/*----------------------TMS570_ESM_ILCR4----------------------*/ +/* field: INTLVLCLR - Clear Interrupt Level */ +/* Whole 32 bits */ + +/*-----------------------TMS570_ESM_SR4-----------------------*/ +/* field: ESF - Error Status Flag. Provides status information on a pending error. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_ESM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h new file mode 100644 index 0000000000..6c5a127d0b --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h @@ -0,0 +1,675 @@ +/* The header file is generated by make_header.py from FLASH.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_FLASH +#define LIBBSP_ARM_TMS570_FLASH + +#include + +typedef struct{ + uint32_t FRDCNTL; /*Flash Option Control Register*/ + uint8_t reserved1 [4]; + uint32_t FEDACTRL1; /*Flash Error Detection and Correction Control Register 1*/ + uint32_t FEDACTRL2; /*Flash Error Detection and Correction Control Register 2*/ + uint32_t FCORERRCNT; /*Flash Correctable Error Count Register*/ + uint32_t FCORERRADD; /*Flash Correctable Error Address Register*/ + uint32_t FCORERRPOS; /*Flash Correctable Error Position Register*/ + uint32_t FEDACSTATUS; /*Flash Error Detection and Correction Status Register*/ + uint32_t FUNCERRADD; /*Flash Un-Correctable Error Address Register*/ + uint32_t FEDACSDIS; /*Flash Error Detection and Correction Sector Disable Register*/ + uint32_t FPRIMADDTAG; /*Flash Primary Address Tag Register*/ + uint32_t FDUPADDTAG; /*Flash Duplicate Address Tag Register*/ + uint32_t FBPROT; /*Flash Bank Protection Register*/ + uint32_t FBSE; /*Flash Bank Sector Enable Register*/ + uint32_t FBBUSY; /*Flash Bank Busy Register*/ + uint32_t FBAC; /*Flash Bank Access Control Register*/ + uint32_t FBFALLBACK; /*Flash Bank Fallback Power Register*/ + uint32_t FBPRDY; /*Flash Bank/Pump Ready Register*/ + uint32_t FPAC1; /*Flash Pump Access Control Register 1*/ + uint32_t FPAC2; /*Flash Pump Access Control Register 2*/ + uint32_t FMAC; /*Flash Module Access Control Register*/ + uint32_t FMSTAT; /*Flash Module Status Register*/ + uint32_t FEMUDMSW; /*EEPROM Emulation Data MSW Register*/ + uint32_t FEMUDLSW; /*EEPROM Emulation Data LSW Register*/ + uint32_t FEMUECC; /*EEPROM Emulation ECC Register*/ + uint8_t reserved2 [4]; + uint32_t FEMUADDR; /*EEPROM Emulation Address Register*/ + uint32_t FDIAGCTRL; /*Diagnostic Control Register*/ + uint32_t FRAWDATAH; /*Uncorrected Raw Data High Register*/ + uint32_t FRAWDATAL; /*Uncorrected Raw Data Low Register*/ + uint32_t FRAWECC; /*Uncorrected Raw ECC Register*/ + uint32_t FPAROVR; /*Parity Override Register*/ + uint8_t reserved3 [64]; + uint32_t FEDACSDIS2; /*Flash Error Detection and Correction Sector Disable Register 2*/ + uint8_t reserved4 [452]; + uint32_t FSMWRENA; /*FSM Register Write Enable*/ + uint8_t reserved5 [24]; + uint32_t FSMSECTOR; /*FSM Sector Register*/ + uint8_t reserved6 [16]; + uint32_t EEPROMCONFIG; /*EEPROM Emulation Configuration Register*/ + uint8_t reserved7 [76]; + uint32_t EECTRL1; /*EEPROM Emulation Error Detection and Correction Control Register 1*/ + uint32_t EECTRL2; /*EEPROM Emulation Error Detection and Correction Control Register 2*/ + uint32_t EECORERRCNT; /*EEPROM Emulation Correctable Error Count Register*/ + uint32_t EECORERRADD; /*EEPROM Emulation Correctable Error Address Register*/ + uint32_t EECORERRPOS; /*EEPROM Emulation Correctable Error Bit Position Register*/ + uint32_t EESTATUS; /*EEPROM Emulation Error Status Register*/ + uint32_t EEUNCERRADD; /*EEPROM Emulation Un-Correctable Error Address Register*/ + uint8_t reserved8 [220]; + uint32_t FCFGBANK; /*Flash Bank Configuration Register*/ +} tms570_flash_t; + + +/*--------------------TMS570_FLASH_FRDCNTL--------------------*/ +/* field: RWAIT - Random/data Read Wait State */ +#define TMS570_FLASH_FRDCNTL_RWAIT(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FRDCNTL_RWAIT_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FRDCNTL_RWAIT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ASWSTEN - Address Setup Wait State Enable */ +#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_BIT32(4) + +/* field: ENPIPE - Enable Pipeline Mode */ +#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_BIT32(0) + + +/*-------------------TMS570_FLASH_FEDACTRL1-------------------*/ +/* field: SUSP_IGNR - Suspend Ignore. */ +#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_BIT32(24) + +/* field: EDACMODE - Error Correction Mode. */ +#define TMS570_FLASH_FEDACTRL1_EDACMODE(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: EOFEN - Event on Ones Fail Enable */ +#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_BIT32(10) + +/* field: EZFEN - Event on Zeros Fail Enable */ +#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_BIT32(9) + +/* field: EPEN - Error Profiling Enable. */ +#define TMS570_FLASH_FEDACTRL1_EPEN BSP_BIT32(8) + +/* field: EDACEN - Error Detection and Correction Enable */ +#define TMS570_FLASH_FEDACTRL1_EDACEN(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACTRL1_EDACEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACTRL1_EDACEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_FLASH_FEDACTRL2-------------------*/ +/* field: SEC_THRESHOLD - Single Error Correction Threshold */ +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_FCORERRCNT------------------*/ +/* field: FERRCNT - Single Error Correction Count */ +#define TMS570_FLASH_FCORERRCNT_FERRCNT(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FCORERRCNT_FERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FCORERRCNT_FERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_FCORERRADD------------------*/ +/* field: COR_ERR_ADD - Correctable Error Address */ +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte Offset */ +#define TMS570_FLASH_FCORERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FCORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FCORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_FLASH_FCORERRPOS------------------*/ +/* field: BUS2 - Bus 2 Error */ +#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_BIT32(9) + +/* field: TYPE - ErrorType */ +#define TMS570_FLASH_FCORERRPOS_TYPE BSP_BIT32(8) + +/* field: ERR_POS - The bit address of the single bit error */ +#define TMS570_FLASH_FCORERRPOS_ERR_POS(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FCORERRPOS_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FCORERRPOS_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FEDACSTATUS------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_FLASH_FEDACSTATUS_Reserved(val) BSP_FLD32(val,26, 31) +#define TMS570_FLASH_FEDACSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,26, 31) +#define TMS570_FLASH_FEDACSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,26, 31) + +/* field: FSM_DONE - Flash State Machine Done */ +#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_BIT32(24) + +/* field: COMB2_MAL_G - Bus 2 Compare Malfunction Flag. */ +#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_BIT32(19) + +/* field: ECC_B2_MAL_ - Bus 2 ECC Malfunction Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_BIT32(18) + +/* field: B2_UNC_ERR - Bus 2 uncorrectable error */ +#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_BIT32(17) + +/* field: B2_COR_ERR - Bus 2 Correctable Error */ +#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_BIT32(16) + +/* field: D_UNC_ERR - Diagnostic Uncorrectable Error */ +#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_BIT32(12) + +/* field: ADD_TAG_ERR - Address Tag Register Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_BIT32(11) + +/* field: ADD_PAR_ERR - Address Parity Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_BIT32(10) + +/* field: B1_UNC_ERR - Bus 1 Uncorrectable Error Flag */ +#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_BIT32(8) + +/* field: D_CORR_ERR - Diagnostic Correctable Error Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_BIT32(3) + +/* field: ERR_ONE_FLG - Error on One Fail Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_BIT32(2) + +/* field: ERR_ZERO__FLG - Error on Zero Fail Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_BIT32(1) + +/* field: ERR_PRF_FLG - Error Profiling Status Flag */ +#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_BIT32(0) + + +/*------------------TMS570_FLASH_FUNCERRADD------------------*/ +/* field: UNC_ERR_ADD - Un-correctable Error Address */ +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_FUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FEDACSDIS-------------------*/ +/* field: BankID1_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse(val) BSP_FLD32(val,29, 31) +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: SectorID1_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse(val) BSP_FLD32(val,24, 27) +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: BankID1 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID1(val) BSP_FLD32(val,21, 23) +#define TMS570_FLASH_FEDACSDIS_BankID1_GET(reg) BSP_FLD32GET(reg,21, 23) +#define TMS570_FLASH_FEDACSDIS_BankID1_SET(reg,val) BSP_FLD32SET(reg, val,21, 23) + +/* field: SectorID1 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID1(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACSDIS_SectorID1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACSDIS_SectorID1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: BankID0_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse(val) BSP_FLD32(val,13, 15) +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15) +#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15) + +/* field: SectorID0_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: BankID0 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS_BankID0(val) BSP_FLD32(val,5, 7) +#define TMS570_FLASH_FEDACSDIS_BankID0_GET(reg) BSP_FLD32GET(reg,5, 7) +#define TMS570_FLASH_FEDACSDIS_BankID0_SET(reg,val) BSP_FLD32SET(reg, val,5, 7) + +/* field: SectorID0 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS_SectorID0(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACSDIS_SectorID0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACSDIS_SectorID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_FLASH_FPRIMADDTAG------------------*/ +/* field: PRIM_ADD_TAG - Primary Address Tag Register */ +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG(val) BSP_FLD32(val,4, 31) +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + +/* field: 0 - Always 0000 */ +#define TMS570_FLASH_FPRIMADDTAG_0(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FPRIMADDTAG_0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FPRIMADDTAG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_FLASH_FDUPADDTAG------------------*/ +/* field: DUP_ADD_TAG - Primary Address Tag Register */ +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG(val) BSP_FLD32(val,4, 31) +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + + +/*--------------------TMS570_FLASH_FBPROT--------------------*/ +/* field: PROTL1DIS - PROTL1DIS: Level 1 Protection Disabled */ +#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_BIT32(0) + + +/*---------------------TMS570_FLASH_FBSE---------------------*/ +/* field: BSE - Bank Sector Enable */ +#define TMS570_FLASH_FBSE_BSE(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FBSE_BSE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FBSE_BSE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLASH_FBBUSY--------------------*/ +/* field: BUSY - Bank Busy */ +#define TMS570_FLASH_FBBUSY_BUSY(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBBUSY_BUSY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBBUSY_BUSY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_FLASH_FBAC---------------------*/ +/* field: OTPPROTDIS - OTP Sector Protection Disable. */ +#define TMS570_FLASH_FBAC_OTPPROTDIS(val) BSP_FLD32(val,16, 23) +#define TMS570_FLASH_FBAC_OTPPROTDIS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_FLASH_FBAC_OTPPROTDIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: 15_8 - BAGP 0-FFh Bank Active Grace Period. */ +#define TMS570_FLASH_FBAC_15_8(val) BSP_FLD32(val,8, 15) +#define TMS570_FLASH_FBAC_15_8_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_FLASH_FBAC_15_8_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: VREADST - VREAD Setup. */ +#define TMS570_FLASH_FBAC_VREADST(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBAC_VREADST_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBAC_VREADST_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FBFALLBACK------------------*/ +/* field: BANKPWR7 - Bank 7 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR7(val) BSP_FLD32(val,14, 15) +#define TMS570_FLASH_FBFALLBACK_BANKPWR7_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_FLASH_FBFALLBACK_BANKPWR7_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + +/* field: BANKPWR1 - Bank 1 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR1(val) BSP_FLD32(val,2, 3) +#define TMS570_FLASH_FBFALLBACK_BANKPWR1_GET(reg) BSP_FLD32GET(reg,2, 3) +#define TMS570_FLASH_FBFALLBACK_BANKPWR1_SET(reg,val) BSP_FLD32SET(reg, val,2, 3) + +/* field: BANKPWR0 - Bank 0 Fallback Power Mode */ +#define TMS570_FLASH_FBFALLBACK_BANKPWR0(val) BSP_FLD32(val,0, 1) +#define TMS570_FLASH_FBFALLBACK_BANKPWR0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_FLASH_FBFALLBACK_BANKPWR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_FLASH_FBPRDY--------------------*/ +/* field: BANKBUSY - Bank busy bits (one bit for each bank) */ +#define TMS570_FLASH_FBPRDY_BANKBUSY(val) BSP_FLD32(val,16, 23) +#define TMS570_FLASH_FBPRDY_BANKBUSY_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_FLASH_FBPRDY_BANKBUSY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: PUMPRDY - Flash pump ready flag */ +#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_BIT32(15) + +/* field: BANKRDY - Bank ready bits (one bit for each bank) */ +#define TMS570_FLASH_FBPRDY_BANKRDY(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FBPRDY_BANKRDY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FBPRDY_BANKRDY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_FLASH_FPAC1---------------------*/ +/* field: PSLEEP - Pump Sleep. */ +#define TMS570_FLASH_FPAC1_PSLEEP(val) BSP_FLD32(val,16, 26) +#define TMS570_FLASH_FPAC1_PSLEEP_GET(reg) BSP_FLD32GET(reg,16, 26) +#define TMS570_FLASH_FPAC1_PSLEEP_SET(reg,val) BSP_FLD32SET(reg, val,16, 26) + +/* field: PUMPPWR - Flash Charge Pump Fallback Power Mode */ +#define TMS570_FLASH_FPAC1_PUMPPWR BSP_BIT32(0) + + +/*---------------------TMS570_FLASH_FPAC2---------------------*/ +/* field: PAGP - Pump Active Grace Period */ +#define TMS570_FLASH_FPAC2_PAGP(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_FPAC2_PAGP_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_FPAC2_PAGP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_FLASH_FMAC---------------------*/ +/* field: BANK - Bank Enable. */ +#define TMS570_FLASH_FMAC_BANK(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FMAC_BANK_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FMAC_BANK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*--------------------TMS570_FLASH_FMSTAT--------------------*/ +/* field: ILA - Illegal Address */ +#define TMS570_FLASH_FMSTAT_ILA BSP_BIT32(14) + +/* field: PGV - Program Verify */ +#define TMS570_FLASH_FMSTAT_PGV BSP_BIT32(12) + +/* field: EV - Erase Verify */ +#define TMS570_FLASH_FMSTAT_EV BSP_BIT32(10) + +/* field: BUSY - Busy */ +#define TMS570_FLASH_FMSTAT_BUSY BSP_BIT32(8) + +/* field: ERS - Erase Active */ +#define TMS570_FLASH_FMSTAT_ERS BSP_BIT32(7) + +/* field: PGM - Program Active */ +#define TMS570_FLASH_FMSTAT_PGM BSP_BIT32(6) + +/* field: INVDAT - Invalid Data */ +#define TMS570_FLASH_FMSTAT_INVDAT BSP_BIT32(5) + +/* field: CSTAT - Command Status */ +#define TMS570_FLASH_FMSTAT_CSTAT BSP_BIT32(4) + +/* field: VOLTSTAT - Core Voltage Status */ +#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_BIT32(3) + +/* field: ESUSP - Erase Suspended */ +#define TMS570_FLASH_FMSTAT_ESUSP BSP_BIT32(2) + +/* field: PSUSP - Program Suspended */ +#define TMS570_FLASH_FMSTAT_PSUSP BSP_BIT32(1) + +/* field: SLOCK - Sector Lock Status */ +#define TMS570_FLASH_FMSTAT_SLOCK BSP_BIT32(0) + + +/*-------------------TMS570_FLASH_FEMUDMSW-------------------*/ +/* field: EMU_DMSW - EEPROM Emulation Most Significant Data Word */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLASH_FEMUDLSW-------------------*/ +/* field: EMU_DLSW - EEPROM Emulation Least Significant Data Word */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLASH_FEMUECC--------------------*/ +/* field: EMU_ECC - This register can be written by the CPU in any mode. */ +#define TMS570_FLASH_FEMUECC_EMU_ECC(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FEMUECC_EMU_ECC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FEMUECC_EMU_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLASH_FEMUADDR-------------------*/ +/* field: EMU_ADDR - EEPROM Emulation Address */ +#define TMS570_FLASH_FEMUADDR_EMU_ADDR(val) BSP_FLD32(val,3, 21) +#define TMS570_FLASH_FEMUADDR_EMU_ADDR_GET(reg) BSP_FLD32GET(reg,3, 21) +#define TMS570_FLASH_FEMUADDR_EMU_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,3, 21) + + +/*-------------------TMS570_FLASH_FDIAGCTRL-------------------*/ +/* field: DIAG_TRIG - Diagnostic Trigger */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_BIT32(24) + +/* field: DIAG_EN_KEY - Diagnostic Enable Key */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: DIAG_ECC_SEL - Diagnostic SECDED Select */ +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL(val) BSP_FLD32(val,12, 14) +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_GET(reg) BSP_FLD32GET(reg,12, 14) +#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_SET(reg,val) BSP_FLD32SET(reg, val,12, 14) + + +/*-------------------TMS570_FLASH_FRAWDATAH-------------------*/ +/* field: RAW_DATA_ - Uncorrected Raw Data */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLASH_FRAWDATAL-------------------*/ +/* field: RAW_DATA_ - Uncorrected Raw Data. Same as FRAW_DATAH but stores lower 32 bits. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLASH_FRAWECC--------------------*/ +/* field: PIPE_BUF - Error came from pipeline buffer hit */ +#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_BIT32(8) + +/* field: RAW_ECC - Uncorrected Raw ECC */ +#define TMS570_FLASH_FRAWECC_RAW_ECC(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FRAWECC_RAW_ECC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FRAWECC_RAW_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_FLASH_FPAROVR--------------------*/ +/* field: BNK_INV_PAR - Buffer Invert Parity */ +#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_BIT32(16) + +/* field: BUS_PAR_DIS - Disable Bus Parity */ +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS(val) BSP_FLD32(val,12, 15) +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_GET(reg) BSP_FLD32GET(reg,12, 15) +#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15) + +/* field: PAR_OVR_KEY - When this value is 101, the selected ADD_INV_PAR and DAT_INV_PAR fields will become active. */ +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY(val) BSP_FLD32(val,9, 11) +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: ADD_INV_PAR - Address Odd Parity */ +#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_BIT32(8) + +/* field: DAT_INV_PAR - Data Odd Parity */ +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_FLASH_FEDACSDIS2------------------*/ +/* field: BankID3_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse(val) BSP_FLD32(val,29, 31) +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: SectorID3_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled. */ +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse(val) BSP_FLD32(val,24, 27) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: BankID3 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID3(val) BSP_FLD32(val,21, 23) +#define TMS570_FLASH_FEDACSDIS2_BankID3_GET(reg) BSP_FLD32GET(reg,21, 23) +#define TMS570_FLASH_FEDACSDIS2_BankID3_SET(reg,val) BSP_FLD32SET(reg, val,21, 23) + +/* field: SectorID3 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID3(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_FEDACSDIS2_SectorID3_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: BankID2_Inverse - is disabled. The only bank that supports sector disable is bank 7. */ +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse(val) BSP_FLD32(val,13, 15) +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15) +#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15) + +/* field: SectorID2_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse(val) BSP_FLD32(val,8, 11) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: BankID2 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */ +#define TMS570_FLASH_FEDACSDIS2_BankID2(val) BSP_FLD32(val,5, 7) +#define TMS570_FLASH_FEDACSDIS2_BankID2_GET(reg) BSP_FLD32GET(reg,5, 7) +#define TMS570_FLASH_FEDACSDIS2_BankID2_SET(reg,val) BSP_FLD32SET(reg, val,5, 7) + +/* field: SectorID2 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */ +#define TMS570_FLASH_FEDACSDIS2_SectorID2(val) BSP_FLD32(val,0, 3) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_FLASH_FEDACSDIS2_SectorID2_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_FLASH_FSMWRENA-------------------*/ +/* field: WR_ENA - Flash State Machine Write Enable */ +#define TMS570_FLASH_FSMWRENA_WR_ENA(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_FSMWRENA_WR_ENA_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_FSMWRENA_WR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FSMSECTOR-------------------*/ +/* field: SECT_ERASED - Sectors Erased */ +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED(val) BSP_FLD32(val,16, 31) +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + + +/*-----------------TMS570_FLASH_EEPROMCONFIG-----------------*/ +/* field: EWAIT - EEPROM Wait state Counter */ +#define TMS570_FLASH_EEPROMCONFIG_EWAIT(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_EEPROMCONFIG_EWAIT_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_EEPROMCONFIG_EWAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: AUTOSUSP_EN - Auto Suspend Enable */ +#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_BIT32(8) + +/* field: AUTOSTART_GRACE - Auto-suspend Startup Grace Period */ +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_FLASH_EECTRL1--------------------*/ +/* field: EDACMODE - Error Correction Mode. */ +#define TMS570_FLASH_EECTRL1_EDACMODE(val) BSP_FLD32(val,16, 19) +#define TMS570_FLASH_EECTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLASH_EECTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: EE_EOFEN - EEPROM Emulation Event on a correctable One's Fail Enable bit */ +#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_BIT32(10) + +/* field: EE_EZFEN - EEPROM Emulation Event on a correctable Zero's Fail Enable bit */ +#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_BIT32(9) + +/* field: EE_EPEN - EEPROM Emulation Error Profiling Enable. */ +#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_BIT32(8) + + +/*--------------------TMS570_FLASH_EECTRL2--------------------*/ +/* field: EE_SEC_THRESHOLD - EEPROM Emulation Single Error Correction Threshold */ +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_EECORERRCNT------------------*/ +/* field: EE_ERRCNT - Single Error Correction Count */ +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT(val) BSP_FLD32(val,0, 15) +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_FLASH_EECORERRADD------------------*/ +/* field: COR_ERR_ADD - Correctable Error Address */ +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_EECORERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_EECORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_EECORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_FLASH_EECORERRPOS------------------*/ +/* field: TYPE - ErrorType */ +#define TMS570_FLASH_EECORERRPOS_TYPE BSP_BIT32(8) + +/* field: EE_ERR_POS - The bit address of the single bit error */ +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS(val) BSP_FLD32(val,0, 7) +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLASH_EESTATUS-------------------*/ +/* field: EE_D_UNC_ERR - Diagnostic Mode Uncorrectable Error Status Flag */ +#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_BIT32(12) + +/* field: EE_UNC_ERR - EEPROM Emulation Uncorrectable Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_BIT32(8) + +/* field: EE_CMG - EEPROM Emulation Compare Malfunction Good */ +#define TMS570_FLASH_EESTATUS_EE_CMG BSP_BIT32(6) + +/* field: EE_CME - . */ +#define TMS570_FLASH_EESTATUS_EE_CME BSP_BIT32(4) + +/* field: EE_D_COR_ERR - Diagnostic Correctable Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_BIT32(3) + +/* field: EE_ERR_ONE_FLG - Error on One Fail Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_BIT32(2) + +/* field: EE_ERR_ZERO_FLG - Error on Zero Fail Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_BIT32(1) + +/* field: EE_ERR_PRF_FLG - Error Profiling Error Flag */ +#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_BIT32(0) + + +/*------------------TMS570_FLASH_EEUNCERRADD------------------*/ +/* field: UNC_ERR_ADD - Un-correctable Error Address */ +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31) +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31) +#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31) + +/* field: B_OFF - Byte offset */ +#define TMS570_FLASH_EEUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2) +#define TMS570_FLASH_EEUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_FLASH_EEUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_FLASH_FCFGBANK-------------------*/ +/* field: EE_BANK_WIDTH - Bank 7 width (144 bits wide) */ +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH(val) BSP_FLD32(val,20, 31) +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,20, 31) +#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,20, 31) + +/* field: MAIN_BANK_WIDTH - Width of main flash banks (144 bits wide) */ +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH(val) BSP_FLD32(val,4, 15) +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,4, 15) +#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,4, 15) + + + +#endif /* LIBBSP_ARM_TMS570_FLASH */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h new file mode 100644 index 0000000000..e077ab65fd --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h @@ -0,0 +1,618 @@ +/* The header file is generated by make_header.py from FLEX_RAY.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_FLEX_RAY +#define LIBBSP_ARM_TMS570_FLEX_RAY + +#include + +typedef struct{ + uint32_t GSN0; /*Global Static Number 0*/ + uint32_t GSN1; /*Global Static Number 1*/ + uint8_t reserved1 [8]; + uint32_t GCS; /*Global Control Set*/ + uint32_t GCR; /*Global Control Reset*/ + uint32_t TSCB; /*Transfer Status Current Buffer*/ + uint32_t LTBCC; /*Last Transferred Buffer to Communication Controller*/ + uint32_t LTBSM; /*Last Transferred Buffer to System Memory*/ + uint32_t TBA; /*Transfer Base Address*/ + uint32_t NTBA; /*Next Transfer Base Address*/ + uint32_t BAMS; /*Base Address of Mirrored Status*/ + uint32_t SAMP; /*Start Address of Memory Protection*/ + uint32_t EAMP; /*End Address of Memory Protection*/ + uint8_t reserved2 [8]; + uint32_t TSMO1; /*Transfer to System Memory Occurred 1*/ + uint32_t TSMO2; /*Transfer to System Memory Occurred 2*/ + uint32_t TSMO3; /*Transfer to System Memory Occurred 3*/ + uint32_t TSMO4; /*Transfer to System Memory Occurred 4*/ + uint32_t TCCO1; /*Transfer to Communication Controller Occurred 1*/ + uint32_t TCCO2; /*Transfer to Communication Controller Occurred 2*/ + uint32_t TCCO3; /*Transfer to Communication Controller Occurred 3*/ + uint32_t TCCO4; /*Transfer to Communication Controller Occurred 4*/ + uint32_t TOOFF; /*Transfer Occurred Offset*/ + uint8_t reserved3 [12]; + uint32_t PEADR; /*Parity Error Address*/ + uint32_t TEIF; /*Transfer Error Interrupt*/ + uint32_t TEIRES; /*Transfer Error Interrupt Enable Set*/ + uint32_t TEIRER; /*Transfer Error Interrupt Enable Reset*/ + uint32_t TTSMS1; /*Trigger Transfer to System Memory Set 1*/ + uint32_t TTSMR1; /*Trigger Transfer to System Memory Reset 1*/ + uint32_t TTSMS2; /*Trigger Transfer to System Memory Set 2*/ + uint32_t TTSMR2; /*Trigger Transfer to System Memory Reset 2*/ + uint32_t TTSMS3; /*Trigger Transfer to System Memory Set 3*/ + uint32_t TTSMR3; /*Trigger Transfer to System Memory Reset 3*/ + uint32_t TTSMS4; /*Trigger Transfer to System Memory Set 4*/ + uint32_t TTSMR4; /*Trigger Transfer to System Memory Reset 4*/ + uint32_t TTCCS1; /*Trigger Transfer to Communication Controller Set 1*/ + uint32_t TTCCR1; /*Trigger Transfer to Communication Controller Reset 1*/ + uint32_t TTCCS2; /*Trigger Transfer to Communication Controller Set 2*/ + uint32_t TTCCR2; /*Trigger Transfer to Communication Controller Reset 2*/ + uint32_t TTCCS3; /*Trigger Transfer to Communication Controller Set 3*/ + uint32_t TTCCR3; /*Trigger Transfer to Communication Controller Reset 3*/ + uint32_t TTCCS4; /*Trigger Transfer to Communication Controller Set 4*/ + uint32_t TTCCR4; /*Trigger Transfer to Communication Controller Reset 4*/ + uint32_t ETESMS1; /*Enable Transfer on Event to System Memory Set 1*/ + uint32_t ETESMR1; /*Enable Transfer on Event to System Memory Reset 1*/ + uint32_t ETESMS2; /*Enable Transfer on Event to System Memory Set 2*/ + uint32_t ETESMR2; /*Enable Transfer on Event to System Memory Reset 2*/ + uint32_t ETESMS3; /*Enable Transfer on Event to System Memory Set 3*/ + uint32_t ETESMR3; /*Enable Transfer on Event to System Memory Reset 3*/ + uint32_t ETESMS4; /*Enable Transfer on Event to System Memory Set 4*/ + uint32_t ETESMR4; /*Enable Transfer on Event to System Memory Reset 4*/ + uint32_t CESMS1; /*Clear on Event to System Memory Set 1*/ + uint32_t CESMR1; /*Clear on Event to System Memory Reset 1*/ + uint32_t CESMS2; /*Clear on Event to System Memory Set 2*/ + uint32_t CESMR2; /*Clear on Event to System Memory Reset 2*/ + uint32_t CESMS3; /*Clear on Event to System Memory Set 3*/ + uint32_t CESMR3; /*Clear on Event to System Memory Reset 3*/ + uint32_t CESMS4; /*Clear on Event to System Memory Set 4*/ + uint32_t CESMR4; /*Clear on Event to System Memory Reset 4*/ + uint32_t TSMIES1; /*Transfer to System Memory Interrupt Enable Set 1*/ + uint32_t TSMIER1; /*Transfer to System Memory Interrupt Enable Reset 1*/ + uint32_t TSMIES2; /*Transfer to System Memory Interrupt Enable Set 2*/ + uint32_t TSMIER2; /*Transfer to System Memory Interrupt Enable Reset 2*/ + uint32_t TSMIES3; /*Transfer to System Memory Interrupt Enable Set 3*/ + uint32_t TSMIER3; /*Transfer to System Memory Interrupt Enable Reset 3*/ + uint32_t TSMIES4; /*Transfer to System Memory Interrupt Enable Set 4*/ + uint32_t TSMIER4; /*Transfer to System Memory Interrupt Enable Reset 4*/ + uint32_t TCCIES1; /*Transfer to Communication Controller Interrupt Enable Set 1*/ + uint32_t TCCIER1; /*Transfer to Communication Controller Interrupt Enable Reset 1*/ + uint32_t TCCIES2; /*Transfer to Communication Controller Interrupt Enable Set 2*/ + uint32_t TCCIER2; /*Transfer to Communication Controller Interrupt Enable Reset 2*/ + uint32_t TCCIES3; /*Transfer to Communication Controller Interrupt Enable Set 3*/ + uint32_t TCCIER3; /*Transfer to Communication Controller Interrupt Enable Reset 3*/ + uint32_t TCCIES4; /*Transfer to Communication Controller Interrupt Enable Set 4*/ + uint32_t TCCIER4; /*Transfer to Communication Controller Interrupt Enable Reset 4*/ +} tms570_flex_ray_t; + + +/*--------------------TMS570_FLEX_RAY_GSN0--------------------*/ +/* field: Data_A - Data_A(15-0) */ +#define TMS570_FLEX_RAY_GSN0_Data_A(val) BSP_FLD32(val,16, 31) +#define TMS570_FLEX_RAY_GSN0_Data_A_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLEX_RAY_GSN0_Data_A_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: Data_B - (complement of Data_A(15-0)) */ +#define TMS570_FLEX_RAY_GSN0_Data_B(val) BSP_FLD32(val,0, 15) +#define TMS570_FLEX_RAY_GSN0_Data_B_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLEX_RAY_GSN0_Data_B_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLEX_RAY_GSN1--------------------*/ +/* field: Data_C - Data_C(15-0) */ +#define TMS570_FLEX_RAY_GSN1_Data_C(val) BSP_FLD32(val,16, 31) +#define TMS570_FLEX_RAY_GSN1_Data_C_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_FLEX_RAY_GSN1_Data_C_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: Data_D - (complement of Data_C(15-0)) */ +#define TMS570_FLEX_RAY_GSN1_Data_D(val) BSP_FLD32(val,0, 15) +#define TMS570_FLEX_RAY_GSN1_Data_D_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_FLEX_RAY_GSN1_Data_D_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_FLEX_RAY_GCS--------------------*/ +/* field: ENDVBM - Endianness Correction on VBusp Master */ +#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_BIT32(31) + +/* field: ENDVBS - Endianness correction on VBusp Slave */ +#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_BIT32(30) + +/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */ +#define TMS570_FLEX_RAY_GCS_ENDRx(val) BSP_FLD32(val,28, 29) +#define TMS570_FLEX_RAY_GCS_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_FLEX_RAY_GCS_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: ENDHx - Endianness Correction for Header */ +#define TMS570_FLEX_RAY_GCS_ENDHx(val) BSP_FLD32(val,26, 27) +#define TMS570_FLEX_RAY_GCS_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27) +#define TMS570_FLEX_RAY_GCS_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27) + +/* field: ENDPx - Endianness Correction for Payload */ +#define TMS570_FLEX_RAY_GCS_ENDPx(val) BSP_FLD32(val,24, 25) +#define TMS570_FLEX_RAY_GCS_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_FLEX_RAY_GCS_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: PRIO - Transfer Priority */ +#define TMS570_FLEX_RAY_GCS_PRIO BSP_BIT32(21) + +/* field: PEFT - Parity for Test */ +#define TMS570_FLEX_RAY_GCS_PEFT BSP_BIT32(20) + +/* field: PELx - Parity Lock */ +#define TMS570_FLEX_RAY_GCS_PELx(val) BSP_FLD32(val,16, 19) +#define TMS570_FLEX_RAY_GCS_PELx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLEX_RAY_GCS_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: CETESM - Clear ETESM Register */ +#define TMS570_FLEX_RAY_GCS_CETESM BSP_BIT32(14) + +/* field: CTTCC - Clear TTCC Register */ +#define TMS570_FLEX_RAY_GCS_CTTCC BSP_BIT32(13) + +/* field: CTTSM - Clear TTSM Register */ +#define TMS570_FLEX_RAY_GCS_CTTSM BSP_BIT32(12) + +/* field: ETSM - Enable Transfer Status Mirrored */ +#define TMS570_FLEX_RAY_GCS_ETSM BSP_BIT32(8) + +/* field: SILE - Status Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCS_SILE BSP_BIT32(5) + +/* field: EILE - Error Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCS_EILE BSP_BIT32(4) + +/* field: TUH - Transfer Unit Halted */ +#define TMS570_FLEX_RAY_GCS_TUH BSP_BIT32(1) + +/* field: TUE - Transfer Unit Enabled */ +#define TMS570_FLEX_RAY_GCS_TUE BSP_BIT32(0) + + +/*--------------------TMS570_FLEX_RAY_GCR--------------------*/ +/* field: ENDVBM - Endianness Correction on VBusp Master */ +#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_BIT32(31) + +/* field: ENDVBS - Endianness correction on VBusp Slave */ +#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_BIT32(30) + +/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */ +#define TMS570_FLEX_RAY_GCR_ENDRx(val) BSP_FLD32(val,28, 29) +#define TMS570_FLEX_RAY_GCR_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_FLEX_RAY_GCR_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: ENDHx - Endianness Correction for Header */ +#define TMS570_FLEX_RAY_GCR_ENDHx(val) BSP_FLD32(val,26, 27) +#define TMS570_FLEX_RAY_GCR_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27) +#define TMS570_FLEX_RAY_GCR_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27) + +/* field: ENDPx - Endianness Correction for Payload */ +#define TMS570_FLEX_RAY_GCR_ENDPx(val) BSP_FLD32(val,24, 25) +#define TMS570_FLEX_RAY_GCR_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_FLEX_RAY_GCR_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: PRIO - Transfer Priority */ +#define TMS570_FLEX_RAY_GCR_PRIO BSP_BIT32(21) + +/* field: PEFT - Parity for Test */ +#define TMS570_FLEX_RAY_GCR_PEFT BSP_BIT32(20) + +/* field: PELx - Parity Lock */ +#define TMS570_FLEX_RAY_GCR_PELx(val) BSP_FLD32(val,16, 19) +#define TMS570_FLEX_RAY_GCR_PELx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_FLEX_RAY_GCR_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: CETESM - Clear ETESM Register */ +#define TMS570_FLEX_RAY_GCR_CETESM BSP_BIT32(14) + +/* field: CTTCC - Clear TTCC Register */ +#define TMS570_FLEX_RAY_GCR_CTTCC BSP_BIT32(13) + +/* field: CTTSM - Clear TTSM Register */ +#define TMS570_FLEX_RAY_GCR_CTTSM BSP_BIT32(12) + +/* field: ETSM - Enable Transfer Status Mirrored */ +#define TMS570_FLEX_RAY_GCR_ETSM BSP_BIT32(8) + +/* field: SILE - Status Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCR_SILE BSP_BIT32(5) + +/* field: EILE - Error Interrupt Line Enable */ +#define TMS570_FLEX_RAY_GCR_EILE BSP_BIT32(4) + +/* field: TUH - Transfer Unit Halted */ +#define TMS570_FLEX_RAY_GCR_TUH BSP_BIT32(1) + +/* field: TUE - Transfer Unit Enabled */ +#define TMS570_FLEX_RAY_GCR_TUE BSP_BIT32(0) + + +/*--------------------TMS570_FLEX_RAY_TSCB--------------------*/ +/* field: TSMS - Transfer State Machine Status */ +#define TMS570_FLEX_RAY_TSCB_TSMS(val) BSP_FLD32(val,16, 20) +#define TMS570_FLEX_RAY_TSCB_TSMS_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_FLEX_RAY_TSCB_TSMS_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: STUH - Status of Transfer Unit State Machine for Halt Detection */ +#define TMS570_FLEX_RAY_TSCB_STUH BSP_BIT32(12) + +/* field: IDLE - Detects Transfer State Machine State IDLE */ +#define TMS570_FLEX_RAY_TSCB_IDLE BSP_BIT32(8) + +/* field: BN - Buffer Number */ +#define TMS570_FLEX_RAY_TSCB_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_TSCB_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_TSCB_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*-------------------TMS570_FLEX_RAY_LTBCC-------------------*/ +/* field: BN - Buffer number. */ +#define TMS570_FLEX_RAY_LTBCC_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_LTBCC_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_LTBCC_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*-------------------TMS570_FLEX_RAY_LTBSM-------------------*/ +/* field: BN - Buffer number. */ +#define TMS570_FLEX_RAY_LTBSM_BN(val) BSP_FLD32(val,0, 6) +#define TMS570_FLEX_RAY_LTBSM_BN_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_FLEX_RAY_LTBSM_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*--------------------TMS570_FLEX_RAY_TBA--------------------*/ +/* field: TBA - Transfer Base Address. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_NTBA--------------------*/ +/* field: nTBA - nTBA(31-0) */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_BAMS--------------------*/ +/* field: BAMS - Base Address of Mirrored Status32-bit base pointer, 2 LSB are not significant (32-bit */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_SAMP--------------------*/ +/* field: SAMP - Start Address Memory Protection. */ +/* Whole 32 bits */ + +/*--------------------TMS570_FLEX_RAY_EAMP--------------------*/ +/* field: EAMP - End Address Memory Protection. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO1-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO2-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO3-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TSMO4-------------------*/ +/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO1-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO2-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO3-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TCCO4-------------------*/ +/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TOOFF-------------------*/ +/* field: TDIR - Transfer Direction. */ +#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_BIT32(8) + +/* field: OFF - Offset Vector */ +#define TMS570_FLEX_RAY_TOOFF_OFF(val) BSP_FLD32(val,0, 7) +#define TMS570_FLEX_RAY_TOOFF_OFF_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_FLEX_RAY_TOOFF_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-------------------TMS570_FLEX_RAY_PEADR-------------------*/ +/* field: ADR - Address of failing TCR location. */ +#define TMS570_FLEX_RAY_PEADR_ADR(val) BSP_FLD32(val,0, 8) +#define TMS570_FLEX_RAY_PEADR_ADR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_FLEX_RAY_PEADR_ADR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_FLEX_RAY_TEIF--------------------*/ +/* field: MPV - Memory Protection Violation. */ +#define TMS570_FLEX_RAY_TEIF_MPV BSP_BIT32(17) + +/* field: PE - Parity Error. The flag signals a parity error to the host. */ +#define TMS570_FLEX_RAY_TEIF_PE BSP_BIT32(16) + +/* field: RSTAT - Status of VBUS on read transfers. */ +#define TMS570_FLEX_RAY_TEIF_RSTAT(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIF_RSTAT_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIF_RSTAT_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTAT - Status of VBUS on write transfers. */ +#define TMS570_FLEX_RAY_TEIF_WSTAT(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIF_WSTAT_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIF_WSTAT_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNR - Transfer Not Ready. */ +#define TMS570_FLEX_RAY_TEIF_TNR BSP_BIT32(1) + +/* field: FAC - Forbidden Access. */ +#define TMS570_FLEX_RAY_TEIF_FAC BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TEIRES-------------------*/ +/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */ +#define TMS570_FLEX_RAY_TEIRES_RSTATE(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIRES_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIRES_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */ +#define TMS570_FLEX_RAY_TEIRES_WSTATE(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIRES_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIRES_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNRE - Transfer Not Ready Enable. */ +#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_BIT32(1) + +/* field: FACE - Forbidden Access Enable. */ +#define TMS570_FLEX_RAY_TEIRES_FACE BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TEIRER-------------------*/ +/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */ +#define TMS570_FLEX_RAY_TEIRER_RSTATE(val) BSP_FLD32(val,8, 10) +#define TMS570_FLEX_RAY_TEIRER_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_FLEX_RAY_TEIRER_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */ +#define TMS570_FLEX_RAY_TEIRER_WSTATE(val) BSP_FLD32(val,4, 6) +#define TMS570_FLEX_RAY_TEIRER_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6) +#define TMS570_FLEX_RAY_TEIRER_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) + +/* field: TNRE - Transfer Not Ready Enable. */ +#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_BIT32(1) + +/* field: FACE - Forbidden Access Enable. */ +#define TMS570_FLEX_RAY_TEIRER_FACE BSP_BIT32(0) + + +/*-------------------TMS570_FLEX_RAY_TTSMS1-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR1-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS2-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR2-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS3-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR3-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMS4-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTSMR4-------------------*/ +/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS1-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR1-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS2-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR2-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS3-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR3-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCS4-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_TTCCR4-------------------*/ +/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS1------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR1------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS2------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR2------------------*/ +/* field: ETESMS1 - message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS3------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR3------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMS4------------------*/ +/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_ETESMR4------------------*/ +/* field: ETESMS1 - message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS1-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR1-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS2-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR2-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS3-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR3-------------------*/ +/* field: CESMS1 - CESMS1(31-0) */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMS4-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*-------------------TMS570_FLEX_RAY_CESMR4-------------------*/ +/* field: CESMS1 - Clear on Event to System Memory Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES1------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER1------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES2------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER2------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES3------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER3------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIES4------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TSMIER4------------------*/ +/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES1------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER1------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES2------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER2------------------*/ +/* field: TCCIES1 - to message buffers 0 to 31. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES3------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER3------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIES4------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + +/*------------------TMS570_FLEX_RAY_TCCIER4------------------*/ +/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_FLEX_RAY */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h new file mode 100644 index 0000000000..3cb7851754 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h @@ -0,0 +1,324 @@ +/* The header file is generated by make_header.py from GIO.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_GIO +#define LIBBSP_ARM_TMS570_GIO + +#include + +typedef struct{ + uint32_t DIR; /*GIO Data Direction Register*/ + uint32_t DIN; /*GIO Data Input Register*/ + uint32_t DOUT; /*GIO Data Output Register*/ + uint32_t DSET; /*GIO Data Set Register*/ + uint32_t DCLR; /*GIO Data Clear Register*/ + uint32_t PDR; /*GIO Open Drain Register*/ + uint32_t PULDIS; /*GIO Pull Disable Register*/ + uint32_t PSL; /*GIO Pull Select Register*/ +} tms570_gio_port_t; + +typedef struct{ + uint32_t GCR0; /*GIO Global Control Register*/ + uint8_t reserved1 [4]; + uint32_t INTDET; /*GIO Interrupt Detect Register*/ + uint32_t POL; /*GIO Interrupt Polarity Register*/ + uint32_t ENASET; /*GIO Interrupt Enable Set Register*/ + uint32_t ENACLR; /*GIO Interrupt Enable Clear Register*/ + uint32_t LVLSET; /*GIO Interrupt Priority Set Register*/ + uint32_t LVLCLR; /*GIO Interrupt Priority Clear Register*/ + uint32_t FLG; /*GIO Interrupt Flag Register*/ + uint32_t OFF1; /*GIO Offset 1 Register*/ + uint32_t OFF2; /*GIO Offset 2 Register*/ + uint32_t EMU1; /*GIO Emulation 1 Register*/ + uint32_t EMU2; /*GIO Emulation 2 Register*/ + tms570_gio_port_t ports[8]; /*GIO ports*/ +} tms570_gio_t; + + +/*-----------------------TMS570_GIO_DIR-----------------------*/ +/* field: GIODIR - GIO data direction, pins [7:0] */ +#define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_DIN-----------------------*/ +/* field: GIODIN - GIO data input, pins [7:0] */ +#define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DOUT----------------------*/ +/* field: GIODOUT - IO data output, pins[7:0]. */ +#define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DSET----------------------*/ +/* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */ +#define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_DCLR----------------------*/ +/* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */ +#define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_PDR-----------------------*/ +/* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */ +#define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_PULDIS---------------------*/ +/* field: GIOPULDIS - GIO pull disable, pins[7:0]. */ +#define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_PSL-----------------------*/ +/* field: GIOPSL - GIO pull select, pins[7:0] */ +#define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_GCR0----------------------*/ +/* field: RESET - GIO reset. */ +#define TMS570_GIO_GCR0_RESET BSP_BIT32(0) + + +/*---------------------TMS570_GIO_INTDET---------------------*/ +/* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_INTDET_GIOINTDET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOINTDET_2 - Interrupt detection select for pins GIOC[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_INTDET_GIOINTDET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_INTDET_GIOINTDET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOINTDET_1 - Interrupt detection select for pins GIOB[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_INTDET_GIOINTDET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_INTDET_GIOINTDET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOINTDET_0 - Interrupt detection select for pins GIOA[7:0] */ +#define TMS570_GIO_INTDET_GIOINTDET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_INTDET_GIOINTDET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_POL-----------------------*/ +/* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */ +#define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_POL_GIOPOL_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOPOL_2 - Interrupt polarity select for pins GIOC[7:0] */ +#define TMS570_GIO_POL_GIOPOL_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_POL_GIOPOL_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_POL_GIOPOL_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOPOL_1 - Interrupt polarity select for pins GIOB[7:0] */ +#define TMS570_GIO_POL_GIOPOL_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_POL_GIOPOL_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_POL_GIOPOL_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOPOL_0 - Interrupt polarity select for pins GIOA[7:0] */ +#define TMS570_GIO_POL_GIOPOL_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_POL_GIOPOL_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_ENASET---------------------*/ +/* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_ENASET_GIOENASET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOENASET_2 - Interrupt enable for pins GIOC[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_ENASET_GIOENASET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_ENASET_GIOENASET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOENASET_1 - Interrupt enable for pins GIOB[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_ENASET_GIOENASET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_ENASET_GIOENASET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOENASET_0 - Interrupt enable for pins GIOA[7:0] */ +#define TMS570_GIO_ENASET_GIOENASET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_ENASET_GIOENASET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_ENACLR---------------------*/ +/* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_ENACLR_GIOENACLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOENACLR_2 - Interrupt enable for pins GIOC[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_ENACLR_GIOENACLR_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_ENACLR_GIOENACLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOENACLR_1 - Interrupt enable for pins GIOB[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_ENACLR_GIOENACLR_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_ENACLR_GIOENACLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOENACLR_0 - Interrupt enable for pins GIOA[7:0] */ +#define TMS570_GIO_ENACLR_GIOENACLR_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_ENACLR_GIOENACLR_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_LVLSET---------------------*/ +/* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_LVLSET_GIOLVLSET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOLVLSET_2 - GIO high priority interrupt for pins GIOC[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_LVLSET_GIOLVLSET_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_LVLSET_GIOLVLSET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOLVLSET_1 - GIO high priority interrupt for pins GIOB[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_LVLSET_GIOLVLSET_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_LVLSET_GIOLVLSET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOLVLSET_0 - GIO high priority interrupt for pins GIOA[7:0]. */ +#define TMS570_GIO_LVLSET_GIOLVLSET_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_LVLSET_GIOLVLSET_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_GIO_LVLCLR---------------------*/ +/* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOLVLCLR_2 - GIO low priority interrupt for pins GIOC[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOLVLCLR_1 - GIO low priority interrupt for pins GIOB[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOLVLCLR_0 - GIO low priority interrupt for pins GIOA[7:0] */ +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_GIO_FLG-----------------------*/ +/* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31) +#define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_GIO_FLG_GIOFLG_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: GIOFLG_2 - GIO flag for pins GIOC[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_2(val) BSP_FLD32(val,16, 23) +#define TMS570_GIO_FLG_GIOFLG_2_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_GIO_FLG_GIOFLG_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: GIOFLG_1 - GIO flag for pins GIOB[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_1(val) BSP_FLD32(val,8, 15) +#define TMS570_GIO_FLG_GIOFLG_1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_GIO_FLG_GIOFLG_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: GIOFLG_0 - GIO flag for pins GIOA[7:0]. */ +#define TMS570_GIO_FLG_GIOFLG_0(val) BSP_FLD32(val,0, 7) +#define TMS570_GIO_FLG_GIOFLG_0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_GIO_OFF1----------------------*/ +/* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */ +#define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_OFF2----------------------*/ +/* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_EMU1----------------------*/ +/* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */ +#define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_EMU2----------------------*/ +/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_GIO_ports----------------------*/ +/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */ +#define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5) +#define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_GIO_ports_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + + +#endif /* LIBBSP_ARM_TMS570_GIO */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h new file mode 100644 index 0000000000..3df27be461 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h @@ -0,0 +1,333 @@ +/* The header file is generated by make_header.py from HTU.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_HTU +#define LIBBSP_ARM_TMS570_HTU + +#include + +typedef struct{ + uint32_t GC; /*Global Control Register*/ + uint32_t CPENA; /*Control Packet Enable Register*/ + uint32_t BUSY0; /*Control Packet Busy Register 0*/ + uint32_t BUSY1; /*Control Packet Busy Register 1*/ + uint32_t BUSY2; /*Control Packet Busy Register 2*/ + uint32_t BUSY3; /*Control Packet Busy Register 3*/ + uint32_t ACPE; /*Active Control Packet and Error Register*/ + uint8_t reserved1 [4]; + uint32_t RLBECTRL; /*Request Lost and Bus Error Control Register*/ + uint32_t BFINTS; /*Buffer Full Interrupt Enable Set Register*/ + uint32_t BFINTC; /*Buffer Full Interrupt Enable Clear Register*/ + uint8_t reserved2 [8]; + uint32_t INTOFF0; /*Interrupt Offset Register 0*/ + uint32_t INTOFF1; /*Interrupt Offset Register 1*/ + uint32_t BIM; /*Buffer Initialization Mode Register*/ + uint32_t RLOSTFL; /*Request Lost Flag Register*/ + uint32_t BFINTFL; /*Buffer Full Interrupt Flag Register*/ + uint32_t BERINTFL; /*BER Interrupt Flag Register*/ + uint32_t MP1S; /*Memory Protection 1 Start Address Register*/ + uint32_t MP1E; /*Memory Protection 1 End Address Register*/ + uint32_t DCTRL; /*Debug Control Register*/ + uint32_t WPR; /*Watch Point Register*/ + uint32_t WMR; /*Watch Mask Register*/ + uint32_t ID; /*Module Identification Register*/ + uint32_t PCR; /*Parity Control Register*/ + uint32_t PAR; /*Parity Address Register*/ + uint8_t reserved3 [4]; + uint32_t MPCS; /*Memory Protection Control and Status Register*/ + uint32_t MP0S; /*Memory Protection 0 Start Address Register*/ + uint32_t MP0E; /*Memory Protection 0 End Address Register*/ +} tms570_htu_t; + + +/*-----------------------TMS570_HTU_GC-----------------------*/ +/* field: VBUSHOLD - Hold the VBUS bus */ +#define TMS570_HTU_GC_VBUSHOLD BSP_BIT32(24) + +/* field: HTUEN - Transfer Unit Enable Bit */ +#define TMS570_HTU_GC_HTUEN BSP_BIT32(16) + +/* field: DEBM - Debug Mode */ +#define TMS570_HTU_GC_DEBM BSP_BIT32(8) + +/* field: HTURES - HTU Software Reset Request */ +#define TMS570_HTU_GC_HTURES BSP_BIT32(0) + + +/*----------------------TMS570_HTU_CPENA----------------------*/ +/* field: CPENA - CP Enable Bits */ +#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_HTU_BUSY0----------------------*/ +/* field: BUSY0A - Busy Flag for CP A of DCP 0 */ +#define TMS570_HTU_BUSY0_BUSY0A BSP_BIT32(24) + +/* field: BUSY0B - Busy Flag for CP B of DCP 0 */ +#define TMS570_HTU_BUSY0_BUSY0B BSP_BIT32(16) + +/* field: BUSY1A - Busy Flag for CP A of DCP 1 */ +#define TMS570_HTU_BUSY0_BUSY1A BSP_BIT32(8) + +/* field: BUSY1B - Busy Flag for CP B of DCP 1 */ +#define TMS570_HTU_BUSY0_BUSY1B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY1----------------------*/ +/* field: BUSY2A - Busy Flag for CP A of DCP 2 */ +#define TMS570_HTU_BUSY1_BUSY2A BSP_BIT32(24) + +/* field: BUSY2B - Busy Flag for CP B of DCP 2 */ +#define TMS570_HTU_BUSY1_BUSY2B BSP_BIT32(16) + +/* field: BUSY3A - Busy Flag for CP A of DCP 3 */ +#define TMS570_HTU_BUSY1_BUSY3A BSP_BIT32(8) + +/* field: BUSY3B - Busy Flag for CP B of DCP 3 */ +#define TMS570_HTU_BUSY1_BUSY3B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY2----------------------*/ +/* field: BUSY4A - Busy Flag for CP A of DCP 4 */ +#define TMS570_HTU_BUSY2_BUSY4A BSP_BIT32(24) + +/* field: BUSY4B - Busy Flag for CP B of DCP 4 */ +#define TMS570_HTU_BUSY2_BUSY4B BSP_BIT32(16) + +/* field: BUSY5A - Busy Flag for CP A of DCP 5 */ +#define TMS570_HTU_BUSY2_BUSY5A BSP_BIT32(8) + +/* field: BUSY5B - Busy Flag for CP B of DCP 5 */ +#define TMS570_HTU_BUSY2_BUSY5B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_BUSY3----------------------*/ +/* field: BUSY6A - Busy Flag for CP A of DCP 6 */ +#define TMS570_HTU_BUSY3_BUSY6A BSP_BIT32(24) + +/* field: BUSY6B - Busy Flag for CP B of DCP 6 */ +#define TMS570_HTU_BUSY3_BUSY6B BSP_BIT32(16) + +/* field: BUSY7A - Busy Flag for CP A of DCP 7 */ +#define TMS570_HTU_BUSY3_BUSY7A BSP_BIT32(8) + +/* field: BUSY7B - Busy Flag for CP B of DCP 7 */ +#define TMS570_HTU_BUSY3_BUSY7B BSP_BIT32(0) + + +/*----------------------TMS570_HTU_ACPE----------------------*/ +/* field: ERRF - Error Flag */ +#define TMS570_HTU_ACPE_ERRF BSP_BIT32(31) + + +/*--------------------TMS570_HTU_RLBECTRL--------------------*/ +/* field: BERINTENA - Bus Error Interrupt Enable Bit */ +#define TMS570_HTU_RLBECTRL_BERINTENA BSP_BIT32(16) + +/* field: CORL - Continue On Request Lost Error */ +#define TMS570_HTU_RLBECTRL_CORL BSP_BIT32(8) + +/* field: RLINTENA - Request Lost Interrupt Enable Bit */ +#define TMS570_HTU_RLBECTRL_RLINTENA BSP_BIT32(0) + + +/*---------------------TMS570_HTU_BFINTS---------------------*/ +/* field: BFINTENA - Bus Full Interrupt Enable Bits. */ +#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_BFINTC---------------------*/ +/* field: BFINTDIS - */ +#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_INTOFF0---------------------*/ +/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */ +#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10) +#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CPOFF0 - CP Offset. */ +#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4) +#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*---------------------TMS570_HTU_INTOFF1---------------------*/ +/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */ +#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10) +#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CPOFF1 - CP Offset. */ +#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4) +#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*-----------------------TMS570_HTU_BIM-----------------------*/ +/* field: BIM - Buffer Initialization Mode */ +#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7) +#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_HTU_RLOSTFL---------------------*/ +/* field: CPRLFL - CP Request Lost Flags */ +#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_HTU_BFINTFL---------------------*/ +/* field: BFINTFL - Buffer Full Interrupt Flags */ +#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_HTU_BERINTFL--------------------*/ +/* field: BERINTFL - Bus Error Interrupt Flags */ +#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15) +#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_HTU_MP1S----------------------*/ +/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_MP1E----------------------*/ +/* field: ENDADDRESS1 - The end address defines at which address the region ends. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_DCTRL----------------------*/ +/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */ +#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27) +#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: HTUDBGS - HTU Debug Status. */ +#define TMS570_HTU_DCTRL_HTUDBGS BSP_BIT32(16) + +/* field: DBREN - Debug Request Enable */ +#define TMS570_HTU_DCTRL_DBREN BSP_BIT32(0) + + +/*-----------------------TMS570_HTU_WPR-----------------------*/ +/* field: WP - Watch Point Register */ +/* Whole 32 bits */ + +/*-----------------------TMS570_HTU_WMR-----------------------*/ +/* field: WM - Watch Mask Register */ +/* Whole 32 bits */ + +/*-----------------------TMS570_HTU_ID-----------------------*/ +/* field: CLASS - Module Class */ +#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23) +#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TYPE - Subtype within a Class */ +#define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15) +#define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: REV - Module Revision Number */ +#define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7) +#define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_HTU_PCR-----------------------*/ +/* field: COPE - Continue on Parity Error */ +#define TMS570_HTU_PCR_COPE BSP_BIT32(16) + +/* field: TEST - Test. */ +#define TMS570_HTU_PCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Enable/Disable Parity Checking. */ +#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_HTU_PAR-----------------------*/ +/* field: PEFT - Parity Error Fault Flag. */ +#define TMS570_HTU_PAR_PEFT BSP_BIT32(16) + +/* field: PAOFF - PAOFF */ +#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8) +#define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_HTU_MPCS----------------------*/ +/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */ +#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27) +#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: MPEFT1 - MPEFT1 */ +#define TMS570_HTU_MPCS_MPEFT1 BSP_BIT32(17) + +/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */ +#define TMS570_HTU_MPCS_MPEFT0 BSP_BIT32(16) + +/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */ +#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11) +#define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + + +/*----------------------TMS570_HTU_MP0S----------------------*/ +/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */ +/* Whole 32 bits */ + +/*----------------------TMS570_HTU_MP0E----------------------*/ +/* field: ENDADDRESS0 - The end address defines at which address the region ends. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_HTU */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h new file mode 100644 index 0000000000..63ed3f8d95 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h @@ -0,0 +1,363 @@ +/* The header file is generated by make_header.py from I2C.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_I2C +#define LIBBSP_ARM_TMS570_I2C + +#include + +typedef struct{ + uint32_t OAR; /*I2C Own Address Manager*/ + uint32_t IMR; /*I2C Interupt Mask Register*/ + uint32_t STR; /*I2C Status Register*/ + uint32_t CKL; /*I2C Clock Divider Low Register*/ + uint32_t CKH; /*I2C Clock Control High Register*/ + uint32_t CNT; /*I2C Data Count Register*/ + uint32_t DRR; /*I2C Data Receive Register*/ + uint32_t SAR; /*I2C Slave Address Register*/ + uint32_t DXR; /*I2C Data Transmit Register*/ + uint32_t MDR; /*I2C Mode Register*/ + uint32_t IVR; /*I2C Interrupt Vector Register*/ + uint32_t EMDR; /*I2C Extended Mode Register*/ + uint32_t PSC; /*I2C Prescale Register*/ + uint32_t PID11; /*I2C Peripheral ID Register 1*/ + uint32_t PID12; /*I2C Peripheral ID Register 2*/ + uint32_t DMACR; /*I2C DMA Control Register*/ + uint8_t reserved1 [8]; + uint32_t PFNC; /*I2C Pin Function Register*/ + uint32_t DIR; /*I2C Pin Direction Register*/ + uint32_t DIN; /*I2C Data Input Register*/ + uint32_t DOUT; /*I2C Data Output Register*/ + uint32_t SET; /*I2C Data Set Register*/ + uint32_t CLR; /*I2C Data Clear Register*/ + uint32_t PDR; /*I2C Pin Open Drain Register*/ + uint32_t PDIS; /*I2C Pull Disable Register*/ + uint32_t PSEL; /*I2C Pull Select Register*/ + uint32_t pSRS; /*I2C Pins Slew Rate Select Register*/ +} tms570_i2c_t; + + +/*-----------------------TMS570_I2C_OAR-----------------------*/ +/* field: OA - Own address */ +#define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9) +#define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------------TMS570_I2C_IMR-----------------------*/ +/* field: AASEN - Address As Slave Interrupt Enable */ +#define TMS570_I2C_IMR_AASEN BSP_BIT32(6) + +/* field: SCDEN - Stop Condition Interrupt Enable */ +#define TMS570_I2C_IMR_SCDEN BSP_BIT32(5) + +/* field: TXRDYEN - Transmit Data Ready Interrupt Enable */ +#define TMS570_I2C_IMR_TXRDYEN BSP_BIT32(4) + +/* field: RXRDYEN - Receive Data Ready Interrupt Enable */ +#define TMS570_I2C_IMR_RXRDYEN BSP_BIT32(3) + +/* field: ARDYEN - Register Access Ready Interrupt Enable */ +#define TMS570_I2C_IMR_ARDYEN BSP_BIT32(2) + +/* field: NACKEN - No Acknowledgement Interrupt Enable */ +#define TMS570_I2C_IMR_NACKEN BSP_BIT32(1) + +/* field: ALEN - Arbitration Lost Interrupt Enable */ +#define TMS570_I2C_IMR_ALEN BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_STR-----------------------*/ +/* field: SDIR - Slave direction */ +#define TMS570_I2C_STR_SDIR BSP_BIT32(14) + +/* field: NACKSNT - No acknowledge sent */ +#define TMS570_I2C_STR_NACKSNT BSP_BIT32(13) + +/* field: BB - Bus busy */ +#define TMS570_I2C_STR_BB BSP_BIT32(12) + +/* field: RSFULL - Receiver shift full */ +#define TMS570_I2C_STR_RSFULL BSP_BIT32(11) + +/* field: XSMT - XSMT */ +#define TMS570_I2C_STR_XSMT BSP_BIT32(10) + +/* field: AAS - Address as slave */ +#define TMS570_I2C_STR_AAS BSP_BIT32(9) + +/* field: AD0 - Address zero status */ +#define TMS570_I2C_STR_AD0 BSP_BIT32(8) + +/* field: SCD - SCD */ +#define TMS570_I2C_STR_SCD BSP_BIT32(5) + +/* field: TXRDY - Transmit data ready interrupt flag */ +#define TMS570_I2C_STR_TXRDY BSP_BIT32(4) + +/* field: RXRDY - Receive data ready interrupt flag */ +#define TMS570_I2C_STR_RXRDY BSP_BIT32(3) + +/* field: ARDY - Register access ready interrupt flag */ +#define TMS570_I2C_STR_ARDY BSP_BIT32(2) + +/* field: NACK - No acknowledgement interrupt */ +#define TMS570_I2C_STR_NACK BSP_BIT32(1) + +/* field: AL - Arbitration lost interrupt flag */ +#define TMS570_I2C_STR_AL BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_CKL-----------------------*/ +/* field: CLKL - Low time clock division factor */ +#define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_CKH-----------------------*/ +/* field: CLKH - High time clock division factor */ +#define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_CNT-----------------------*/ +/* field: CNT - Data counter */ +#define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15) +#define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_I2C_DRR-----------------------*/ +/* field: DATARX - Receive data */ +#define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_I2C_SAR-----------------------*/ +/* field: SA - 7- or 10-bit programmable slave address */ +#define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9) +#define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-----------------------TMS570_I2C_DXR-----------------------*/ +/* field: DATATX - Transmit data */ +#define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_I2C_MDR-----------------------*/ +/* field: NACKMOD - No-acknowledge (NACK) mode */ +#define TMS570_I2C_MDR_NACKMOD BSP_BIT32(15) + +/* field: FREE - Free running bit */ +#define TMS570_I2C_MDR_FREE BSP_BIT32(14) + +/* field: STT - Start condition */ +#define TMS570_I2C_MDR_STT BSP_BIT32(13) + +/* field: STP - Stop condition */ +#define TMS570_I2C_MDR_STP BSP_BIT32(11) + +/* field: MST - Master/slave mode bit */ +#define TMS570_I2C_MDR_MST BSP_BIT32(10) + +/* field: TRX - Transmit/receive bit */ +#define TMS570_I2C_MDR_TRX BSP_BIT32(9) + +/* field: XA - Expand address enable bit */ +#define TMS570_I2C_MDR_XA BSP_BIT32(8) + +/* field: RM - RM */ +#define TMS570_I2C_MDR_RM BSP_BIT32(7) + +/* field: DLB - Digital loop back enable bit */ +#define TMS570_I2C_MDR_DLB BSP_BIT32(6) + +/* field: nIRS - I2C reset enable bit */ +#define TMS570_I2C_MDR_nIRS BSP_BIT32(5) + +/* field: STB - Start byte mode enable bit (Master mode only) */ +#define TMS570_I2C_MDR_STB BSP_BIT32(4) + +/* field: FDF - Free data format enable bit */ +#define TMS570_I2C_MDR_FDF BSP_BIT32(3) + +/* field: BC - Bit count */ +#define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2) +#define TMS570_I2C_MDR_BC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_I2C_IVR-----------------------*/ +/* field: TESTMD - Reserved for internal testing. */ +#define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11) +#define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_I2C_IVR_TESTMD_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: INTCODE - Interrupt Code Bits */ +#define TMS570_I2C_IVR_INTCODE(val) BSP_FLD32(val,0, 2) +#define TMS570_I2C_IVR_INTCODE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*----------------------TMS570_I2C_EMDR----------------------*/ +/* field: IGNACK - Ignore NACK mode */ +#define TMS570_I2C_EMDR_IGNACK BSP_BIT32(1) + +/* field: BCM - Backwards compatibility mode */ +#define TMS570_I2C_EMDR_BCM BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_PSC-----------------------*/ +/* field: PSC - Prescale */ +#define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_PID11----------------------*/ +/* field: CLASS - Peripheral class */ +#define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15) +#define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_I2C_PID11_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: REVISION - Revision level of the I2C */ +#define TMS570_I2C_PID11_REVISION(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PID11_REVISION_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_PID12----------------------*/ +/* field: TYPE - Peripheral type */ +#define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7) +#define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_I2C_DMACR----------------------*/ +/* field: TXDMAEN - Transmitter DMA enable */ +#define TMS570_I2C_DMACR_TXDMAEN BSP_BIT32(1) + +/* field: RXDMAEN - Receive DMA enable */ +#define TMS570_I2C_DMACR_RXDMAEN BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PFNC----------------------*/ +/* field: PINFUNC - SDA and SCL Pin Function */ +#define TMS570_I2C_PFNC_PINFUNC BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_DIR-----------------------*/ +/* field: SDADIR - SDA direction */ +#define TMS570_I2C_DIR_SDADIR BSP_BIT32(1) + +/* field: SCLDIR - SCL direction */ +#define TMS570_I2C_DIR_SCLDIR BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_DIN-----------------------*/ +/* field: SDAIN - Serial data in */ +#define TMS570_I2C_DIN_SDAIN BSP_BIT32(1) + +/* field: SCLIN - Serial clock data in */ +#define TMS570_I2C_DIN_SCLIN BSP_BIT32(0) + + +/*----------------------TMS570_I2C_DOUT----------------------*/ +/* field: SDAOUT - SDA Data Output */ +#define TMS570_I2C_DOUT_SDAOUT BSP_BIT32(1) + +/* field: SCLOUT - SCL Data Output */ +#define TMS570_I2C_DOUT_SCLOUT BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_SET-----------------------*/ +/* field: SDASET - Serial Data Set */ +#define TMS570_I2C_SET_SDASET BSP_BIT32(1) + +/* field: SCLSET - Serial Clock Set */ +#define TMS570_I2C_SET_SCLSET BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_CLR-----------------------*/ +/* field: SDACLR - Serial Data Clear */ +#define TMS570_I2C_CLR_SDACLR BSP_BIT32(1) + +/* field: SCLCLR - Serial Clock Clear */ +#define TMS570_I2C_CLR_SCLCLR BSP_BIT32(0) + + +/*-----------------------TMS570_I2C_PDR-----------------------*/ +/* field: SDAPDR - SDA pin open drain enable */ +#define TMS570_I2C_PDR_SDAPDR BSP_BIT32(1) + +/* field: SCLPDR - SCL pin open drain enable */ +#define TMS570_I2C_PDR_SCLPDR BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PDIS----------------------*/ +/* field: SDAPDIS - SDA pull disable */ +#define TMS570_I2C_PDIS_SDAPDIS BSP_BIT32(1) + +/* field: SCLPDIS - SCL pull disable */ +#define TMS570_I2C_PDIS_SCLPDIS BSP_BIT32(0) + + +/*----------------------TMS570_I2C_PSEL----------------------*/ +/* field: SDAPSEL - SDA pull select */ +#define TMS570_I2C_PSEL_SDAPSEL BSP_BIT32(1) + +/* field: SCLPSEL - SCL pull select */ +#define TMS570_I2C_PSEL_SCLPSEL BSP_BIT32(0) + + +/*----------------------TMS570_I2C_pSRS----------------------*/ +/* field: SDASRS - SDA Slew Rate select */ +#define TMS570_I2C_pSRS_SDASRS BSP_BIT32(1) + +/* field: SCLSRS - SCL Slew Rate select */ +#define TMS570_I2C_pSRS_SCLSRS BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_I2C */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h new file mode 100644 index 0000000000..f6197e811c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h @@ -0,0 +1,235 @@ +/* The header file is generated by make_header.py from IOMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_IOMM +#define LIBBSP_ARM_TMS570_IOMM + +#include + +typedef struct{ + uint32_t PINMMR0; /*Pin Multiplexing Control Register 0*/ + uint32_t PINMMR1; /*Pin Multiplexing Control Register 1*/ + uint32_t PINMMR2; /*Pin Multiplexing Control Register 2*/ + uint32_t PINMMR3; /*Pin Multiplexing Control Register 3*/ + uint32_t PINMMR4; /*Pin Multiplexing Control Register 4*/ + uint32_t PINMMR5; /*Pin Multiplexing Control Register 5*/ + uint32_t PINMMR6; /*Pin Multiplexing Control Register 6*/ + uint32_t PINMMR7; /*Pin Multiplexing Control Register 7*/ + uint32_t PINMMR8; /*Pin Multiplexing Control Register 8*/ + uint32_t PINMMR9; /*Pin Multiplexing Control Register 9*/ + uint32_t PINMMR10; /*Pin Multiplexing Control Register 10*/ + uint32_t PINMMR11; /*Pin Multiplexing Control Register 11*/ + uint32_t PINMMR12; /*Pin Multiplexing Control Register 12*/ + uint32_t PINMMR13; /*Pin Multiplexing Control Register 13*/ + uint32_t PINMMR14; /*Pin Multiplexing Control Register 14*/ + uint32_t PINMMR15; /*Pin Multiplexing Control Register 15*/ + uint32_t PINMMR16; /*Pin Multiplexing Control Register 16*/ + uint32_t PINMMR17; /*Pin Multiplexing Control Register 17*/ + uint32_t PINMMR18; /*Pin Multiplexing Control Register 18*/ + uint32_t PINMMR19; /*Pin Multiplexing Control Register 19*/ + uint32_t PINMMR20; /*Pin Multiplexing Control Register 20*/ + uint32_t PINMMR21; /*Pin Multiplexing Control Register 21*/ + uint32_t PINMMR22; /*Pin Multiplexing Control Register 22*/ + uint32_t PINMMR23; /*Pin Multiplexing Control Register 23*/ + uint32_t PINMMR24; /*Pin Multiplexing Control Register 24*/ + uint32_t PINMMR25; /*Pin Multiplexing Control Register 25*/ + uint32_t PINMMR26; /*Pin Multiplexing Control Register 26*/ + uint32_t PINMMR27; /*Pin Multiplexing Control Register 27*/ + uint32_t PINMMR28; /*Pin Multiplexing Control Register 28*/ + uint32_t PINMMR29; /*Pin Multiplexing Control Register 29*/ + uint32_t PINMMR30; /*Pin Multiplexing Control Register 30*/ +} tms570_pinmux_t; + +typedef struct{ + uint32_t REVISION_REG; /*Revision Register*/ + uint8_t reserved1 [28]; + uint32_t ENDIAN_REG; /*Device Endianness Register*/ + uint8_t reserved2 [20]; + uint32_t KICK_REG0; /*Kicker Register 0*/ + uint32_t KICK_REG1; /*Kicker Register 1*/ + uint8_t reserved3 [160]; + uint32_t ERR_RAW_STATUS_REG;/*Error Raw Status / Set Register*/ + uint32_t ERR_ENABLED_STATUS_REG;/*Error Enabled Status / Clear Register*/ + uint32_t ERR_ENABLE_REG; /*Error Signaling Enable Register*/ + uint32_t ERR_ENABLE_CLR_REG;/*Error Signaling Enable Clear Register*/ + uint8_t reserved4 [4]; + uint32_t FAULT_ADDRESS_REG; /*Fault Address Register*/ + uint32_t FAULT_STATUS_REG; /*Fault Status Register*/ + uint32_t FAULT_CLEAR_REG; /*Fault Clear Register*/ + uint8_t reserved5 [16]; + tms570_pinmux_t PINMUX; /*Pin Multiplexing Control Registers*/ +} tms570_iomm_t; + + +/*--------------------TMS570_IOMM_PINMMRx--------------------*/ +/* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx24To31(val) BSP_FLD32(val,24, 31) +#define TMS570_IOMM_PINMMRx_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_IOMM_PINMMRx_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx16To23(val) BSP_FLD32(val,16, 23) +#define TMS570_IOMM_PINMMRx_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_IOMM_PINMMRx_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx8To16(val) BSP_FLD32(val,8, 15) +#define TMS570_IOMM_PINMMRx_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_IOMM_PINMMRx_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */ +#define TMS570_IOMM_PINMMRx_PINMMRx0To7(val) BSP_FLD32(val,0, 7) +#define TMS570_IOMM_PINMMRx_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_IOMM_PINMMRx_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_IOMM_REVISION_REG------------------*/ +/* field: REV_SCHEME - Revision Scheme */ +#define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_IOMM_REVISION_REG_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: REV_MODULE - Module Id */ +#define TMS570_IOMM_REVISION_REG_REV_MODULE(val) BSP_FLD32(val,16, 27) +#define TMS570_IOMM_REVISION_REG_REV_MODULE_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_IOMM_REVISION_REG_REV_MODULE_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: REV_RTL - RTL Revision */ +#define TMS570_IOMM_REVISION_REG_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_IOMM_REVISION_REG_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_IOMM_REVISION_REG_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: REV_MAJOR - Major Revision */ +#define TMS570_IOMM_REVISION_REG_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_IOMM_REVISION_REG_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_IOMM_REVISION_REG_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: REV_CUSTOM - REV CUSTOM 0 Custom Revision */ +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: REV_MINOR - Minor Revision */ +#define TMS570_IOMM_REVISION_REG_REV_MINOR(val) BSP_FLD32(val,0, 5) +#define TMS570_IOMM_REVISION_REG_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_IOMM_ENDIAN_REG-------------------*/ +/* field: ENDIAN - Device endianness */ +#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_BIT32(0) + + +/*-------------------TMS570_IOMM_KICK_REG0-------------------*/ +/* field: KICK0 - Kicker 0 Register. */ +/* Whole 32 bits */ + +/*-------------------TMS570_IOMM_KICK_REG1-------------------*/ +/* field: KICK1 - Kicker 1 Register. */ +/* Whole 32 bits */ + +/*---------------TMS570_IOMM_ERR_RAW_STATUS_REG---------------*/ +/* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */ +#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_BIT32(1) + +/* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */ +#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_BIT32(0) + + +/*-------------TMS570_IOMM_ERR_ENABLED_STATUS_REG-------------*/ +/* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */ +#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_BIT32(1) + +/* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */ +#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_BIT32(0) + + +/*-----------------TMS570_IOMM_ERR_ENABLE_REG-----------------*/ +/* field: ADDR_ERR_EN - Addressing Error Signaling Enable */ +#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_BIT32(1) + +/* field: PROT_ERR_EN - Protection ErrorSignaling Enable */ +#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_BIT32(0) + + +/*---------------TMS570_IOMM_ERR_ENABLE_CLR_REG---------------*/ +/* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */ +#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_BIT32(1) + +/* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */ +#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_BIT32(0) + + +/*---------------TMS570_IOMM_FAULT_ADDRESS_REG---------------*/ +/* field: FAULT_ADDR - Fault Address. */ +/* Whole 32 bits */ + +/*----------------TMS570_IOMM_FAULT_STATUS_REG----------------*/ +/* field: FAULT_ID - Faulting Transaction ID */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: FAULT_MSTID - ID of Master that initiated the faulting transaction */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID(val) BSP_FLD32(val,16, 23) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: FAULT_PRIVID - Faulting Privilege ID */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID(val) BSP_FLD32(val,9, 12) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_GET(reg) BSP_FLD32GET(reg,9, 12) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_SET(reg,val) BSP_FLD32SET(reg, val,9, 12) + +/* field: FAULT_TYPE - Type of fault detected */ +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE(val) BSP_FLD32(val,0, 5) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------TMS570_IOMM_FAULT_CLEAR_REG----------------*/ +/* field: FAULT_CLEAR - Fault Clear */ +#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_BIT32(0) + + +/*---------------------TMS570_IOMM_PINMUX---------------------*/ +/* field: FAULT_CLEAR - Fault Clear */ +#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_IOMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h new file mode 100644 index 0000000000..d2c3a3bfe8 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h @@ -0,0 +1,594 @@ +/* The header file is generated by make_header.py from LIN.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_LIN +#define LIBBSP_ARM_TMS570_LIN + +#include + +typedef struct{ + uint32_t GCR0; /*SCI Global Control Register 0*/ + uint32_t GCR1; /*SCI Global Control Register 1*/ + uint32_t GCR2; /*SCI Global Control Register 2*/ + uint32_t SETINT; /*SCI Set Interrupt Register*/ + uint32_t CLEARINT; /*SCI Clear Interrupt Register*/ + uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/ + uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/ + uint32_t FLR; /*SCI Flags Register*/ + uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/ + uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/ + uint32_t FORMAT; /*SCI Format Control Register*/ + uint32_t BRS; /*Baud Rate Selection Register*/ + uint32_t ED; /*Receiver Emulation Data Buffer*/ + uint32_t RD; /*Receiver Data Buffer*/ + uint32_t TD; /*Transmit Data Buffer*/ + uint32_t PIO0; /*SCI Pin I/O Control Register 0*/ + uint32_t PIO1; /*SCI Pin I/O Control Register 1*/ + uint32_t PIO2; /*SCI Pin I/O Control Register 2*/ + uint32_t PIO3; /*SCI Pin I/O Control Register 3*/ + uint32_t PIO4; /*SCI Pin I/O Control Register 4*/ + uint32_t PIO5; /*SCI Pin I/O Control Register 5*/ + uint32_t PIO6; /*SCI Pin I/O Control Register 6*/ + uint32_t PIO7; /*SCI Pin I/O Control Register 7*/ + uint32_t PIO8; /*SCI Pin I/O Control Register 8*/ + uint32_t COMP; /*LIN Compare Register*/ + uint32_t RD0; /*LIN Receive Buffer 0 Register*/ + uint32_t RD1; /*LIN Receive Buffer 1 Register*/ + uint32_t MASK; /*LIN Mask Register*/ + uint32_t ID; /*LIN Identification Register*/ + uint32_t TD0; /*LIN Transmit Buffer 0*/ + uint32_t TD1; /*LIN Transmit Buffer 1*/ + uint32_t MBRSR; /*Maximum Baud Rate Selection Register*/ + uint8_t reserved1 [16]; + uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/ +} tms570_lin_t; + + +/*----------------------TMS570_LIN_GCR0----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_LIN_GCR0_Reserved(val) BSP_FLD32(val,1, 31) +#define TMS570_LIN_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) +#define TMS570_LIN_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31) + +/* field: RESET - This bit resets the SCI module. */ +#define TMS570_LIN_GCR0_RESET BSP_BIT32(0) + + +/*----------------------TMS570_LIN_GCR1----------------------*/ +/* field: TXENA - Transmit enable. */ +#define TMS570_LIN_GCR1_TXENA BSP_BIT32(25) + +/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */ +#define TMS570_LIN_GCR1_RXENA BSP_BIT32(24) + +/* field: CONT - Continue on suspend. */ +#define TMS570_LIN_GCR1_CONT BSP_BIT32(17) + +/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */ +#define TMS570_LIN_GCR1_LOOP_BACK BSP_BIT32(16) + +/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */ +#define TMS570_LIN_GCR1_POWERDOWN BSP_BIT32(9) + +/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */ +#define TMS570_LIN_GCR1_SLEEP BSP_BIT32(8) + +/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */ +#define TMS570_LIN_GCR1_SWnRST BSP_BIT32(7) + +/* field: CLOCK - CLOCK */ +#define TMS570_LIN_GCR1_CLOCK BSP_BIT32(5) + +/* field: STOP - SCI number of stop bits per frame. */ +#define TMS570_LIN_GCR1_STOP BSP_BIT32(4) + +/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */ +#define TMS570_LIN_GCR1_PARITY BSP_BIT32(3) + +/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */ +#define TMS570_LIN_GCR1_PARITY_ENA BSP_BIT32(2) + +/* field: TIMING_MODE - SCI timing mode bit. */ +#define TMS570_LIN_GCR1_TIMING_MODE BSP_BIT32(1) + +/* field: COMM_MODE - SCI communication mode bit. */ +#define TMS570_LIN_GCR1_COMM_MODE BSP_BIT32(0) + + +/*----------------------TMS570_LIN_GCR2----------------------*/ +/* field: CC - Compare checksum. LIN mode only. */ +#define TMS570_LIN_GCR2_CC BSP_BIT32(17) + +/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */ +#define TMS570_LIN_GCR2_SC BSP_BIT32(16) + +/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */ +#define TMS570_LIN_GCR2_GEN_WU BSP_BIT32(8) + +/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */ +#define TMS570_LIN_GCR2_POWERDOWN BSP_BIT32(0) + + +/*---------------------TMS570_LIN_SETINT---------------------*/ +/* field: SET_FE_INT - */ +#define TMS570_LIN_SETINT_SET_FE_INT BSP_BIT32(26) + +/* field: SET_OE_INT - SET OE INT */ +#define TMS570_LIN_SETINT_SET_OE_INT BSP_BIT32(25) + +/* field: SET_PE_INT - Set parity interrupt. */ +#define TMS570_LIN_SETINT_SET_PE_INT BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL - SET RX DMA ALL */ +#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) + +/* field: SET_RX_DMA - SET RX DMA */ +#define TMS570_LIN_SETINT_SET_RX_DMA BSP_BIT32(17) + +/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */ +#define TMS570_LIN_SETINT_SET_TX_DMA BSP_BIT32(16) + +/* field: SET_RX_INT - SET RX INT */ +#define TMS570_LIN_SETINT_SET_RX_INT BSP_BIT32(9) + +/* field: SET_TX_INT - Set transmitter interrupt. */ +#define TMS570_LIN_SETINT_SET_TX_INT BSP_BIT32(8) + +/* field: SET_WAKEUP_INT - Set wakeup interrupt. */ +#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_BIT32(1) + +/* field: SET_BRKDT_INT - Set breakdetect interrupt. */ +#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_CLEARINT--------------------*/ +/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_BIT32(26) + +/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_BIT32(25) + +/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) + +/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_BIT32(17) + +/* field: CLR_TX_DMA - CLR TX DMA */ +#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_BIT32(16) + +/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_BIT32(9) + +/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) + +/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */ +#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_SETINTLVL--------------------*/ +/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) + +/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) + +/* field: SET_PE_INT_LVL - Set parity error interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */ +#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: SET_RX_INT_LVL - Set receiver interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) + +/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) + +/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */ +#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */ +#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-------------------TMS570_LIN_CLEARINTLVL-------------------*/ +/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_PE_INT_LVL - */ +#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */ +#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) + +/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */ +#define TMS570_LIN_CLEARINTLVL_8 BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */ +#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-----------------------TMS570_LIN_FLR-----------------------*/ +/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */ +#define TMS570_LIN_FLR_FE BSP_BIT32(26) + +/* field: OE - Overrun error flag. */ +#define TMS570_LIN_FLR_OE BSP_BIT32(25) + +/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */ +#define TMS570_LIN_FLR_PE BSP_BIT32(24) + +/* field: RXWAKE - Receiver wakeup detect flag. */ +#define TMS570_LIN_FLR_RXWAKE BSP_BIT32(12) + +/* field: TX_EMPTY - Transmitter empty flag. */ +#define TMS570_LIN_FLR_TX_EMPTY BSP_BIT32(11) + +/* field: TXWAKE - Transmitter wakeup method select. */ +#define TMS570_LIN_FLR_TXWAKE BSP_BIT32(10) + +/* field: RXRDY - Receiver ready flag. */ +#define TMS570_LIN_FLR_RXRDY BSP_BIT32(9) + +/* field: TXRDY - Transmitter buffer register ready flag. */ +#define TMS570_LIN_FLR_TXRDY BSP_BIT32(8) + +/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */ +#define TMS570_LIN_FLR_BUSY BSP_BIT32(3) + +/* field: IDLE - SCI receiver in idle state. */ +#define TMS570_LIN_FLR_IDLE BSP_BIT32(2) + +/* field: WAKEUP - Wakeup flag. */ +#define TMS570_LIN_FLR_WAKEUP BSP_BIT32(1) + +/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */ +#define TMS570_LIN_FLR_BRKDT BSP_BIT32(0) + + +/*--------------------TMS570_LIN_INTVECT0--------------------*/ +/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */ +#define TMS570_LIN_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) +#define TMS570_LIN_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_LIN_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_LIN_INTVECT1--------------------*/ +/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */ +#define TMS570_LIN_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) +#define TMS570_LIN_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_LIN_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_LIN_FORMAT---------------------*/ +/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */ +#define TMS570_LIN_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) +#define TMS570_LIN_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_LIN_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_LIN_BRS-----------------------*/ +/* field: BAUD - SCI 24-bit baud selection. */ +#define TMS570_LIN_BRS_BAUD(val) BSP_FLD32(val,0, 23) +#define TMS570_LIN_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_LIN_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*-----------------------TMS570_LIN_ED-----------------------*/ +/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */ +#define TMS570_LIN_ED_ED(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_RD-----------------------*/ +/* field: RD - Receiver data. */ +#define TMS570_LIN_RD_RD(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD-----------------------*/ +/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */ +#define TMS570_LIN_TD_TD(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_PIO0----------------------*/ +/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */ +#define TMS570_LIN_PIO0_TX_FUNC BSP_BIT32(2) + +/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */ +#define TMS570_LIN_PIO0_RX_FUNC BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO1----------------------*/ +/* field: TX_DIR - Transmit pin direction. */ +#define TMS570_LIN_PIO1_TX_DIR BSP_BIT32(2) + +/* field: RX_DIR - Receive pin direction. */ +#define TMS570_LIN_PIO1_RX_DIR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO2----------------------*/ +/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */ +#define TMS570_LIN_PIO2_TX_IN BSP_BIT32(2) + +/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */ +#define TMS570_LIN_PIO2_RX_IN BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO3----------------------*/ +/* field: TX_OUT - Transmit pin out. */ +#define TMS570_LIN_PIO3_TX_OUT BSP_BIT32(2) + +/* field: RX_OUT - Receive pin out. */ +#define TMS570_LIN_PIO3_RX_OUT BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO4----------------------*/ +/* field: TX_SET - Transmit pin set. */ +#define TMS570_LIN_PIO4_TX_SET BSP_BIT32(2) + +/* field: RX_SET - Receive pin set. */ +#define TMS570_LIN_PIO4_RX_SET BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO5----------------------*/ +/* field: TX_CLR - Transmit pin clear. */ +#define TMS570_LIN_PIO5_TX_CLR BSP_BIT32(2) + +/* field: RX_CLR - Receive pin clear. */ +#define TMS570_LIN_PIO5_RX_CLR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO6----------------------*/ +/* field: TX_PDR - Transmit pin open drain enable. */ +#define TMS570_LIN_PIO6_TX_PDR BSP_BIT32(2) + +/* field: RX_PDR - Receive pin open drain enable. */ +#define TMS570_LIN_PIO6_RX_PDR BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO7----------------------*/ +/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */ +#define TMS570_LIN_PIO7_TX_PD BSP_BIT32(2) + +/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */ +#define TMS570_LIN_PIO7_RX_PD BSP_BIT32(1) + + +/*----------------------TMS570_LIN_PIO8----------------------*/ +/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */ +#define TMS570_LIN_PIO8_TX_PSL BSP_BIT32(2) + +/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */ +#define TMS570_LIN_PIO8_RX_PSL BSP_BIT32(1) + + +/*----------------------TMS570_LIN_COMP----------------------*/ +/* field: SDEL - 2-bit synch delimiter compare. These bits are effective in LIN mode only. */ +#define TMS570_LIN_COMP_SDEL(val) BSP_FLD32(val,8, 9) +#define TMS570_LIN_COMP_SDEL_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_LIN_COMP_SDEL_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: SBREAK - Synch break extend. These bits are effective in LIN mode only. */ +#define TMS570_LIN_COMP_SBREAK(val) BSP_FLD32(val,0, 2) +#define TMS570_LIN_COMP_SBREAK_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_LIN_COMP_SBREAK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_LIN_RD0-----------------------*/ +/* field: RD0 - Receive buffer 0. Byte 0 of the response data byte. */ +#define TMS570_LIN_RD0_RD0(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_RD0_RD0_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_RD0_RD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RD1 - Receive buffer 1. Byte 1 of the response data byte. */ +#define TMS570_LIN_RD0_RD1(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_RD0_RD1_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_RD0_RD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RD2 - Receive buffer 2. Byte 2 of the response data byte. */ +#define TMS570_LIN_RD0_RD2(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_RD0_RD2_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_RD0_RD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RD3 - Receive buffer 3. Byte 3 of the response data byte. */ +#define TMS570_LIN_RD0_RD3(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD0_RD3_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD0_RD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_RD1-----------------------*/ +/* field: RD4 - Receive buffer 4. Byte 4 of the response data byte. */ +#define TMS570_LIN_RD1_RD4(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_RD1_RD4_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_RD1_RD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RD5 - Receive buffer 5. Byte 5 of the response data byte. */ +#define TMS570_LIN_RD1_RD5(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_RD1_RD5_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_RD1_RD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RD6 - Receive buffer 6. Byte 6 of the response data byte. */ +#define TMS570_LIN_RD1_RD6(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_RD1_RD6_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_RD1_RD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: RD7 - Receive buffer 7. Byte 7 of the response data byte. */ +#define TMS570_LIN_RD1_RD7(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_RD1_RD7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_RD1_RD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_MASK----------------------*/ +/* field: RX_ID_MASK - Receive ID mask. These bits are effective in LIN mode only. */ +#define TMS570_LIN_MASK_RX_ID_MASK(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_MASK_RX_ID_MASK_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_MASK_RX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TX_ID_MASK - Transmit ID mask. These bits are effective in LIN mode only. */ +#define TMS570_LIN_MASK_TX_ID_MASK(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_MASK_TX_ID_MASK_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_MASK_TX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_ID-----------------------*/ +/* field: RECEIVED_ID - Received identification. These bits are effective in LIN mode only. */ +#define TMS570_LIN_ID_RECEIVED_ID(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_ID_RECEIVED_ID_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_ID_RECEIVED_ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: ID_SLAVETASK_BYTE - ID-SlaveTask Byte. These bits are effective in LIN mode only. */ +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: ID_BYTE - ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. */ +#define TMS570_LIN_ID_ID_BYTE(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_ID_ID_BYTE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_ID_ID_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD0-----------------------*/ +/* field: TD0 - 8-Bit transmit buffer 0. */ +#define TMS570_LIN_TD0_TD0(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_TD0_TD0_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_TD0_TD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: TD1 - 8-Bit transmit buffer 1. */ +#define TMS570_LIN_TD0_TD1(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_TD0_TD1_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_TD0_TD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TD2 - 8-Bit transmit buffer 2. */ +#define TMS570_LIN_TD0_TD2(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_TD0_TD2_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_TD0_TD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: TD3 - 8-Bit transmit buffer 3. */ +#define TMS570_LIN_TD0_TD3(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD0_TD3_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD0_TD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_LIN_TD1-----------------------*/ +/* field: TD4 - 8-Bit transmit buffer 4. */ +#define TMS570_LIN_TD1_TD4(val) BSP_FLD32(val,24, 31) +#define TMS570_LIN_TD1_TD4_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_LIN_TD1_TD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: TD5 - 8-Bit transmit buffer 5. */ +#define TMS570_LIN_TD1_TD5(val) BSP_FLD32(val,16, 23) +#define TMS570_LIN_TD1_TD5_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_LIN_TD1_TD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TD6 - 8-Bit transmit buffer 6. */ +#define TMS570_LIN_TD1_TD6(val) BSP_FLD32(val,8, 15) +#define TMS570_LIN_TD1_TD6_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_LIN_TD1_TD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: TD7 - 8-Bit transmit buffer 7. */ +#define TMS570_LIN_TD1_TD7(val) BSP_FLD32(val,0, 7) +#define TMS570_LIN_TD1_TD7_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_LIN_TD1_TD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_LIN_MBRSR----------------------*/ +/* field: MBR - Maximum baud rate prescaler. This bit is effective in LIN mode only. */ +#define TMS570_LIN_MBRSR_MBR(val) BSP_FLD32(val,0, 12) +#define TMS570_LIN_MBRSR_MBR_GET(reg) BSP_FLD32GET(reg,0, 12) +#define TMS570_LIN_MBRSR_MBR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) + + +/*--------------------TMS570_LIN_IODFTCTRL--------------------*/ +/* field: FEN - Frame error enable. This bit is used to create a frame error. */ +#define TMS570_LIN_IODFTCTRL_FEN BSP_BIT32(26) + +/* field: PEN - Parity error enable. This bit is used to create a parity error. */ +#define TMS570_LIN_IODFTCTRL_PEN BSP_BIT32(25) + +/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */ +#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_BIT32(24) + +/* field: PIN_SAMPLE_MASK - Pin sample mask. */ +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) +#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20) + +/* field: TX_SHIFT - Transmit shift. */ +#define TMS570_LIN_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) +#define TMS570_LIN_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_LIN_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */ +#define TMS570_LIN_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_LIN_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_LIN_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */ +#define TMS570_LIN_IODFTCTRL_LPBENA BSP_BIT32(1) + +/* field: RXPENA - Module analog loopback through receive pin enable. */ +#define TMS570_LIN_IODFTCTRL_RXPENA BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_LIN */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h new file mode 100644 index 0000000000..704a0bc8a4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h @@ -0,0 +1,230 @@ +/* The header file is generated by make_header.py from MDIO.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_MDIO +#define LIBBSP_ARM_TMS570_MDIO + +#include + +typedef struct{ + uint32_t REVID; /*MDIO Revision ID Register*/ + uint32_t CONTROL; /*MDIO Control Register*/ + uint32_t ALIVE; /*PHY Alive Status register*/ + uint32_t LINK; /*PHY Link Status Register*/ + uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/ + uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/ + uint8_t reserved1 [8]; + uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/ + uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/ + uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/ + uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/ + uint8_t reserved2 [80]; + uint32_t USERACCESS0; /*MDIO User Access Register 0*/ + uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/ + uint32_t USERACCESS1; /*MDIO User Access Register 1*/ + uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/ +} tms570_mdio_t; + + +/*---------------------TMS570_MDIO_REVID---------------------*/ +/* field: REV - Identifies the MDIO Module revision. */ +/* Whole 32 bits */ + +/*--------------------TMS570_MDIO_CONTROL--------------------*/ +/* field: IDLE - State machine IDLE status bit. */ +#define TMS570_MDIO_CONTROL_IDLE BSP_BIT32(31) + +/* field: ENABLE - State machine enable control bit. */ +#define TMS570_MDIO_CONTROL_ENABLE BSP_BIT32(30) + +/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */ +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28) +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: PREAMBLE - Preamble disable */ +#define TMS570_MDIO_CONTROL_PREAMBLE BSP_BIT32(20) + +/* field: FAULT - Fault indicator. */ +#define TMS570_MDIO_CONTROL_FAULT BSP_BIT32(19) + +/* field: FAULTENB - Fault detect enable. */ +#define TMS570_MDIO_CONTROL_FAULTENB BSP_BIT32(18) + +/* field: CLKDIV - Clock Divider bits. */ +#define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_MDIO_ALIVE---------------------*/ +/* field: ALIVE - MDIO Alive bits. */ +/* Whole 32 bits */ + +/*----------------------TMS570_MDIO_LINK----------------------*/ +/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */ +/* Whole 32 bits */ + +/*-------------------TMS570_MDIO_LINKINTRAW-------------------*/ +/* field: USERPHY1 - MDIO Link change event, raw value. */ +#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_BIT32(1) + +/* field: USERPHY0 - MDIO Link change event, raw value. */ +#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_LINKINTMASKED-----------------*/ +/* field: USERPHY1 - MDIO Link change interrupt, masked value. */ +#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_BIT32(1) + +/* field: USERPHY0 - MDIO Link change interrupt, masked value. */ +#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_BIT32(0) + + +/*-------------------TMS570_MDIO_USERINTRAW-------------------*/ +/* field: USERACCESS1 - MDIO User command complete event bit. */ +#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO User command complete event bit. */ +#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_USERINTMASKED-----------------*/ +/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */ +#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */ +#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_BIT32(0) + + +/*-----------------TMS570_MDIO_USERINTMASKSET-----------------*/ +/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */ +#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */ +#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_BIT32(0) + + +/*----------------TMS570_MDIO_USERINTMASKCLEAR----------------*/ +/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */ +#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1) + +/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */ +#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0) + + +/*------------------TMS570_MDIO_USERACCESS0------------------*/ +/* field: GO - Go bit. */ +#define TMS570_MDIO_USERACCESS0_GO BSP_BIT32(31) + +/* field: WRITE - Write enable bit. */ +#define TMS570_MDIO_USERACCESS0_WRITE BSP_BIT32(30) + +/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ +#define TMS570_MDIO_USERACCESS0_ACK BSP_BIT32(29) + +/* field: REGADR - Register address bits. */ +#define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25) +#define TMS570_MDIO_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) +#define TMS570_MDIO_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) + +/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ +#define TMS570_MDIO_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20) +#define TMS570_MDIO_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_MDIO_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: DATA - User data bits. */ +#define TMS570_MDIO_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_MDIO_USERPHYSEL0------------------*/ +/* field: LINKSEL - Link status determination select bit. */ +#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_BIT32(7) + +/* field: LINKINTENB - Link change interrupt enable. */ +#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_BIT32(6) + +/* field: PHYADRMON - PHY address whose link status is to be monitored. */ +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4) +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*------------------TMS570_MDIO_USERACCESS1------------------*/ +/* field: GO - Go bit. */ +#define TMS570_MDIO_USERACCESS1_GO BSP_BIT32(31) + +/* field: WRITE - Write enable bit. */ +#define TMS570_MDIO_USERACCESS1_WRITE BSP_BIT32(30) + +/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ +#define TMS570_MDIO_USERACCESS1_ACK BSP_BIT32(29) + +/* field: REGADR - Register address bits. */ +#define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25) +#define TMS570_MDIO_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) +#define TMS570_MDIO_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) + +/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ +#define TMS570_MDIO_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20) +#define TMS570_MDIO_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) +#define TMS570_MDIO_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) + +/* field: DATA - User data bits. */ +#define TMS570_MDIO_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15) +#define TMS570_MDIO_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_MDIO_USERPHYSEL1------------------*/ +/* field: LINKSEL - Link status determination select bit. */ +#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_BIT32(7) + +/* field: LINKINTENB - Link change interrupt enable. */ +#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_BIT32(6) + +/* field: PHYADRMON - PHY address whose link status is to be monitored. */ +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4) +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + + +#endif /* LIBBSP_ARM_TMS570_MDIO */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h new file mode 100644 index 0000000000..06b8bbeb0a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h @@ -0,0 +1,332 @@ +/* The header file is generated by make_header.py from N2HET.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_NHET +#define LIBBSP_ARM_TMS570_NHET + +#include + +typedef struct{ + uint32_t GCR; /*Global Configuration Register*/ + uint32_t PFR; /*Prescale Factor Register*/ + uint32_t ADDR; /*NHET Current Address Register*/ + uint32_t OFF1; /*Offset Index Priority Level 1 Register*/ + uint32_t OFF2; /*Offset Index Priority Level 2 Register*/ + uint32_t INTENAS; /*Interrupt Enable Set Register*/ + uint32_t INTENAC; /*Interrupt Enable Clear Register*/ + uint32_t EXC1; /*Exception Control Register 1*/ + uint32_t EXC2; /*Exception Control Register 2*/ + uint32_t PRY; /*Interrupt Priority Register*/ + uint32_t FLG; /*Interrupt Flag Register*/ + uint32_t AND; /*AND Share Control Register*/ + uint8_t reserved1 [4]; + uint32_t HRSH; /*HR Share Control Register*/ + uint32_t XOR; /*HR XOR-Share Control Register*/ + uint32_t REQENS; /*Request Enable Set Register*/ + uint32_t REQENC; /*Request Enable Clear Register*/ + uint32_t REQDS; /*Request Destination Select Register*/ + uint8_t reserved2 [4]; + uint32_t DIR; /*NHET Direction Register*/ + uint32_t DIN; /*NHET Data Input Register*/ + uint32_t DOUT; /*NHET Data Output Register*/ + uint32_t DSET; /*NHET Data Set Register*/ + uint32_t DCLR; /*NHET Data Clear Register*/ + uint32_t PDR; /*NHET Open Drain Register*/ + uint32_t PULDIS; /*NHET Pull Disable Register*/ + uint32_t PSL; /*NHET Pull Select Register*/ + uint8_t reserved3 [8]; + uint32_t PCR; /*Parity Control Register*/ + uint32_t PAR; /*Parity Address Register*/ + uint32_t PPR; /*Parity Pin Register*/ + uint32_t SFPRLD; /*Suppression Filter Preload Register*/ + uint32_t SFENA; /*Suppression Filter Enable Register*/ + uint8_t reserved4 [4]; + uint32_t LBPSEL; /*Loop Back Pair Select Register*/ + uint32_t LBPDIR; /*Loop Back Pair Direction Register*/ + uint32_t PINDIS; /*NHET Pin Disable Register*/ +} tms570_nhet_t; + + +/*----------------------TMS570_NHET_GCR----------------------*/ +/* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */ +#define TMS570_NHET_GCR_HET_PIN_ENA BSP_BIT32(24) + +/* field: MP - Master Priority */ +#define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22) +#define TMS570_NHET_GCR_MP_GET(reg) BSP_FLD32GET(reg,21, 22) +#define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22) + +/* field: PPF - Protect Program Fields */ +#define TMS570_NHET_GCR_PPF BSP_BIT32(18) + +/* field: IS - Ignore Suspend */ +#define TMS570_NHET_GCR_IS BSP_BIT32(17) + +/* field: CMS - Clk_master/slave */ +#define TMS570_NHET_GCR_CMS BSP_BIT32(16) + + +/*----------------------TMS570_NHET_PFR----------------------*/ +/* field: LRPFC - oop Resolution Pre-scale Factor Code */ +#define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10) +#define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_NHET_PFR_LRPFC_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: HRPFC - High Resolution Pre-scale Factor Code */ +#define TMS570_NHET_PFR_HRPFC(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_PFR_HRPFC_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_NHET_ADDR----------------------*/ +/* field: HETADDR - N2HET Current Address */ +#define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8) +#define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*----------------------TMS570_NHET_OFF1----------------------*/ +/* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */ +#define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*----------------------TMS570_NHET_OFF2----------------------*/ +/* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */ +#define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5) +#define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_NHET_INTENAS--------------------*/ +/* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */ +/* Whole 32 bits */ + +/*--------------------TMS570_NHET_INTENAC--------------------*/ +/* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_EXC1----------------------*/ +/* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */ +#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_BIT32(24) + +/* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */ +#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_BIT32(16) + +/* field: PRGM_OVRFL_ENA - Program Overflow Enable */ +#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_BIT32(8) + +/* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_BIT32(2) + +/* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_BIT32(1) + +/* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */ +#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_BIT32(0) + + +/*----------------------TMS570_NHET_EXC2----------------------*/ +/* field: DEBUG_STATUS_FLAG - Debug Status Flag. */ +#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_BIT32(8) + +/* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */ +#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_BIT32(2) + +/* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */ +#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_BIT32(1) + +/* field: PRGM_OVERFL_FLAG - Program Overflow Flag */ +#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_BIT32(0) + + +/*----------------------TMS570_NHET_PRY----------------------*/ +/* field: HETPRY - HET Interrupt Priority Level bits */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_FLG----------------------*/ +/* field: HETFLAG - Interrupt Flag Register Bits */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_AND----------------------*/ +/* field: AND_SHARE - AND Share Enable */ +#define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_NHET_HRSH----------------------*/ +/* field: HR_SHARE - HR Share Bits */ +#define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_NHET_XOR----------------------*/ +/* field: XOR_SHARE - XOR Share Enable */ +#define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_REQENS---------------------*/ +/* field: REQ_ENA_n - Request Enable Bits */ +#define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_NHET_REQENC---------------------*/ +/* field: REQ_DIS_n - Request Disable Bits */ +#define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_NHET_REQDS---------------------*/ +/* field: TDBS_n - HTU, DMA or Both Select Bits */ +#define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23) +#define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_NHET_REQDS_TDBS_n_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TDS_n - HTU or DMA Select Bits */ +#define TMS570_NHET_REQDS_TDS_n(val) BSP_FLD32(val,0, 7) +#define TMS570_NHET_REQDS_TDS_n_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_NHET_DIR----------------------*/ +/* field: HETDIR_n - Data direction of NHET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DIN----------------------*/ +/* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DOUT----------------------*/ +/* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DSET----------------------*/ +/* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_DCLR----------------------*/ +/* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PDR----------------------*/ +/* field: HETPDR_n - Open drain control for HET[n] pins */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_PULDIS---------------------*/ +/* field: HETPULDIS_n - Pull disable for N2HET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PSL----------------------*/ +/* field: HETPSL_n - Pull select for NHET pins */ +/* Whole 32 bits */ + +/*----------------------TMS570_NHET_PCR----------------------*/ +/* field: TEST - Test Bit. */ +#define TMS570_NHET_PCR_TEST BSP_BIT32(8) + +/* field: PARITY_ENA - Enable/disable parity checking. */ +#define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_NHET_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_NHET_PAR----------------------*/ +/* field: PAOFF - Parity Error Address Offset. */ +#define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12) +#define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12) +#define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12) + + +/*----------------------TMS570_NHET_PPR----------------------*/ +/* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_SFPRLD---------------------*/ +/* field: CCDIV - Counter Clock Divider */ +#define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17) +#define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_NHET_SFPRLD_CCDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: CPRLD - Counter Preload Value */ +#define TMS570_NHET_SFPRLD_CPRLD(val) BSP_FLD32(val,0, 9) +#define TMS570_NHET_SFPRLD_CPRLD_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*---------------------TMS570_NHET_SFENA---------------------*/ +/* field: HETSFENA_n - Suppression Filter Enable Bits */ +/* Whole 32 bits */ + +/*---------------------TMS570_NHET_LBPSEL---------------------*/ +/* field: LBPTYPE - Loop Back Pair Type Select Bits */ +#define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31) +#define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_NHET_LBPSEL_LBPTYPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: LBPSEL - Loop Back Pair Select Bits */ +#define TMS570_NHET_LBPSEL_LBPSEL(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_LBPSEL_LBPSEL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_LBPDIR---------------------*/ +/* field: LBPTSTENA - Loopback Test Enable Key */ +#define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19) +#define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_NHET_LBPDIR_LBPTSTENA_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LBPDIR - Loop Back Pair Direction Bits */ +#define TMS570_NHET_LBPDIR_LBPDIR(val) BSP_FLD32(val,0, 15) +#define TMS570_NHET_LBPDIR_LBPDIR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_NHET_PINDIS---------------------*/ +/* field: HETPINDIS_n - N2HET Pin Disable Bits */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_NHET */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h new file mode 100644 index 0000000000..2c5ed29760 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h @@ -0,0 +1,195 @@ +/* The header file is generated by make_header.py from PBIST.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PBIST +#define LIBBSP_ARM_TMS570_PBIST + +#include + +typedef struct{ + uint32_t DNW[88]; /*Reserved DO NOT WRITE*/ + uint32_t RAMT; /*RAM Configuration Register*/ + uint32_t DLR; /*Datalogger Register*/ + uint8_t reserved1 [24]; + uint32_t PACT; /*PBIST Activate/ROM Clock Enable Register*/ + uint32_t PBISTID; /*PBIST ID Register*/ + uint32_t OVER; /*Override Register*/ + uint8_t reserved2 [4]; + uint32_t FSRF0; /*Fail Status Fail Register 0*/ + uint8_t reserved3 [4]; + uint32_t FSRC0; /*Fail Status Count Register 0*/ + uint32_t FSRC1; /*Fail Status Count Register 1*/ + uint32_t FSRA0; /*Fail Status Address 0 Register*/ + uint32_t FSRA1; /*Fail Status Address 1 Register*/ + uint32_t FSRDL0; /*Fail Status Data Register 0*/ + uint8_t reserved4 [4]; + uint32_t FSRDL1; /*Fail Status Data Register 1*/ + uint8_t reserved5 [12]; + uint32_t ROM; /*ROM Mask Register*/ + uint32_t ALGO; /*ROM Algorithm Mask Register*/ + uint32_t RINFOL; /*RAM Info Mask Lower Register*/ + uint32_t RINFOUL; /*RAM Info Mask Lower Register*/ +} tms570_pbist_t; + + +/*----------------------TMS570_PBIST_DNW----------------------*/ +/* field: Reserved - Do not write */ +/* Whole 32 bits */ + +/*---------------------TMS570_PBIST_RAMT---------------------*/ +/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */ +#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31) +#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */ +#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23) +#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: DWR - Data Width Register */ +#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15) +#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SMS - Sense Margin Select Register */ +#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7) +#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: PLS - Pipeline Latency Select */ +#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5) +#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5) +#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5) + +/* field: RLS - RAM Latency Select */ +#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1) +#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*----------------------TMS570_PBIST_DLR----------------------*/ +/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */ +#define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4) + +/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */ +#define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2) + + +/*---------------------TMS570_PBIST_PACT---------------------*/ +/* field: PACT1 - PBIST Activate */ +#define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1) + +/* field: PACT0 - ROM Clock Enable Register */ +#define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0) + + +/*--------------------TMS570_PBIST_PBISTID--------------------*/ +/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */ +#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_OVER---------------------*/ +/* field: OVER0 - RINFO Override Bit */ +#define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0) + + +/*---------------------TMS570_PBIST_FSRF0---------------------*/ +/* field: FSRF0 - Fail Status 0. */ +#define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0) + + +/*---------------------TMS570_PBIST_FSRC0---------------------*/ +/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */ +#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_FSRC1---------------------*/ +/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */ +#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7) +#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_PBIST_FSRA0---------------------*/ +/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */ +#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15) +#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PBIST_FSRA1---------------------*/ +/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */ +#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15) +#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_PBIST_FSRDL0--------------------*/ +/* field: FSRDL1 - Failure data on port 1 */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_FSRDL1--------------------*/ +/* field: FSRDL1 - Failure data on port 1 */ +/* Whole 32 bits */ + +/*----------------------TMS570_PBIST_ROM----------------------*/ +/* field: ROM - ROM Mask */ +#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1) +#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PBIST_ALGO---------------------*/ +/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_RINFOL--------------------*/ +/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + +/*--------------------TMS570_PBIST_RINFOUL--------------------*/ +/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_PBIST */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h new file mode 100644 index 0000000000..4d5613aa9f --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h @@ -0,0 +1,120 @@ +/* The header file is generated by make_header.py from PCR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PCR +#define LIBBSP_ARM_TMS570_PCR + +#include + +typedef struct{ + uint32_t PMPROTSET0; /*Peripheral Memory Protection Set Register 0*/ + uint32_t PMPROTSET1; /*Peripheral Memory Protection Set Register 1*/ + uint8_t reserved1 [8]; + uint32_t PMPROTCLR0; /*Peripheral Memory Protection Clear Register 0*/ + uint32_t PMPROTCLR1; /*Peripheral Memory Protection Clear Register 1*/ + uint8_t reserved2 [8]; + uint32_t PPROTSET0; /*Peripheral Protection Set Register 0*/ + uint32_t PPROTSET1; /*Peripheral Protection Set Register 1*/ + uint32_t PPROTSET2; /*Peripheral Protection Set Register 2*/ + uint32_t PPROTSET3; /*Peripheral Protection Set Register 3*/ + uint8_t reserved3 [16]; + uint32_t PPROTCLR0; /*Peripheral Protection Clear Register 0*/ + uint32_t PPROTCLR1; /*Peripheral Protection Clear Register 1*/ + uint32_t PPROTCLR2; /*Peripheral Protection Clear Register 2*/ + uint32_t PPROTCLR3; /*Peripheral Protection Clear Register 3*/ + uint8_t reserved4 [16]; + uint32_t PCSPWRDWNSET0; /*Peripheral Memory Power-Down Set Register 0*/ + uint32_t PCSPWRDWNSET1; /*Peripheral Memory Power-Down Set Register 1*/ + uint8_t reserved5 [8]; + uint32_t PCSPWRDWNCLR0; /*Peripheral Memory Power-Down Clear Register 0*/ + uint32_t PCSPWRDWNCLR1; /*Peripheral Memory Power-Down Clear Register 1*/ + uint8_t reserved6 [8]; + uint32_t PSPWRDWNSET0; /*Peripheral Power-Down Set Register 0*/ + uint32_t PSPWRDWNSET1; /*Peripheral Power-Down Set Register 1*/ + uint32_t PSPWRDWNSET2; /*Peripheral Power-Down Set Register 2*/ + uint32_t PSPWRDWNSET3; /*Peripheral Power-Down Set Register 3*/ + uint8_t reserved7 [16]; + uint32_t PSPWRDWNCLR0; /*Peripheral Power-Down Clear Register 0*/ + uint32_t PSPWRDWNCLR1; /*Peripheral Power-Down Clear Register 1*/ + uint32_t PSPWRDWNCLR2; /*Peripheral Power-Down Clear Register 2*/ + uint32_t PSPWRDWNCLR3; /*Peripheral Power-Down Clear Register 3*/ +} tms570_pcr_t; + + +/*-------------------TMS570_PCR_PMPROTSET0-------------------*/ +/* field: PCSPROTSET - Peripheral memory frame protection set. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTSET1-------------------*/ +/* field: PCSPROTSET - Peripheral memory frame protection set. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTCLR0-------------------*/ +/* field: PCSPROTCLR - Peripheral memory frame protection clear. */ +/* Whole 32 bits */ + +/*-------------------TMS570_PCR_PMPROTCLR1-------------------*/ +/* field: PCSPROTCLR - Peripheral memory frame protection clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_PCR_PPROTSETx--------------------*/ +/* field: PROTSET - Peripheral select quadrant protection set. */ +/* Whole 32 bits */ + +/*--------------------TMS570_PCR_PPROTCLRx--------------------*/ +/* field: PROTCLR - Peripheral select quadrant protection clear. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PCSPWRDWNSETx------------------*/ +/* field: PWRDNSET - Peripheral memory clock power-down set. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PCSPWRDWNCLRx------------------*/ +/* field: PWRDNCLR - Peripheral memory clock power-down clear. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PSPWRDWNSETx------------------*/ +/* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */ +/* Whole 32 bits */ + +/*------------------TMS570_PCR_PSPWRDWNCLRx------------------*/ +/* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_PCR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h new file mode 100644 index 0000000000..1cb8b03308 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h @@ -0,0 +1,298 @@ +/* The header file is generated by make_header.py from PLL.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PLL +#define LIBBSP_ARM_TMS570_PLL + +#include + +typedef struct{ + uint32_t PLLCTL3; /*PLL Control 3 Register*/ + uint8_t reserved1 [108]; + uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/ + uint8_t reserved2 [7600]; + uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/ + uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/ + uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/ + uint32_t CSDIS; /*Clock Source Disable Register*/ + uint32_t CSDISSET; /*Clock Source Disable Set Register*/ + uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ + uint8_t reserved3 [24]; + uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ + uint8_t reserved4 [24]; + uint32_t PLLCTL1; /*PLL Control 1 Register*/ + uint32_t PLLCTL2; /*PLL Control 2 Register*/ + uint8_t reserved5 [16]; + uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ + uint32_t CLKTEST; /*Clock Test Register*/ + uint8_t reserved6 [16]; + uint32_t GPREG1; /*General Purpose Register*/ + uint8_t reserved7 [72]; + uint32_t GLBSTAT; /*Global Status Register*/ +} tms570_pll_t; + + +/*---------------------TMS570_PLL_PLLCTL3---------------------*/ +/* field: ODPLL2 - Internal PLL Output Divider */ +#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) +#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: PLLDIV2 - PLL2 Output Clock Divider */ +#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) +#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: REFCLKDIV2 - Reference Clock Divider */ +#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) +#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL2 - PLL2 Multiplication Factor */ +#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_CLKSLIP---------------------*/ +/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_PLL_SSWPLL1---------------------*/ +/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */ +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15) +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: COUNTER_READ_READY - Counter read ready. */ +#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6) + +/* field: COUNTER_RESET - Counter reset. */ +#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5) + +/* field: COUNTER_EN - Counter enable. */ +#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4) + +/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */ +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3) +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3) +#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3) + +/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */ +#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0) + + +/*---------------------TMS570_PLL_SSWPLL2---------------------*/ +/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */ +/* Whole 32 bits */ + +/*---------------------TMS570_PLL_SSWPLL3---------------------*/ +/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */ +/* Whole 32 bits */ + +/*----------------------TMS570_PLL_CSDIS----------------------*/ +/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */ +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */ +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_PLL_CSDISSET--------------------*/ +/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */ +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */ +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_PLL_CSDISCLR--------------------*/ +/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */ +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */ +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PLL_CSVSTAT---------------------*/ +/* field: CLKSR_7_3V - Clock source[7-0] valid. */ +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7) +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR_1_0V - Clock source[1-0] valid. */ +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1) +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_PLL_PLLCTL1---------------------*/ +/* field: ROS - Reset on PLL Slip */ +#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31) + +/* field: MASK_SLIP - Mask detection of PLL slip */ +#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) +#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: PLLDIV - PLL Output Clock Divider */ +#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) +#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: ROF - Reset on Oscillator Fail */ +#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23) + +/* field: REFCLKDIV - Reference Clock Divider */ +#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) +#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL - PLL Multiplication Factor */ +#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_PLLCTL2---------------------*/ +/* field: FMENA - Frequency Modulation Enable. */ +#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31) + +/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ +#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) +#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) +#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) + +/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ +#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) +#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) +#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) + +/* field: ODPLL - Internal PLL Output Divider. */ +#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) +#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: SPR_AMOUNT - Spreading Amount. */ +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_PLL_LPOMONCTL--------------------*/ +/* field: BIAS_ENABLE - Bias enable. */ +#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) + +/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ +#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) + +/* field: HFTRIM - High frequency oscillator trim value. */ +#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) +#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + + +/*---------------------TMS570_PLL_CLKTEST---------------------*/ +/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ +#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) + +/* field: RANGEDETCTRL - Range detection control. */ +#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25) + +/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ +#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) + +/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ +#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + + +/*---------------------TMS570_PLL_GPREG1---------------------*/ +/* field: EMIF_FUNC - Enable EMIF functions to be output. */ +#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31) + +/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_PLL_GLBSTAT---------------------*/ +/* field: FBSLIP - PLL over cycle slip detection. */ +#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9) + +/* field: RFSLIP - PLL under cycle slip detection. */ +#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8) + +/* field: OSCFAIL - Oscillator fail flag bit. */ +#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_PLL */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h new file mode 100644 index 0000000000..c834b83999 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h @@ -0,0 +1,258 @@ +/* The header file is generated by make_header.py from PMM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_PMM +#define LIBBSP_ARM_TMS570_PMM + +#include + +typedef struct{ + uint32_t LOGICPDPWRCTRL0; /*Logic Power Domain Control Register 0*/ + uint8_t reserved1 [12]; + uint32_t MEMPDPWRCTRL0; /*Memory Power Domain Control Register 0*/ + uint8_t reserved2 [12]; + uint32_t PDCLKDISREG; /*Power Domain Clock Disable Register*/ + uint32_t PDCLKDISSETREG; /*Power Domain Clock Disable Set Register*/ + uint32_t PDCLKDISCLRREG; /*Power Domain Clock Disable Clear Register*/ + uint8_t reserved3 [20]; + uint32_t LOGICPDPWRSTAT[4]; /*Logic Power Domain PD2 Power Status Registers*/ + uint8_t reserved4 [48]; + uint32_t MEMPDPWRSTAT[3]; /*Memory Power Domain RAM_PD1 Power Status Registers*/ + uint8_t reserved5 [20]; + uint32_t GLOBALCTRL1; /*Global Control Register 1*/ + uint8_t reserved6 [4]; + uint32_t GLOBALSTAT; /*Global Status Register*/ + uint32_t PRCKEYREG; /*PSCON Diagnostic Compare Key Register*/ + uint32_t LPDDCSTAT1; /*LogicPD PSCON Diagnostic Compare Status Register 1*/ + uint32_t LPDDCSTAT2; /*LogicPD PSCON Diagnostic Compare Status Register 2*/ + uint32_t MPDDCSTAT1; /*Memory PD PSCON Diagnostic Compare Status Register 1*/ + uint32_t MPDDCSTAT2; /*Memory PD PSCON Diagnostic Compare Status Register 2*/ + uint32_t ISODIAGSTAT; /*Isolation Diagnostic Status Register*/ +} tms570_pmm_t; + + +/*-----------------TMS570_PMM_LOGICPDPWRCTRL0-----------------*/ +/* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: LOGICPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LOGICPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2(val) BSP_FLD32(val,8, 11) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LOGICPDON3 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_PMM_MEMPDPWRCTRL0------------------*/ +/* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: MEMPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: MEMPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */ +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2(val) BSP_FLD32(val,8, 11) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + + +/*-------------------TMS570_PMM_PDCLKDISREG-------------------*/ +/* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_BIT32(3) + +/* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_BIT32(2) + +/* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_BIT32(1) + +/* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */ +#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_PDCLKDISSETREG-----------------*/ +/* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_BIT32(3) + +/* field: PDCLK_DISSET_2 - Privileged Mode only. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_BIT32(2) + +/* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_BIT32(1) + +/* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */ +#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_PDCLKDISCLRREG-----------------*/ +/* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_BIT32(3) + +/* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_BIT32(2) + +/* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_BIT32(1) + +/* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */ +#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_BIT32(0) + + +/*-----------------TMS570_PMM_LOGICPDPWRSTAT-----------------*/ +/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24) + +/* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16) + +/* field: DOMAIN_ON0 - Current state of power domain PD2. */ +#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8) + +/* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */ +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1) +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*------------------TMS570_PMM_MEMPDPWRSTAT------------------*/ +/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24) + +/* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16) + +/* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */ +#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8) + +/* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */ +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1) +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*-------------------TMS570_PMM_GLOBALCTRL1-------------------*/ +/* field: PMCTRL_PWRDN - PMC/PSCON Power Down */ +#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_BIT32(8) + +/* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */ +#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_BIT32(0) + + +/*-------------------TMS570_PMM_GLOBALSTAT-------------------*/ +/* field: PMCTRL_IDLE - State of PMC and all PSCONs. */ +#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_BIT32(0) + + +/*--------------------TMS570_PMM_PRCKEYREG--------------------*/ +/* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */ +#define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_LPDDCSTAT1-------------------*/ +/* field: LCMPE - Logic Power Domain Compare Error */ +#define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LPDDCSTAT1_LCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LSTC - Logic Power Domain Self-test Complete */ +#define TMS570_PMM_LPDDCSTAT1_LSTC(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LPDDCSTAT1_LSTC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_LPDDCSTAT2-------------------*/ +/* field: LSTET - Logic Power Domain Self-test Error Type */ +#define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19) +#define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_PMM_LPDDCSTAT2_LSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: LSTE - Logic Power Domain Self-test Error */ +#define TMS570_PMM_LPDDCSTAT2_LSTE(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_LPDDCSTAT2_LSTE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_PMM_MPDDCSTAT1-------------------*/ +/* field: MCMPE - Memory Power Domain Compare Error */ +#define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18) +#define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_PMM_MPDDCSTAT1_MCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MSTC - Memory Power Domain Self-test Complete */ +#define TMS570_PMM_MPDDCSTAT1_MSTC(val) BSP_FLD32(val,0, 2) +#define TMS570_PMM_MPDDCSTAT1_MSTC_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_PMM_MPDDCSTAT2-------------------*/ +/* field: MSTET - Memory Power Domain Self-test Error Type */ +#define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18) +#define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_PMM_MPDDCSTAT2_MSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: MSTE - Memory Power Domain Self-test Error */ +#define TMS570_PMM_MPDDCSTAT2_MSTE(val) BSP_FLD32(val,0, 2) +#define TMS570_PMM_MPDDCSTAT2_MSTE_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-------------------TMS570_PMM_ISODIAGSTAT-------------------*/ +/* field: ISO_DIAG - Isolation Diagnostic */ +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3) +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_PMM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h new file mode 100644 index 0000000000..1a4df19f8a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h @@ -0,0 +1,309 @@ +/* The header file is generated by make_header.py from POM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_POM +#define LIBBSP_ARM_TMS570_POM + +#include + +typedef struct{ + uint32_t PROGSTART; /*POM Program Region Start Address Register*/ + uint32_t OVLSTART; /*POM Overlay Region Start Address Register*/ + uint32_t REGSIZE; /*POM Region Size Register */ + uint32_t Reser; /*Reserved*/ +} tms570_pom_region_t; + +typedef struct{ + uint32_t GLBCTRL; /*POM Global Control Register*/ + uint32_t REV; /*POM Revision ID*/ + uint32_t CLKCTRL; /*POM Clock Gate Control Register*/ + uint32_t FLG; /*POM Status Register*/ + uint8_t reserved1 [496]; + tms570_pom_region_t REG[32];/*Program Regions*/ + uint8_t reserved2 [2816]; + uint32_t ITCTRL; /*POM Integration Control Register*/ + uint8_t reserved3 [156]; + uint32_t CLAIMSET; /*POM Claim Set Register*/ + uint32_t CLAIMCLR; /*POM Claim Clear Register*/ + uint8_t reserved4 [8]; + uint32_t LOCKACCESS; /*POM Lock Access Register*/ + uint32_t LOCKSTATUS; /*POM Lock Status Register*/ + uint32_t AUTHSTATUS; /*POM Authentication Status Register*/ + uint8_t reserved5 [12]; + uint32_t DEVID; /*POM Device ID Register*/ + uint32_t DEVTYPE; /*POM Device Type Register*/ + uint32_t PERIPHERALID4; /*POM Peripheral ID 4 Register*/ + uint32_t PERIPHERALID5; /*POM Peripheral ID 5 Register*/ + uint32_t PERIPHERALID6; /*POM Peripheral ID 6 Register*/ + uint32_t PERIPHERALID7; /*POM Peripheral ID 7 Register*/ + uint32_t PERIPHERALID0; /*POM Peripheral ID 0 Register*/ + uint32_t PERIPHERALID1; /*POM Peripheral ID 1 Register*/ + uint32_t PERIPHERALID2; /*POM Peripheral ID 2 Register*/ + uint32_t PERIPHERALID3; /*POM Peripheral ID 3 Register*/ + uint32_t COMPONENTID0; /*POM Component ID 0 Register*/ + uint32_t COMPONENTID1; /*POM Component ID 1 Register*/ + uint32_t COMPONENTID2; /*POM Component ID 2 Register*/ + uint32_t COMPONENTID3; /*POM Component ID 3 Register*/ +} tms570_pom_t; + + +/*--------------------TMS570_POM_PROGSTART--------------------*/ +/* field: STARTADDRESS - Defines the start address of the program memory region. */ +#define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22) +#define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22) +#define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22) + + +/*--------------------TMS570_POM_OVLSTART--------------------*/ +/* field: STARTADDRESS - Defines the start address of the overlay memory region. */ +#define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22) +#define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22) +#define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22) + + +/*---------------------TMS570_POM_REGSIZE---------------------*/ +/* field: SIZE - Region size */ +#define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_POM_GLBCTRL---------------------*/ +/* field: OTADDR - Overlay target Address. */ +#define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31) +#define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31) +#define TMS570_POM_GLBCTRL_OTADDR_SET(reg,val) BSP_FLD32SET(reg, val,23, 31) + +/* field: ETO - Enable Timeout. Refer to Section 18.2.2 for more details on the timeout error. */ +#define TMS570_POM_GLBCTRL_ETO(val) BSP_FLD32(val,8, 11) +#define TMS570_POM_GLBCTRL_ETO_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_POM_GLBCTRL_ETO_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ON_OFF - Turn functionality of POM on or off. */ +#define TMS570_POM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_POM_REV-----------------------*/ +/* field: SCHEME - Used to distinguish between different ID schemes. */ +#define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31) +#define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31) +#define TMS570_POM_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31) + +/* field: FUNC - Indicates the SW compatible module family */ +#define TMS570_POM_REV_FUNC(val) BSP_FLD32(val,16, 27) +#define TMS570_POM_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27) +#define TMS570_POM_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27) + +/* field: RTL - RTL version number */ +#define TMS570_POM_REV_RTL(val) BSP_FLD32(val,11, 15) +#define TMS570_POM_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15) +#define TMS570_POM_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15) + +/* field: MAJOR - Major revision number */ +#define TMS570_POM_REV_MAJOR(val) BSP_FLD32(val,8, 10) +#define TMS570_POM_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_POM_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: CUSTOM - Indicates a device specific implementation */ +#define TMS570_POM_REV_CUSTOM(val) BSP_FLD32(val,6, 7) +#define TMS570_POM_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_POM_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: 5_0 - MINOR 8h Minor revision number */ +#define TMS570_POM_REV_5_0(val) BSP_FLD32(val,0, 5) +#define TMS570_POM_REV_5_0_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*---------------------TMS570_POM_CLKCTRL---------------------*/ +/* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */ +#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_BIT32(0) + + +/*-----------------------TMS570_POM_FLG-----------------------*/ +/* field: TO - Timeout. */ +#define TMS570_POM_FLG_TO BSP_BIT32(0) + + +/*---------------------TMS570_POM_ITCTRL---------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*--------------------TMS570_POM_CLAIMSET--------------------*/ +/* field: SET1 - The module is claimed */ +#define TMS570_POM_CLAIMSET_SET1 BSP_BIT32(1) + +/* field: SET0 - The module is claimed */ +#define TMS570_POM_CLAIMSET_SET0 BSP_BIT32(0) + + +/*--------------------TMS570_POM_CLAIMCLR--------------------*/ +/* field: CLR1 - The module is claimed */ +#define TMS570_POM_CLAIMCLR_CLR1 BSP_BIT32(1) + +/* field: CLR0 - The module is claimed */ +#define TMS570_POM_CLAIMCLR_CLR0 BSP_BIT32(0) + + +/*-------------------TMS570_POM_LOCKACCESS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*-------------------TMS570_POM_LOCKSTATUS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*-------------------TMS570_POM_AUTHSTATUS-------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*----------------------TMS570_POM_DEVID----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*---------------------TMS570_POM_DEVTYPE---------------------*/ +/* field: Sub_Type - Other */ +#define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_DEVTYPE_Sub_Type_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Major_Type - Debug Control */ +#define TMS570_POM_DEVTYPE_Major_Type(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_DEVTYPE_Major_Type_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID4------------------*/ +/* field: 4KB_Count - Only 4KB implemented */ +#define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID4_4KB_Count_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: JEP_Continuation - JEP106 Code */ +#define TMS570_POM_PERIPHERALID4_JEP_Continuation(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_PERIPHERALID4_JEP_Continuation_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID5------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID6------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID7------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_PERIPHERALID0------------------*/ +/* field: Part_Number - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_PERIPHERALID1------------------*/ +/* field: JEP106_Identity - Part of TI JEDEC number */ +#define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID1_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Part_Number - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID1_Part_Number(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_PERIPHERALID1_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_PERIPHERALID2------------------*/ +/* field: Revision - Reads 0, since POMREV defines the module */ +#define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: JEDEC - Indicates JEDEC assigned value */ +#define TMS570_POM_PERIPHERALID2_JEDEC BSP_BIT32(3) + +/* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */ +#define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2) +#define TMS570_POM_PERIPHERALID2_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*------------------TMS570_POM_PERIPHERALID3------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +/* Whole 32 bits */ + +/*------------------TMS570_POM_COMPONENTID0------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_COMPONENTID1------------------*/ +/* field: Component_Class - CoreSight Component */ +#define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7) +#define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7) +#define TMS570_POM_COMPONENTID1_Component_Class_SET(reg,val) BSP_FLD32SET(reg, val,4, 7) + +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID1_Preamble(val) BSP_FLD32(val,0, 3) +#define TMS570_POM_COMPONENTID1_Preamble_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_POM_COMPONENTID2------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*------------------TMS570_POM_COMPONENTID3------------------*/ +/* field: Preamble - Preamble */ +#define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7) +#define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_POM_COMPONENTID3_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + + +#endif /* LIBBSP_ARM_TMS570_POM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h new file mode 100644 index 0000000000..029b3b5721 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h @@ -0,0 +1,359 @@ +/* The header file is generated by make_header.py from RTI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_RTI +#define LIBBSP_ARM_TMS570_RTI + +#include + +typedef struct{ + uint32_t COMPx; /*RTI Compare x Register*/ + uint32_t UDCPx; /*RTI Update Compare x Register*/ +} tms570_rti_compare_t; + +typedef struct{ + uint32_t FRCx; /*RTI Free Running Counter x Register*/ + uint32_t UCx; /*RTI Up Counter x Register*/ + uint32_t CPUCx; /*RTI Compare Up Counter x Register*/ + uint8_t reserved1 [4]; + uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/ + uint32_t CAUCx; /*RTI Capture Up Counter x Register*/ + uint32_t rsvd[2]; /*Reserved*/ +} tms570_rti_counter_t; + +typedef struct{ + uint32_t GCTRL; /*RTI Global Control Register*/ + uint32_t TBCTRL; /*RTI Timebase Control Register*/ + uint32_t CAPCTRL; /*RTI Capture Control Register*/ + uint32_t COMPCTRL; /*RTI Compare Control Register*/ + tms570_rti_counter_t CNT[2];/*Counters*/ + tms570_rti_compare_t CMP[4];/*Compares*/ + uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/ + uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/ + uint8_t reserved2 [8]; + uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/ + uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/ + uint32_t INTFLAG; /*RTI Interrupt Flag Register*/ + uint8_t reserved3 [4]; + uint32_t DWDCTRL; /*Digital Watchdog Control Register*/ + uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/ + uint32_t WDSTATUS; /*Watchdog Status Register*/ + uint32_t WDKEY; /*RTI Watchdog Key Register*/ + uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/ + uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/ + uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/ + uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/ + uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/ + uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/ + uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/ + uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/ +} tms570_rti_t; + + +/*----------------------TMS570_RTI_COMPx----------------------*/ +/* field: COMPx - Compare x. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_UDCPx----------------------*/ +/* field: UDCPx - Update compare x. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_FRCx----------------------*/ +/* field: FRC0 - FRC0 */ +/* Whole 32 bits */ + +/*-----------------------TMS570_RTI_UCx-----------------------*/ +/* field: UC0 - Up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_CPUCx----------------------*/ +/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_CAFRCx---------------------*/ +/* field: CAFRC0 - Capture free running counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_CAUCx----------------------*/ +/* field: CAUC0 - Capture up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_rsvd----------------------*/ +/* field: CAUC0 - Capture up counter 0. */ +/* Whole 32 bits */ + +/*----------------------TMS570_RTI_GCTRL----------------------*/ +/* field: NTUSEL - Select NTU signal. */ +#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19) +#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: COS - Continue on suspend. */ +#define TMS570_RTI_GCTRL_COS BSP_BIT32(15) + +/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */ +#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1) + +/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */ +#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0) + + +/*---------------------TMS570_RTI_TBCTRL---------------------*/ +/* field: INC - Increment free running counter 0. */ +#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1) + +/* field: TBEXT - Timebase external. */ +#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0) + + +/*---------------------TMS570_RTI_CAPCTRL---------------------*/ +/* field: CAPCNTR1 - Capture counter 1. */ +#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1) + +/* field: CAPCNTR0 - Capture counter 0. */ +#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0) + + +/*--------------------TMS570_RTI_COMPCTRL--------------------*/ +/* field: COMPSEL3 - Compare select 3. */ +#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12) + +/* field: COMPSEL2 - Compare select 2. */ +#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8) + +/* field: COMPSEL1 - Compare select 1. */ +#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4) + +/* field: COMPSEL0 - Compare select 0. */ +#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_TBLCOMP---------------------*/ +/* field: TBLCOMP - Timebase low compare value. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_TBHCOMP---------------------*/ +/* field: TBHCOMP - Timebase high compare value. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_SETINTENA--------------------*/ +/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */ +#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18) + +/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */ +#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17) + +/* field: SETTBINT - Set timebase interrupt. */ +#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16) + +/* field: SETDMA3 - Set compare DMA request 3. */ +#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11) + +/* field: SETDMA2 - Set compare DMA request 2. */ +#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10) + +/* field: SETDMA1 - Set compare DMA request 1. */ +#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9) + +/* field: SETDMA0 - Set compare DMA request 0. */ +#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8) + +/* field: SETINT3 - Set compare interrupt 3. */ +#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3) + +/* field: SETINT2 - Set compare interrupt 2. */ +#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2) + +/* field: SETINT1 - Set compare interrupt 1. */ +#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1) + +/* field: SETINT0 - Set compare interrupt 0. */ +#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0) + + +/*-------------------TMS570_RTI_CLEARINTENA-------------------*/ +/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18) + +/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17) + +/* field: CLEARTBINT - Clear timebase interrupt. */ +#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16) + +/* field: CLEARDMA3 - Clear compare DMA request 3. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11) + +/* field: CLEARDMA2 - Clear compare DMA request 2. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10) + +/* field: CLEARDMA1 - Clear compare DMA request 1. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9) + +/* field: CLEARDMA0 - Clear compare DMA request 0. */ +#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8) + +/* field: CLEARINT3 - Clear compare interrupt 3. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3) + +/* field: CLEARINT2 - Clear compare interrupt 2. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2) + +/* field: CLEARINT1 - Clear compare interrupt 1. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1) + +/* field: CLEARINT0 - Clear compare interrupt 0. */ +#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_INTFLAG---------------------*/ +/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */ +#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18) + +/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */ +#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17) + +/* field: TBINT - Timebase interrupt flag. */ +#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16) + +/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */ +#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3) + +/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */ +#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2) + +/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */ +#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1) + +/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */ +#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0) + + +/*---------------------TMS570_RTI_DWDCTRL---------------------*/ +/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */ +/* Whole 32 bits */ + +/*---------------------TMS570_RTI_DWDPRLD---------------------*/ +/* field: DWDPRLD - Digital Watchdog Preload Value. */ +#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15) +#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_RTI_WDSTATUS--------------------*/ +/* field: DWWD_ST - Windowed Watchdog Status */ +#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5) + +/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */ +#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4) + +/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */ +#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3) + +/* field: KEY_ST - Watchdog key status. */ +#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2) + +/* field: DWD_ST - DWD status. */ +#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1) + + +/*----------------------TMS570_RTI_WDKEY----------------------*/ +/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */ +#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15) +#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_RTI_DWDCNTR---------------------*/ +/* field: DWDCNTR - DWD down counter. */ +#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24) +#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24) +#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24) + + +/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/ +/* field: WWDRXN - The DWWD reaction */ +#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3) +#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/ +/* field: WWDSIZE - The DWWD window size */ +/* Whole 32 bits */ + +/*------------------TMS570_RTI_INTCLRENABLE------------------*/ +/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */ +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_RTI_COMP0CLR--------------------*/ +/* field: CMP0CLR - Compare 0 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP1CLR--------------------*/ +/* field: CMP0CLR - Compare 1 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP2CLR--------------------*/ +/* field: CMP2CLR - Compare 2 clear. */ +/* Whole 32 bits */ + +/*--------------------TMS570_RTI_COMP3CLR--------------------*/ +/* field: CMP3CLR - Compare 3 clear. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_RTI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h new file mode 100644 index 0000000000..cd54b29050 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h @@ -0,0 +1,227 @@ +/* The header file is generated by make_header.py from RTP.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_RTP +#define LIBBSP_ARM_TMS570_RTP + +#include + +typedef struct{ + uint32_t GLBCTRL; /*RTP Global Control Register*/ + uint32_t TRENA; /*RTP Trace Enable Register*/ + uint32_t GSR; /*RTP Global Status Register*/ + uint32_t RAM1REG1; /*RTP RAM 1 Trace Region 1 Register*/ + uint32_t RAM1REG2; /*RTP RAM 1 Trace Region 2 Register*/ + uint32_t RAM2REG1; /*RTP RAM 2 Trace Region 1 Register*/ + uint32_t RAM2REG2; /*RTP RAM 2 Trace Region 2 Register*/ + uint8_t reserved1 [8]; + uint32_t PERREG1; /*RTP Peripheral Trace Region 1 Register*/ + uint32_t PERREG2; /*RTP Peripheral Trace Region 2 Register*/ + uint32_t DDMW; /*RTP Direct Data Mode Write Register*/ + uint8_t reserved2 [4]; + uint32_t PC0; /*RTP Pin Control 0 Register*/ + uint32_t PC1; /*RTP Pin Control 1 Register*/ + uint32_t PC2; /*RTP Pin Control 2 Register*/ + uint32_t PC3; /*RTP Pin Control 3 Register*/ + uint32_t PC4; /*RTP Pin Control 4 Register*/ + uint32_t PC5; /*RTP Pin Control 5 Register*/ + uint32_t PC6; /*RTP Pin Control 6 Register*/ + uint32_t PC7; /*RTP Pin Control 7 Register*/ + uint32_t PC8; /*RTP Pin Control 8 Register*/ +} tms570_rtp_t; + + +/*---------------------TMS570_RTP_GLBCTRL---------------------*/ +/* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */ +#define TMS570_RTP_GLBCTRL_TEST BSP_BIT32(24) + +/* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */ +#define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18) +#define TMS570_RTP_GLBCTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_RTP_GLBCTRL_PRESCALER_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: DDM_WIDTH - Direct data mode word size width. */ +#define TMS570_RTP_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,12, 13) +#define TMS570_RTP_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: DDM_RW - */ +#define TMS570_RTP_GLBCTRL_DDM_RW BSP_BIT32(11) + +/* field: TM_DDM - Trace Mode or Direct Data Mode */ +#define TMS570_RTP_GLBCTRL_TM_DDM BSP_BIT32(10) + +/* field: PW - Port width. This bit field configures the RTP to the desired port width. */ +#define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9) +#define TMS570_RTP_GLBCTRL_PW_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: RESET - This bit resets the state machine and the registers to their reset value. */ +#define TMS570_RTP_GLBCTRL_RESET BSP_BIT32(7) + +/* field: CONTCLK - Continuous RTPCLK enable. */ +#define TMS570_RTP_GLBCTRL_CONTCLK BSP_BIT32(6) + +/* field: HOVF - Halt on overflow. */ +#define TMS570_RTP_GLBCTRL_HOVF BSP_BIT32(5) + +/* field: INV_RGN - Trace inside or outside of defined trace regions. */ +#define TMS570_RTP_GLBCTRL_INV_RGN BSP_BIT32(4) + +/* field: ON_OFF - ON/Off switch. */ +#define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3) +#define TMS570_RTP_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------------TMS570_RTP_TRENA----------------------*/ +/* field: ENA4 - Enable tracing for peripherals. */ +#define TMS570_RTP_TRENA_ENA4 BSP_BIT32(24) + +/* field: ENA2 - Enable tracing for RAM block 2. */ +#define TMS570_RTP_TRENA_ENA2 BSP_BIT32(8) + +/* field: ENA1 - */ +#define TMS570_RTP_TRENA_ENA1 BSP_BIT32(0) + + +/*-----------------------TMS570_RTP_GSR-----------------------*/ +/* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */ +#define TMS570_RTP_GSR_EMPTYSER BSP_BIT32(12) + +/* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTYPER BSP_BIT32(11) + +/* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTY2 BSP_BIT32(9) + +/* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */ +#define TMS570_RTP_GSR_EMPTY1 BSP_BIT32(8) + +/* field: OVFPER - Overflow peripheral FIFO. */ +#define TMS570_RTP_GSR_OVFPER BSP_BIT32(3) + +/* field: OVF2 - Overflow RAM block 2 FIFO. */ +#define TMS570_RTP_GSR_OVF2 BSP_BIT32(1) + +/* field: OVF1 - Overflow RAM block 1 FIFO. */ +#define TMS570_RTP_GSR_OVF1 BSP_BIT32(0) + + +/*--------------------TMS570_RTP_RAM1REGx--------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_RAM1REGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_RAM1REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_RAM1REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_RAM1REGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_RAM1REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_RAM1REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_RAM1REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_RAM1REGx_STARTADDR(val) BSP_FLD32(val,0, 17) +#define TMS570_RTP_RAM1REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17) +#define TMS570_RTP_RAM1REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17) + + +/*--------------------TMS570_RTP_RAM2REGx--------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_RAM2REGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_RAM2REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_RAM2REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_RAM2REGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_RAM2REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_RAM2REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_RAM2REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_RAM2REGx_STARTADDR(val) BSP_FLD32(val,0, 23) +#define TMS570_RTP_RAM2REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_RTP_RAM2REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*---------------------TMS570_RTP_PERREGx---------------------*/ +/* field: CPU_DMA - CPU and/or other master access. */ +#define TMS570_RTP_PERREGx_CPU_DMA(val) BSP_FLD32(val,29, 30) +#define TMS570_RTP_PERREGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_RTP_PERREGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: RW - Read/Write. */ +#define TMS570_RTP_PERREGx_RW BSP_BIT32(28) + +/* field: BLOCKSIZE - These bits define the length of the trace region. */ +#define TMS570_RTP_PERREGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27) +#define TMS570_RTP_PERREGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_RTP_PERREGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */ +#define TMS570_RTP_PERREGx_STARTADDR(val) BSP_FLD32(val,0, 23) +#define TMS570_RTP_PERREGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_RTP_PERREGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*----------------------TMS570_RTP_DDMW----------------------*/ +/* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */ +/* Whole 32 bits */ + +/*-----------------------TMS570_RTP_PCx-----------------------*/ +/* field: ENAFUNC - Functional mode of RTPENA pin. */ +#define TMS570_RTP_PCx_ENAFUNC BSP_BIT32(18) + +/* field: CLKFUNC - Functional mode of RTPCLK pin. */ +#define TMS570_RTP_PCx_CLKFUNC BSP_BIT32(17) + +/* field: SYNCFUNC - Functional mode of RTPSYNC pin. */ +#define TMS570_RTP_PCx_SYNCFUNC BSP_BIT32(16) + +/* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */ +#define TMS570_RTP_PCx_DATAFUNC(val) BSP_FLD32(val,0, 15) +#define TMS570_RTP_PCx_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_RTP_PCx_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + + +#endif /* LIBBSP_ARM_TMS570_RTP */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h new file mode 100644 index 0000000000..6b954f7fcf --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h @@ -0,0 +1,450 @@ +/* The header file is generated by make_header.py from SCI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SCI +#define LIBBSP_ARM_TMS570_SCI + +#include + +typedef struct{ + uint32_t GCR0; /*SCI Global Control Register 0*/ + uint32_t GCR1; /*SCI Global Control Register 1*/ + uint32_t GCR2; /*SCI Global Control Register 2*/ + uint32_t SETINT; /*SCI Set Interrupt Register*/ + uint32_t CLEARINT; /*SCI Clear Interrupt Register*/ + uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/ + uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/ + uint32_t FLR; /*SCI Flags Register*/ + uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/ + uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/ + uint32_t FORMAT; /*SCI Format Control Register*/ + uint32_t BRS; /*Baud Rate Selection Register*/ + uint32_t ED; /*Receiver Emulation Data Buffer*/ + uint32_t RD; /*Receiver Data Buffer*/ + uint32_t TD; /*Transmit Data Buffer*/ + uint32_t PIO0; /*SCI Pin I/O Control Register 0*/ + uint32_t PIO1; /*SCI Pin I/O Control Register 1*/ + uint32_t PIO2; /*SCI Pin I/O Control Register 2*/ + uint32_t PIO3; /*SCI Pin I/O Control Register 3*/ + uint32_t PIO4; /*SCI Pin I/O Control Register 4*/ + uint32_t PIO5; /*SCI Pin I/O Control Register 5*/ + uint32_t PIO6; /*SCI Pin I/O Control Register 6*/ + uint32_t PIO7; /*SCI Pin I/O Control Register 7*/ + uint32_t PIO8; /*SCI Pin I/O Control Register 8*/ + uint8_t reserved1 [48]; + uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/ +} tms570_sci_t; + + +/*----------------------TMS570_SCI_GCR0----------------------*/ +/* field: Reserved - Read returns 0. Writes have no effect. */ +#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31) +#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) +#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31) + +/* field: RESET - This bit resets the SCI module. */ +#define TMS570_SCI_GCR0_RESET BSP_BIT32(0) + + +/*----------------------TMS570_SCI_GCR1----------------------*/ +/* field: TXENA - Transmit enable. */ +#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25) + +/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */ +#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24) + +/* field: CONT - Continue on suspend. */ +#define TMS570_SCI_GCR1_CONT BSP_BIT32(17) + +/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */ +#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16) + +/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */ +#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9) + +/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */ +#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8) + +/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */ +#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7) + +/* field: CLOCK - CLOCK */ +#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5) + +/* field: STOP - SCI number of stop bits per frame. */ +#define TMS570_SCI_GCR1_STOP BSP_BIT32(4) + +/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */ +#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3) + +/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */ +#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2) + +/* field: TIMING_MODE - SCI timing mode bit. */ +#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1) + +/* field: COMM_MODE - SCI communication mode bit. */ +#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0) + + +/*----------------------TMS570_SCI_GCR2----------------------*/ +/* field: CC - Compare checksum. LIN mode only. */ +#define TMS570_SCI_GCR2_CC BSP_BIT32(17) + +/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */ +#define TMS570_SCI_GCR2_SC BSP_BIT32(16) + +/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */ +#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8) + +/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */ +#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0) + + +/*---------------------TMS570_SCI_SETINT---------------------*/ +/* field: SET_FE_INT - */ +#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26) + +/* field: SET_OE_INT - SET OE INT */ +#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25) + +/* field: SET_PE_INT - Set parity interrupt. */ +#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL - SET RX DMA ALL */ +#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) + +/* field: SET_RX_DMA - SET RX DMA */ +#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17) + +/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */ +#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16) + +/* field: SET_RX_INT - SET RX INT */ +#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9) + +/* field: SET_TX_INT - Set transmitter interrupt. */ +#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8) + +/* field: SET_WAKEUP_INT - Set wakeup interrupt. */ +#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1) + +/* field: SET_BRKDT_INT - Set breakdetect interrupt. */ +#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_CLEARINT--------------------*/ +/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26) + +/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25) + +/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) + +/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17) + +/* field: CLR_TX_DMA - CLR TX DMA */ +#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16) + +/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9) + +/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) + +/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */ +#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_SETINTLVL--------------------*/ +/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) + +/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) + +/* field: SET_PE_INT_LVL - Set parity error interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) + +/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */ +#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: SET_RX_INT_LVL - Set receiver interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) + +/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) + +/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */ +#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */ +#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/ +/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_CE_INT_LVL - CLR CE INT LVL */ +#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) + +/* field: CLR_PE_INT_LVL - */ +#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) + +/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */ +#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) + +/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) + +/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */ +#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8) + +/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) + +/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */ +#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) + + +/*-----------------------TMS570_SCI_FLR-----------------------*/ +/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */ +#define TMS570_SCI_FLR_FE BSP_BIT32(26) + +/* field: OE - Overrun error flag. */ +#define TMS570_SCI_FLR_OE BSP_BIT32(25) + +/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */ +#define TMS570_SCI_FLR_PE BSP_BIT32(24) + +/* field: RXWAKE - Receiver wakeup detect flag. */ +#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12) + +/* field: TX_EMPTY - Transmitter empty flag. */ +#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11) + +/* field: TXWAKE - Transmitter wakeup method select. */ +#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10) + +/* field: RXRDY - Receiver ready flag. */ +#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9) + +/* field: TXRDY - Transmitter buffer register ready flag. */ +#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8) + +/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */ +#define TMS570_SCI_FLR_BUSY BSP_BIT32(3) + +/* field: IDLE - SCI receiver in idle state. */ +#define TMS570_SCI_FLR_IDLE BSP_BIT32(2) + +/* field: WAKEUP - Wakeup flag. */ +#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1) + +/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */ +#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0) + + +/*--------------------TMS570_SCI_INTVECT0--------------------*/ +/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */ +#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) +#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SCI_INTVECT1--------------------*/ +/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */ +#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) +#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SCI_FORMAT---------------------*/ +/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */ +#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) +#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*-----------------------TMS570_SCI_BRS-----------------------*/ +/* field: BAUD - SCI 24-bit baud selection. */ +#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23) +#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) +#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) + + +/*-----------------------TMS570_SCI_ED-----------------------*/ +/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */ +#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SCI_RD-----------------------*/ +/* field: RD - Receiver data. */ +#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SCI_TD-----------------------*/ +/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */ +#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7) +#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SCI_PIO0----------------------*/ +/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */ +#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2) + +/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */ +#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO1----------------------*/ +/* field: TX_DIR - Transmit pin direction. */ +#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2) + +/* field: RX_DIR - Receive pin direction. */ +#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO2----------------------*/ +/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */ +#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2) + +/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */ +#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO3----------------------*/ +/* field: TX_OUT - Transmit pin out. */ +#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2) + +/* field: RX_OUT - Receive pin out. */ +#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO4----------------------*/ +/* field: TX_SET - Transmit pin set. */ +#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2) + +/* field: RX_SET - Receive pin set. */ +#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO5----------------------*/ +/* field: TX_CLR - Transmit pin clear. */ +#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2) + +/* field: RX_CLR - Receive pin clear. */ +#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO6----------------------*/ +/* field: TX_PDR - Transmit pin open drain enable. */ +#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2) + +/* field: RX_PDR - Receive pin open drain enable. */ +#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO7----------------------*/ +/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */ +#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2) + +/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */ +#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1) + + +/*----------------------TMS570_SCI_PIO8----------------------*/ +/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */ +#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2) + +/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */ +#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1) + + +/*--------------------TMS570_SCI_IODFTCTRL--------------------*/ +/* field: FEN - Frame error enable. This bit is used to create a frame error. */ +#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26) + +/* field: PEN - Parity error enable. This bit is used to create a parity error. */ +#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25) + +/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */ +#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24) + +/* field: PIN_SAMPLE_MASK - Pin sample mask. */ +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) +#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20) + +/* field: TX_SHIFT - Transmit shift. */ +#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) +#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) +#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18) + +/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */ +#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */ +#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1) + +/* field: RXPENA - Module analog loopback through receive pin enable. */ +#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_SCI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h new file mode 100644 index 0000000000..35335c61e0 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h @@ -0,0 +1,918 @@ +/* The header file is generated by make_header.py from SPI.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SPI +#define LIBBSP_ARM_TMS570_SPI + +#include + +typedef struct{ + uint32_t GCR0; /*SPI Global Control Register 0*/ + uint32_t GCR1; /*SPI Global Control Register 1*/ + uint32_t INT0; /*SPI Interrupt Register*/ + uint32_t LVL; /*SPI Interrupt Level Register*/ + uint32_t FLG; /*SPI Flag Register*/ + uint32_t PC0; /*SPI Pin Control Register 0*/ + uint32_t PC1; /*SPI Pin Control Register 1*/ + uint32_t PC2; /*SPI Pin Control Register 2*/ + uint32_t PC3; /*SPI Pin Control Register 3*/ + uint32_t PC4; /*SPI Pin Control Register 4*/ + uint32_t PC5; /*SPI Pin Control Register 5*/ + uint32_t PC6; /*SPI Pin Control Register 6*/ + uint32_t PC7; /*SPI Pin Control Register 7*/ + uint32_t PC8; /*SPI Pin Control Register 8*/ + uint32_t DAT0; /*SPI Transmit Data Register 0*/ + uint32_t DAT1; /*SPI Transmit Data Register 1*/ + uint32_t BUF; /*SPI Receive Buffer Register*/ + uint32_t EMU; /*SPI Emulation Register*/ + uint32_t DELAY; /*SPI Delay Register*/ + uint32_t DEF; /*SPI Default Chip Select Register*/ + uint32_t FMT0; /*SPI Data Format Register 0*/ + uint32_t FMT1; /*SPI Data Format Register 1*/ + uint32_t FMT2; /*SPI Data Format Register 2*/ + uint32_t FMT3; /*SPI Data Format Register 3*/ + uint32_t INTVECT0; /*Interrupt Vector 0*/ + uint32_t INTVECT1; /*Interrupt Vector 1*/ + uint8_t reserved1 [4]; + uint32_t PMCTRL; /*Parallel/Modulo Mode Control Register*/ + uint32_t MIBSPIE; /*Multi-buffer Mode Enable Register*/ + uint32_t TGITENST; /*TG Interrupt Enable Set Register*/ + uint32_t TGITENCR; /*TG Interrupt Enable Clear Register*/ + uint32_t TGITLVST; /*Transfer Group Interrupt Level Set Register*/ + uint32_t TGITLVCR; /*Transfer Group Interrupt Level Clear Register*/ + uint32_t TGINTFLG; /*Transfer Group Interrupt Flag Register*/ + uint8_t reserved2 [8]; + uint32_t TICKCNT; /*Tick Count Register*/ + uint32_t LTGPEND; /*Last TG End Pointer*/ + uint32_t TGCTRL[16]; /*TG Control Registers*/ + uint32_t DMACTRL[8]; /*DMA Channel Control Register*/ + uint32_t DMACOUNT[8]; /*DMA COUNT Register*/ + uint32_t DMACNTLEN; /*DMA Large Count*/ + uint8_t reserved3 [4]; + uint32_t UERRCTRL; /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/ + uint32_t UERRSTAT; /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/ + uint32_t UERRADDRRX; /*RXRAM Uncorrectable Parity Error Address Register*/ + uint32_t UERRADDRTX; /*TXRAM Uncorrectable Parity Error Address Register*/ + uint32_t RXOVRN_BUF_ADDR; /*RXRAM Overrun Buffer Address Register*/ + uint32_t IOLPBKTSTCR; /*I/O Loopback Test Control Register*/ + uint32_t EXT_PRESCALE1; /*SPI Extended Prescale Register 1*/ + uint32_t EXT_PRESCALE2; /*SPI Extended Prescale Register 2*/ +} tms570_spi_t; + + +/*----------------------TMS570_SPI_GCR0----------------------*/ +/* field: nRESET - This is the local reset control for the module. */ +#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0) + + +/*----------------------TMS570_SPI_GCR1----------------------*/ +/* field: SPIEN - SPI enable. This bit enables SPI transfers. */ +#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24) + +/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */ +#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16) + +/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */ +#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8) + +/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */ +#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1) + +/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */ +#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0) + + +/*----------------------TMS570_SPI_INT0----------------------*/ +/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */ +#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24) + +/* field: DMAREQEN - DMA request enable. */ +#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16) + + +/*-----------------------TMS570_SPI_LVL-----------------------*/ +/* field: TXINTLVL - Transmit interrupt level. */ +#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9) + +/* field: RXINTLVL - Receive interrupt level. */ +#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8) + +/* field: RXOVRNINTLVL - Receive overrun interrupt level. */ +#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6) + +/* field: BITERRLVL - Bit error interrupt level. */ +#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4) + +/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */ +#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3) + +/* field: PARERRLVL - Parity error interrupt level. */ +#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2) + +/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */ +#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1) + +/* field: DLENERRLVL - Data length error interrupt level (line) select. */ +#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0) + + +/*-----------------------TMS570_SPI_FLG-----------------------*/ +/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */ +#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24) + +/* field: TXINTFLG - Transmitter-empty interrupt flag. */ +#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9) + +/* field: RXINTFLG - Receiver-full interrupt flag. */ +#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8) + +/* field: RXOVRNINTFLG - Receiver overrun flag. */ +#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6) + +/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */ +#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4) + +/* field: DESYNCFLG - Desynchronization of slave device. */ +#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3) + +/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */ +#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2) + +/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */ +#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1) + +/* field: DLENERRFLG - Data-length error flag. */ +#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0) + + +/*-----------------------TMS570_SPI_PC0-----------------------*/ +/* field: SOMIFUN - Slave out, master in function. */ +#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOFUN - Slave in, master out function. */ +#define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIFUN0 - SOMIFUN0 */ +#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11) + +/* field: SIMOFUN0 - Slave in, master out function. */ +#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10) + +/* field: CLKFUN - CLKFUN */ +#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9) + +/* field: ENAFUN - SPIENA function. */ +#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8) + +/* field: SCSFUN - SPISCSx function. */ +#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC1-----------------------*/ +/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */ +#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */ +#define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDIR0 - PISOMI0 direction. */ +#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11) + +/* field: SIMODIR0 - SPISIMO0 direction. */ +#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10) + +/* field: CLKDIR - SPICLK direction. */ +#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9) + +/* field: ENADIR - SPIENA direction. */ +#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8) + +/* field: SCSDIR - SPISCSx direction. */ +#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC2-----------------------*/ +/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */ +#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */ +#define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */ +#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11) + +/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */ +#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10) + +/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */ +#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9) + +/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */ +#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8) + +/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */ +#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC3-----------------------*/ +/* field: SOMIDOUT - SPISOMIx data out write. */ +#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODOUT - SPISIMOx data out write. */ +#define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIDOUT0 - SPISOMI0 data out write. */ +#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11) + +/* field: SIMODOUT0 - SPISIMO0 data out write. */ +#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10) + +/* field: CLKDOUT - SPICLK data out write. */ +#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9) + +/* field: ENADOUT - SPIENA data out write. */ +#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8) + +/* field: SCSDOUT - SPISCSx data out write. */ +#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC4-----------------------*/ +/* field: SOMISET - SPISOMIx data out set. */ +#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOSET - SPISIMOx data out set. */ +#define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMISET0 - SPISOMI0 data out set. */ +#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11) + +/* field: SIMOSET0 - purpose */ +#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10) + +/* field: CLKSET - SPICLK data out set. */ +#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9) + +/* field: ENASET - SPIENA data out set. */ +#define TMS570_SPI_PC4_ENASET BSP_BIT32(8) + +/* field: SCSSET - SPISCSx data out set. */ +#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC5-----------------------*/ +/* field: SOMICLR - SPISOMIx data out clear. */ +#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOCLR - SPISIMOx data out clear. */ +#define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMICLR0 - SPISOMI0 data out cleart. */ +#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11) + +/* field: SIMOCLR0 - SPISIMO0 data out clear. */ +#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10) + +/* field: CLKCLR - SPICLK data out clear. */ +#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9) + +/* field: ENACLR - SPIENA data out clear. */ +#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8) + +/* field: SCSCLR - SPISCSx data out clear. */ +#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC6-----------------------*/ +/* field: SOMIPDR - SPISOMIx open drain enable. */ +#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOPDR - SPISIMOx open drain enable. */ +#define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPDR0 - SOMI0 open-drain enable. */ +#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11) + +/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */ +#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10) + +/* field: CLKPDR - CLK open drain enable. */ +#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9) + +/* field: ENAPDR - SPIENA pin open drain enable. */ +#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8) + +/* field: SCSPDR - SPISCSx open drain enable. */ +#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC7-----------------------*/ +/* field: SOMIDIS - SOMIx pull control enable/disable. */ +#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMODIS - SIMOx pull control enable/disable. */ +#define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */ +#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11) + +/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */ +#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10) + +/* field: CLKPDIS - CLK pull control enable/disable. */ +#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9) + +/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */ +#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8) + +/* field: SCSPDIS - SCSx pull control enable/disable. */ +#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_PC8-----------------------*/ +/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */ +#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */ +#define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */ +#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11) + +/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */ +#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10) + +/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */ +#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9) + +/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */ +#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8) + +/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */ +#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SPI_DAT0----------------------*/ +/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */ +#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_SPI_DAT1----------------------*/ +/* field: CSHOLD - Chip select hold mode. */ +#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28) + +/* field: WDEL - Enable the delay counter at the end of the current transaction. */ +#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26) + +/* field: DFSEL - Data word format select */ +#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25) +#define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */ +#define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */ +#define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_SPI_BUF-----------------------*/ +/* field: RXEMPTY - Receive data buffer empty. */ +#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31) + +/* field: RXOVR - Receive data buffer overrun. */ +#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30) + +/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */ +#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29) + +/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */ +#define TMS570_SPI_BUF_BITERR BSP_BIT32(28) + +/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */ +#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27) + +/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */ +#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26) + +/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */ +#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25) + +/* field: DLENERR - Data length error flag. */ +#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24) + +/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */ +#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: RXDATA - SPI receive data. */ +#define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-----------------------TMS570_SPI_EMU-----------------------*/ +/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */ +#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*----------------------TMS570_SPI_DELAY----------------------*/ +/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */ +#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: T2CDELAY - T2CDELAY */ +#define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23) +#define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23) +#define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23) + +/* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */ +#define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15) +#define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */ +#define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*-----------------------TMS570_SPI_DEF-----------------------*/ +/* field: CDEF - Chip select default pattern. Master-mode only. */ +#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7) +#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SPI_FMTx----------------------*/ +/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */ +#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31) +#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31) +#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31) + +/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */ +#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23) + +/* field: PARITYENA - Parity enable for data format x. */ +#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22) + +/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */ +#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21) + +/* field: SHIFTDIR - Shift direction for data format x. */ +#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20) + +/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */ +#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19) + +/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */ +#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18) + +/* field: POLARITY - POLARITY */ +#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17) + +/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */ +#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16) + +/* field: PRESCALE - SPI data format x prescaler. */ +#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15) +#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */ +#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4) +#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_SPI_INTVECT0--------------------*/ +/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */ +#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5) +#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5) +#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5) + +/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */ +#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0) + + +/*--------------------TMS570_SPI_INTVECT1--------------------*/ +/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */ +#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5) +#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5) +#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5) + +/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */ +#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0) + + +/*---------------------TMS570_SPI_PMCTRL---------------------*/ +/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29) + +/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28) +#define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28) +#define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28) + +/* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25) +#define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25) +#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25) + +/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21) + +/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20) +#define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20) +#define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20) + +/* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17) +#define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17) +#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17) + +/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13) + +/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12) +#define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12) +#define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12) + +/* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9) +#define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */ +#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5) + +/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */ +#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4) +#define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4) +#define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4) + +/* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */ +#define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1) +#define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SPI_MIBSPIE---------------------*/ +/* field: RXRAM_ACCESS - Receive-RAM access control. */ +#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16) + +/* field: MSPIENA - Multi-buffer mode enable. */ +#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0) + + +/*--------------------TMS570_SPI_TGITENST--------------------*/ +/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */ +#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */ +#define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITENCR--------------------*/ +/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */ +#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: CLR_INTENSUS - CLR INTENSUS */ +#define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITLVST--------------------*/ +/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */ +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */ +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGITLVCR--------------------*/ +/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */ +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */ +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_TGINTFLG--------------------*/ +/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */ +#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */ +#define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SPI_TICKCNT---------------------*/ +/* field: TICKENA - Tick counter enable. */ +#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31) + +/* field: RELOAD - Pre-load the tick counter. */ +#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30) + +/* field: CLKCTRL - Tick counter clock source control. */ +#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29) +#define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29) +#define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29) + +/* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */ +#define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SPI_LTGPEND---------------------*/ +/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */ +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28) +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: LPEND - Last TG end pointer. */ +#define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14) +#define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + + +/*---------------------TMS570_SPI_TGCTRL---------------------*/ +/* field: TGENA - TGx enable. */ +#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31) + +/* field: ONESHOTx - Single transfer for TGx. */ +#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30) + +/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */ +#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29) + +/* field: TGTDx - TG triggered. */ +#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28) + + +/*---------------------TMS570_SPI_DMACTRL---------------------*/ +/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */ +#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31) + +/* field: BUFIDx - Buffer utilized for DMA transfer. */ +#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30) +#define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30) +#define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30) + +/* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */ +#define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23) +#define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23) +#define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23) + +/* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */ +#define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19) +#define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: RXDMAENAx - Receive data DMA channel enable. */ +#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15) + +/* field: TXDAMENAx - Transmit data DMA channel enable. */ +#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14) + +/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */ +#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13) + +/* field: ICOUNTx - Initial count of DMA transfers. */ +#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12) +#define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + +/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */ +#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6) + +/* field: COUNTx - Actual number of remaining DMA transfers. */ +#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5) +#define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*--------------------TMS570_SPI_DMACOUNT--------------------*/ +/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */ +#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31) +#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: COUNTx - The actual number of remaining DMA transfers. */ +#define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15) +#define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SPI_DMACNTLEN--------------------*/ +/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */ +#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0) + + +/*--------------------TMS570_SPI_UERRCTRL--------------------*/ +/* field: PTESTEN - Parity memory test enable. */ +#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8) + +/* field: EDEN - Error detection enable. These bits enable parity error detection. */ +#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3) +#define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SPI_UERRSTAT--------------------*/ +/* field: EDFLG1 - RXRAM. */ +#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1) + +/* field: EDFLG0 - Uncorrectable parity error detection flag. */ +#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0) + + +/*-------------------TMS570_SPI_UERRADDRRX-------------------*/ +/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */ +#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9) +#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_SPI_UERRADDRTX-------------------*/ +/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */ +#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8) +#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/ +/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */ +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9) +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9) +#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9) + + +/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/ +/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */ +#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24) + +/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20) + +/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19) + +/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18) + +/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17) + +/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16) + +/* field: IOLPBKSTENA - Module I/O loopback test enable key. */ +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11) +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */ +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5) +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5) +#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5) + +/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */ +#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2) + +/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */ +#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1) + +/* field: RXP_ENA - Enable analog loopback through the receive pin. */ +#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0) + + +/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/ +/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */ +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26) +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26) +#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26) + + + +#endif /* LIBBSP_ARM_TMS570_SPI */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h new file mode 100644 index 0000000000..e935f450b8 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h @@ -0,0 +1,158 @@ +/* The header file is generated by make_header.py from STC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_STC +#define LIBBSP_ARM_TMS570_STC + +#include + +typedef struct{ + uint32_t STCGCR0; /*STC Global Control Register 0*/ + uint32_t STCGCR1; /*STCGlobal Control Register 1*/ + uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/ + uint32_t STC_CADDR; /*STC Current ROM Address Register*/ + uint32_t STCCICR; /*STC Current Interval Count Register*/ + uint32_t STCGSTAT; /*Self-Test Global Status Register*/ + uint32_t STCFSTAT; /*Self-Test Fail Status Register*/ + uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/ + uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/ + uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/ + uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/ + uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/ + uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/ + uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/ + uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/ + uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/ +} tms570_stc_t; + + +/*---------------------TMS570_STC_STCGCR0---------------------*/ +/* field: INTCOUNT - Number of intervals of self-test run */ +#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31) +#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31) +#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31) + +/* field: RS_CNT - Restart or Continue */ +#define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0) + + +/*---------------------TMS570_STC_STCGCR1---------------------*/ +/* field: STC_ENA - Self-test run enable key */ +#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3) +#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_STC_STCTPR---------------------*/ +/* field: RTOD - Self-test timeout count preload */ +/* Whole 32 bits */ + +/*--------------------TMS570_STC_STC_CADDR--------------------*/ +/* field: ADDR - Current ROM Address */ +/* Whole 32 bits */ + +/*---------------------TMS570_STC_STCCICR---------------------*/ +/* field: N - Interval Number */ +#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15) +#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_STC_STCGSTAT--------------------*/ +/* field: TEST_FAIL - Test Fail */ +#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1) + +/* field: TEST_DONE - Test Done */ +#define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0) + + +/*--------------------TMS570_STC_STCFSTAT--------------------*/ +/* field: TO_ERR - Timeout Error */ +#define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2) + +/* field: CPU2_FAIL - CPU2 failure info */ +#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1) + +/* field: CPU1_FAIL - CPU1 failure info */ +#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0) + + +/*------------------TMS570_STC_CPU1_CURMISR3------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR2------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR1------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU1_CURMISR0------------------*/ +/* field: MISR - MISR data from CPU1 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR3------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR2------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR1------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*------------------TMS570_STC_CPU2_CURMISR0------------------*/ +/* field: MISR - MISR data from CPU2 */ +/* Whole 32 bits */ + +/*--------------------TMS570_STC_STCSCSCR--------------------*/ +/* field: FAULT_INS - Enable / Disable fault insertion. */ +#define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4) + +/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */ +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_STC */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h new file mode 100644 index 0000000000..e191970ad6 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h @@ -0,0 +1,695 @@ +/* The header file is generated by make_header.py from SYS.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SYS1 +#define LIBBSP_ARM_TMS570_SYS1 + +#include + +typedef struct{ + uint32_t SYSPC1; /*SYS Pin Control Register 1*/ + uint32_t SYSPC2; /*SYS Pin Control Register 2*/ + uint32_t SYSPC3; /*SYS Pin Control Register 3*/ + uint32_t SYSPC4; /*SYS Pin Control Register 4*/ + uint32_t SYSPC5; /*SYS Pin Control Register 5*/ + uint32_t SYSPC6; /*SYS Pin Control Register 6*/ + uint32_t SYSPC7; /*SYS Pin Control Register 7*/ + uint32_t SYSPC8; /*SYS Pin Control Register 8*/ + uint32_t SYSPC9; /*SYS Pin Control Register 9*/ + uint8_t reserved1 [12]; + uint32_t CSDIS; /*Clock Source Disable Register*/ + uint32_t CSDISSET; /*Clock Source Disable Set Register*/ + uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/ + uint32_t CDDIS; /*Clock Domain Disable Register*/ + uint32_t CDDISSET; /*Clock Domain Disable Set Register*/ + uint32_t CDDISCLR; /*Clock Domain Disable Clear Register*/ + uint32_t GHVSRC; /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/ + uint32_t VCLKASRC; /*Peripheral Asynchronous Clock Source Register*/ + uint32_t RCLKSRC; /*RTI Clock Source Register*/ + uint32_t CSVSTAT; /*Clock Source Valid Status Register*/ + uint32_t MSTGCR; /*Memory Self-Test Global Control Register*/ + uint32_t MINITGCR; /*Memory Hardware Initialization Global Control Register*/ + uint32_t MSIENA; /*Memory Self-Test/Initialization Enable Register*/ + uint8_t reserved2 [4]; + uint32_t MSTCGSTAT; /*MSTC Global Status Register*/ + uint32_t MINISTAT; /*Memory Hardware Initialization Status Register*/ + uint32_t PLLCTL1; /*PLL Control Register 1*/ + uint32_t PLLCTL2; /*PLL Control Register 2*/ + uint32_t SYSPC10; /*SYS Pin Control Register 10*/ + uint32_t DIEIDL; /*Die Identification Register, Lower Word*/ + uint32_t DIEIDH; /*Die Identification Register, Upper Word*/ + uint8_t reserved3 [4]; + uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/ + uint32_t CLKTEST; /*Clock Test Register*/ + uint32_t DFTCTRLREG1; /*DFT Control Register*/ + uint32_t DFTCTRLREG2; /*DFT Control Register 2*/ + uint8_t reserved4 [8]; + uint32_t GPREG1; /*General Purpose Register*/ + uint8_t reserved5 [4]; + uint32_t IMPFASTS; /*Imprecise Fault Status Register*/ + uint32_t IMPFTADD; /*Imprecise Fault Write Address Register*/ + uint32_t SSIR1; /*System Software Interrupt Request 1 Register*/ + uint32_t SSIR2; /*System Software Interrupt Request 2 Register*/ + uint32_t SSIR3; /*System Software Interrupt Request 3 Register*/ + uint32_t SSIR4; /*System Software Interrupt Request 4 Register*/ + uint32_t RAMGCR; /*RAM Control Register*/ + uint32_t BMMCR1; /*Bus Matrix Module Control Register 1*/ + uint8_t reserved6 [4]; + uint32_t CPURSTCR; /*CPU Reset Control Register*/ + uint32_t CLKCNTL; /*Clock Control Register*/ + uint32_t ECPCNTL; /*ECP Control Register*/ + uint8_t reserved7 [4]; + uint32_t DEVCR1; /*DEV Parity Control Register 1*/ + uint32_t SYSECR; /*System Exception Control Register*/ + uint32_t SYSESR; /*System Exception Status Register*/ + uint32_t SYSTASR; /*System Test Abort Status Register*/ + uint32_t GLBSTAT; /*Global Status Register*/ + uint32_t DEVID; /*Device Identification Register*/ + uint32_t SSIVEC; /*Software Interrupt Vector Register*/ + uint32_t SSIF; /*System Software Interrupt Flag Register*/ +} tms570_sys1_t; + + +/*---------------------TMS570_SYS1_SYSPCx---------------------*/ +/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ +#define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_CSDIS---------------------*/ +/* field: CLKSROFF - Clock source[7-3] off. */ +#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSROFF - Clock source[1-0] off. */ +#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_SYS1_CSDISSET--------------------*/ +/* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */ +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: SETCLKSR_OFF - Set clock source[1-0] to the disabled state. */ +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_SYS1_CSDISCLR--------------------*/ +/* field: CLRCLKSR_OFF - Enables clock source[7-3]. */ +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLRCLKSR_OFF - Enables clock source[1-0]. */ +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SYS1_CDDIS---------------------*/ +/* field: VCLKAOFF - VCLKA[4-3] domain off. */ +#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: VCLK3OFF - VCLK3 domain off. */ +#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8) + +/* field: RTICLK1OFF - RTICLK1 domain off. */ +#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6) + +/* field: VCLKAOFF - VCLKA[2-1] domain off. */ +#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5) +#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,4, 5) +#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5) + +/* field: VCLK2OFF - VCLK2 domain off. */ +#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3) + +/* field: VCLKPOFF - VCLK_periph domain off. */ +#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2) + +/* field: HCLKOFF - HCLK and VCLK_sys domains off. */ +#define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1) + +/* field: GCLKOFF - GCLK domain off. */ +#define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CDDISSET--------------------*/ +/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: SETVCLK3OFF - Set VCLK3 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8) + +/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */ +#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6) + +/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */ +#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5) + +/* field: SETVCLKA1OFF - Set VCLKA1 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4) + +/* field: SETVCLK2OFF - Set VCLK2 domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3) + +/* field: SETVCLKPOFF - Set VCLK_periph domain. */ +#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2) + +/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */ +#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1) + +/* field: SETGCLKOFF - Set GCLK domain. */ +#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CDDISCLR--------------------*/ +/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11) +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11) +#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11) + +/* field: Reserved - Reserved */ +#define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9) + +/* field: CLRVCLK3OFF - Clear VCLK3 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8) + +/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6) + +/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5) + +/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4) + +/* field: CLRVCLK2OFF - Clear VCLK2 domain. */ +#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3) + +/* field: CLRVCLKPOFF - CLRVCLKPOFF */ +#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2) + +/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */ +#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1) + +/* field: CLRGCLKOFF - Clear GCLK domain. */ +#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_GHVSRC---------------------*/ +/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */ +#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27) +#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */ +#define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */ +#define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_VCLKASRC--------------------*/ +/* field: VCLKA2S - Peripheral asynchronous clock2 source. */ +#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11) +#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: VCLKA1S - Peripheral asynchronous clock1 source. */ +#define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_RCLKSRC--------------------*/ +/* field: RTI1DIV - RTI clock1 Divider. */ +#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: RTI1SRC - RTI clock1 source. */ +#define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_CSVSTAT--------------------*/ +/* field: CLKSRV - Clock source[7-0] valid. */ +#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: CLKSR - Clock source[1-0] valid. */ +#define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1) +#define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*---------------------TMS570_SYS1_MSTGCR---------------------*/ +/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */ +#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: MSTGENA - Memory self-test controller global enable key */ +#define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_MINITGCR--------------------*/ +/* field: MINITGENA - Memory hardware initialization global enable key. */ +#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_MSIENA---------------------*/ +/* field: MSIENA - PBIST controller and memory initialization enable register. */ +/* Whole 32 bits */ + +/*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/ +/* field: MINIDONE - Memory hardware initialization complete status. */ +#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8) + +/* field: MSTDONE - Memory self-test run complete status. */ +#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_MINISTAT--------------------*/ +/* field: MIDONE - Memory hardware initialization status bit. */ +/* Whole 32 bits */ + +/*--------------------TMS570_SYS1_PLLCTL1--------------------*/ +/* field: ROS - Reset on PLL Slip */ +#define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31) + +/* field: MASK_SLIP - Mask detection of PLL slip */ +#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30) +#define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30) +#define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30) + +/* field: PLLDIV - PLL Output Clock Divider */ +#define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28) +#define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: ROF - Reset on Oscillator Fail */ +#define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23) + +/* field: REFCLKDIV - Reference Clock Divider */ +#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL - PLL Multiplication Factor */ +#define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SYS1_PLLCTL2--------------------*/ +/* field: FMENA - Frequency Modulation Enable. */ +#define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31) + +/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */ +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30) +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30) +#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30) + +/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */ +#define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20) +#define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20) +#define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20) + +/* field: ODPLL - Internal PLL Output Divider. */ +#define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11) +#define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11) +#define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) + +/* field: SPR_AMOUNT - Spreading Amount. */ +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8) +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8) +#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8) + + +/*--------------------TMS570_SYS1_SYSPC10--------------------*/ +/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */ +#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_DIEIDL---------------------*/ +/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */ +#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31) +#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31) +#define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31) + +/* field: WAFER - These read only bits contain the wafer number of the device. */ +#define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */ +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */ +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_SYS1_DIEIDH---------------------*/ +/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */ +#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13) +#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13) +#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13) + + +/*-------------------TMS570_SYS1_LPOMONCTL-------------------*/ +/* field: BIAS_ENABLE - Bias enable. */ +#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24) + +/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */ +#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16) + +/* field: HFTRIM - High frequency oscillator trim value. */ +#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12) +#define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12) +#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12) + + +/*--------------------TMS570_SYS1_CLKTEST--------------------*/ +/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */ +#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26) + +/* field: RANGEDETCTRL - Range detection control. */ +#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25) + +/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */ +#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24) + +/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */ +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */ +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11) +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11) +#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) + +/* field: SEL_ECP_PIN - ECLK pin clock source select */ +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_SYS1_DFTCTRLREG1------------------*/ +/* field: DFTWRITE - DFT logic access. */ +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13) +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13) +#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13) + +/* field: DFTREAD - DFT logic access. */ +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9) +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9) +#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) + +/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*------------------TMS570_SYS1_DFTCTRLREG2------------------*/ +/* field: IMPDF - DFT Implementation defined bits. */ +#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31) +#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31) +#define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31) + +/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */ +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_GPREG1---------------------*/ +/* field: EMIF_FUNC - Enable EMIF functions to be output. */ +#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31) + +/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */ +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25) +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25) +#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25) + +/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */ +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */ +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*--------------------TMS570_SYS1_IMPFASTS--------------------*/ +/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */ +#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_IMPFTADD--------------------*/ +/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */ +/* Whole 32 bits */ + +/*---------------------TMS570_SYS1_SSIRx---------------------*/ +/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */ +#define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */ +#define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_SYS1_RAMGCR---------------------*/ +/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */ +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */ +#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2) + +/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */ +#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_BMMCR1---------------------*/ +/* field: MEMSW - Memory swap key. */ +#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS1_CPURSTCR--------------------*/ +/* field: CPU_RESET - CPU Reset. */ +#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_CLKCNTL--------------------*/ +/* field: VCLK2R - VBUS clock2 ratio. */ +#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27) +#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: VCLKR - VBUS clock ratio. */ +#define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: PENA - Peripheral enable bit. */ +#define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8) + + +/*--------------------TMS570_SYS1_ECPCNTL--------------------*/ +/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ +#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24) + +/* field: ECPCOS - ECP continue on suspend. */ +#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23) + +/* field: ECPINSEL - Select ECP input clock source. */ +#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) +#define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) +#define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) + +/* field: ECPDIV - ECP divider value. */ +#define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*---------------------TMS570_SYS1_DEVCR1---------------------*/ +/* field: DEVPARSEL - Device parity select bit key. */ +#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_SYS1_SYSECR---------------------*/ +/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */ +#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15) +#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15) +#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15) + + +/*---------------------TMS570_SYS1_SYSESR---------------------*/ +/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */ +#define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15) + +/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */ +#define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14) + +/* field: WDRST - Watchdog reset flag. */ +#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13) + +/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */ +#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5) + +/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */ +#define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4) + +/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */ +#define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3) + +/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */ +#define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0) + + +/*--------------------TMS570_SYS1_SYSTASR--------------------*/ +/* field: EFUSE_Abort - Test Abort status flag. */ +#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4) +#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4) +#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) + + +/*--------------------TMS570_SYS1_GLBSTAT--------------------*/ +/* field: FBSLIP - PLL over cycle slip detection. */ +#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9) + +/* field: RFSLIP - PLL under cycle slip detection. */ +#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8) + +/* field: OSCFAIL - Oscillator fail flag bit. */ +#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0) + + +/*---------------------TMS570_SYS1_DEVID---------------------*/ +/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */ +#define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31) + +/* field: TECH - These bits define the process technology by which the device was manufactured. */ +#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16) +#define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16) +#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16) + +/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */ +#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12) + +/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */ +#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11) + +/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */ +#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10) +#define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10) +#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10) + +/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */ +#define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8) + +/* field: VERSION - Version. These bits provide the revision of the device. */ +#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7) +#define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7) +#define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7) + +/* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */ +#define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2) +#define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2) +#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) + + +/*---------------------TMS570_SYS1_SSIVEC---------------------*/ +/* field: SSIDATA - System software interrupt data key. */ +#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15) +#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15) +#define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15) + +/* field: SSIVECT - These bits contain the source for the system software interrupt. */ +#define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7) +#define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*----------------------TMS570_SYS1_SSIF----------------------*/ +/* field: SSI_FLAG - System software interrupt flag[4-1]. */ +#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + + +#endif /* LIBBSP_ARM_TMS570_SYS1 */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h new file mode 100644 index 0000000000..29ec5a141c --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from SYS2.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_SYS2 +#define LIBBSP_ARM_TMS570_SYS2 + +#include + +typedef struct{ + uint32_t PLLCTL3; /*PLL Control Register 3*/ + uint8_t reserved1 [4]; + uint32_t STCCLKDIV; /*CPU Logic BIST Clock Divider*/ + uint8_t reserved2 [24]; + uint32_t ECPCNTL; /*ECP Control Register*/ + uint8_t reserved3 [20]; + uint32_t CLK2CNTRL; /*Clock 2 Control Register*/ + uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/ + uint8_t reserved4 [44]; + uint32_t CLKSLIP; /*Clock Slip Register*/ + uint8_t reserved5 [120]; + uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/ + uint32_t DIEDL_REG0; /*Die Identification Register*/ + uint32_t DIEDH_REG1; /*Die Identification Register*/ + uint32_t DIEDL_REG2; /*Die Identification Register*/ + uint32_t DIEDH_REG3; /*Die Identification Register*/ +} tms570_sys2_t; + + +/*--------------------TMS570_SYS2_PLLCTL3--------------------*/ +/* field: ODPLL2 - Internal PLL Output Divider */ +#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31) +#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31) +#define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31) + +/* field: PLLDIV2 - PLL2 Output Clock Divider */ +#define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28) +#define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28) +#define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) + +/* field: REFCLKDIV2 - REFCLKDIV2 */ +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21) +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21) +#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21) + +/* field: PLLMUL2 - PLL2 Multiplication Factor */ +#define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_SYS2_STCCLKDIV-------------------*/ +/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */ +#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26) +#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + + +/*--------------------TMS570_SYS2_ECPCNTL--------------------*/ +/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */ +#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_BIT32(24) + +/* field: ECPCOS - ECP continue on suspend. */ +#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_BIT32(23) + +/* field: ECPINSEL - Select ECP input clock source. */ +#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17) +#define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17) +#define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17) + +/* field: ECPDIV - ECP divider value. */ +#define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15) +#define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_SYS2_CLK2CNTRL-------------------*/ +/* field: VCLK3R - VBUS clock3 ratio. */ +#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_SYS2_VCLKACON1-------------------*/ +/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26) +#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26) +#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26) + +/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_BIT32(20) + +/* field: VCLKA4S - Peripheral asynchronous clock4 source. */ +#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19) +#define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10) +#define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10) +#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10) + +/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_BIT32(4) + +/* field: VCLKA3S - Peripheral asynchronous clock3 source. */ +#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*--------------------TMS570_SYS2_CLKSLIP--------------------*/ +/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */ +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13) + +/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */ +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-------------------TMS570_SYS2_EFC_CTLREG-------------------*/ +/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */ +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3) +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------------TMS570_SYS2_x-----------------------*/ +/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */ +/* Whole 32 bits */ + + +#endif /* LIBBSP_ARM_TMS570_SYS2 */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h new file mode 100644 index 0000000000..5304504afc --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h @@ -0,0 +1,84 @@ +/* The header file is generated by make_header.py from TCR.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_TCR +#define LIBBSP_ARM_TMS570_TCR + +#include + +typedef struct{ + uint32_t TCR[128]; /*Transfer Configuration RAM*/ + uint32_t TCR_Parity[128]; /*TCR Parity Test Mode*/ +} tms570_tcr_t; + + +/*-----------------------TMS570_TCR_TCR-----------------------*/ +/* field: STXR - Set Transmit Request. */ +#define TMS570_TCR_TCR_STXR BSP_BIT32(18) + +/* field: THTSM - Transfer Header to System Memory. */ +#define TMS570_TCR_TCR_THTSM BSP_BIT32(17) + +/* field: TPTSM - Transfer Payload to System Memory. */ +#define TMS570_TCR_TCR_TPTSM BSP_BIT32(16) + +/* field: THTCC - Transfer Header to Communication Controller. */ +#define TMS570_TCR_TCR_THTCC BSP_BIT32(15) + +/* field: TPTCC - Transfer Payload to Communication Controller. */ +#define TMS570_TCR_TCR_TPTCC BSP_BIT32(14) + +/* field: TSO - Transfer Start Offset. */ +#define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13) +#define TMS570_TCR_TCR_TSO_GET(reg) BSP_FLD32GET(reg,0, 13) +#define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13) + + +/*-------------------TMS570_TCR_TCR_Parity-------------------*/ +/* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */ +#define TMS570_TCR_TCR_Parity_PAB2 BSP_BIT32(16) + +/* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */ +#define TMS570_TCR_TCR_Parity_PAB1 BSP_BIT32(8) + +/* field: PAB0 - Parity Bit for Byte 0. */ +#define TMS570_TCR_TCR_Parity_PAB0 BSP_BIT32(0) + + + +#endif /* LIBBSP_ARM_TMS570_TCR */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h new file mode 100644 index 0000000000..1a48848e76 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h @@ -0,0 +1,170 @@ +/* The header file is generated by make_header.py from TCRAM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_TCRAM +#define LIBBSP_ARM_TMS570_TCRAM + +#include + +typedef struct{ + uint32_t RAMCTRL; /*TCRAM Module Control Register*/ + uint32_t RAMTHRESHOLD; /*TCRAM Module Single-Bit Error Correction Threshold Register*/ + uint32_t RAMOCCUR; /*TCRAM Module Single-Bit Error Occurrences Control Register*/ + uint32_t RAMINTCTRL; /*TCRAM Module Interrupt Control Register*/ + uint32_t RAMERRSTATUS; /*TCRAM Module Error Status Register*/ + uint32_t RAMSERRADDR; /*TCRAM Module Single-Bit Error Address Register*/ + uint8_t reserved1 [4]; + uint32_t RAMUERRADDR; /*TCRAM Module Uncorrectable Error Address Register*/ + uint8_t reserved2 [16]; + uint32_t RAMTEST; /*TCRAM Module Test Mode Control Register*/ + uint8_t reserved3 [4]; + uint32_t RAMADDRDECVECT; /*TCRAM Module Test Mode Vector Register*/ + uint32_t RAMPERADDR; /*TCRAM Module Parity Error Address Register*/ +} tms570_tcram_t; + + +/*--------------------TMS570_TCRAM_RAMCTRL--------------------*/ +/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */ +#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30) + +/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */ +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) + +/* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */ +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19) +#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) + +/* field: ECC_WR_EN - ECC Memory Write Enable. */ +#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8) + +/* field: ECC_DETECT_EN - ECC Detect Enable. */ +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3) +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/ +/* field: THRESHOLD - Single-bit Error Threshold Count. */ +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/ +/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */ +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_TCRAM_RAMINTCTRL------------------*/ +/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */ +#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0) + + +/*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/ +/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */ +#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9) + +/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */ +#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8) + +/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */ +#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5) + +/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */ +#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4) + +/* field: ADDR_DEC_FAIL - Address decode failed. */ +#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2) + +/* field: SERR - Single Error Status. */ +#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0) + + +/*------------------TMS570_TCRAM_RAMSERRADDR------------------*/ +/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */ +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17) +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17) +#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17) + + +/*------------------TMS570_TCRAM_RAMUERRADDR------------------*/ +/* field: UNCORRECTABLE - address parity error. */ +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22) +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22) +#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) + + +/*--------------------TMS570_TCRAM_RAMTEST--------------------*/ +/* field: TRIGGER - Test Trigger. */ +#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8) + +/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */ +#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7) +#define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7) +#define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) + +/* field: TEST_ENABLE - Test Enable. */ +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3) +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/ +/* field: ECC_SELECT - ECC Select. */ +#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26) + +/* field: RAM_CHIP_SELECT - RAM Chip Select. */ +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15) +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15) +#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) + + +/*------------------TMS570_TCRAM_RAMPERADDR------------------*/ +/* field: ADDRESS_PARITY - Parity Error Address. */ +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22) +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22) +#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) + + + +#endif /* LIBBSP_ARM_TMS570_TCRAM */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h new file mode 100644 index 0000000000..d0347a4509 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h @@ -0,0 +1,190 @@ +/* The header file is generated by make_header.py from VIM.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_VIM +#define LIBBSP_ARM_TMS570_VIM + +#include + +typedef struct{ + uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/ + uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/ + uint32_t ADDERR; /*Address Parity Error Register*/ + uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/ + uint8_t reserved1 [4]; + uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/ + uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/ + uint8_t reserved2 [8]; + uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/ + uint8_t reserved3 [4]; + uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/ + uint8_t reserved4 [4]; + uint32_t REQENASET[3]; /*Interrupt Enable Set Register */ + uint8_t reserved5 [4]; + uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */ + uint8_t reserved6 [4]; + uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/ + uint8_t reserved7 [4]; + uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/ + uint8_t reserved8 [4]; + uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/ + uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/ + uint32_t CAPEVT; /*Capture Event Register*/ + uint8_t reserved9 [4]; + uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/ +} tms570_vim_t; + + +/*---------------------TMS570_VIM_PARFLG---------------------*/ +/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */ +#define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0) + + +/*---------------------TMS570_VIM_PARCTL---------------------*/ +/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */ +#define TMS570_VIM_PARCTL_TEST BSP_BIT32(8) + +/* field: PARENA - VIM parity enable. */ +#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3) +#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3) +#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) + + +/*---------------------TMS570_VIM_ADDERR---------------------*/ +/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */ +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31) +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31) +#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31) + +/* field: ADDERR - Address parity error register. */ +#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8) +#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8) +#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8) + +/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */ +#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1) +#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1) +#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) + + +/*--------------------TMS570_VIM_FBPARERR--------------------*/ +/* field: FBPARERR - Fall back address parity error. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_IRQINDEX--------------------*/ +/* field: IRQINDEX - IRQ index vector. */ +#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7) +#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*--------------------TMS570_VIM_FIQINDEX--------------------*/ +/* field: FIQINDEX - FIQ index offset vector. */ +#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7) +#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7) +#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) + + +/*---------------------TMS570_VIM_FIRQPR---------------------*/ +/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*---------------------TMS570_VIM_INTREQ---------------------*/ +/* field: INTREQx - Pending interrupt bits. 96 bit register. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_REQENASET--------------------*/ +/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_REQENACLR--------------------*/ +/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */ +/* Whole 32 bits */ + +/*-------------------TMS570_VIM_WAKEENASET-------------------*/ +/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */ +/* Whole 32 bits */ + +/*-------------------TMS570_VIM_WAKEENACLR-------------------*/ +/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_IRQVECREG--------------------*/ +/* field: IRQVECREG - IRQ interrupt vector register. */ +/* Whole 32 bits */ + +/*--------------------TMS570_VIM_FIQVECREG--------------------*/ +/* field: FIQVECREG - FIQ interrupt vector register. */ +/* Whole 32 bits */ + +/*---------------------TMS570_VIM_CAPEVT---------------------*/ +/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */ +#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22) +#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22) +#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) + +/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */ +#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6) +#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + +/*--------------------TMS570_VIM_CHANCTRL--------------------*/ +/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30) +#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30) +#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30) + +/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22) +#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22) +#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22) + +/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14) +#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14) +#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14) + +/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */ +#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6) +#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6) +#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6) + + + +#endif /* LIBBSP_ARM_TMS570_VIM */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pinmux.h b/bsps/arm/tms570/include/bsp/tms570-pinmux.h new file mode 100644 index 0000000000..8b93c66bfa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pinmux.h @@ -0,0 +1,137 @@ +/** + * @file tms570-pinmux.h + * + * @ingroup tms570 + * + * @brief I/O Multiplexing Module (IOMM) basic support + */ + +/* + * Copyright (c) 2015 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_PINMUX_H +#define LIBBSP_ARM_TMS570_PINMUX_H + +#ifndef ASM +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +#define TMS570_PIN_NUM_SHIFT 0 +#define TMS570_PIN_NUM_MASK 0x000007ff + +/* + * Request clear of interconnection in setup + * to ensure that previous peripheral to pin + * connection is not enabled in parallel to other one. + * Mask is ored with pin number in such list. + */ +#define TMS570_PIN_CLEAR_RQ_MASK 0x00000800 + +#define TMS570_PIN_FNC_SHIFT 12 +#define TMS570_PIN_FNC_MASK 0x0000f000 + +#define TMS570_PIN_NUM_FNC_MASK 0x0000ffff + +#define TMS570_PIN_IN_ALT_SHIFT 16 +#define TMS570_PIN_IN_ALT_MASK 0xffff0000 + +#define TMS570_PIN_FNC_AUTO (-1) + +#define TMS570_PIN_AND_FNC(pin, fnc) \ + ((pin) | ((fnc) << TMS570_PIN_FNC_SHIFT)) + +#define TMS570_PIN_WITH_IN_ALT(pin_num_and_fnc, pin_in_alt_num_and_fnc) \ + ((pin_num_and_fnc) | ((pin_in_alt_num_and_fnc) << TMS570_PIN_IN_ALT_SHIFT)) + +#define TMS570_BALL_WITH_MMR(mmrx, pos) \ + ((pos) | ((mmrx) << 2)) + +/* Generic functions select pin to peripheral connection */ + +void tms570_bsp_pin_set_function(int pin_num, int pin_fnc); + +void tms570_bsp_pin_clear_function(int pin_num, int pin_fnc); + +void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc); + +void tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_count); + +static inline void +tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift, + int pin_num) +{ + pin_num = (pin_num & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT; + *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2); + *pin_shift = (pin_num & 0x3)*8; +} + +#define TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) \ + (((((pin) & TMS570_PIN_NUM_MASK) >> 2 != (reg)) || ((pin) & TMS570_PIN_CLEAR_RQ_MASK))? 0: \ + 1 << ((((pin) & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT) + \ + ((pin) & 3) * 8) \ + ) + +#define TMS570_PINMMR_REG_VAL_ACTION(reg, pin) \ + TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) | \ + ((pin) & TMS570_PIN_IN_ALT_MASK? \ + TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, (pin) >> TMS570_PIN_IN_ALT_SHIFT ): \ + 0) | + +/** + * Macro which computes value for PINMMRx register from pin list + * which is defined as macro calling action macro for each pin + * + * @param reg PINMMR register number (0 .. 30 for TMS570LS3137) + * @param pin_list declared as macro with parameters + * \c per_pin_action and \c common_arg which expands + * to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function) + * + * @retval number which represents connections which should be enabled + * in given PINMMR register. Pin setup for other registers than specified + * are ignored + */ +#define TMS570_PINMMR_REG_VAL(reg, pin_list) \ + pin_list(TMS570_PINMMR_REG_VAL_ACTION, reg) 0 + +#define TMS570_PINMMR_COMA_LIST_ACTION(reg, pin) \ + (pin), + +/** + * Macro which generates list of pin and function specification from + * from pin list which is defined as macro calling action macro for each pin + * + * @param pin_list declared as macro with parameters + * \c per_pin_action and \c common_arg which expands + * to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function) + * + * @retval list of coma separated pin+function combined values which is terminated by coma + * at the end + */ +#define TMS570_PINMMR_COMA_LIST(pin_list) \ + pin_list(TMS570_PINMMR_COMA_LIST_ACTION, 0) + + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pins.h b/bsps/arm/tms570/include/bsp/tms570-pins.h new file mode 100644 index 0000000000..f8db69fa19 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pins.h @@ -0,0 +1,10 @@ +/** + * @file tms570-pins.h + * + * @ingroup tms570 + * + * @brief Select pin mapping according to selected chip. + * Defaults to TMS570LS3137ZWT for now. + */ + +#include diff --git a/bsps/arm/tms570/include/bsp/tms570-pom.h b/bsps/arm/tms570/include/bsp/tms570-pom.h new file mode 100644 index 0000000000..2c54a016dc --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-pom.h @@ -0,0 +1,60 @@ +/** + * @file tms570-pom.h + * @ingroup tms570 + * @brief Parameter Overlay Module (POM) header file + */ + +/* + * Copyright (c) 2014 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_POM_H +#define LIBBSP_ARM_TMS570_POM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TMS570_POM_REGIONS 32 +#define TMS570_POM_GLBCTRL_ENABLE 0x000000a0a + +/* Specification of memory size used for field REGSIZE of tms570_pom_region_t */ +#define TMS570_POM_REGSIZE_DISABLED 0x0 +#define TMS570_POM_REGSIZE_64B 0x1 +#define TMS570_POM_REGSIZE_128B 0x2 +#define TMS570_POM_REGSIZE_256B 0x3 +#define TMS570_POM_REGSIZE_512B 0x4 +#define TMS570_POM_REGSIZE_1KB 0x5 +#define TMS570_POM_REGSIZE_2KB 0x6 +#define TMS570_POM_REGSIZE_4KB 0x7 +#define TMS570_POM_REGSIZE_8KB 0x8 +#define TMS570_POM_REGSIZE_16KB 0x9 +#define TMS570_POM_REGSIZE_32KB 0xa +#define TMS570_POM_REGSIZE_64KB 0xb +#define TMS570_POM_REGSIZE_128KB 0xc +#define TMS570_POM_REGSIZE_256KB 0xd + +#define TMS570_POM_REGADDRMASK ((1<<23)-1) + +void tms570_initialize_and_clear(void); +void tms570_pom_remap(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_POM_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-rti.h b/bsps/arm/tms570/include/bsp/tms570-rti.h new file mode 100644 index 0000000000..552db88a62 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-rti.h @@ -0,0 +1,46 @@ +/** + * @file tms570-rti.h + * + * @ingroup tms570 + * + * @brief Real Time Interrupt module (RTI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_RTI_H +#define LIBBSP_ARM_TMS570_RTI_H + +#ifndef ASM + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-sci-driver.h b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h new file mode 100644 index 0000000000..61693ce0ff --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h @@ -0,0 +1,65 @@ +/** + * @file tms570-sci-driver.h + * + * @ingroup tms570 + * + * @brief Declaration of serial's driver inner structure. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef TMS570_SCI_DRIVER +#define TMS570_SCI_DRIVER + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Low-level driver specific data structure */ +typedef struct { + rtems_termios_device_context base; + const char *device_name; + volatile tms570_sci_t *regs; + int tx_chars_in_hw; + rtems_vector_number irq; +} tms570_sci_context; + +extern const rtems_termios_device_handler tms570_sci_handler_polled; + +extern const rtems_termios_device_handler tms570_sci_handler_interrupt; + +extern tms570_sci_context driver_context_table[]; + +void tms570_sci_initialize(tms570_sci_context *ctx); + +bool tms570_sci_set_attributes( + rtems_termios_device_context *base, + const struct termios *term +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* TMS570_SCI_DRIVER */ diff --git a/bsps/arm/tms570/include/bsp/tms570-sci.h b/bsps/arm/tms570/include/bsp/tms570-sci.h new file mode 100644 index 0000000000..9c502dcd6a --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-sci.h @@ -0,0 +1,45 @@ +/** + * @file tms570-sci.h + * + * @ingroup tms570 + * + * @brief Serial Communication Interface (SCI) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SCI_H +#define LIBBSP_ARM_TMS570_SCI_H + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/bsps/arm/tms570/include/bsp/tms570-vim.h b/bsps/arm/tms570/include/bsp/tms570-vim.h new file mode 100644 index 0000000000..9fa7e056f4 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570-vim.h @@ -0,0 +1,48 @@ +/** + * @file tms570-vim.h + * + * @ingroup tms570 + * + * @brief Vectored Interrupt Module (VIM) header file. + */ + +/* + * Copyright (c) 2014 Premysl Houdek + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Based on LPC24xx and LPC1768 BSP + * by embedded brains GmbH and others + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_VIM_H +#define LIBBSP_ARM_TMS570_VIM_H + +#ifndef ASM +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570.h b/bsps/arm/tms570/include/bsp/tms570.h new file mode 100644 index 0000000000..f278a93606 --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570.h @@ -0,0 +1,137 @@ +/* This file is generated by make_central_header.py */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570 +#define LIBBSP_ARM_TMS570 + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000) +#define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200) +#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0XFFFFF600) +#define TMS570_CRC (*(volatile tms570_crc_t*)0xFE000000) +#define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00) +#define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00) +#define TMS570_DCAN3 (*(volatile tms570_dcan_t*)0xFFF7E000) +#define TMS570_DCC1 (*(volatile tms570_dcc_t*)0xFFFFEC00) +#define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xFFFFF400) +#define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000) +#define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700) +#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C) +#define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800) +#define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000) +#define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800) +#define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500) +#define TMS570_FLASH (*(volatile tms570_flash_t*)0XFFF87000) +#define TMS570_FLEX_RAY (*(volatile tms570_flex_ray_t*)0xFFF7C800) +#define TMS570_GIO (*(volatile tms570_gio_t*)0xFFF7BC00) +#define TMS570_GIO_PORTA (*(volatile tms570_gio_port_t*)0xFFF7BC34) +#define TMS570_GIO_PORTB (*(volatile tms570_gio_port_t*)0xFFF7BC54) +#define TMS570_GIO_PORTC (*(volatile tms570_gio_port_t*)0xFFF7BC74) +#define TMS570_GIO_PORTD (*(volatile tms570_gio_port_t*)0xFFF7BC94) +#define TMS570_GIO_PORTE (*(volatile tms570_gio_port_t*)0xFFF7BCB4) +#define TMS570_GIO_PORTF (*(volatile tms570_gio_port_t*)0xFFF7BCD4) +#define TMS570_GIO_PORTG (*(volatile tms570_gio_port_t*)0xFFF7BCF4) +#define TMS570_GIO_PORTH (*(volatile tms570_gio_port_t*)0xFFF7BD14) +#define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400) +#define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500) +#define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400) +#define TMS570_IOMM (*(volatile tms570_iomm_t*)0XFFFFEA00) +#define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xFFFFEB10) +#define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400) +#define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900) +#define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800) +#define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900) +#define TMS570_PBIST (*(volatile tms570_pbist_t*)0xFFFFE400) +#define TMS570_PLL (*(volatile tms570_pll_t*)0XFFFFE100) +#define TMS570_PMM (*(volatile tms570_pmm_t*)0xFFFF0000) +#define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00) +#define TMS570_RTP (*(volatile tms570_rtp_t*)0xFFFFFA00) +#define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E500) +#define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800) +#define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xFFFFF800) +#define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xFFFFF900) +#define TMS570_VIM (*(volatile tms570_vim_t*)0XFFFFFDEC) +#define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000) +#define TMS570_SPI1 (*(volatile tms570_spi_t*)0xFFF7F400) +#define TMS570_SPI2 (*(volatile tms570_spi_t*)0xFFF7F600) +#define TMS570_SPI3 (*(volatile tms570_spi_t*)0xFFF7F800) +#define TMS570_SPI4 (*(volatile tms570_spi_t*)0xFFF7FA00) +#define TMS570_SPI5 (*(volatile tms570_spi_t*)0xFFF7FC00) +#define TMS570_STC (*(volatile tms570_stc_t*)0xFFFFE600) +#define TMS570_SYS1 (*(volatile tms570_sys1_t*)0xFFFFFF00) +#define TMS570_SYS2 (*(volatile tms570_sys2_t*)0xFFFFE100) +#define TMS570_PCR (*(volatile tms570_pcr_t*)0xFFFFE000) +#endif /* LIBBSP_ARM_TMS570 */ diff --git a/bsps/arm/tms570/include/bsp/tms570_hwinit.h b/bsps/arm/tms570/include/bsp/tms570_hwinit.h new file mode 100644 index 0000000000..2c84b6e5fa --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570_hwinit.h @@ -0,0 +1,31 @@ +#ifndef LIBBSP_ARM_TMS570_HWINIT_H +#define LIBBSP_ARM_TMS570_HWINIT_H + +#define TMS570_TCRAM_START_PTR ( (void *) ( 0x08000000U ) ) +#define TMS570_TCRAM_WINDOW_END_PTR ( (void *) ( 0x08080000U ) ) + +#define TMS570_SDRAM_START_PTR ( (void *) ( 0x80000000U ) ) +#define TMS570_SDRAM_WINDOW_END_PTR ( (void *) ( 0xA0000000U ) ) + +/* Ti TMS570 core setup implemented in assembly */ +void _esmCcmErrorsClear_( void ); +void _coreEnableEventBusExport_( void ); +void _errata_CORTEXR4_66_( void ); +void _errata_CORTEXR4_57_( void ); +void _coreEnableRamEcc_( void ); +void _coreDisableRamEcc_( void ); +void _mpuInit_( void ); + +void tms570_emif_sdram_init( void ); +void tms570_memory_init( uint32_t ram ); +void tms570_system_hw_init( void ); +void tms570_pinmux_init( void ); +void tms570_pll_init( void ); +void tms570_trim_lpo_init( void ); +void tms570_flash_init( void ); +void tms570_periph_init( void ); +void tms570_map_clock_init( void ); +void tms570_system_hw_init( void ); +void tms570_esm_init( void ); + +#endif /* LIBBSP_ARM_TMS570_HWINIT_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570_selftest.h b/bsps/arm/tms570/include/bsp/tms570_selftest.h new file mode 100644 index 0000000000..bbec8c2adf --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570_selftest.h @@ -0,0 +1,214 @@ +/** + * @file tms570_selftest.h + * + * @ingroup tms570 + * + * @brief Definition of TMS570 selftest error codes, addresses and functions. + */ +/* + * Copyright (c) 2016 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code available under following copyright. + */ +/* + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef LIBBSP_ARM_TMS570_SELFTEST_H +#define LIBBSP_ARM_TMS570_SELFTEST_H + +#include +#include + +#define CCMSELFCHECK_FAIL1 1U +#define CCMSELFCHECK_FAIL2 2U +#define CCMSELFCHECK_FAIL3 3U +#define CCMSELFCHECK_FAIL4 4U +#define PBISTSELFCHECK_FAIL1 5U +#define EFCCHECK_FAIL1 6U +#define EFCCHECK_FAIL2 7U +#define FMCECCCHECK_FAIL1 8U +#define CHECKB0RAMECC_FAIL1 9U +#define CHECKB1RAMECC_FAIL1 10U +#define CHECKFLASHECC_FAIL1 11U +#define VIMPARITYCHECK_FAIL1 12U +#define DMAPARITYCHECK_FAIL1 13U +#define HET1PARITYCHECK_FAIL1 14U +#define HTU1PARITYCHECK_FAIL1 15U +#define HET2PARITYCHECK_FAIL1 16U +#define HTU2PARITYCHECK_FAIL1 17U +#define ADC1PARITYCHECK_FAIL1 18U +#define ADC2PARITYCHECK_FAIL1 19U +#define CAN1PARITYCHECK_FAIL1 20U +#define CAN2PARITYCHECK_FAIL1 21U +#define CAN3PARITYCHECK_FAIL1 22U +#define MIBSPI1PARITYCHECK_FAIL1 23U +#define MIBSPI3PARITYCHECK_FAIL1 24U +#define MIBSPI5PARITYCHECK_FAIL1 25U +#define CHECKRAMECC_FAIL1 26U +#define CHECKRAMECC_FAIL2 27U +#define CHECKCLOCKMONITOR_FAIL1 28U +#define CHECKFLASHEEPROMECC_FAIL1 29U +#define CHECKFLASHEEPROMECC_FAIL2 31U +#define CHECKFLASHEEPROMECC_FAIL3 32U +#define CHECKFLASHEEPROMECC_FAIL4 33U +#define CHECKPLL1SLIP_FAIL1 34U +#define CHECKRAMADDRPARITY_FAIL1 35U +#define CHECKRAMADDRPARITY_FAIL2 36U +#define CHECKRAMUERRTEST_FAIL1 37U +#define CHECKRAMUERRTEST_FAIL2 38U +#define FMCBUS1PARITYCHECK_FAIL1 39U +#define FMCBUS1PARITYCHECK_FAIL2 40U +#define PBISTSELFCHECK_FAIL2 41U +#define PBISTSELFCHECK_FAIL3 42U + +/* PBIST and STC ROM - PBIST RAM GROUPING */ +#define PBIST_ROM_PBIST_RAM_GROUP 1U +#define STC_ROM_PBIST_RAM_GROUP 2U + +#define VIMRAMLOC (*(volatile uint32_t *)0xFFF82000U) +#define VIMRAMPARLOC (*(volatile uint32_t *)0xFFF82400U) + +#define NHET1RAMPARLOC (*(volatile uint32_t *)0xFF462000U) +#define NHET2RAMPARLOC (*(volatile uint32_t *)0xFF442000U) +#define adcPARRAM1 (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U)) +#define adcPARRAM2 (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U)) +#define canPARRAM1 (*(volatile uint32_t *)(0xFF1E0000U + 0x10U)) +#define canPARRAM2 (*(volatile uint32_t *)(0xFF1C0000U + 0x10U)) +#define canPARRAM3 (*(volatile uint32_t *)(0xFF1A0000U + 0x10U)) +#define HTU1PARLOC (*(volatile uint32_t *)0xFF4E0200U) +#define HTU2PARLOC (*(volatile uint32_t *)0xFF4C0200U) + +#define NHET1RAMLOC (*(volatile uint32_t *)0xFF460000U) +#define NHET2RAMLOC (*(volatile uint32_t *)0xFF440000U) +#define HTU1RAMLOC (*(volatile uint32_t *)0xFF4E0000U) +#define HTU2RAMLOC (*(volatile uint32_t *)0xFF4C0000U) + +#define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U) +#define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U) +#define canRAM1 (*(volatile uint32_t *)0xFF1E0000U) +#define canRAM2 (*(volatile uint32_t *)0xFF1C0000U) +#define canRAM3 (*(volatile uint32_t *)0xFF1A0000U) + +#define DMARAMPARLOC (*(volatile uint32_t *)(0xFFF80A00U)) +#define DMARAMLOC (*(volatile uint32_t *)(0xFFF80000U)) + +#define MIBSPI1RAMLOC (*(volatile uint32_t *)(0xFF0E0000U)) +#define MIBSPI3RAMLOC (*(volatile uint32_t *)(0xFF0C0000U)) +#define MIBSPI5RAMLOC (*(volatile uint32_t *)(0xFF0A0000U)) + +#define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U)) +#define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U)) +#define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U)) + +/** @enum pbistPort + * @brief Alias names for pbist Port number + * + * This enumeration is used to provide alias names for the pbist Port number + * - PBIST_PORT0 + * - PBIST_PORT1 + * + * @Note Check the datasheet for the port avaiability + */ +enum pbistPort { + PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */ + PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */ +}; + +enum { + PBIST_TripleReadSlow = 0x00000001U, /** + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_SELFTEST_PARITY_H +#define LIBBSP_ARM_TMS570_SELFTEST_PARITY_H + +#include + +/** + * The magic number used to switch most of the peripherals + * into parity protection test mode + */ +#define TMS570_SELFTEST_PAR_CR_KEY 0xA + +typedef struct tms570_selftest_par_desc tms570_selftest_par_desc_t; + +typedef void tms570_selftest_par_fnc_t( const tms570_selftest_par_desc_t *desc ); + +/** + * Decriptor specifying registers addresses and values used to test + * that parity protection is working for given hardware + * module/peripheral. It is used during initial chip self-tests. + */ +struct tms570_selftest_par_desc { + unsigned char esm_prim_grp; /**< ESM primary signalling group number. */ + unsigned char esm_prim_chan; /**< ESM primary signalling channel number. */ + unsigned char esm_sec_grp; /**< ESM optional/alternative signalling group. */ + unsigned char esm_sec_chan; /**< ESM optional/alternative signalling channel. */ + int fail_code; /**< Error code reported to + bsp_selftest_fail_notification() in the case of the test failure. */ + volatile uint32_t *ram_loc; /**< Address of memory protected by parity. */ + volatile uint32_t *par_loc; /**< Address of mapping of parity bits into CPU + * address space. */ + uint32_t par_xor; /**< Bitmask used to alter parity to cause + * intentional parity failure. */ + volatile uint32_t *par_cr_reg; /**< Address of module parity test control register. */ + uint32_t par_cr_test; /**< Mask of bit which cause switch to a test mode. */ + volatile uint32_t *par_st_reg; /**< Optional module parity status register which. */ + uint32_t par_st_clear; /**< Optional value which is written to status register + * to clear error. */ + tms570_selftest_par_fnc_t *partest_fnc; /**< Function which specialized for given kind + * of peripheral/module mechanism testing. */ + volatile void *fnc_data; /**< Pointer to the base of tested peripheral registers. + * It is required by some test functions (CAN and MibSPI) */ +}; + +extern const tms570_selftest_par_desc_t + tms570_selftest_par_het1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_htu1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_het2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_htu2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_adc1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_adc2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can1_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can2_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_can3_desc; +extern const tms570_selftest_par_desc_t + tms570_selftest_par_vim_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_dma_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi1_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi3_desc; +const tms570_selftest_par_desc_t + tms570_selftest_par_spi5_desc; + +extern const tms570_selftest_par_desc_t *const +tms570_selftest_par_list[]; + +extern const int tms570_selftest_par_list_size; + +void tms570_selftest_par_check_std( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_check_can( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_check_mibspi( const tms570_selftest_par_desc_t *desc ); + +void tms570_selftest_par_run( + const tms570_selftest_par_desc_t * + const *desc_arr, + int desc_cnt +); + +#endif /* LIBBSP_ARM_TMS570_SELFTEST_PARITY_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h new file mode 100644 index 0000000000..2beeae8bab --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h @@ -0,0 +1,1114 @@ +/** + * @file tms570lc4357-pins.h + * + * @ingroup tms570 + * + * @brief Specification of individual pins mapping to the package + */ + +/* + * Copyright (c) 2015-2017 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H +#define LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H + +#define TMS570_PIN_MMR_ALT_AD2EVT TMS570_BALL_WITH_MMR(80, 0) +#define TMS570_PIN_MMR_ALT_ECAP1 TMS570_BALL_WITH_MMR(80, 1) +#define TMS570_PIN_MMR_ALT_ECAP2 TMS570_BALL_WITH_MMR(80, 2) +#define TMS570_PIN_MMR_ALT_ECAP3 TMS570_BALL_WITH_MMR(80, 3) +#define TMS570_PIN_MMR_ALT_ECAP4 TMS570_BALL_WITH_MMR(81, 0) +#define TMS570_PIN_MMR_ALT_ECAP5 TMS570_BALL_WITH_MMR(81, 1) +#define TMS570_PIN_MMR_ALT_ECAP6 TMS570_BALL_WITH_MMR(81, 2) +#define TMS570_PIN_MMR_ALT_GIOA_0 TMS570_BALL_WITH_MMR(83, 3) +#define TMS570_PIN_MMR_ALT_GIOA_1 TMS570_BALL_WITH_MMR(84, 0) +#define TMS570_PIN_MMR_ALT_GIOA_2 TMS570_BALL_WITH_MMR(84, 1) +#define TMS570_PIN_MMR_ALT_GIOA_3 TMS570_BALL_WITH_MMR(84, 2) +#define TMS570_PIN_MMR_ALT_GIOA_4 TMS570_BALL_WITH_MMR(84, 3) +#define TMS570_PIN_MMR_ALT_GIOA_5 TMS570_BALL_WITH_MMR(85, 0) +#define TMS570_PIN_MMR_ALT_GIOA_6 TMS570_BALL_WITH_MMR(85, 1) +#define TMS570_PIN_MMR_ALT_GIOA_7 TMS570_BALL_WITH_MMR(85, 2) +#define TMS570_PIN_MMR_ALT_GIOB_0 TMS570_BALL_WITH_MMR(85, 3) +#define TMS570_PIN_MMR_ALT_GIOB_1 TMS570_BALL_WITH_MMR(86, 0) +#define TMS570_PIN_MMR_ALT_GIOB_2 TMS570_BALL_WITH_MMR(86, 1) +#define TMS570_PIN_MMR_ALT_GIOB_3 TMS570_BALL_WITH_MMR(86, 2) +#define TMS570_PIN_MMR_ALT_GIOB_4 TMS570_BALL_WITH_MMR(86, 3) +#define TMS570_PIN_MMR_ALT_GIOB_5 TMS570_BALL_WITH_MMR(87, 0) +#define TMS570_PIN_MMR_ALT_GIOB_6 TMS570_BALL_WITH_MMR(87, 1) +#define TMS570_PIN_MMR_ALT_GIOB_7 TMS570_BALL_WITH_MMR(87, 2) +#define TMS570_PIN_MMR_ALT_HET1_17 TMS570_BALL_WITH_MMR(92, 0) +#define TMS570_PIN_MMR_ALT_HET1_19 TMS570_BALL_WITH_MMR(92, 1) +#define TMS570_PIN_MMR_ALT_HET1_21 TMS570_BALL_WITH_MMR(92, 2) +#define TMS570_PIN_MMR_ALT_HET1_23 TMS570_BALL_WITH_MMR(92, 3) +#define TMS570_PIN_MMR_ALT_HET1_25 TMS570_BALL_WITH_MMR(93, 0) +#define TMS570_PIN_MMR_ALT_HET1_27 TMS570_BALL_WITH_MMR(93, 1) +#define TMS570_PIN_MMR_ALT_HET1_29 TMS570_BALL_WITH_MMR(93, 2) +#define TMS570_PIN_MMR_ALT_HET1_31 TMS570_BALL_WITH_MMR(93, 3) +#define TMS570_PIN_MMR_ALT_HET2_00 TMS570_BALL_WITH_MMR(94, 0) +#define TMS570_PIN_MMR_ALT_HET2_01 TMS570_BALL_WITH_MMR(94, 1) +#define TMS570_PIN_MMR_ALT_HET2_02 TMS570_BALL_WITH_MMR(94, 2) +#define TMS570_PIN_MMR_ALT_HET2_03 TMS570_BALL_WITH_MMR(94, 3) +#define TMS570_PIN_MMR_ALT_HET2_04 TMS570_BALL_WITH_MMR(95, 0) +#define TMS570_PIN_MMR_ALT_HET2_05 TMS570_BALL_WITH_MMR(95, 1) +#define TMS570_PIN_MMR_ALT_HET2_06 TMS570_BALL_WITH_MMR(95, 2) +#define TMS570_PIN_MMR_ALT_HET2_07 TMS570_BALL_WITH_MMR(95, 3) +#define TMS570_PIN_MMR_ALT_HET2_08 TMS570_BALL_WITH_MMR(96, 0) +#define TMS570_PIN_MMR_ALT_HET2_09 TMS570_BALL_WITH_MMR(96, 1) +#define TMS570_PIN_MMR_ALT_HET2_10 TMS570_BALL_WITH_MMR(96, 2) +#define TMS570_PIN_MMR_ALT_HET2_11 TMS570_BALL_WITH_MMR(96, 3) +#define TMS570_PIN_MMR_ALT_HET2_12 TMS570_BALL_WITH_MMR(97, 0) +#define TMS570_PIN_MMR_ALT_HET2_13 TMS570_BALL_WITH_MMR(97, 1) +#define TMS570_PIN_MMR_ALT_HET2_14 TMS570_BALL_WITH_MMR(97, 2) +#define TMS570_PIN_MMR_ALT_HET2_15 TMS570_BALL_WITH_MMR(97, 3) +#define TMS570_PIN_MMR_ALT_HET2_16 TMS570_BALL_WITH_MMR(98, 0) +#define TMS570_PIN_MMR_ALT_HET2_18 TMS570_BALL_WITH_MMR(98, 1) +#define TMS570_PIN_MMR_ALT_HET2_20 TMS570_BALL_WITH_MMR(98, 2) +#define TMS570_PIN_MMR_ALT_HET2_22 TMS570_BALL_WITH_MMR(98, 3) +#define TMS570_PIN_MMR_ALT_MDIO TMS570_BALL_WITH_MMR(87, 3) +#define TMS570_PIN_MMR_ALT_MIBSPI1NCS_4 TMS570_BALL_WITH_MMR(88, 0) +#define TMS570_PIN_MMR_ALT_MIBSPI1NCS_5 TMS570_BALL_WITH_MMR(88, 1) +#define TMS570_PIN_MMR_ALT_MIBSPI2NCS_1 TMS570_BALL_WITH_MMR(88, 2) +#define TMS570_PIN_MMR_ALT_MII_COL TMS570_BALL_WITH_MMR(89, 2) +#define TMS570_PIN_MMR_ALT_MII_CRS TMS570_BALL_WITH_MMR(89, 3) +#define TMS570_PIN_MMR_ALT_MII_RXCLK TMS570_BALL_WITH_MMR(90, 2) +#define TMS570_PIN_MMR_ALT_MII_RXD_0 TMS570_BALL_WITH_MMR(90, 3) +#define TMS570_PIN_MMR_ALT_MII_RXD_1 TMS570_BALL_WITH_MMR(91, 0) +#define TMS570_PIN_MMR_ALT_MII_RXD_2 TMS570_BALL_WITH_MMR(91, 1) +#define TMS570_PIN_MMR_ALT_MII_RXD_3 TMS570_BALL_WITH_MMR(91, 2) +#define TMS570_PIN_MMR_ALT_MII_RX_DV TMS570_BALL_WITH_MMR(90, 0) +#define TMS570_PIN_MMR_ALT_MII_RX_ER TMS570_BALL_WITH_MMR(90, 1) +#define TMS570_PIN_MMR_ALT_MII_TX_CLK TMS570_BALL_WITH_MMR(91, 3) +#define TMS570_PIN_MMR_ALT_eQEP1A TMS570_BALL_WITH_MMR(81, 3) +#define TMS570_PIN_MMR_ALT_eQEP1B TMS570_BALL_WITH_MMR(82, 0) +#define TMS570_PIN_MMR_ALT_eQEP1I TMS570_BALL_WITH_MMR(82, 1) +#define TMS570_PIN_MMR_ALT_eQEP1S TMS570_BALL_WITH_MMR(82, 2) +#define TMS570_PIN_MMR_ALT_eQEP2A TMS570_BALL_WITH_MMR(82, 3) +#define TMS570_PIN_MMR_ALT_eQEP2B TMS570_BALL_WITH_MMR(83, 0) +#define TMS570_PIN_MMR_ALT_eQEP2I TMS570_BALL_WITH_MMR(83, 1) +#define TMS570_PIN_MMR_ALT_eQEP2S TMS570_BALL_WITH_MMR(83, 2) +#define TMS570_PIN_MMR_ALT_nTZ1_1 TMS570_BALL_WITH_MMR(99, 0) +#define TMS570_PIN_MMR_ALT_nTZ1_2 TMS570_BALL_WITH_MMR(99, 1) +#define TMS570_PIN_MMR_ALT_nTZ1_3 TMS570_BALL_WITH_MMR(99, 2) + +#define TMS570_BALL_N19 TMS570_BALL_WITH_MMR(0, 0) +#define TMS570_BALL_N19_AD1EVT TMS570_PIN_AND_FNC(TMS570_BALL_N19, 0) +#define TMS570_BALL_N19_MII_RX_ER TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RX_ER, 1)) +#define TMS570_BALL_N19_RMII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 3) +#define TMS570_BALL_N19_nTZ1_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_1, 0)) + +#define TMS570_BALL_D4 TMS570_BALL_WITH_MMR(0, 1) +#define TMS570_BALL_D4_EMIF_ADDR_00 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 0) +#define TMS570_BALL_D4_HET2_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_01, 1)) + +#define TMS570_BALL_D5 TMS570_BALL_WITH_MMR(0, 2) +#define TMS570_BALL_D5_EMIF_ADDR_01 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 0) +#define TMS570_BALL_D5_HET2_03 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D5, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_03, 1)) + +#define TMS570_BALL_C4 TMS570_BALL_WITH_MMR(0, 3) +#define TMS570_BALL_C4_EMIF_ADDR_06 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 0) +#define TMS570_BALL_C4_RTP_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 1) +#define TMS570_BALL_C4_HET2_11 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_11, 1)) + +#define TMS570_BALL_C5 TMS570_BALL_WITH_MMR(1, 0) +#define TMS570_BALL_C5_EMIF_ADDR_07 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 0) +#define TMS570_BALL_C5_RTP_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 1) +#define TMS570_BALL_C5_HET2_13 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C5, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_13, 1)) + +#define TMS570_BALL_C6 TMS570_BALL_WITH_MMR(1, 1) +#define TMS570_BALL_C6_EMIF_ADDR_08 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 0) +#define TMS570_BALL_C6_RTP_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 1) +#define TMS570_BALL_C6_HET2_15 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C6, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_15, 1)) + +#define TMS570_BALL_C7 TMS570_BALL_WITH_MMR(1, 2) +#define TMS570_BALL_C7_EMIF_ADDR_09 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 0) +#define TMS570_BALL_C7_RTP_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 1) + +#define TMS570_BALL_C8 TMS570_BALL_WITH_MMR(1, 3) +#define TMS570_BALL_C8_EMIF_ADDR_10 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 0) +#define TMS570_BALL_C8_RTP_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 1) + +#define TMS570_BALL_C9 TMS570_BALL_WITH_MMR(2, 0) +#define TMS570_BALL_C9_EMIF_ADDR_11 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 0) +#define TMS570_BALL_C9_RTP_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 1) + +#define TMS570_BALL_C10 TMS570_BALL_WITH_MMR(2, 1) +#define TMS570_BALL_C10_EMIF_ADDR_12 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 0) +#define TMS570_BALL_C10_RTP_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 1) + +#define TMS570_BALL_C11 TMS570_BALL_WITH_MMR(2, 2) +#define TMS570_BALL_C11_EMIF_ADDR_13 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 0) +#define TMS570_BALL_C11_RTP_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 1) + +#define TMS570_BALL_C12 TMS570_BALL_WITH_MMR(2, 3) +#define TMS570_BALL_C12_EMIF_ADDR_14 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 0) +#define TMS570_BALL_C12_RTP_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 1) + +#define TMS570_BALL_C13 TMS570_BALL_WITH_MMR(3, 0) +#define TMS570_BALL_C13_EMIF_ADDR_15 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 0) +#define TMS570_BALL_C13_RTP_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 1) + +#define TMS570_BALL_D14 TMS570_BALL_WITH_MMR(3, 1) +#define TMS570_BALL_D14_EMIF_ADDR_16 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 0) +#define TMS570_BALL_D14_RTP_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 1) + +#define TMS570_BALL_C14 TMS570_BALL_WITH_MMR(3, 2) +#define TMS570_BALL_C14_EMIF_ADDR_17 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 0) +#define TMS570_BALL_C14_RTP_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 1) + +#define TMS570_BALL_D15 TMS570_BALL_WITH_MMR(3, 3) +#define TMS570_BALL_D15_EMIF_ADDR_18 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 0) +#define TMS570_BALL_D15_RTP_DATA_00 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 1) + +#define TMS570_BALL_C15 TMS570_BALL_WITH_MMR(4, 0) +#define TMS570_BALL_C15_EMIF_ADDR_19 TMS570_PIN_AND_FNC(TMS570_BALL_C15, 0) +#define TMS570_BALL_C15_RTP_nENA TMS570_PIN_AND_FNC(TMS570_BALL_C15, 1) + +#define TMS570_BALL_C16 TMS570_BALL_WITH_MMR(4, 1) +#define TMS570_BALL_C16_EMIF_ADDR_20 TMS570_PIN_AND_FNC(TMS570_BALL_C16, 0) +#define TMS570_BALL_C16_RTP_nSYNC TMS570_PIN_AND_FNC(TMS570_BALL_C16, 1) + +#define TMS570_BALL_C17 TMS570_BALL_WITH_MMR(4, 2) +#define TMS570_BALL_C17_EMIF_ADDR_21 TMS570_PIN_AND_FNC(TMS570_BALL_C17, 0) +#define TMS570_BALL_C17_RTP_CLK TMS570_PIN_AND_FNC(TMS570_BALL_C17, 1) + +#define TMS570_BALL_D16 TMS570_BALL_WITH_MMR(8, 3) +#define TMS570_BALL_D16_EMIF_BA_1 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 0) +#define TMS570_BALL_D16_ TMS570_PIN_AND_FNC(TMS570_BALL_D16, 1) +#define TMS570_BALL_D16_HET2_05 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D16, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_05, 1)) + +#define TMS570_BALL_K3 TMS570_BALL_WITH_MMR(9, 0) +#define TMS570_BALL_K3_EMIF_CLK TMS570_PIN_AND_FNC(TMS570_BALL_K3, 1) +#define TMS570_BALL_K3_ECLK2 TMS570_PIN_AND_FNC(TMS570_BALL_K3, 2) + +#define TMS570_BALL_R4 TMS570_BALL_WITH_MMR(9, 1) +#define TMS570_BALL_R4_EMIF_nCAS TMS570_PIN_AND_FNC(TMS570_BALL_R4, 0) +#define TMS570_BALL_R4_GIOB_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_3, 1)) + +#define TMS570_BALL_N17 TMS570_BALL_WITH_MMR(9, 2) +#define TMS570_BALL_N17_EMIF_nCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 0) +#define TMS570_BALL_N17_RTP_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 1) +#define TMS570_BALL_N17_HET2_07 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 1)) + +#define TMS570_BALL_L17 TMS570_BALL_WITH_MMR(9, 3) +#define TMS570_BALL_L17_EMIF_nCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_L17, 0) +#define TMS570_BALL_L17_GIOB_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_L17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_4, 1)) + +#define TMS570_BALL_K17 TMS570_BALL_WITH_MMR(10, 0) +#define TMS570_BALL_K17_EMIF_nCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 0) +#define TMS570_BALL_K17_RTP_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 1) +#define TMS570_BALL_K17_HET2_09 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_09, 1)) + +#define TMS570_BALL_M17 TMS570_BALL_WITH_MMR(10, 1) +#define TMS570_BALL_M17_EMIF_nCSl_4 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 0) +#define TMS570_BALL_M17_RTP_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 1) +#define TMS570_BALL_M17_GIOB_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M17, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_5, 1)) + +#define TMS570_BALL_R3 TMS570_BALL_WITH_MMR(10, 2) +#define TMS570_BALL_R3_EMIF_nRAS TMS570_PIN_AND_FNC(TMS570_BALL_R3, 0) +#define TMS570_BALL_R3_GIOB_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_6, 1)) + +#define TMS570_BALL_P3 TMS570_BALL_WITH_MMR(10, 3) +#define TMS570_BALL_P3_EMIF_nWAIT TMS570_PIN_AND_FNC(TMS570_BALL_P3, 0) +#define TMS570_BALL_P3_GIOB_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_7, 1)) + +#define TMS570_BALL_D17 TMS570_BALL_WITH_MMR(11, 0) +#define TMS570_BALL_D17_EMIF_nWE TMS570_PIN_AND_FNC(TMS570_BALL_D17, 0) +#define TMS570_BALL_D17_EMIF_RNW TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J1, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E9 TMS570_BALL_WITH_MMR(11, 1) +#define TMS570_BALL_E9_ETMDATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 0) +#define TMS570_BALL_E9_EMIF_ADDR_05 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 1) + +#define TMS570_BALL_E8 TMS570_BALL_WITH_MMR(11, 2) +#define TMS570_BALL_E8_ETMDATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 0) +#define TMS570_BALL_E8_EMIF_ADDR_04 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 1) + +#define TMS570_BALL_E7 TMS570_BALL_WITH_MMR(11, 3) +#define TMS570_BALL_E7_ETMDATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 0) +#define TMS570_BALL_E7_EMIF_ADDR_03 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 1) + +#define TMS570_BALL_E6 TMS570_BALL_WITH_MMR(12, 0) +#define TMS570_BALL_E6_ETMDATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 0) +#define TMS570_BALL_E6_EMIF_ADDR_02 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 1) + +#define TMS570_BALL_E13 TMS570_BALL_WITH_MMR(12, 1) +#define TMS570_BALL_E13_ETMDATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 0) +#define TMS570_BALL_E13_EMIF_BA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E12 TMS570_BALL_WITH_MMR(12, 2) +#define TMS570_BALL_E12_ETMDATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E12, 0) +#define TMS570_BALL_E12_EMIF_nOE TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E11 TMS570_BALL_WITH_MMR(12, 3) +#define TMS570_BALL_E11_ETMDATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 0) +#define TMS570_BALL_E11_EMIF_nDQM_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_P2, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_E10 TMS570_BALL_WITH_MMR(13, 0) +#define TMS570_BALL_E10_ETMDATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 0) +#define TMS570_BALL_E10_EMIF_nDQM_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_K15 TMS570_BALL_WITH_MMR(13, 1) +#define TMS570_BALL_K15_ETMDATA_16 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 0) +#define TMS570_BALL_K15_EMIF_DATA_00 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 1) + +#define TMS570_BALL_L15 TMS570_BALL_WITH_MMR(13, 2) +#define TMS570_BALL_L15_ETMDATA_17 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 0) +#define TMS570_BALL_L15_EMIF_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 1) + +#define TMS570_BALL_M15 TMS570_BALL_WITH_MMR(13, 3) +#define TMS570_BALL_M15_ETMDATA_18 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 0) +#define TMS570_BALL_M15_EMIF_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 1) + +#define TMS570_BALL_N15 TMS570_BALL_WITH_MMR(14, 0) +#define TMS570_BALL_N15_ETMDATA_19 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 0) +#define TMS570_BALL_N15_EMIF_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 1) + +#define TMS570_BALL_E5 TMS570_BALL_WITH_MMR(14, 1) +#define TMS570_BALL_E5_ETMDATA_20 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 0) +#define TMS570_BALL_E5_EMIF_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 1) + +#define TMS570_BALL_F5 TMS570_BALL_WITH_MMR(14, 2) +#define TMS570_BALL_F5_ETMDATA_21 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 0) +#define TMS570_BALL_F5_EMIF_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 1) + +#define TMS570_BALL_G5 TMS570_BALL_WITH_MMR(14, 3) +#define TMS570_BALL_G5_ETMDATA_22 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 0) +#define TMS570_BALL_G5_EMIF_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 1) + +#define TMS570_BALL_K5 TMS570_BALL_WITH_MMR(15, 0) +#define TMS570_BALL_K5_ETMDATA_23 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 0) +#define TMS570_BALL_K5_EMIF_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 1) + +#define TMS570_BALL_L5 TMS570_BALL_WITH_MMR(15, 1) +#define TMS570_BALL_L5_ETMDATA_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 0) +#define TMS570_BALL_L5_EMIF_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 1) +#define TMS570_BALL_L5_HET2_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 2) +#define TMS570_BALL_L5_MIBSPI5NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 3) + +#define TMS570_BALL_M5 TMS570_BALL_WITH_MMR(15, 2) +#define TMS570_BALL_M5_ETMDATA_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 0) +#define TMS570_BALL_M5_EMIF_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 1) +#define TMS570_BALL_M5_HET2_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 2) +#define TMS570_BALL_M5_MIBSPI5NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 3) + +#define TMS570_BALL_N5 TMS570_BALL_WITH_MMR(15, 3) +#define TMS570_BALL_N5_ETMDATA_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 0) +#define TMS570_BALL_N5_EMIF_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 1) +#define TMS570_BALL_N5_HET2_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 2) + +#define TMS570_BALL_P5 TMS570_BALL_WITH_MMR(16, 0) +#define TMS570_BALL_P5_ETMDATA_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 0) +#define TMS570_BALL_P5_EMIF_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 1) +#define TMS570_BALL_P5_HET2_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 2) + +#define TMS570_BALL_R5 TMS570_BALL_WITH_MMR(16, 1) +#define TMS570_BALL_R5_ETMDATA_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 0) +#define TMS570_BALL_R5_EMIF_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 1) +#define TMS570_BALL_R5_HET2_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 2) +#define TMS570_BALL_R5_GIOA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R5, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_0, 1)) + +#define TMS570_BALL_R6 TMS570_BALL_WITH_MMR(16, 2) +#define TMS570_BALL_R6_ETMDATA_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 0) +#define TMS570_BALL_R6_EMIF_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 1) +#define TMS570_BALL_R6_HET2_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 2) +#define TMS570_BALL_R6_GIOA_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R6, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_1, 1)) + +#define TMS570_BALL_R7 TMS570_BALL_WITH_MMR(16, 3) +#define TMS570_BALL_R7_ETMDATA_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 0) +#define TMS570_BALL_R7_EMIF_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 1) +#define TMS570_BALL_R7_HET2_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 2) +#define TMS570_BALL_R7_GIOA_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R7, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_3, 1)) + +#define TMS570_BALL_R8 TMS570_BALL_WITH_MMR(17, 0) +#define TMS570_BALL_R8_ETMDATA_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 0) +#define TMS570_BALL_R8_EMIF_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 1) +#define TMS570_BALL_R8_HET2_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 2) +#define TMS570_BALL_R8_GIOA_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R8, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_4, 1)) + +#define TMS570_BALL_R9 TMS570_BALL_WITH_MMR(17, 1) +#define TMS570_BALL_R9_ETMTRACECLKIN TMS570_PIN_AND_FNC(TMS570_BALL_R9, 0) +#define TMS570_BALL_R9_EXTCLKIN2 TMS570_PIN_AND_FNC(TMS570_BALL_R9, 1) +#define TMS570_BALL_R9_GIOA_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_5, 1)) + +#define TMS570_BALL_R10 TMS570_BALL_WITH_MMR(17, 2) +#define TMS570_BALL_R10_ETMTRACECLKOUT TMS570_PIN_AND_FNC(TMS570_BALL_R10, 0) +#define TMS570_BALL_R10_GIOA_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R10, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_6, 1)) + +#define TMS570_BALL_R11 TMS570_BALL_WITH_MMR(17, 3) +#define TMS570_BALL_R11_ETMTRACECTL TMS570_PIN_AND_FNC(TMS570_BALL_R11, 0) +#define TMS570_BALL_R11_GIOA_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R11, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_7, 1)) + +#define TMS570_BALL_B15 TMS570_BALL_WITH_MMR(18, 0) +#define TMS570_BALL_B15_FRAYTX1 TMS570_PIN_AND_FNC(TMS570_BALL_B15, 0) +#define TMS570_BALL_B15_GIOA_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B15, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_2, 1)) + +#define TMS570_BALL_B8 TMS570_BALL_WITH_MMR(18, 1) +#define TMS570_BALL_B8_FRAYTX2 TMS570_PIN_AND_FNC(TMS570_BALL_B8, 0) +#define TMS570_BALL_B8_GIOB_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B8, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_0, 1)) + +#define TMS570_BALL_B16 TMS570_BALL_WITH_MMR(18, 2) +#define TMS570_BALL_B16_FRAYTXEN1 TMS570_PIN_AND_FNC(TMS570_BALL_B16, 0) +#define TMS570_BALL_B16_GIOB_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B16, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_1, 1)) + +#define TMS570_BALL_B9 TMS570_BALL_WITH_MMR(18, 3) +#define TMS570_BALL_B9_FRAYTXEN2 TMS570_PIN_AND_FNC(TMS570_BALL_B9, 0) +#define TMS570_BALL_B9_GIOB_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_2, 1)) + +#define TMS570_BALL_C1 TMS570_BALL_WITH_MMR(19, 0) +#define TMS570_BALL_C1_GIOA_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_2, 0)) +#define TMS570_BALL_C1_HET2_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_00, 1)) +#define TMS570_BALL_C1_eQEP2I TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2I, 1)) + +#define TMS570_BALL_E1 TMS570_BALL_WITH_MMR(19, 1) +#define TMS570_BALL_E1_GIOA_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_3, 0)) +#define TMS570_BALL_E1_HET2_02 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_02, 1)) + +#define TMS570_BALL_B5 TMS570_BALL_WITH_MMR(19, 2) +#define TMS570_BALL_B5_GIOA_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B5, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_5, 0)) +#define TMS570_BALL_B5_EXTCLKIN TMS570_PIN_AND_FNC(TMS570_BALL_B5, 3) +#define TMS570_BALL_B5_ePWM1A TMS570_PIN_AND_FNC(TMS570_BALL_B5, 5) + +#define TMS570_BALL_H3 TMS570_BALL_WITH_MMR(19, 3) +#define TMS570_BALL_H3_GIOA_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_6, 0)) +#define TMS570_BALL_H3_HET2_04 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_04, 1)) +#define TMS570_BALL_H3_ePWM1B TMS570_PIN_AND_FNC(TMS570_BALL_H3, 5) + +#define TMS570_BALL_M1 TMS570_BALL_WITH_MMR(20, 0) +#define TMS570_BALL_M1_GIOA_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOA_7, 0)) +#define TMS570_BALL_M1_HET2_06 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_06, 1)) +#define TMS570_BALL_M1_ePWM2A TMS570_PIN_AND_FNC(TMS570_BALL_M1, 5) + +#define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(20, 1) +#define TMS570_BALL_F2_GIOB_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_2, 0)) +#define TMS570_BALL_F2_DCAN4TX TMS570_PIN_AND_FNC(TMS570_BALL_F2, 3) + +#define TMS570_BALL_W10 TMS570_BALL_WITH_MMR(20, 2) +#define TMS570_BALL_W10_GIOB_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W10, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_3, 0)) +#define TMS570_BALL_W10_DCAN4RX TMS570_PIN_AND_FNC(TMS570_BALL_W10, 3) + +#define TMS570_BALL_J2 TMS570_BALL_WITH_MMR(20, 3) +#define TMS570_BALL_J2_GIOB_6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_6, 0)) +#define TMS570_BALL_J2_nERROR1 TMS570_PIN_AND_FNC(TMS570_BALL_J2, 1) + +#define TMS570_BALL_F1 TMS570_BALL_WITH_MMR(21, 0) +#define TMS570_BALL_F1_GIOB_7 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_GIOB_7, 0)) +#define TMS570_BALL_F1_nERROR2 TMS570_PIN_AND_FNC(TMS570_BALL_F1, 1) +#define TMS570_BALL_F1_nTZ1_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_2, 0)) + +#define TMS570_BALL_R2 TMS570_BALL_WITH_MMR(21, 1) +#define TMS570_BALL_R2_MIBSPI1NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 0) +#define TMS570_BALL_R2_MIBSPI1SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 1) +#define TMS570_BALL_R2_MII_TXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 2) +#define TMS570_BALL_R2_ECAP6 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_R2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP6, 1)) + +#define TMS570_BALL_F3 TMS570_BALL_WITH_MMR(21, 2) +#define TMS570_BALL_F3_MIBSPI1NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_F3, 0) +#define TMS570_BALL_F3_MII_COL TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_COL, 1)) +#define TMS570_BALL_F3_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_17, 1)) +#define TMS570_BALL_F3_eQEP1S TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1S, 1)) + +#define TMS570_BALL_G3 TMS570_BALL_WITH_MMR(21, 3) +#define TMS570_BALL_G3_MIBSPI1NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_G3, 0) +#define TMS570_BALL_G3_MDIO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MDIO, 1)) +#define TMS570_BALL_G3_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_19, 1)) + +#define TMS570_BALL_J3 TMS570_BALL_WITH_MMR(22, 0) +#define TMS570_BALL_J3_MIBSPI1NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_J3, 0) +#define TMS570_BALL_J3_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_21, 1)) +#define TMS570_BALL_J3_nTZ1_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_3, 0)) + +#define TMS570_BALL_G19 TMS570_BALL_WITH_MMR(22, 1) +#define TMS570_BALL_G19_MIBSPI1NENA TMS570_PIN_AND_FNC(TMS570_BALL_G19, 0) +#define TMS570_BALL_G19_MII_RXD_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_2, 1)) +#define TMS570_BALL_G19_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_23, 1)) +#define TMS570_BALL_G19_ECAP4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP4, 1)) + +#define TMS570_BALL_V9 TMS570_BALL_WITH_MMR(22, 2) +#define TMS570_BALL_V9_MIBSPI3CLK TMS570_PIN_AND_FNC(TMS570_BALL_V9, 0) +#define TMS570_BALL_V9_AD1EXT_SEL_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_H17, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V9_eQEP1A TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1A, 1)) + +#define TMS570_BALL_V10 TMS570_BALL_WITH_MMR(22, 3) +#define TMS570_BALL_V10_MIBSPI3NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_V10, 0) +#define TMS570_BALL_V10_AD2EVT TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V10, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_AD2EVT, 1)) +#define TMS570_BALL_V10_eQEP1I TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V10, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1I, 1)) + +#define TMS570_BALL_V5 TMS570_BALL_WITH_MMR(23, 0) +#define TMS570_BALL_V5_MIBSPI3NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_V5, 0) +#define TMS570_BALL_V5_MDCLK TMS570_PIN_AND_FNC(TMS570_BALL_V5, 2) +#define TMS570_BALL_V5_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_25, 1)) + +#define TMS570_BALL_B2 TMS570_BALL_WITH_MMR(23, 1) +#define TMS570_BALL_B2_MIBSPI3NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_B2, 0) +#define TMS570_BALL_B2_I2C1_SDA TMS570_PIN_AND_FNC(TMS570_BALL_B2, 1) +#define TMS570_BALL_B2_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_27, 1)) +#define TMS570_BALL_B2_nTZ1_2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_2, 1)) + +#define TMS570_BALL_C3 TMS570_BALL_WITH_MMR(23, 2) +#define TMS570_BALL_C3_MIBSPI3NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_C3, 0) +#define TMS570_BALL_C3_I2C1_SCL TMS570_PIN_AND_FNC(TMS570_BALL_C3, 1) +#define TMS570_BALL_C3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_29, 1)) +#define TMS570_BALL_C3_nTZ1_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_1, 1)) + +#define TMS570_BALL_W9 TMS570_BALL_WITH_MMR(23, 3) +#define TMS570_BALL_W9_MIBSPI3NENA TMS570_PIN_AND_FNC(TMS570_BALL_W9, 0) +#define TMS570_BALL_W9_MIBSPI3NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_W9, 1) +#define TMS570_BALL_W9_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_31, 1)) +#define TMS570_BALL_W9_eQEP1B TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP1B, 1)) + +#define TMS570_BALL_W8 TMS570_BALL_WITH_MMR(24, 0) +#define TMS570_BALL_W8_MIBSPI3SIMO TMS570_PIN_AND_FNC(TMS570_BALL_W8, 0) +#define TMS570_BALL_W8_AD1EXT_SEL_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E16, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_W8_ECAP3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP3, 1)) + +#define TMS570_BALL_V8 TMS570_BALL_WITH_MMR(24, 1) +#define TMS570_BALL_V8_MIBSPI3SOMI TMS570_PIN_AND_FNC(TMS570_BALL_V8, 0) +#define TMS570_BALL_V8_EXT_ENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G16, 4) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V8_ECAP2 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP2, 1)) + +#define TMS570_BALL_H19 TMS570_BALL_WITH_MMR(24, 2) +#define TMS570_BALL_H19_MIBSPI5CLK TMS570_PIN_AND_FNC(TMS570_BALL_H19, 0) +#define TMS570_BALL_H19_DMM_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_H19, 1) +#define TMS570_BALL_H19_MII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 2) +#define TMS570_BALL_H19_RMII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 3) + +#define TMS570_BALL_E19 TMS570_BALL_WITH_MMR(24, 3) +#define TMS570_BALL_E19_MIBSPI5NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 0) +#define TMS570_BALL_E19_DMM_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 1) +#define TMS570_BALL_E19_ePWM4A TMS570_PIN_AND_FNC(TMS570_BALL_E19, 5) + +#define TMS570_BALL_B6 TMS570_BALL_WITH_MMR(25, 0) +#define TMS570_BALL_B6_MIBSPI5NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 0) +#define TMS570_BALL_B6_DMM_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 1) + +#define TMS570_BALL_W6 TMS570_BALL_WITH_MMR(25, 1) +#define TMS570_BALL_W6_MIBSPI5NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 0) +#define TMS570_BALL_W6_DMM_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 1) + +#define TMS570_BALL_T12 TMS570_BALL_WITH_MMR(25, 2) +#define TMS570_BALL_T12_MIBSPI5NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 0) +#define TMS570_BALL_T12_DMM_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 1) + +#define TMS570_BALL_H18 TMS570_BALL_WITH_MMR(25, 3) +#define TMS570_BALL_H18_MIBSPI5NENA TMS570_PIN_AND_FNC(TMS570_BALL_H18, 0) +#define TMS570_BALL_H18_DMM_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 1) +#define TMS570_BALL_H18_MII_RXD_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H18, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_3, 1)) +#define TMS570_BALL_H18_ECAP5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H18, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP5, 1)) + +#define TMS570_BALL_J19 TMS570_BALL_WITH_MMR(26, 0) +#define TMS570_BALL_J19_MIBSPI5SIMO_0 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 0) +#define TMS570_BALL_J19_DMM_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 1) +#define TMS570_BALL_J19_MII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 2) +#define TMS570_BALL_J19_RMII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 3) + +#define TMS570_BALL_E16 TMS570_BALL_WITH_MMR(26, 1) +#define TMS570_BALL_E16_MIBSPI5SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 0) +#define TMS570_BALL_E16_DMM_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 1) +#define TMS570_BALL_E16_AD1EXT_SEL_00 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E16, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W8, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_H17 TMS570_BALL_WITH_MMR(26, 2) +#define TMS570_BALL_H17_MIBSPI5SIMO_2 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 0) +#define TMS570_BALL_H17_DMM_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 1) +#define TMS570_BALL_H17_AD1EXT_SEL_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H17, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V9, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_G17 TMS570_BALL_WITH_MMR(26, 3) +#define TMS570_BALL_G17_MIBSPI5SIMO_3 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 0) +#define TMS570_BALL_G17_DMM_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 1) +#define TMS570_BALL_G17_I2C2_SDA TMS570_PIN_AND_FNC(TMS570_BALL_G17, 2) +#define TMS570_BALL_G17_AD1EXT_SEL_02 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 4) + +#define TMS570_BALL_J18 TMS570_BALL_WITH_MMR(27, 0) +#define TMS570_BALL_J18_MIBSPI5SOMI_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 0) +#define TMS570_BALL_J18_DMM_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 1) +#define TMS570_BALL_J18_MII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 2) +#define TMS570_BALL_J18_RMII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 3) + +#define TMS570_BALL_E17 TMS570_BALL_WITH_MMR(27, 1) +#define TMS570_BALL_E17_MIBSPI5SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 0) +#define TMS570_BALL_E17_DMM_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 1) +#define TMS570_BALL_E17_AD1EXT_SEL_03 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 4) + +#define TMS570_BALL_H16 TMS570_BALL_WITH_MMR(27, 2) +#define TMS570_BALL_H16_MIBSPI5SOMI_2 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 0) +#define TMS570_BALL_H16_DMM_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 1) +#define TMS570_BALL_H16_AD1EXT_SEL_04 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 4) + +#define TMS570_BALL_G16 TMS570_BALL_WITH_MMR(27, 3) +#define TMS570_BALL_G16_MIBSPI5SOMI_3 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 0) +#define TMS570_BALL_G16_DMM_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 1) +#define TMS570_BALL_G16_I2C2_SCL TMS570_PIN_AND_FNC(TMS570_BALL_G16, 2) +#define TMS570_BALL_G16_EXT_ENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G16, 4), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V8, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_K18 TMS570_BALL_WITH_MMR(28, 0) +#define TMS570_BALL_K18_HET1_00 TMS570_PIN_AND_FNC(TMS570_BALL_K18, 0) +#define TMS570_BALL_K18_MIBSPI4CLK TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1) +#define TMS570_BALL_K18_ePWM2B TMS570_PIN_AND_FNC(TMS570_BALL_K18, 5) + +#define TMS570_BALL_V2 TMS570_BALL_WITH_MMR(28, 1) +#define TMS570_BALL_V2_HET1_01 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 0) +#define TMS570_BALL_V2_MIBSPI4NENA TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1) +#define TMS570_BALL_V2_HET2_08 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_08, 1)) +#define TMS570_BALL_V2_eQEP2A TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2A, 1)) + +#define TMS570_BALL_W5 TMS570_BALL_WITH_MMR(28, 2) +#define TMS570_BALL_W5_HET1_02 TMS570_PIN_AND_FNC(TMS570_BALL_W5, 0) +#define TMS570_BALL_W5_MIBSPI4SIMO TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1) +#define TMS570_BALL_W5_ePWM3A TMS570_PIN_AND_FNC(TMS570_BALL_W5, 5) + +#define TMS570_BALL_U1 TMS570_BALL_WITH_MMR(28, 3) +#define TMS570_BALL_U1_HET1_03 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 0) +#define TMS570_BALL_U1_MIBSPI4NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1) +#define TMS570_BALL_U1_HET2_10 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_10, 1)) +#define TMS570_BALL_U1_eQEP2B TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2B, 1)) + +#define TMS570_BALL_B12 TMS570_BALL_WITH_MMR(29, 0) +#define TMS570_BALL_B12_HET1_04 TMS570_PIN_AND_FNC(TMS570_BALL_B12, 0) +#define TMS570_BALL_B12_MIBSPI4NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B12, 1) +#define TMS570_BALL_B12_ePWM4B TMS570_PIN_AND_FNC(TMS570_BALL_B12, 5) + +#define TMS570_BALL_V6 TMS570_BALL_WITH_MMR(29, 1) +#define TMS570_BALL_V6_HET1_05 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 0) +#define TMS570_BALL_V6_MIBSPI4SOMI TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1) +#define TMS570_BALL_V6_HET2_12 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_12, 1)) +#define TMS570_BALL_V6_ePWM3B TMS570_PIN_AND_FNC(TMS570_BALL_V6, 5) + +#define TMS570_BALL_W3 TMS570_BALL_WITH_MMR(29, 2) +#define TMS570_BALL_W3_HET1_06 TMS570_PIN_AND_FNC(TMS570_BALL_W3, 0) +#define TMS570_BALL_W3_SCI3RX TMS570_PIN_AND_FNC(TMS570_BALL_W3, 1) +#define TMS570_BALL_W3_ePWM5A TMS570_PIN_AND_FNC(TMS570_BALL_W3, 5) + +#define TMS570_BALL_T1 TMS570_BALL_WITH_MMR(29, 3) +#define TMS570_BALL_T1_HET1_07 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 0) +#define TMS570_BALL_T1_MIBSPI4NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 1) +#define TMS570_BALL_T1_HET2_14 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_14, 1)) +#define TMS570_BALL_T1_ePWM7B TMS570_PIN_AND_FNC(TMS570_BALL_T1, 5) + +#define TMS570_BALL_E18 TMS570_BALL_WITH_MMR(30, 0) +#define TMS570_BALL_E18_HET1_08 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 0) +#define TMS570_BALL_E18_MIBSPI1SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 1) +#define TMS570_BALL_E18_MII_TXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 2) + +#define TMS570_BALL_V7 TMS570_BALL_WITH_MMR(30, 1) +#define TMS570_BALL_V7_HET1_09 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 0) +#define TMS570_BALL_V7_MIBSPI4NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 1) +#define TMS570_BALL_V7_HET2_16 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V7, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_16, 1)) +#define TMS570_BALL_V7_ePWM7A TMS570_PIN_AND_FNC(TMS570_BALL_V7, 5) + +#define TMS570_BALL_D19 TMS570_BALL_WITH_MMR(30, 2) +#define TMS570_BALL_D19_HET1_10 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 0) +#define TMS570_BALL_D19_MIBSPI4NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 1) +#define TMS570_BALL_D19_MII_TX_CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_TX_CLK, 1)) +#define TMS570_BALL_D19_nTZ1_3 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D19, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_nTZ1_3, 1)) + +#define TMS570_BALL_E3 TMS570_BALL_WITH_MMR(30, 3) +#define TMS570_BALL_E3_HET1_11 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 0) +#define TMS570_BALL_E3_MIBSPI3NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 1) +#define TMS570_BALL_E3_HET2_18 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_18, 1)) +#define TMS570_BALL_E3_EPWM1SYNCO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 5), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A4, 5) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B4 TMS570_BALL_WITH_MMR(31, 0) +#define TMS570_BALL_B4_HET1_12 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 0) +#define TMS570_BALL_B4_MIBSPI4NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 1) +#define TMS570_BALL_B4_MII_CRS TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B4, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_CRS, 1)) +#define TMS570_BALL_B4_RMII_CRS_DV TMS570_PIN_AND_FNC(TMS570_BALL_B4, 3) + +#define TMS570_BALL_N2 TMS570_BALL_WITH_MMR(31, 1) +#define TMS570_BALL_N2_HET1_13 TMS570_PIN_AND_FNC(TMS570_BALL_N2, 0) +#define TMS570_BALL_N2_SCI3TX TMS570_PIN_AND_FNC(TMS570_BALL_N2, 1) +#define TMS570_BALL_N2_HET2_20 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N2, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_20, 1)) +#define TMS570_BALL_N2_ePWM5B TMS570_PIN_AND_FNC(TMS570_BALL_N2, 5) + +#define TMS570_BALL_N1 TMS570_BALL_WITH_MMR(31, 2) +#define TMS570_BALL_N1_HET1_15 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 0) +#define TMS570_BALL_N1_MIBSPI1NCS_4 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI1NCS_4, 1)) +#define TMS570_BALL_N1_HET2_22 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 3), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_22, 1)) +#define TMS570_BALL_N1_ECAP1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N1, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_ECAP1, 1)) + +#define TMS570_BALL_A4 TMS570_BALL_WITH_MMR(31, 3) +#define TMS570_BALL_A4_HET1_16 TMS570_PIN_AND_FNC(TMS570_BALL_A4, 0) +#define TMS570_BALL_A4_EPWM1SYNCI TMS570_PIN_AND_FNC(TMS570_BALL_A4, 3) +#define TMS570_BALL_A4_EPWM1SYNCO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A4, 5), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E3, 5) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A13 TMS570_BALL_WITH_MMR(32, 0) +#define TMS570_BALL_A13_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_17, 0)) +#define TMS570_BALL_A13_EMIF_nOE TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_A13_SCI4RX TMS570_PIN_AND_FNC(TMS570_BALL_A13, 2) + +#define TMS570_BALL_J1 TMS570_BALL_WITH_MMR(32, 1) +#define TMS570_BALL_J1_HET1_18 TMS570_PIN_AND_FNC(TMS570_BALL_J1, 0) +#define TMS570_BALL_J1_EMIF_RNW TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J1, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_J1_ePWM6A TMS570_PIN_AND_FNC(TMS570_BALL_J1, 5) + +#define TMS570_BALL_B13 TMS570_BALL_WITH_MMR(32, 2) +#define TMS570_BALL_B13_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_19, 0)) +#define TMS570_BALL_B13_EMIF_nDQM_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_B13_SCI4TX TMS570_PIN_AND_FNC(TMS570_BALL_B13, 2) + +#define TMS570_BALL_P2 TMS570_BALL_WITH_MMR(32, 3) +#define TMS570_BALL_P2_HET1_20 TMS570_PIN_AND_FNC(TMS570_BALL_P2, 0) +#define TMS570_BALL_P2_EMIF_nDQM_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P2, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_P2_ePWM6B TMS570_PIN_AND_FNC(TMS570_BALL_P2, 5) + +#define TMS570_BALL_H4 TMS570_BALL_WITH_MMR(33, 0) +#define TMS570_BALL_H4_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_21, 0)) +#define TMS570_BALL_H4_EMIF_nDQM_2 TMS570_PIN_AND_FNC(TMS570_BALL_H4, 1) + +#define TMS570_BALL_B3 TMS570_BALL_WITH_MMR(33, 1) +#define TMS570_BALL_B3_HET1_22 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 0) +#define TMS570_BALL_B3_EMIF_nDQM_3 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 1) + +#define TMS570_BALL_J4 TMS570_BALL_WITH_MMR(33, 2) +#define TMS570_BALL_J4_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET1_23, 0)) +#define TMS570_BALL_J4_EMIF_BA_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_P1 TMS570_BALL_WITH_MMR(33, 3) +#define TMS570_BALL_P1_HET1_24 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 0) +#define TMS570_BALL_P1_MIBSPI1NCS_5 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P1, 1), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI1NCS_5, 1)) +#define TMS570_BALL_P1_MII_RXD_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_P1, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_0, 1)) +#define TMS570_BALL_P1_RMII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 3) + +#define TMS570_BALL_A14 TMS570_BALL_WITH_MMR(34, 0) +#define TMS570_BALL_A14_HET1_26 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 0) +#define TMS570_BALL_A14_MII_RXD_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A14, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXD_1, 1)) +#define TMS570_BALL_A14_RMII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 3) + +#define TMS570_BALL_K19 TMS570_BALL_WITH_MMR(34, 1) +#define TMS570_BALL_K19_HET1_28 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 0) +#define TMS570_BALL_K19_MII_RXCLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K19, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXCLK, 1)) +#define TMS570_BALL_K19_RMII_REFCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 3) + +#define TMS570_BALL_B11 TMS570_BALL_WITH_MMR(34, 2) +#define TMS570_BALL_B11_HET1_30 TMS570_PIN_AND_FNC(TMS570_BALL_B11, 0) +#define TMS570_BALL_B11_MII_RX_DV TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B11, 2), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RX_DV, 1)) +#define TMS570_BALL_B11_eQEP2S TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B11, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2S, 1)) + +#define TMS570_BALL_D8 TMS570_BALL_WITH_MMR(34, 3) +#define TMS570_BALL_D8_HET2_01 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D8, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_01, 0)) + +#define TMS570_BALL_D7 TMS570_BALL_WITH_MMR(35, 0) +#define TMS570_BALL_D7_HET2_02 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D7, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_02, 0)) + +#define TMS570_BALL_D3 TMS570_BALL_WITH_MMR(35, 1) +#define TMS570_BALL_D3_HET2_12 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_12, 0)) +#define TMS570_BALL_D3_MIBSPI2NENA TMS570_PIN_AND_FNC(TMS570_BALL_D3, 4) +#define TMS570_BALL_D3_MIBSPI2NCS_1 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D3, 5), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MIBSPI2NCS_1, 1)) + +#define TMS570_BALL_D2 TMS570_BALL_WITH_MMR(35, 2) +#define TMS570_BALL_D2_HET2_13 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_13, 0)) +#define TMS570_BALL_D2_MIBSPI2SOMI TMS570_PIN_AND_FNC(TMS570_BALL_D2, 4) + +#define TMS570_BALL_D1 TMS570_BALL_WITH_MMR(35, 3) +#define TMS570_BALL_D1_HET2_14 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_D1, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_14, 0)) +#define TMS570_BALL_D1_MIBSPI2SIMO TMS570_PIN_AND_FNC(TMS570_BALL_D1, 4) + +#define TMS570_BALL_P4 TMS570_BALL_WITH_MMR(36, 0) +#define TMS570_BALL_P4_HET2_19 TMS570_PIN_AND_FNC(TMS570_BALL_P4, 0) +#define TMS570_BALL_P4_LIN2RX TMS570_PIN_AND_FNC(TMS570_BALL_P4, 1) + +#define TMS570_BALL_T5 TMS570_BALL_WITH_MMR(36, 1) +#define TMS570_BALL_T5_HET2_20 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T5, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_20, 0)) +#define TMS570_BALL_T5_LIN2TX TMS570_PIN_AND_FNC(TMS570_BALL_T5, 1) + +#define TMS570_BALL_T4 TMS570_BALL_WITH_MMR(36, 2) +#define TMS570_BALL_T4_MII_RXCLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_T4, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_RXCLK, 0)) + +#define TMS570_BALL_U7 TMS570_BALL_WITH_MMR(36, 3) +#define TMS570_BALL_U7_MII_TX_CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U7, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_MII_TX_CLK, 0)) + +#define TMS570_BALL_E2 TMS570_BALL_WITH_MMR(37, 0) +#define TMS570_BALL_E2_HET2_03 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_E2, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_03, 0)) +#define TMS570_BALL_E2_MIBSPI2CLK TMS570_PIN_AND_FNC(TMS570_BALL_E2, 4) + +#define TMS570_BALL_N3 TMS570_BALL_WITH_MMR(37, 1) +#define TMS570_BALL_N3_HET2_07 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_N3, 0), \ + TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 0)) +#define TMS570_BALL_N3_MIBSPI2NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N3, 4) + +/* Default pinmux select */ + +#define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ + per_pin_action(common_arg, TMS570_BALL_N19_AD1EVT) \ + per_pin_action(common_arg, TMS570_BALL_D4_EMIF_ADDR_00) \ + per_pin_action(common_arg, TMS570_BALL_D5_EMIF_ADDR_01) \ + per_pin_action(common_arg, TMS570_BALL_C4_EMIF_ADDR_06) \ + per_pin_action(common_arg, TMS570_BALL_C5_EMIF_ADDR_07) \ + per_pin_action(common_arg, TMS570_BALL_C6_EMIF_ADDR_08) \ + per_pin_action(common_arg, TMS570_BALL_C7_EMIF_ADDR_09) \ + per_pin_action(common_arg, TMS570_BALL_C8_EMIF_ADDR_10) \ + per_pin_action(common_arg, TMS570_BALL_C9_EMIF_ADDR_11) \ + per_pin_action(common_arg, TMS570_BALL_C10_EMIF_ADDR_12) \ + per_pin_action(common_arg, TMS570_BALL_C11_EMIF_ADDR_13) \ + per_pin_action(common_arg, TMS570_BALL_C12_EMIF_ADDR_14) \ + per_pin_action(common_arg, TMS570_BALL_C13_EMIF_ADDR_15) \ + per_pin_action(common_arg, TMS570_BALL_D14_EMIF_ADDR_16) \ + per_pin_action(common_arg, TMS570_BALL_C14_EMIF_ADDR_17) \ + per_pin_action(common_arg, TMS570_BALL_D15_EMIF_ADDR_18) \ + per_pin_action(common_arg, TMS570_BALL_C15_EMIF_ADDR_19) \ + per_pin_action(common_arg, TMS570_BALL_C16_EMIF_ADDR_20) \ + per_pin_action(common_arg, TMS570_BALL_C17_EMIF_ADDR_21) \ + per_pin_action(common_arg, TMS570_BALL_D16_EMIF_BA_1) \ + per_pin_action(common_arg, TMS570_BALL_R4_EMIF_nCAS) \ + per_pin_action(common_arg, TMS570_BALL_N17_EMIF_nCS_0) \ + per_pin_action(common_arg, TMS570_BALL_L17_EMIF_nCS_2) \ + per_pin_action(common_arg, TMS570_BALL_K17_EMIF_nCS_3) \ + per_pin_action(common_arg, TMS570_BALL_M17_EMIF_nCSl_4) \ + per_pin_action(common_arg, TMS570_BALL_R3_EMIF_nRAS) \ + per_pin_action(common_arg, TMS570_BALL_P3_EMIF_nWAIT) \ + per_pin_action(common_arg, TMS570_BALL_D17_EMIF_nWE) \ + per_pin_action(common_arg, TMS570_BALL_E9_ETMDATA_08) \ + per_pin_action(common_arg, TMS570_BALL_E8_ETMDATA_09) \ + per_pin_action(common_arg, TMS570_BALL_E7_ETMDATA_10) \ + per_pin_action(common_arg, TMS570_BALL_E6_ETMDATA_11) \ + per_pin_action(common_arg, TMS570_BALL_E13_ETMDATA_12) \ + per_pin_action(common_arg, TMS570_BALL_E12_ETMDATA_13) \ + per_pin_action(common_arg, TMS570_BALL_E11_ETMDATA_14) \ + per_pin_action(common_arg, TMS570_BALL_E10_ETMDATA_15) \ + per_pin_action(common_arg, TMS570_BALL_K15_ETMDATA_16) \ + per_pin_action(common_arg, TMS570_BALL_L15_ETMDATA_17) \ + per_pin_action(common_arg, TMS570_BALL_M15_ETMDATA_18) \ + per_pin_action(common_arg, TMS570_BALL_N15_ETMDATA_19) \ + per_pin_action(common_arg, TMS570_BALL_E5_ETMDATA_20) \ + per_pin_action(common_arg, TMS570_BALL_F5_ETMDATA_21) \ + per_pin_action(common_arg, TMS570_BALL_G5_ETMDATA_22) \ + per_pin_action(common_arg, TMS570_BALL_K5_ETMDATA_23) \ + per_pin_action(common_arg, TMS570_BALL_L5_ETMDATA_24) \ + per_pin_action(common_arg, TMS570_BALL_M5_ETMDATA_25) \ + per_pin_action(common_arg, TMS570_BALL_N5_ETMDATA_26) \ + per_pin_action(common_arg, TMS570_BALL_P5_ETMDATA_27) \ + per_pin_action(common_arg, TMS570_BALL_R5_ETMDATA_28) \ + per_pin_action(common_arg, TMS570_BALL_R6_ETMDATA_29) \ + per_pin_action(common_arg, TMS570_BALL_R7_ETMDATA_30) \ + per_pin_action(common_arg, TMS570_BALL_R8_ETMDATA_31) \ + per_pin_action(common_arg, TMS570_BALL_R9_ETMTRACECLKIN) \ + per_pin_action(common_arg, TMS570_BALL_R10_ETMTRACECLKOUT) \ + per_pin_action(common_arg, TMS570_BALL_R11_ETMTRACECTL) \ + per_pin_action(common_arg, TMS570_BALL_B15_FRAYTX1) \ + per_pin_action(common_arg, TMS570_BALL_B8_FRAYTX2) \ + per_pin_action(common_arg, TMS570_BALL_B16_FRAYTXEN1) \ + per_pin_action(common_arg, TMS570_BALL_B9_FRAYTXEN2) \ + per_pin_action(common_arg, TMS570_BALL_C1_GIOA_2) \ + per_pin_action(common_arg, TMS570_BALL_E1_GIOA_3) \ + per_pin_action(common_arg, TMS570_BALL_B5_GIOA_5) \ + per_pin_action(common_arg, TMS570_BALL_H3_GIOA_6) \ + per_pin_action(common_arg, TMS570_BALL_M1_GIOA_7) \ + per_pin_action(common_arg, TMS570_BALL_F2_GIOB_2) \ + per_pin_action(common_arg, TMS570_BALL_W10_GIOB_3) \ + per_pin_action(common_arg, TMS570_BALL_J2_GIOB_6) \ + per_pin_action(common_arg, TMS570_BALL_F1_GIOB_7) \ + per_pin_action(common_arg, TMS570_BALL_R2_MIBSPI1NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_F3_MIBSPI1NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_G3_MIBSPI1NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_J3_MIBSPI1NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_G19_MIBSPI1NENA) \ + per_pin_action(common_arg, TMS570_BALL_V9_MIBSPI3CLK) \ + per_pin_action(common_arg, TMS570_BALL_V10_MIBSPI3NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_V5_MIBSPI3NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_B2_MIBSPI3NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_C3_MIBSPI3NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_W9_MIBSPI3NENA) \ + per_pin_action(common_arg, TMS570_BALL_W8_MIBSPI3SIMO) \ + per_pin_action(common_arg, TMS570_BALL_V8_MIBSPI3SOMI) \ + per_pin_action(common_arg, TMS570_BALL_H19_MIBSPI5CLK) \ + per_pin_action(common_arg, TMS570_BALL_E19_MIBSPI5NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_B6_MIBSPI5NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_W6_MIBSPI5NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_T12_MIBSPI5NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_H18_MIBSPI5NENA) \ + per_pin_action(common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0) \ + per_pin_action(common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1) \ + per_pin_action(common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2) \ + per_pin_action(common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3) \ + per_pin_action(common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0) \ + per_pin_action(common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1) \ + per_pin_action(common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2) \ + per_pin_action(common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3) \ + per_pin_action(common_arg, TMS570_BALL_K18_HET1_00) \ + per_pin_action(common_arg, TMS570_BALL_V2_HET1_01) \ + per_pin_action(common_arg, TMS570_BALL_W5_HET1_02) \ + per_pin_action(common_arg, TMS570_BALL_U1_HET1_03) \ + per_pin_action(common_arg, TMS570_BALL_B12_HET1_04) \ + per_pin_action(common_arg, TMS570_BALL_V6_HET1_05) \ + per_pin_action(common_arg, TMS570_BALL_W3_HET1_06) \ + per_pin_action(common_arg, TMS570_BALL_T1_HET1_07) \ + per_pin_action(common_arg, TMS570_BALL_E18_HET1_08) \ + per_pin_action(common_arg, TMS570_BALL_V7_HET1_09) \ + per_pin_action(common_arg, TMS570_BALL_D19_HET1_10) \ + per_pin_action(common_arg, TMS570_BALL_E3_HET1_11) \ + per_pin_action(common_arg, TMS570_BALL_B4_HET1_12) \ + per_pin_action(common_arg, TMS570_BALL_N2_HET1_13) \ + per_pin_action(common_arg, TMS570_BALL_N1_HET1_15) \ + per_pin_action(common_arg, TMS570_BALL_A4_HET1_16) \ + per_pin_action(common_arg, TMS570_BALL_A13_HET1_17) \ + per_pin_action(common_arg, TMS570_BALL_J1_HET1_18) \ + per_pin_action(common_arg, TMS570_BALL_B13_HET1_19) \ + per_pin_action(common_arg, TMS570_BALL_P2_HET1_20) \ + per_pin_action(common_arg, TMS570_BALL_H4_HET1_21) \ + per_pin_action(common_arg, TMS570_BALL_B3_HET1_22) \ + per_pin_action(common_arg, TMS570_BALL_J4_HET1_23) \ + per_pin_action(common_arg, TMS570_BALL_P1_HET1_24) \ + per_pin_action(common_arg, TMS570_BALL_A14_HET1_26) \ + per_pin_action(common_arg, TMS570_BALL_K19_HET1_28) \ + per_pin_action(common_arg, TMS570_BALL_B11_HET1_30) \ + per_pin_action(common_arg, TMS570_BALL_D8_HET2_01) \ + per_pin_action(common_arg, TMS570_BALL_D7_HET2_02) \ + per_pin_action(common_arg, TMS570_BALL_D3_HET2_12) \ + per_pin_action(common_arg, TMS570_BALL_D2_HET2_13) \ + per_pin_action(common_arg, TMS570_BALL_D1_HET2_14) \ + per_pin_action(common_arg, TMS570_BALL_P4_HET2_19) \ + per_pin_action(common_arg, TMS570_BALL_T5_HET2_20) \ + per_pin_action(common_arg, TMS570_BALL_T4_MII_RXCLK) \ + per_pin_action(common_arg, TMS570_BALL_U7_MII_TX_CLK) \ + per_pin_action(common_arg, TMS570_BALL_E2_HET2_03) \ + per_pin_action(common_arg, TMS570_BALL_N3_HET2_07) \ + +/* End of default PINMMR list */ + +#endif /*LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H*/ diff --git a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h new file mode 100644 index 0000000000..63c08e8ddb --- /dev/null +++ b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h @@ -0,0 +1,690 @@ +/** + * @file tms570ls3137zwt-pins.h + * + * @ingroup tms570 + * + * @brief Specification of individual pins mapping to the package + */ + +/* + * Copyright (c) 2015 Pavel Pisa + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H +#define LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H + +#define TMS570_BALL_W10 TMS570_BALL_WITH_MMR(0, 0) +#define TMS570_BALL_W10_GIOB_3 TMS570_PIN_AND_FNC(TMS570_BALL_W10, 0) + +#define TMS570_BALL_A5 TMS570_BALL_WITH_MMR(0, 1) +#define TMS570_BALL_A5_GIOA_0 TMS570_PIN_AND_FNC(TMS570_BALL_A5, 0) + +#define TMS570_BALL_C3 TMS570_BALL_WITH_MMR(0, 2) +#define TMS570_BALL_C3_MIBSPI3NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_C3, 0) +#define TMS570_BALL_C3_I2C_SCL TMS570_PIN_AND_FNC(TMS570_BALL_C3, 1) +#define TMS570_BALL_C3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A3, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B2 TMS570_BALL_WITH_MMR(0, 3) +#define TMS570_BALL_B2_MIBSPI3NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_B2, 0) +#define TMS570_BALL_B2_I2C_SDA TMS570_PIN_AND_FNC(TMS570_BALL_B2, 1) +#define TMS570_BALL_B2_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A9, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_C2 TMS570_BALL_WITH_MMR(1, 0) +#define TMS570_BALL_C2_GIOA_1 TMS570_PIN_AND_FNC(TMS570_BALL_C2, 0) + +#define TMS570_BALL_E3 TMS570_BALL_WITH_MMR(1, 1) +#define TMS570_BALL_E3_HET1_11 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 0) +#define TMS570_BALL_E3_MIBSPI3NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 1) +#define TMS570_BALL_E3_HET2_18 TMS570_PIN_AND_FNC(TMS570_BALL_E3, 2) + +#define TMS570_BALL_E5 TMS570_BALL_WITH_MMR(1, 2) +#define TMS570_BALL_E5_ETMDATA_20 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 0) +#define TMS570_BALL_E5_EMIF_DATA_4 TMS570_PIN_AND_FNC(TMS570_BALL_E5, 1) + +#define TMS570_BALL_F5 TMS570_BALL_WITH_MMR(1, 3) +#define TMS570_BALL_F5_ETMDATA_21 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 0) +#define TMS570_BALL_F5_EMIF_DATA_5 TMS570_PIN_AND_FNC(TMS570_BALL_F5, 1) + +#define TMS570_BALL_C1 TMS570_BALL_WITH_MMR(2, 0) +#define TMS570_BALL_C1_GIOA_2 TMS570_PIN_AND_FNC(TMS570_BALL_C1, 0) +#define TMS570_BALL_C1_HET2_00 TMS570_PIN_AND_FNC(TMS570_BALL_C1, 3) + +#define TMS570_BALL_G5 TMS570_BALL_WITH_MMR(2, 1) +#define TMS570_BALL_G5_ETMDATA_22 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 0) +#define TMS570_BALL_G5_EMIF_DATA_6 TMS570_PIN_AND_FNC(TMS570_BALL_G5, 1) + +#define TMS570_BALL_E1 TMS570_BALL_WITH_MMR(2, 2) +#define TMS570_BALL_E1_GIOA_3 TMS570_PIN_AND_FNC(TMS570_BALL_E1, 0) +#define TMS570_BALL_E1_HET2_02 TMS570_PIN_AND_FNC(TMS570_BALL_E1, 1) + +#define TMS570_BALL_B5 TMS570_BALL_WITH_MMR(2, 3) +#define TMS570_BALL_B5_GIOA_5 TMS570_PIN_AND_FNC(TMS570_BALL_B5, 0) +#define TMS570_BALL_B5_EXTCLKIN TMS570_PIN_AND_FNC(TMS570_BALL_B5, 1) + +#define TMS570_BALL_K5 TMS570_BALL_WITH_MMR(3, 0) +#define TMS570_BALL_K5_ETMDATA_23 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 0) +#define TMS570_BALL_K5_EMIF_DATA_7 TMS570_PIN_AND_FNC(TMS570_BALL_K5, 1) + +#define TMS570_BALL_B3 TMS570_BALL_WITH_MMR(3, 1) +#define TMS570_BALL_B3_HET1_22 TMS570_PIN_AND_FNC(TMS570_BALL_B3, 0) + +#define TMS570_BALL_H3 TMS570_BALL_WITH_MMR(3, 2) +#define TMS570_BALL_H3_GIOA_6 TMS570_PIN_AND_FNC(TMS570_BALL_H3, 0) +#define TMS570_BALL_H3_HET2_04 TMS570_PIN_AND_FNC(TMS570_BALL_H3, 1) + +#define TMS570_BALL_L5 TMS570_BALL_WITH_MMR(3, 3) +#define TMS570_BALL_L5_ETMDATA_24 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 0) +#define TMS570_BALL_L5_EMIF_DATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_L5, 1) + +#define TMS570_BALL_M1 TMS570_BALL_WITH_MMR(4, 0) +#define TMS570_BALL_M1_GIOA_7 TMS570_PIN_AND_FNC(TMS570_BALL_M1, 0) +#define TMS570_BALL_M1_HET2_06 TMS570_PIN_AND_FNC(TMS570_BALL_M1, 1) + +#define TMS570_BALL_M5 TMS570_BALL_WITH_MMR(4, 1) +#define TMS570_BALL_M5_ETMDATA_25 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 0) +#define TMS570_BALL_M5_EMIF_DATA_9 TMS570_PIN_AND_FNC(TMS570_BALL_M5, 1) + +#define TMS570_BALL_V2 TMS570_BALL_WITH_MMR(4, 2) +#define TMS570_BALL_V2_HET1_01 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 0) +#define TMS570_BALL_V2_SPI4NENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 0), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V2_HET2_08 TMS570_PIN_AND_FNC(TMS570_BALL_V2, 4) + +#define TMS570_BALL_U1 TMS570_BALL_WITH_MMR(4, 3) +#define TMS570_BALL_U1_HET1_03 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 0) +#define TMS570_BALL_U1_SPI4NCS_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 1), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_U1_HET2_10 TMS570_PIN_AND_FNC(TMS570_BALL_U1, 4) + +#define TMS570_BALL_K18 TMS570_BALL_WITH_MMR(5, 0) +#define TMS570_BALL_K18_HET1_00 TMS570_PIN_AND_FNC(TMS570_BALL_K18, 0) +#define TMS570_BALL_K18_SPI4CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 1), 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_W5 TMS570_BALL_WITH_MMR(5, 1) +#define TMS570_BALL_W5_HET1_02 TMS570_PIN_AND_FNC(TMS570_BALL_W5, 0) +#define TMS570_BALL_W5_SPI4SIMO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 2), 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_V6 TMS570_BALL_WITH_MMR(5, 2) +#define TMS570_BALL_V6_HET1_05 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 0) +#define TMS570_BALL_V6_SPI4SOMI TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 3), 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V6_HET2_12 TMS570_PIN_AND_FNC(TMS570_BALL_V6, 2) + +#define TMS570_BALL_N5 TMS570_BALL_WITH_MMR(5, 3) +#define TMS570_BALL_N5_ETMDATA_26 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 0) +#define TMS570_BALL_N5_EMIF_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_N5, 1) + +#define TMS570_BALL_T1 TMS570_BALL_WITH_MMR(6, 0) +#define TMS570_BALL_T1_HET1_07 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 0) +#define TMS570_BALL_T1_HET2_14 TMS570_PIN_AND_FNC(TMS570_BALL_T1, 3) + +#define TMS570_BALL_P5 TMS570_BALL_WITH_MMR(6, 1) +#define TMS570_BALL_P5_ETMDATA_27 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 0) +#define TMS570_BALL_P5_EMIF_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_P5, 1) + +#define TMS570_BALL_V7 TMS570_BALL_WITH_MMR(6, 2) +#define TMS570_BALL_V7_HET1_09 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 0) +#define TMS570_BALL_V7_HET2_16 TMS570_PIN_AND_FNC(TMS570_BALL_V7, 1) + +#define TMS570_BALL_R5 TMS570_BALL_WITH_MMR(6, 3) +#define TMS570_BALL_R5_ETMDATA_28 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 0) +#define TMS570_BALL_R5_EMIF_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_R5, 1) + +#define TMS570_BALL_R6 TMS570_BALL_WITH_MMR(7, 0) +#define TMS570_BALL_R6_ETMDATA_29 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 0) +#define TMS570_BALL_R6_EMIF_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_R6, 1) + +#define TMS570_BALL_V5 TMS570_BALL_WITH_MMR(7, 1) +#define TMS570_BALL_V5_MIBSPI3NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_V5, 0) +#define TMS570_BALL_V5_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_M3, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_V5_MDCLK TMS570_PIN_AND_FNC(TMS570_BALL_V5, 2) + +#define TMS570_BALL_W3 TMS570_BALL_WITH_MMR(7, 2) +#define TMS570_BALL_W3_HET1_06 TMS570_PIN_AND_FNC(TMS570_BALL_W3, 0) +#define TMS570_BALL_W3_SCIRX TMS570_PIN_AND_FNC(TMS570_BALL_W3, 1) + +#define TMS570_BALL_R7 TMS570_BALL_WITH_MMR(7, 3) +#define TMS570_BALL_R7_ETMDATA_30 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 0) +#define TMS570_BALL_R7_EMIF_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_R7, 1) + +#define TMS570_BALL_N2 TMS570_BALL_WITH_MMR(8, 0) +#define TMS570_BALL_N2_HET1_13 TMS570_PIN_AND_FNC(TMS570_BALL_N2, 0) +#define TMS570_BALL_N2_SCITX TMS570_PIN_AND_FNC(TMS570_BALL_N2, 1) + +#define TMS570_BALL_G3 TMS570_BALL_WITH_MMR(8, 1) +#define TMS570_BALL_G3_MIBSPI1NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_G3, 0) +#define TMS570_BALL_G3_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_G3_MDIO TMS570_PIN_AND_FNC(TMS570_BALL_G3, 2) + +#define TMS570_BALL_N1 TMS570_BALL_WITH_MMR(8, 2) +#define TMS570_BALL_N1_HET1_15 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 0) +#define TMS570_BALL_N1_MIBSPI1NCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_N1, 1) + +#define TMS570_BALL_R8 TMS570_BALL_WITH_MMR(8, 3) +#define TMS570_BALL_R8_ETMDATA_31 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 0) +#define TMS570_BALL_R8_EMIF_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_R8, 1) + +#define TMS570_BALL_R9 TMS570_BALL_WITH_MMR(9, 0) +#define TMS570_BALL_R9_ETMTRACECLKIN TMS570_PIN_AND_FNC(TMS570_BALL_R9, 0) +#define TMS570_BALL_R9_EXTCLKIN2 TMS570_PIN_AND_FNC(TMS570_BALL_R9, 1) + +#define TMS570_BALL_W9 TMS570_BALL_WITH_MMR(9, 1) +#define TMS570_BALL_W9_MIBSPI3NENA TMS570_PIN_AND_FNC(TMS570_BALL_W9, 0) +#define TMS570_BALL_W9_MIBSPI3NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_W9, 1) +#define TMS570_BALL_W9_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 2), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J17, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_V10 TMS570_BALL_WITH_MMR(9, 2) +#define TMS570_BALL_V10_MIBSPI3NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_V10, 0) +#define TMS570_BALL_V10_AD2EVT TMS570_PIN_AND_FNC(TMS570_BALL_V10, 1) + +#define TMS570_BALL_J3 TMS570_BALL_WITH_MMR(9, 3) +#define TMS570_BALL_J3_MIBSPI1NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_J3, 0) +#define TMS570_BALL_J3_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_N19 TMS570_BALL_WITH_MMR(10, 0) +#define TMS570_BALL_N19_AD1EVT TMS570_PIN_AND_FNC(TMS570_BALL_N19, 0) +#define TMS570_BALL_N19_MII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 1) +#define TMS570_BALL_N19_RMII_RX_ER TMS570_PIN_AND_FNC(TMS570_BALL_N19, 2) + +#define TMS570_BALL_N15 TMS570_BALL_WITH_MMR(10, 1) +#define TMS570_BALL_N15_ETMDATA_19 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 0) +#define TMS570_BALL_N15_EMIF_DATA_3 TMS570_PIN_AND_FNC(TMS570_BALL_N15, 1) + +#define TMS570_BALL_N17 TMS570_BALL_WITH_MMR(10, 2) +#define TMS570_BALL_N17_EMIF_nCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 0) +#define TMS570_BALL_N17_RTP_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 1) +#define TMS570_BALL_N17_HET2_07 TMS570_PIN_AND_FNC(TMS570_BALL_N17, 2) + +#define TMS570_BALL_M15 TMS570_BALL_WITH_MMR(10, 3) +#define TMS570_BALL_M15_ETMDATA_18 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 0) +#define TMS570_BALL_M15_EMIF_DATA_2 TMS570_PIN_AND_FNC(TMS570_BALL_M15, 1) + +#define TMS570_BALL_K17 TMS570_BALL_WITH_MMR(11, 0) +#define TMS570_BALL_K17_EMIF_nCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 0) +#define TMS570_BALL_K17_RTP_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 1) +#define TMS570_BALL_K17_HET2_09 TMS570_PIN_AND_FNC(TMS570_BALL_K17, 2) + +#define TMS570_BALL_M17 TMS570_BALL_WITH_MMR(11, 1) +#define TMS570_BALL_M17_EMIF_nCS_4 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 0) +#define TMS570_BALL_M17_RTP_DATA_07 TMS570_PIN_AND_FNC(TMS570_BALL_M17, 1) + +#define TMS570_BALL_L15 TMS570_BALL_WITH_MMR(11, 2) +#define TMS570_BALL_L15_ETMDATA_17 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 0) +#define TMS570_BALL_L15_EMIF_DATA_1 TMS570_PIN_AND_FNC(TMS570_BALL_L15, 1) + +#define TMS570_BALL_P1 TMS570_BALL_WITH_MMR(11, 3) +#define TMS570_BALL_P1_HET1_24 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 0) +#define TMS570_BALL_P1_MIBSPI1NCS_5 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 1) +#define TMS570_BALL_P1_MII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 2) +#define TMS570_BALL_P1_RMII_RXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_P1, 3) + +#define TMS570_BALL_A14 TMS570_BALL_WITH_MMR(12, 0) +#define TMS570_BALL_A14_HET1_26 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 0) +#define TMS570_BALL_A14_MII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 1) +#define TMS570_BALL_A14_RMII_RXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_A14, 2) + +#define TMS570_BALL_K15 TMS570_BALL_WITH_MMR(12, 1) +#define TMS570_BALL_K15_ETMDATA_16 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 0) +#define TMS570_BALL_K15_EMIF_DATA_0 TMS570_PIN_AND_FNC(TMS570_BALL_K15, 1) + +#define TMS570_BALL_G19 TMS570_BALL_WITH_MMR(12, 2) +#define TMS570_BALL_G19_MIBSPI1NENA TMS570_PIN_AND_FNC(TMS570_BALL_G19, 0) +#define TMS570_BALL_G19_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_G19_MII_RXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_G19, 2) + +#define TMS570_BALL_H18 TMS570_BALL_WITH_MMR(12, 3) +#define TMS570_BALL_H18_MIBSPI5NENA TMS570_PIN_AND_FNC(TMS570_BALL_H18, 0) +#define TMS570_BALL_H18_DMM_DATA_7 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 1) +#define TMS570_BALL_H18_MII_RXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_H18, 2) + +#define TMS570_BALL_J18 TMS570_BALL_WITH_MMR(13, 0) +#define TMS570_BALL_J18_MIBSPI5SOMI_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 0) +#define TMS570_BALL_J18_DMM_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 1) +#define TMS570_BALL_J18_MII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 2) +#define TMS570_BALL_J18_RMII_TXD_0 TMS570_PIN_AND_FNC(TMS570_BALL_J18, 3) + +#define TMS570_BALL_J19 TMS570_BALL_WITH_MMR(13, 1) +#define TMS570_BALL_J19_MIBSPI5SIMO_0 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 0) +#define TMS570_BALL_J19_DMM_DATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 1) +#define TMS570_BALL_J19_MII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 2) +#define TMS570_BALL_J19_RMII_TXD_1 TMS570_PIN_AND_FNC(TMS570_BALL_J19, 3) + +#define TMS570_BALL_H19 TMS570_BALL_WITH_MMR(13, 2) +#define TMS570_BALL_H19_MIBSPI5CLK TMS570_PIN_AND_FNC(TMS570_BALL_H19, 0) +#define TMS570_BALL_H19_DMM_DATA_4 TMS570_PIN_AND_FNC(TMS570_BALL_H19, 1) +#define TMS570_BALL_H19_MII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 2) +#define TMS570_BALL_H19_RMII_TXEN TMS570_PIN_AND_FNC(TMS570_BALL_H19, 3) + +#define TMS570_BALL_R2 TMS570_BALL_WITH_MMR(13, 3) +#define TMS570_BALL_R2_MIBSPI1NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 0) +#define TMS570_BALL_R2_MIBSPI1SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 1) +#define TMS570_BALL_R2_MII_TXD_2 TMS570_PIN_AND_FNC(TMS570_BALL_R2, 2) + +#define TMS570_BALL_E18 TMS570_BALL_WITH_MMR(14, 0) +#define TMS570_BALL_E18_HET1_08 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 0) +#define TMS570_BALL_E18_MIBSPI1SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 1) +#define TMS570_BALL_E18_MII_TXD_3 TMS570_PIN_AND_FNC(TMS570_BALL_E18, 2) + +#define TMS570_BALL_K19 TMS570_BALL_WITH_MMR(14, 1) +#define TMS570_BALL_K19_HET1_28 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 0) +#define TMS570_BALL_K19_MII_RXCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 1) +#define TMS570_BALL_K19_RMII_REFCLK TMS570_PIN_AND_FNC(TMS570_BALL_K19, 2) +#define TMS570_BALL_K19_MII_RX_AVCLK4 TMS570_PIN_AND_FNC(TMS570_BALL_K19, 3) + +#define TMS570_BALL_D17 TMS570_BALL_WITH_MMR(14, 2) +#define TMS570_BALL_D17_EMIF_nWE TMS570_PIN_AND_FNC(TMS570_BALL_D17, 0) +#define TMS570_BALL_D17_EMIF_RNW TMS570_PIN_AND_FNC(TMS570_BALL_D17, 1) + +#define TMS570_BALL_D16 TMS570_BALL_WITH_MMR(14, 3) +#define TMS570_BALL_D16_EMIF_BA_1 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 0) +#define TMS570_BALL_D16_HET2_05 TMS570_PIN_AND_FNC(TMS570_BALL_D16, 1) + +#define TMS570_BALL_C17 TMS570_BALL_WITH_MMR(15, 0) +#define TMS570_BALL_C17_EMIF_ADDR_21 TMS570_PIN_AND_FNC(TMS570_BALL_C17, 0) +#define TMS570_BALL_C17_RTP_CLK TMS570_PIN_AND_FNC(TMS570_BALL_C17, 1) + +#define TMS570_BALL_C16 TMS570_BALL_WITH_MMR(15, 1) +#define TMS570_BALL_C16_EMIF_ADDR_20 TMS570_PIN_AND_FNC(TMS570_BALL_C16, 0) +#define TMS570_BALL_C16_RTP_nSYNC TMS570_PIN_AND_FNC(TMS570_BALL_C16, 1) + +#define TMS570_BALL_C15 TMS570_BALL_WITH_MMR(15, 2) +#define TMS570_BALL_C15_EMIF_ADDR_19 TMS570_PIN_AND_FNC(TMS570_BALL_C15, 0) +#define TMS570_BALL_C15_RTP_nENA TMS570_PIN_AND_FNC(TMS570_BALL_C15, 1) + +#define TMS570_BALL_D15 TMS570_BALL_WITH_MMR(15, 3) +#define TMS570_BALL_D15_EMIF_ADDR_18 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 0) +#define TMS570_BALL_D15_RTP_DATA_0 TMS570_PIN_AND_FNC(TMS570_BALL_D15, 1) + +#define TMS570_BALL_E13 TMS570_BALL_WITH_MMR(16, 0) +#define TMS570_BALL_E13_ETMDATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 0) +#define TMS570_BALL_E13_EMIF_BA_0 TMS570_PIN_AND_FNC(TMS570_BALL_E13, 1) + +#define TMS570_BALL_C14 TMS570_BALL_WITH_MMR(16, 1) +#define TMS570_BALL_C14_EMIF_ADDR_17 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 0) +#define TMS570_BALL_C14_RTP_DATA_01 TMS570_PIN_AND_FNC(TMS570_BALL_C14, 1) + +#define TMS570_BALL_D14 TMS570_BALL_WITH_MMR(16, 2) +#define TMS570_BALL_D14_EMIF_ADDR_16 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 0) +#define TMS570_BALL_D14_RTP_DATA_02 TMS570_PIN_AND_FNC(TMS570_BALL_D14, 1) + +#define TMS570_BALL_E12 TMS570_BALL_WITH_MMR(16, 3) +#define TMS570_BALL_E12_ETMDATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E12, 0) +#define TMS570_BALL_E12_EMIF_nOE TMS570_PIN_AND_FNC(TMS570_BALL_E12, 1) + +#define TMS570_BALL_D19 TMS570_BALL_WITH_MMR(17, 0) +#define TMS570_BALL_D19_HET1_10 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 0) +#define TMS570_BALL_D19_MII_TX_CLK TMS570_PIN_AND_FNC(TMS570_BALL_D19, 1) +#define TMS570_BALL_D19_MII_TX_AVCLK4 TMS570_PIN_AND_FNC(TMS570_BALL_D19, 3) + +#define TMS570_BALL_E11 TMS570_BALL_WITH_MMR(17, 1) +#define TMS570_BALL_E11_ETMDATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 0) +#define TMS570_BALL_E11_EMIF_nDQM_1 TMS570_PIN_AND_FNC(TMS570_BALL_E11, 1) + +#define TMS570_BALL_B4 TMS570_BALL_WITH_MMR(17, 2) +#define TMS570_BALL_B4_HET1_12 TMS570_PIN_AND_FNC(TMS570_BALL_B4, 0) +#define TMS570_BALL_B4_MII_CRS TMS570_PIN_AND_FNC(TMS570_BALL_B4, 1) +#define TMS570_BALL_B4_RMII_CRS_DV TMS570_PIN_AND_FNC(TMS570_BALL_B4, 2) + +#define TMS570_BALL_E9 TMS570_BALL_WITH_MMR(17, 3) +#define TMS570_BALL_E9_ETMDATA_8 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 0) +#define TMS570_BALL_E9_EMIF_ADDR_5 TMS570_PIN_AND_FNC(TMS570_BALL_E9, 1) + +#define TMS570_BALL_C13 TMS570_BALL_WITH_MMR(18, 0) +#define TMS570_BALL_C13_EMIF_ADDR_15 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 0) +#define TMS570_BALL_C13_RTP_DATA_03 TMS570_PIN_AND_FNC(TMS570_BALL_C13, 1) + +#define TMS570_BALL_A11 TMS570_BALL_WITH_MMR(18, 1) +#define TMS570_BALL_A11_HET1_14 TMS570_PIN_AND_FNC(TMS570_BALL_A11, 0) + +#define TMS570_BALL_C12 TMS570_BALL_WITH_MMR(18, 2) +#define TMS570_BALL_C12_EMIF_ADDR_14 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 0) +#define TMS570_BALL_C12_RTP_DATA_04 TMS570_PIN_AND_FNC(TMS570_BALL_C12, 1) + +#define TMS570_BALL_M2 TMS570_BALL_WITH_MMR(18, 3) +#define TMS570_BALL_M2_GIOB_0 TMS570_PIN_AND_FNC(TMS570_BALL_M2, 0) + +#define TMS570_BALL_E8 TMS570_BALL_WITH_MMR(19, 0) +#define TMS570_BALL_E8_ETMDATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 0) +#define TMS570_BALL_E8_EMIF_ADDR_4 TMS570_PIN_AND_FNC(TMS570_BALL_E8, 1) + +#define TMS570_BALL_B11 TMS570_BALL_WITH_MMR(19, 1) +#define TMS570_BALL_B11_HET1_30 TMS570_PIN_AND_FNC(TMS570_BALL_B11, 0) +#define TMS570_BALL_B11_MII_RX_DV TMS570_PIN_AND_FNC(TMS570_BALL_B11, 1) + +#define TMS570_BALL_E10 TMS570_BALL_WITH_MMR(19, 2) +#define TMS570_BALL_E10_ETMDATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 0) +#define TMS570_BALL_E10_EMIF_nDQM_0 TMS570_PIN_AND_FNC(TMS570_BALL_E10, 1) + +#define TMS570_BALL_E7 TMS570_BALL_WITH_MMR(19, 3) +#define TMS570_BALL_E7_ETMDATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 0) +#define TMS570_BALL_E7_EMIF_ADDR_3 TMS570_PIN_AND_FNC(TMS570_BALL_E7, 1) + +#define TMS570_BALL_C11 TMS570_BALL_WITH_MMR(20, 0) +#define TMS570_BALL_C11_EMIF_ADDR_13 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 0) +#define TMS570_BALL_C11_RTP_DATA_05 TMS570_PIN_AND_FNC(TMS570_BALL_C11, 1) + +#define TMS570_BALL_C10 TMS570_BALL_WITH_MMR(20, 1) +#define TMS570_BALL_C10_EMIF_ADDR_12 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 0) +#define TMS570_BALL_C10_RTP_DATA_06 TMS570_PIN_AND_FNC(TMS570_BALL_C10, 1) + +#define TMS570_BALL_F3 TMS570_BALL_WITH_MMR(20, 2) +#define TMS570_BALL_F3_MIBSPI1NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_F3, 0) +#define TMS570_BALL_F3_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 1), \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0) | TMS570_PIN_CLEAR_RQ_MASK) +#define TMS570_BALL_F3_MII_COL TMS570_PIN_AND_FNC(TMS570_BALL_F3, 2) + +#define TMS570_BALL_C9 TMS570_BALL_WITH_MMR(20, 3) +#define TMS570_BALL_C9_EMIF_ADDR_11 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 0) +#define TMS570_BALL_C9_RTP_DATA_08 TMS570_PIN_AND_FNC(TMS570_BALL_C9, 1) + +#define TMS570_BALL_D5 TMS570_BALL_WITH_MMR(21, 0) +#define TMS570_BALL_D5_EMIF_ADDR_1 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 0) +#define TMS570_BALL_D5_HET2_03 TMS570_PIN_AND_FNC(TMS570_BALL_D5, 1) + +#define TMS570_BALL_K2 TMS570_BALL_WITH_MMR(21, 1) +#define TMS570_BALL_K2_GIOB_1 TMS570_PIN_AND_FNC(TMS570_BALL_K2, 0) + +#define TMS570_BALL_C8 TMS570_BALL_WITH_MMR(21, 2) +#define TMS570_BALL_C8_EMIF_ADDR_10 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 0) +#define TMS570_BALL_C8_RTP_DATA_09 TMS570_PIN_AND_FNC(TMS570_BALL_C8, 1) + +#define TMS570_BALL_C7 TMS570_BALL_WITH_MMR(21, 3) +#define TMS570_BALL_C7_EMIF_ADDR_9 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 0) +#define TMS570_BALL_C7_RTP_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_C7, 1) + +#define TMS570_BALL_D4 TMS570_BALL_WITH_MMR(22, 0) +#define TMS570_BALL_D4_EMIF_ADDR_0 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 0) +#define TMS570_BALL_D4_HET2_01 TMS570_PIN_AND_FNC(TMS570_BALL_D4, 1) + +#define TMS570_BALL_C5 TMS570_BALL_WITH_MMR(22, 1) +#define TMS570_BALL_C5_EMIF_ADDR_7 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 0) +#define TMS570_BALL_C5_RTP_DATA_12 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 1) +#define TMS570_BALL_C5_HET2_13 TMS570_PIN_AND_FNC(TMS570_BALL_C5, 2) + +#define TMS570_BALL_C4 TMS570_BALL_WITH_MMR(22, 2) +#define TMS570_BALL_C4_EMIF_ADDR_6 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 0) +#define TMS570_BALL_C4_RTP_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 1) +#define TMS570_BALL_C4_HET2_11 TMS570_PIN_AND_FNC(TMS570_BALL_C4, 2) + +#define TMS570_BALL_E6 TMS570_BALL_WITH_MMR(22, 3) +#define TMS570_BALL_E6_ETMDATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 0) +#define TMS570_BALL_E6_EMIF_ADDR_2 TMS570_PIN_AND_FNC(TMS570_BALL_E6, 1) + +#define TMS570_BALL_C6 TMS570_BALL_WITH_MMR(23, 0) +#define TMS570_BALL_C6_EMIF_ADDR_8 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 0) +#define TMS570_BALL_C6_RTP_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 1) +#define TMS570_BALL_C6_HET2_15 TMS570_PIN_AND_FNC(TMS570_BALL_C6, 2) + +#define TMS570_MMR_SELECT_SPI4CLK TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 1), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_K18, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4SIMO TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 2), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W5, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4SOMI TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(23, 3), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V6, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4NENA TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 0), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V2, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_MMR_SELECT_SPI4NCS_0 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(24, 1), 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_U1, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A13 TMS570_BALL_WITH_MMR(24, 2) +#define TMS570_BALL_A13_HET1_17 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A13, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_F3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_B13 TMS570_BALL_WITH_MMR(24, 3) +#define TMS570_BALL_B13_HET1_19 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_B13, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_H4 TMS570_BALL_WITH_MMR(25, 0) +#define TMS570_BALL_H4_HET1_21 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_H4, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_J3, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_J4 TMS570_BALL_WITH_MMR(25, 1) +#define TMS570_BALL_J4_HET1_23 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J4, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_G19, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_M3 TMS570_BALL_WITH_MMR(25, 2) +#define TMS570_BALL_M3_HET1_25 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_M3, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_V5, 1) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A9 TMS570_BALL_WITH_MMR(25, 3) +#define TMS570_BALL_A9_HET1_27 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A9, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_B2, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_A3 TMS570_BALL_WITH_MMR(26, 0) +#define TMS570_BALL_A3_HET1_29 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_A3, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_C3, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_J17 TMS570_BALL_WITH_MMR(26, 1) +#define TMS570_BALL_J17_HET1_31 TMS570_PIN_WITH_IN_ALT( \ + TMS570_PIN_AND_FNC(TMS570_BALL_J17, 0), \ + TMS570_PIN_AND_FNC(TMS570_BALL_W9, 2) | TMS570_PIN_CLEAR_RQ_MASK) + +#define TMS570_BALL_W6 TMS570_BALL_WITH_MMR(26, 2) +#define TMS570_BALL_W6_MIBSPI5NCS_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 0) +#define TMS570_BALL_W6_DMM_DATA_2 TMS570_PIN_AND_FNC(TMS570_BALL_W6, 1) + +#define TMS570_BALL_T12 TMS570_BALL_WITH_MMR(26, 3) +#define TMS570_BALL_T12_MIBSPI5NCS_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 0) +#define TMS570_BALL_T12_DMM_DATA_3 TMS570_PIN_AND_FNC(TMS570_BALL_T12, 1) + +#define TMS570_BALL_E19 TMS570_BALL_WITH_MMR(27, 0) +#define TMS570_BALL_E19_MIBSPI5NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 0) +#define TMS570_BALL_E19_DMM_DATA_5 TMS570_PIN_AND_FNC(TMS570_BALL_E19, 1) + +#define TMS570_BALL_B6 TMS570_BALL_WITH_MMR(27, 1) +#define TMS570_BALL_B6_MIBSPI5NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 0) +#define TMS570_BALL_B6_DMM_DATA_6 TMS570_PIN_AND_FNC(TMS570_BALL_B6, 1) + +#define TMS570_BALL_E16 TMS570_BALL_WITH_MMR(27, 2) +#define TMS570_BALL_E16_MIBSPI5SIMO_1 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 0) +#define TMS570_BALL_E16_DMM_DATA_9 TMS570_PIN_AND_FNC(TMS570_BALL_E16, 1) + +#define TMS570_BALL_H17 TMS570_BALL_WITH_MMR(27, 3) +#define TMS570_BALL_H17_MIBSPI5SIMO_2 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 0) +#define TMS570_BALL_H17_DMM_DATA_10 TMS570_PIN_AND_FNC(TMS570_BALL_H17, 1) + +#define TMS570_BALL_G17 TMS570_BALL_WITH_MMR(28, 0) +#define TMS570_BALL_G17_MIBSPI5SIMO_3 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 0) +#define TMS570_BALL_G17_DMM_DATA_11 TMS570_PIN_AND_FNC(TMS570_BALL_G17, 1) + +#define TMS570_BALL_E17 TMS570_BALL_WITH_MMR(28, 1) +#define TMS570_BALL_E17_MIBSPI5SOMI_1 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 0) +#define TMS570_BALL_E17_DMM_DATA_13 TMS570_PIN_AND_FNC(TMS570_BALL_E17, 1) + +#define TMS570_BALL_H16 TMS570_BALL_WITH_MMR(28, 2) +#define TMS570_BALL_H16_MIBSPI5SOMI_2 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 0) +#define TMS570_BALL_H16_DMM_DATA_14 TMS570_PIN_AND_FNC(TMS570_BALL_H16, 1) + +#define TMS570_BALL_G16 TMS570_BALL_WITH_MMR(28, 3) +#define TMS570_BALL_G16_MIBSPI5SOMI_3 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 0) +#define TMS570_BALL_G16_DMM_DATA_15 TMS570_PIN_AND_FNC(TMS570_BALL_G16, 1) + +#define TMS570_BALL_D3 TMS570_BALL_WITH_MMR(29, 0) +#define TMS570_BALL_D3_SPI2NENA TMS570_PIN_AND_FNC(TMS570_BALL_D3, 0) +#define TMS570_BALL_D3_SPI2NCS_1 TMS570_PIN_AND_FNC(TMS570_BALL_D3, 1) + +#define TMS570_MMR_SELECT_EMIF_CLK_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 1), 0) + +#define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(29, 2) +#define TMS570_BALL_F2_GIOB_2 TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0) + +#define TMS570_MMR_SELECT_GMII_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0) + +#define TMS570_MMR_SELECT_ADC_TRG1 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 0) +#define TMS570_MMR_SELECT_ADC_TRG2 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 1) + +/* Default pinmux select */ + +#define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ + per_pin_action(common_arg, TMS570_BALL_W10_GIOB_3) \ + per_pin_action(common_arg, TMS570_BALL_A5_GIOA_0) \ + per_pin_action(common_arg, TMS570_BALL_C3_MIBSPI3NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_B2_MIBSPI3NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_C2_GIOA_1) \ + per_pin_action(common_arg, TMS570_BALL_E3_HET1_11) \ + per_pin_action(common_arg, TMS570_BALL_E5_ETMDATA_20) \ + per_pin_action(common_arg, TMS570_BALL_F5_ETMDATA_21) \ + per_pin_action(common_arg, TMS570_BALL_C1_GIOA_2) \ + per_pin_action(common_arg, TMS570_BALL_G5_ETMDATA_22) \ + per_pin_action(common_arg, TMS570_BALL_E1_GIOA_3) \ + per_pin_action(common_arg, TMS570_BALL_B5_GIOA_5) \ + per_pin_action(common_arg, TMS570_BALL_K5_ETMDATA_23) \ + per_pin_action(common_arg, TMS570_BALL_B3_HET1_22) \ + per_pin_action(common_arg, TMS570_BALL_H3_GIOA_6) \ + per_pin_action(common_arg, TMS570_BALL_L5_ETMDATA_24) \ + per_pin_action(common_arg, TMS570_BALL_M1_GIOA_7) \ + per_pin_action(common_arg, TMS570_BALL_M5_ETMDATA_25) \ + per_pin_action(common_arg, TMS570_BALL_V2_HET1_01) \ + per_pin_action(common_arg, TMS570_BALL_U1_HET1_03) \ + per_pin_action(common_arg, TMS570_BALL_K18_HET1_00) \ + per_pin_action(common_arg, TMS570_BALL_W5_HET1_02) \ + per_pin_action(common_arg, TMS570_BALL_V6_HET1_05) \ + per_pin_action(common_arg, TMS570_BALL_N5_ETMDATA_26) \ + per_pin_action(common_arg, TMS570_BALL_T1_HET1_07) \ + per_pin_action(common_arg, TMS570_BALL_P5_ETMDATA_27) \ + per_pin_action(common_arg, TMS570_BALL_V7_HET1_09) \ + per_pin_action(common_arg, TMS570_BALL_R5_ETMDATA_28) \ + per_pin_action(common_arg, TMS570_BALL_R6_ETMDATA_29) \ + per_pin_action(common_arg, TMS570_BALL_V5_MIBSPI3NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_W3_HET1_06) \ + per_pin_action(common_arg, TMS570_BALL_R7_ETMDATA_30) \ + per_pin_action(common_arg, TMS570_BALL_N2_HET1_13) \ + per_pin_action(common_arg, TMS570_BALL_G3_MIBSPI1NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_N1_HET1_15) \ + per_pin_action(common_arg, TMS570_BALL_R8_ETMDATA_31) \ + per_pin_action(common_arg, TMS570_BALL_R9_ETMTRACECLKIN) \ + per_pin_action(common_arg, TMS570_BALL_W9_MIBSPI3NENA) \ + per_pin_action(common_arg, TMS570_BALL_V10_MIBSPI3NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_J3_MIBSPI1NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_N19_AD1EVT) \ + per_pin_action(common_arg, TMS570_BALL_N15_ETMDATA_19) \ + per_pin_action(common_arg, TMS570_BALL_N17_EMIF_nCS_0) \ + per_pin_action(common_arg, TMS570_BALL_M15_ETMDATA_18) \ + per_pin_action(common_arg, TMS570_BALL_K17_EMIF_nCS_3) \ + per_pin_action(common_arg, TMS570_BALL_M17_EMIF_nCS_4) \ + per_pin_action(common_arg, TMS570_BALL_L15_ETMDATA_17) \ + per_pin_action(common_arg, TMS570_BALL_P1_HET1_24) \ + per_pin_action(common_arg, TMS570_BALL_A14_HET1_26) \ + per_pin_action(common_arg, TMS570_BALL_K15_ETMDATA_16) \ + per_pin_action(common_arg, TMS570_BALL_G19_MIBSPI1NENA) \ + per_pin_action(common_arg, TMS570_BALL_H18_MIBSPI5NENA) \ + per_pin_action(common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0) \ + per_pin_action(common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0) \ + per_pin_action(common_arg, TMS570_BALL_H19_MIBSPI5CLK) \ + per_pin_action(common_arg, TMS570_BALL_R2_MIBSPI1NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_E18_HET1_08) \ + per_pin_action(common_arg, TMS570_BALL_K19_HET1_28) \ + per_pin_action(common_arg, TMS570_BALL_D17_EMIF_nWE) \ + per_pin_action(common_arg, TMS570_BALL_D16_EMIF_BA_1) \ + per_pin_action(common_arg, TMS570_BALL_C17_EMIF_ADDR_21) \ + per_pin_action(common_arg, TMS570_BALL_C16_EMIF_ADDR_20) \ + per_pin_action(common_arg, TMS570_BALL_C15_EMIF_ADDR_19) \ + per_pin_action(common_arg, TMS570_BALL_D15_EMIF_ADDR_18) \ + per_pin_action(common_arg, TMS570_BALL_E13_ETMDATA_12) \ + per_pin_action(common_arg, TMS570_BALL_C14_EMIF_ADDR_17) \ + per_pin_action(common_arg, TMS570_BALL_D14_EMIF_ADDR_16) \ + per_pin_action(common_arg, TMS570_BALL_E12_ETMDATA_13) \ + per_pin_action(common_arg, TMS570_BALL_D19_HET1_10) \ + per_pin_action(common_arg, TMS570_BALL_E11_ETMDATA_14) \ + per_pin_action(common_arg, TMS570_BALL_B4_HET1_12) \ + per_pin_action(common_arg, TMS570_BALL_E9_ETMDATA_8) \ + per_pin_action(common_arg, TMS570_BALL_C13_EMIF_ADDR_15) \ + per_pin_action(common_arg, TMS570_BALL_A11_HET1_14) \ + per_pin_action(common_arg, TMS570_BALL_C12_EMIF_ADDR_14) \ + per_pin_action(common_arg, TMS570_BALL_M2_GIOB_0) \ + per_pin_action(common_arg, TMS570_BALL_E8_ETMDATA_09) \ + per_pin_action(common_arg, TMS570_BALL_B11_HET1_30) \ + per_pin_action(common_arg, TMS570_BALL_E10_ETMDATA_15) \ + per_pin_action(common_arg, TMS570_BALL_E7_ETMDATA_10) \ + per_pin_action(common_arg, TMS570_BALL_C11_EMIF_ADDR_13) \ + per_pin_action(common_arg, TMS570_BALL_C10_EMIF_ADDR_12) \ + per_pin_action(common_arg, TMS570_BALL_F3_MIBSPI1NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_C9_EMIF_ADDR_11) \ + per_pin_action(common_arg, TMS570_BALL_D5_EMIF_ADDR_1) \ + per_pin_action(common_arg, TMS570_BALL_K2_GIOB_1) \ + per_pin_action(common_arg, TMS570_BALL_C8_EMIF_ADDR_10) \ + per_pin_action(common_arg, TMS570_BALL_C7_EMIF_ADDR_9) \ + per_pin_action(common_arg, TMS570_BALL_D4_EMIF_ADDR_0) \ + per_pin_action(common_arg, TMS570_BALL_C5_EMIF_ADDR_7) \ + per_pin_action(common_arg, TMS570_BALL_C4_EMIF_ADDR_6) \ + per_pin_action(common_arg, TMS570_BALL_E6_ETMDATA_11) \ + per_pin_action(common_arg, TMS570_BALL_C6_EMIF_ADDR_8) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4CLK) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4SIMO) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4SOMI) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4NENA) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_SPI4NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_A13_HET1_17) \ + per_pin_action(common_arg, TMS570_BALL_B13_HET1_19) \ + per_pin_action(common_arg, TMS570_BALL_H4_HET1_21) \ + per_pin_action(common_arg, TMS570_BALL_J4_HET1_23) \ + per_pin_action(common_arg, TMS570_BALL_M3_HET1_25) \ + per_pin_action(common_arg, TMS570_BALL_A9_HET1_27) \ + per_pin_action(common_arg, TMS570_BALL_A3_HET1_29) \ + per_pin_action(common_arg, TMS570_BALL_J17_HET1_31) \ + per_pin_action(common_arg, TMS570_BALL_W6_MIBSPI5NCS_2) \ + per_pin_action(common_arg, TMS570_BALL_T12_MIBSPI5NCS_3) \ + per_pin_action(common_arg, TMS570_BALL_E19_MIBSPI5NCS_0) \ + per_pin_action(common_arg, TMS570_BALL_B6_MIBSPI5NCS_1) \ + per_pin_action(common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1) \ + per_pin_action(common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2) \ + per_pin_action(common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3) \ + per_pin_action(common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1) \ + per_pin_action(common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2) \ + per_pin_action(common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3) \ + per_pin_action(common_arg, TMS570_BALL_D3_SPI2NENA) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_EMIF_CLK_SEL) \ + per_pin_action(common_arg, TMS570_BALL_F2_GIOB_2) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_GMII_SEL) \ + per_pin_action(common_arg, TMS570_MMR_SELECT_ADC_TRG1) \ + +/* End of default PINMMR list */ + +#endif /*LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H*/ diff --git a/bsps/arm/tms570/include/tm27.h b/bsps/arm/tms570/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/tms570/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/arm/xilinx-zynq/headers.am b/bsps/arm/xilinx-zynq/headers.am new file mode 100644 index 0000000000..708bd6411a --- /dev/null +++ b/bsps/arm/xilinx-zynq/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h diff --git a/bsps/arm/xilinx-zynq/include/bsp.h b/bsps/arm/xilinx-zynq/include/bsp.h new file mode 100644 index 0000000000..afc6a66a06 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp.h @@ -0,0 +1,80 @@ +/** + * @file + * @ingroup arm_zynq + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H +#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_zynq Xilinx-Zynq Support + * @ingroup bsp_arm + * @brief Xilinz-Zynq Board Support Package + * @{ + */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 + +#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 + +#define BSP_ARM_GIC_DIST_BASE 0xf8f01000 + +#define BSP_ARM_L2C_310_BASE 0xf8f02000 + +#define BSP_ARM_L2C_310_ID 0x410000c8 + +/** + * @brief Zynq specific set up of the MMU. + * + * Provide in the application to override + * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 + * AXI ports. You should add the specific regions that map into your + * PL rather than just open the whole of the GP[01] address space up. + */ +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void); + +uint32_t zynq_clock_cpu_1x(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h new file mode 100644 index 0000000000..c06a47c7f1 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H + +#include + +typedef struct { + uint32_t control; +#define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6) +#define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5) +#define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4) +#define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3) +#define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2) +#define CADENCE_I2C_CONTROL_MS BSP_BIT32(1) +#define CADENCE_I2C_CONTROL_RW BSP_BIT32(0) + uint32_t status; +#define CADENCE_I2C_STATUS_BA BSP_BIT32(8) +#define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7) +#define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6) +#define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5) +#define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3) + uint32_t address; +#define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9) +#define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t data; + uint32_t irqstatus; +#define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9) +#define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7) +#define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6) +#define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5) +#define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4) +#define CADENCE_I2C_IXR_TO BSP_BIT32(3) +#define CADENCE_I2C_IXR_NACK BSP_BIT32(2) +#define CADENCE_I2C_IXR_DATA BSP_BIT32(1) +#define CADENCE_I2C_IXR_COMP BSP_BIT32(0) + uint32_t transfer_size; +#define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t slave_mon_pause; +#define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t timeout; +#define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t irqmask; + uint32_t irqenable; + uint32_t irqdisable; +} cadence_i2c; + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h new file mode 100644 index 0000000000..9697cf3354 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int i2c_bus_register_cadence( + const char *bus_path, + uintptr_t register_base, + uint32_t input_clock, + rtems_vector_number irq +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/i2c.h b/bsps/arm/xilinx-zynq/include/bsp/i2c.h new file mode 100644 index 0000000000..709ea0178e --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/i2c.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline int zynq_register_i2c_0(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-0", + 0xe0004000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_0 + ); +} + +static inline int zynq_register_i2c_1(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-1", + 0xe0005000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_1 + ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h b/bsps/arm/xilinx-zynq/include/bsp/irq.h new file mode 100644 index 0000000000..e8288938fe --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h @@ -0,0 +1,115 @@ +/** + * @file + * @ingroup zynq_interrupt + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H +#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_interrupt Interrupt Support + * @ingroup arm_zynq + * @brief Interrupt Support + * @{ + */ + +#define ZYNQ_IRQ_CPU_0 32 +#define ZYNQ_IRQ_CPU_1 33 +#define ZYNQ_IRQ_L2_CACHE 34 +#define ZYNQ_IRQ_OCM 35 +#define ZYNQ_IRQ_PMU_0 37 +#define ZYNQ_IRQ_PMU_1 38 +#define ZYNQ_IRQ_XADC 39 +#define ZYNQ_IRQ_DVI 40 +#define ZYNQ_IRQ_SWDT 41 +#define ZYNQ_IRQ_TTC_0_0 42 +#define ZYNQ_IRQ_TTC_1_0 43 +#define ZYNQ_IRQ_TTC_2_0 44 +#define ZYNQ_IRQ_DMAC_ABORT 45 +#define ZYNQ_IRQ_DMAC_0 46 +#define ZYNQ_IRQ_DMAC_1 47 +#define ZYNQ_IRQ_DMAC_2 48 +#define ZYNQ_IRQ_DMAC_3 49 +#define ZYNQ_IRQ_SMC 50 +#define ZYNQ_IRQ_QUAD_SPI 51 +#define ZYNQ_IRQ_GPIO 52 +#define ZYNQ_IRQ_USB_0 53 +#define ZYNQ_IRQ_ETHERNET_0 54 +#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 +#define ZYNQ_IRQ_SDIO_0 56 +#define ZYNQ_IRQ_I2C_0 57 +#define ZYNQ_IRQ_SPI_0 58 +#define ZYNQ_IRQ_UART_0 59 +#define ZYNQ_IRQ_CAN_0 60 +#define ZYNQ_IRQ_FPGA_0 61 +#define ZYNQ_IRQ_FPGA_1 62 +#define ZYNQ_IRQ_FPGA_2 63 +#define ZYNQ_IRQ_FPGA_3 64 +#define ZYNQ_IRQ_FPGA_4 65 +#define ZYNQ_IRQ_FPGA_5 66 +#define ZYNQ_IRQ_FPGA_6 67 +#define ZYNQ_IRQ_FPGA_7 68 +#define ZYNQ_IRQ_TTC_0_1 69 +#define ZYNQ_IRQ_TTC_1_1 70 +#define ZYNQ_IRQ_TTC_2_1 71 +#define ZYNQ_IRQ_DMAC_4 72 +#define ZYNQ_IRQ_DMAC_5 73 +#define ZYNQ_IRQ_DMAC_6 74 +#define ZYNQ_IRQ_DMAC_7 75 +#define ZYNQ_IRQ_USB_1 76 +#define ZYNQ_IRQ_ETHERNET_1 77 +#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 +#define ZYNQ_IRQ_SDIO_1 79 +#define ZYNQ_IRQ_I2C_1 80 +#define ZYNQ_IRQ_SPI_1 81 +#define ZYNQ_IRQ_UART_1 82 +#define ZYNQ_IRQ_CAN_1 83 +#define ZYNQ_IRQ_FPGA_8 84 +#define ZYNQ_IRQ_FPGA_9 85 +#define ZYNQ_IRQ_FPGA_10 86 +#define ZYNQ_IRQ_FPGA_11 87 +#define ZYNQ_IRQ_FPGA_12 88 +#define ZYNQ_IRQ_FPGA_13 89 +#define ZYNQ_IRQ_FPGA_14 90 +#define ZYNQ_IRQ_FPGA_15 91 +#define ZYNQ_IRQ_PARITY 92 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 92 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h new file mode 100644 index 0000000000..127f272fd9 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h @@ -0,0 +1,150 @@ +/** + * @file + * @ingroup zynq_uart_regs + * @brief UART register definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup zynq_uart_regs UART Register Definitions + * @ingroup zynq_uart + * @brief UART Register Definitions + * @{ + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H + +#include + +#define ZYNQ_UART_FIFO_DEPTH 64 + +typedef struct zynq_uart { + uint32_t control; +#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8) +#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7) +#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6) +#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5) +#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4) +#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3) +#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2) +#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1) +#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0) + uint32_t mode; +#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U +#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U +#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U +#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U +#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U +#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U +#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U +#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5) +#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define ZYNQ_UART_MODE_PAR_EVEN 0x00U +#define ZYNQ_UART_MODE_PAR_ODD 0x01U +#define ZYNQ_UART_MODE_PAR_SPACE 0x02U +#define ZYNQ_UART_MODE_PAR_MARK 0x03U +#define ZYNQ_UART_MODE_PAR_NONE 0x04U +#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_8 0x00U +#define ZYNQ_UART_MODE_CHRL_7 0x02U +#define ZYNQ_UART_MODE_CHRL_6 0x03U +#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0) + uint32_t irq_en; + uint32_t irq_dis; + uint32_t irq_mask; + uint32_t irq_sts; +#define ZYNQ_UART_TOVR BSP_BIT32(12) +#define ZYNQ_UART_TNFUL BSP_BIT32(11) +#define ZYNQ_UART_TTRIG BSP_BIT32(10) +#define ZYNQ_UART_DMSI BSP_BIT32(9) +#define ZYNQ_UART_TIMEOUT BSP_BIT32(8) +#define ZYNQ_UART_PARE BSP_BIT32(7) +#define ZYNQ_UART_FRAME BSP_BIT32(6) +#define ZYNQ_UART_ROVR BSP_BIT32(5) +#define ZYNQ_UART_TFUL BSP_BIT32(4) +#define ZYNQ_UART_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_RFUL BSP_BIT32(2) +#define ZYNQ_UART_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_RTRIG BSP_BIT32(0) + uint32_t baud_rate_gen; +#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t rx_timeout; +#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t rx_fifo_trg_lvl; +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t modem_ctrl; +#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5) +#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1) +#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0) + uint32_t modem_sts; +#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8) +#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7) +#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6) +#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5) +#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4) +#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3) +#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2) +#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1) +#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0) + uint32_t channel_sts; +#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14) +#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13) +#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12) +#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11) +#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10) +#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4) +#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2) +#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0) + uint32_t tx_rx_fifo; +#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t baud_rate_div; +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t flow_delay; +#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t reserved_3c[2]; + uint32_t tx_fifo_trg_lvl; +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +} zynq_uart; + +/** @} */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h new file mode 100644 index 0000000000..4d3edfabef --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h @@ -0,0 +1,67 @@ +/** + * @file + * @ingroup zynq_uart + * @brief UART support. + */ + +/* + * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_uart UART Support + * @ingroup arm_zynq + * @brief UART Support + */ + +typedef struct { + rtems_termios_device_context base; + volatile struct zynq_uart *regs; + bool transmitting; + rtems_vector_number irq; +} zynq_uart_context; + +const rtems_termios_device_handler zynq_uart_handler; + +extern zynq_uart_context zynq_uart_instances[2]; + +#define ZYNQ_UART_DEFAULT_BAUD 115200 + +void zynq_uart_initialize(rtems_termios_device_context *base); + +int zynq_uart_read_polled(rtems_termios_device_context *base); + +void zynq_uart_write_polled( + rtems_termios_device_context *base, + char c +); + +/** + * Flush TX FIFO and wait until it is empty. Used in bsp_reset. + */ +void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */ diff --git a/bsps/arm/xilinx-zynq/include/tm27.h b/bsps/arm/xilinx-zynq/include/tm27.h new file mode 100644 index 0000000000..39b8ecafec --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/tm27.h @@ -0,0 +1,36 @@ +/** + * @file + * @ingroup zynq_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup zynq_tm27 TM27 Test Support + * @ingroup arm_zynq + * @brief Interrupt Mechanisms for tm27 test + */ + +#include + +#endif /* __tm27_h */ -- cgit v1.2.3